git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "ath9k.h"
  21 #include "initvals.h"
  22
  23 static int btcoex_enable;
  24 module_param(btcoex_enable, bool, 0);
  25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
  26
  27 #define ATH9K_CLOCK_RATE_CCK            22
  28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
  33                               enum ath9k_ht_macmode macmode);
  34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  35                               struct ar5416_eeprom_def *pEepData,
  36                               u32 reg, u32 value);
  37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  39
  40 /********************/
  41 /* Helper Functions */
  42 /********************/
  43
  44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  45 {
  46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  47
  48         if (!ah->curchan) /* should really check for CCK instead */
  49                 return clks / ATH9K_CLOCK_RATE_CCK;
  50         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  51                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  52
  53         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  54 }
  55
  56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  57 {
  58         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  59
  60         if (conf_is_ht40(conf))
  61                 return ath9k_hw_mac_usec(ah, clks) / 2;
  62         else
  63                 return ath9k_hw_mac_usec(ah, clks);
  64 }
  65
  66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  69
  70         if (!ah->curchan) /* should really check for CCK instead */
  71                 return usecs *ATH9K_CLOCK_RATE_CCK;
  72         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  73                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  74         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  75 }
  76
  77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  78 {
  79         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  80
  81         if (conf_is_ht40(conf))
  82                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  83         else
  84                 return ath9k_hw_mac_clks(ah, usecs);
  85 }
  86
  87 /*
  88  * Read and write, they both share the same lock. We do this to serialize
  89  * reads and writes on Atheros 802.11n PCI devices only. This is required
  90  * as the FIFO on these devices can only accept sanely 2 requests. After
  91  * that the device goes bananas. Serializing the reads/writes prevents this
  92  * from happening.
  93  */
  94
  95 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
  96 {
  97         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
  98                 unsigned long flags;
  99                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 100                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 101                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 102         } else
 103                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 104 }
 105
 106 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
 107 {
 108         u32 val;
 109         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
 110                 unsigned long flags;
 111                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 112                 val = ioread32(ah->ah_sc->mem + reg_offset);
 113                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 114         } else
 115                 val = ioread32(ah->ah_sc->mem + reg_offset);
 116         return val;
 117 }
 118
 119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 120 {
 121         int i;
 122
 123         BUG_ON(timeout < AH_TIME_QUANTUM);
 124
 125         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 126                 if ((REG_READ(ah, reg) & mask) == val)
 127                         return true;
 128
 129                 udelay(AH_TIME_QUANTUM);
 130         }
 131
 132         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
 133                 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 134                 timeout, reg, REG_READ(ah, reg), mask, val);
 135
 136         return false;
 137 }
 138
 139 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 140 {
 141         u32 retval;
 142         int i;
 143
 144         for (i = 0, retval = 0; i < n; i++) {
 145                 retval = (retval << 1) | (val & 1);
 146                 val >>= 1;
 147         }
 148         return retval;
 149 }
 150
 151 bool ath9k_get_channel_edges(struct ath_hw *ah,
 152                              u16 flags, u16 *low,
 153                              u16 *high)
 154 {
 155         struct ath9k_hw_capabilities *pCap = &ah->caps;
 156
 157         if (flags & CHANNEL_5GHZ) {
 158                 *low = pCap->low_5ghz_chan;
 159                 *high = pCap->high_5ghz_chan;
 160                 return true;
 161         }
 162         if ((flags & CHANNEL_2GHZ)) {
 163                 *low = pCap->low_2ghz_chan;
 164                 *high = pCap->high_2ghz_chan;
 165                 return true;
 166         }
 167         return false;
 168 }
 169
 170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 171                            const struct ath_rate_table *rates,
 172                            u32 frameLen, u16 rateix,
 173                            bool shortPreamble)
 174 {
 175         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 176         u32 kbps;
 177
 178         kbps = rates->info[rateix].ratekbps;
 179
 180         if (kbps == 0)
 181                 return 0;
 182
 183         switch (rates->info[rateix].phy) {
 184         case WLAN_RC_PHY_CCK:
 185                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 186                 if (shortPreamble && rates->info[rateix].short_preamble)
 187                         phyTime >>= 1;
 188                 numBits = frameLen << 3;
 189                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 190                 break;
 191         case WLAN_RC_PHY_OFDM:
 192                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 193                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 194                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 195                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 196                         txTime = OFDM_SIFS_TIME_QUARTER
 197                                 + OFDM_PREAMBLE_TIME_QUARTER
 198                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 199                 } else if (ah->curchan &&
 200                            IS_CHAN_HALF_RATE(ah->curchan)) {
 201                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 202                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 203                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 204                         txTime = OFDM_SIFS_TIME_HALF +
 205                                 OFDM_PREAMBLE_TIME_HALF
 206                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 207                 } else {
 208                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 209                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 210                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 211                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 212                                 + (numSymbols * OFDM_SYMBOL_TIME);
 213                 }
 214                 break;
 215         default:
 216                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 217                         "Unknown phy %u (rate ix %u)\n",
 218                         rates->info[rateix].phy, rateix);
 219                 txTime = 0;
 220                 break;
 221         }
 222
 223         return txTime;
 224 }
 225
 226 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 227                                   struct ath9k_channel *chan,
 228                                   struct chan_centers *centers)
 229 {
 230         int8_t extoff;
 231
 232         if (!IS_CHAN_HT40(chan)) {
 233                 centers->ctl_center = centers->ext_center =
 234                         centers->synth_center = chan->channel;
 235                 return;
 236         }
 237
 238         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 239             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 240                 centers->synth_center =
 241                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 242                 extoff = 1;
 243         } else {
 244                 centers->synth_center =
 245                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 246                 extoff = -1;
 247         }
 248
 249         centers->ctl_center =
 250                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 251         centers->ext_center =
 252                 centers->synth_center + (extoff *
 253                          ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 254                           HT40_CHANNEL_CENTER_SHIFT : 15));
 255 }
 256
 257 /******************/
 258 /* Chip Revisions */
 259 /******************/
 260
 261 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 262 {
 263         u32 val;
 264
 265         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 266
 267         if (val == 0xFF) {
 268                 val = REG_READ(ah, AR_SREV);
 269                 ah->hw_version.macVersion =
 270                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 271                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 272                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 273         } else {
 274                 if (!AR_SREV_9100(ah))
 275                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 276
 277                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 278
 279                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 280                         ah->is_pciexpress = true;
 281         }
 282 }
 283
 284 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 285 {
 286         u32 val;
 287         int i;
 288
 289         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 290
 291         for (i = 0; i < 8; i++)
 292                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 293         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 294         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 295
 296         return ath9k_hw_reverse_bits(val, 8);
 297 }
 298
 299 /************************************/
 300 /* HW Attach, Detach, Init Routines */
 301 /************************************/
 302
 303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 304 {
 305         if (AR_SREV_9100(ah))
 306                 return;
 307
 308         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 309         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 310         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 311         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 312         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 313         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 314         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 315         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 316         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 317
 318         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 319 }
 320
 321 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 322 {
 323         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 324         u32 regHold[2];
 325         u32 patternData[4] = { 0x55555555,
 326                                0xaaaaaaaa,
 327                                0x66666666,
 328                                0x99999999 };
 329         int i, j;
 330
 331         for (i = 0; i < 2; i++) {
 332                 u32 addr = regAddr[i];
 333                 u32 wrData, rdData;
 334
 335                 regHold[i] = REG_READ(ah, addr);
 336                 for (j = 0; j < 0x100; j++) {
 337                         wrData = (j << 16) | j;
 338                         REG_WRITE(ah, addr, wrData);
 339                         rdData = REG_READ(ah, addr);
 340                         if (rdData != wrData) {
 341                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 342                                         "address test failed "
 343                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 344                                         addr, wrData, rdData);
 345                                 return false;
 346                         }
 347                 }
 348                 for (j = 0; j < 4; j++) {
 349                         wrData = patternData[j];
 350                         REG_WRITE(ah, addr, wrData);
 351                         rdData = REG_READ(ah, addr);
 352                         if (wrData != rdData) {
 353                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 354                                         "address test failed "
 355                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 356                                         addr, wrData, rdData);
 357                                 return false;
 358                         }
 359                 }
 360                 REG_WRITE(ah, regAddr[i], regHold[i]);
 361         }
 362         udelay(100);
 363
 364         return true;
 365 }
 366
 367 static const char *ath9k_hw_devname(u16 devid)
 368 {
 369         switch (devid) {
 370         case AR5416_DEVID_PCI:
 371                 return "Atheros 5416";
 372         case AR5416_DEVID_PCIE:
 373                 return "Atheros 5418";
 374         case AR9160_DEVID_PCI:
 375                 return "Atheros 9160";
 376         case AR5416_AR9100_DEVID:
 377                 return "Atheros 9100";
 378         case AR9280_DEVID_PCI:
 379         case AR9280_DEVID_PCIE:
 380                 return "Atheros 9280";
 381         case AR9285_DEVID_PCIE:
 382                 return "Atheros 9285";
 383         }
 384
 385         return NULL;
 386 }
 387
 388 static void ath9k_hw_set_defaults(struct ath_hw *ah)
 389 {
 390         int i;
 391
 392         ah->config.dma_beacon_response_time = 2;
 393         ah->config.sw_beacon_response_time = 10;
 394         ah->config.additional_swba_backoff = 0;
 395         ah->config.ack_6mb = 0x0;
 396         ah->config.cwm_ignore_extcca = 0;
 397         ah->config.pcie_powersave_enable = 0;
 398         ah->config.pcie_clock_req = 0;
 399         ah->config.pcie_waen = 0;
 400         ah->config.analog_shiftreg = 1;
 401         ah->config.ht_enable = 1;
 402         ah->config.ofdm_trig_low = 200;
 403         ah->config.ofdm_trig_high = 500;
 404         ah->config.cck_trig_high = 200;
 405         ah->config.cck_trig_low = 100;
 406         ah->config.enable_ani = 1;
 407         ah->config.diversity_control = 0;
 408         ah->config.antenna_switch_swap = 0;
 409
 410         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 411                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 412                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 413         }
 414
 415         ah->config.intr_mitigation = true;
 416
 417         /*
 418          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 419          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 420          * This means we use it for all AR5416 devices, and the few
 421          * minor PCI AR9280 devices out there.
 422          *
 423          * Serialization is required because these devices do not handle
 424          * well the case of two concurrent reads/writes due to the latency
 425          * involved. During one read/write another read/write can be issued
 426          * on another CPU while the previous read/write may still be working
 427          * on our hardware, if we hit this case the hardware poops in a loop.
 428          * We prevent this by serializing reads and writes.
 429          *
 430          * This issue is not present on PCI-Express devices or pre-AR5416
 431          * devices (legacy, 802.11abg).
 432          */
 433         if (num_possible_cpus() > 1)
 434                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 435 }
 436
 437 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
 438                                         int *status)
 439 {
 440         struct ath_hw *ah;
 441
 442         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
 443         if (ah == NULL) {
 444                 DPRINTF(sc, ATH_DBG_FATAL,
 445                         "Cannot allocate memory for state block\n");
 446                 *status = -ENOMEM;
 447                 return NULL;
 448         }
 449
 450         ah->ah_sc = sc;
 451         ah->hw_version.magic = AR5416_MAGIC;
 452         ah->regulatory.country_code = CTRY_DEFAULT;
 453         ah->hw_version.devid = devid;
 454         ah->hw_version.subvendorid = 0;
 455
 456         ah->ah_flags = 0;
 457         if ((devid == AR5416_AR9100_DEVID))
 458                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 459         if (!AR_SREV_9100(ah))
 460                 ah->ah_flags = AH_USE_EEPROM;
 461
 462         ah->regulatory.power_limit = MAX_RATE_POWER;
 463         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
 464         ah->atim_window = 0;
 465         ah->diversity_control = ah->config.diversity_control;
 466         ah->antenna_switch_swap =
 467                 ah->config.antenna_switch_swap;
 468         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 469         ah->beacon_interval = 100;
 470         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 471         ah->slottime = (u32) -1;
 472         ah->acktimeout = (u32) -1;
 473         ah->ctstimeout = (u32) -1;
 474         ah->globaltxtimeout = (u32) -1;
 475
 476         ah->gbeacon_rate = 0;
 477
 478         return ah;
 479 }
 480
 481 static int ath9k_hw_rfattach(struct ath_hw *ah)
 482 {
 483         bool rfStatus = false;
 484         int ecode = 0;
 485
 486         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 487         if (!rfStatus) {
 488                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 489                         "RF setup failed, status: %u\n", ecode);
 490                 return ecode;
 491         }
 492
 493         return 0;
 494 }
 495
 496 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 497 {
 498         u32 val;
 499
 500         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 501
 502         val = ath9k_hw_get_radiorev(ah);
 503         switch (val & AR_RADIO_SREV_MAJOR) {
 504         case 0:
 505                 val = AR_RAD5133_SREV_MAJOR;
 506                 break;
 507         case AR_RAD5133_SREV_MAJOR:
 508         case AR_RAD5122_SREV_MAJOR:
 509         case AR_RAD2133_SREV_MAJOR:
 510         case AR_RAD2122_SREV_MAJOR:
 511                 break;
 512         default:
 513                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 514                         "Radio Chip Rev 0x%02X not supported\n",
 515                         val & AR_RADIO_SREV_MAJOR);
 516                 return -EOPNOTSUPP;
 517         }
 518
 519         ah->hw_version.analog5GhzRev = val;
 520
 521         return 0;
 522 }
 523
 524 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 525 {
 526         u32 sum;
 527         int i;
 528         u16 eeval;
 529
 530         sum = 0;
 531         for (i = 0; i < 3; i++) {
 532                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 533                 sum += eeval;
 534                 ah->macaddr[2 * i] = eeval >> 8;
 535                 ah->macaddr[2 * i + 1] = eeval & 0xff;
 536         }
 537         if (sum == 0 || sum == 0xffff * 3)
 538                 return -EADDRNOTAVAIL;
 539
 540         return 0;
 541 }
 542
 543 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 544 {
 545         u32 rxgain_type;
 546
 547         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 548                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 549
 550                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 551                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 552                         ar9280Modes_backoff_13db_rxgain_9280_2,
 553                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 554                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 555                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 556                         ar9280Modes_backoff_23db_rxgain_9280_2,
 557                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 558                 else
 559                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 560                         ar9280Modes_original_rxgain_9280_2,
 561                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 562         } else {
 563                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 564                         ar9280Modes_original_rxgain_9280_2,
 565                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 566         }
 567 }
 568
 569 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 570 {
 571         u32 txgain_type;
 572
 573         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 574                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 575
 576                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 577                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 578                         ar9280Modes_high_power_tx_gain_9280_2,
 579                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 580                 else
 581                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 582                         ar9280Modes_original_tx_gain_9280_2,
 583                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 584         } else {
 585                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 586                 ar9280Modes_original_tx_gain_9280_2,
 587                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 588         }
 589 }
 590
 591 static int ath9k_hw_post_attach(struct ath_hw *ah)
 592 {
 593         int ecode;
 594
 595         if (!ath9k_hw_chip_test(ah))
 596                 return -ENODEV;
 597
 598         ecode = ath9k_hw_rf_claim(ah);
 599         if (ecode != 0)
 600                 return ecode;
 601
 602         ecode = ath9k_hw_eeprom_attach(ah);
 603         if (ecode != 0)
 604                 return ecode;
 605
 606         DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
 607                 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
 608
 609         ecode = ath9k_hw_rfattach(ah);
 610         if (ecode != 0)
 611                 return ecode;
 612
 613         if (!AR_SREV_9100(ah)) {
 614                 ath9k_hw_ani_setup(ah);
 615                 ath9k_hw_ani_attach(ah);
 616         }
 617
 618         return 0;
 619 }
 620
 621 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 622                                          int *status)
 623 {
 624         struct ath_hw *ah;
 625         int ecode;
 626         u32 i, j;
 627
 628         ah = ath9k_hw_newstate(devid, sc, status);
 629         if (ah == NULL)
 630                 return NULL;
 631
 632         ath9k_hw_set_defaults(ah);
 633
 634         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 635                 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
 636                 ecode = -EIO;
 637                 goto bad;
 638         }
 639
 640         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 641                 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 642                 ecode = -EIO;
 643                 goto bad;
 644         }
 645
 646         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 647                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 648                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 649                         ah->config.serialize_regmode =
 650                                 SER_REG_MODE_ON;
 651                 } else {
 652                         ah->config.serialize_regmode =
 653                                 SER_REG_MODE_OFF;
 654                 }
 655         }
 656
 657         DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
 658                 ah->config.serialize_regmode);
 659
 660         if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
 661             (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
 662             (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
 663             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
 664                 DPRINTF(sc, ATH_DBG_FATAL,
 665                         "Mac Chip Rev 0x%02x.%x is not supported by "
 666                         "this driver\n", ah->hw_version.macVersion,
 667                         ah->hw_version.macRev);
 668                 ecode = -EOPNOTSUPP;
 669                 goto bad;
 670         }
 671
 672         if (AR_SREV_9100(ah)) {
 673                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 674                 ah->supp_cals = IQ_MISMATCH_CAL;
 675                 ah->is_pciexpress = false;
 676         }
 677         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 678
 679         if (AR_SREV_9160_10_OR_LATER(ah)) {
 680                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 681                         ah->iq_caldata.calData = &iq_cal_single_sample;
 682                         ah->adcgain_caldata.calData =
 683                                 &adc_gain_cal_single_sample;
 684                         ah->adcdc_caldata.calData =
 685                                 &adc_dc_cal_single_sample;
 686                         ah->adcdc_calinitdata.calData =
 687                                 &adc_init_dc_cal;
 688                 } else {
 689                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 690                         ah->adcgain_caldata.calData =
 691                                 &adc_gain_cal_multi_sample;
 692                         ah->adcdc_caldata.calData =
 693                                 &adc_dc_cal_multi_sample;
 694                         ah->adcdc_calinitdata.calData =
 695                                 &adc_init_dc_cal;
 696                 }
 697                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 698         }
 699
 700         ah->ani_function = ATH9K_ANI_ALL;
 701         if (AR_SREV_9280_10_OR_LATER(ah))
 702                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 703
 704         if (AR_SREV_9285_12_OR_LATER(ah)) {
 705
 706                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 707                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 708                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 709                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 710
 711                 if (ah->config.pcie_clock_req) {
 712                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 713                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 714                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 715                 } else {
 716                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 717                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 718                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 719                                   2);
 720                 }
 721         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 722                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 723                                ARRAY_SIZE(ar9285Modes_9285), 6);
 724                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 725                                ARRAY_SIZE(ar9285Common_9285), 2);
 726
 727                 if (ah->config.pcie_clock_req) {
 728                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 729                         ar9285PciePhy_clkreq_off_L1_9285,
 730                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 731                 } else {
 732                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 733                         ar9285PciePhy_clkreq_always_on_L1_9285,
 734                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 735                 }
 736         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 737                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 738                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 739                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 740                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 741
 742                 if (ah->config.pcie_clock_req) {
 743                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 744                                ar9280PciePhy_clkreq_off_L1_9280,
 745                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 746                 } else {
 747                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 748                                ar9280PciePhy_clkreq_always_on_L1_9280,
 749                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 750                 }
 751                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 752                                ar9280Modes_fast_clock_9280_2,
 753                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 754         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 755                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 756                                ARRAY_SIZE(ar9280Modes_9280), 6);
 757                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 758                                ARRAY_SIZE(ar9280Common_9280), 2);
 759         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 760                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 761                                ARRAY_SIZE(ar5416Modes_9160), 6);
 762                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 763                                ARRAY_SIZE(ar5416Common_9160), 2);
 764                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 765                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 766                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 767                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 768                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 769                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 770                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 771                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 772                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 773                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 774                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 775                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 776                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 777                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 778                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 779                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 780                 if (AR_SREV_9160_11(ah)) {
 781                         INIT_INI_ARRAY(&ah->iniAddac,
 782                                        ar5416Addac_91601_1,
 783                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 784                 } else {
 785                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 786                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 787                 }
 788         } else if (AR_SREV_9100_OR_LATER(ah)) {
 789                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 790                                ARRAY_SIZE(ar5416Modes_9100), 6);
 791                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 792                                ARRAY_SIZE(ar5416Common_9100), 2);
 793                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 794                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 795                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 796                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 797                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 798                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 799                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 800                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 801                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 802                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 803                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 804                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 805                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 806                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 807                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 808                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 809                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 810                                ARRAY_SIZE(ar5416Addac_9100), 2);
 811         } else {
 812                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 813                                ARRAY_SIZE(ar5416Modes), 6);
 814                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 815                                ARRAY_SIZE(ar5416Common), 2);
 816                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 817                                ARRAY_SIZE(ar5416Bank0), 2);
 818                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 819                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 820                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 821                                ARRAY_SIZE(ar5416Bank1), 2);
 822                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 823                                ARRAY_SIZE(ar5416Bank2), 2);
 824                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 825                                ARRAY_SIZE(ar5416Bank3), 3);
 826                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 827                                ARRAY_SIZE(ar5416Bank6), 3);
 828                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 829                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 830                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 831                                ARRAY_SIZE(ar5416Bank7), 2);
 832                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 833                                ARRAY_SIZE(ar5416Addac), 2);
 834         }
 835
 836         if (ah->is_pciexpress)
 837                 ath9k_hw_configpcipowersave(ah, 0);
 838         else
 839                 ath9k_hw_disablepcie(ah);
 840
 841         ecode = ath9k_hw_post_attach(ah);
 842         if (ecode != 0)
 843                 goto bad;
 844
 845         if (AR_SREV_9285_12_OR_LATER(ah)) {
 846                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 847
 848                 /* txgain table */
 849                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 850                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 851                         ar9285Modes_high_power_tx_gain_9285_1_2,
 852                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 853                 } else {
 854                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 855                         ar9285Modes_original_tx_gain_9285_1_2,
 856                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 857                 }
 858
 859         }
 860
 861         /* rxgain table */
 862         if (AR_SREV_9280_20(ah))
 863                 ath9k_hw_init_rxgain_ini(ah);
 864
 865         /* txgain table */
 866         if (AR_SREV_9280_20(ah))
 867                 ath9k_hw_init_txgain_ini(ah);
 868
 869         ath9k_hw_fill_cap_info(ah);
 870
 871         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 872             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
 873
 874                 /* EEPROM Fixup */
 875                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 876                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 877
 878                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 879                                 u32 val = INI_RA(&ah->iniModes, i, j);
 880
 881                                 INI_RA(&ah->iniModes, i, j) =
 882                                         ath9k_hw_ini_fixup(ah,
 883                                                            &ah->eeprom.def,
 884                                                            reg, val);
 885                         }
 886                 }
 887         }
 888
 889         ecode = ath9k_hw_init_macaddr(ah);
 890         if (ecode != 0) {
 891                 DPRINTF(sc, ATH_DBG_FATAL,
 892                         "Failed to initialize MAC address\n");
 893                 goto bad;
 894         }
 895
 896         if (AR_SREV_9285(ah))
 897                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 898         else
 899                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 900
 901         ath9k_init_nfcal_hist_buffer(ah);
 902
 903         return ah;
 904 bad:
 905         if (ah)
 906                 ath9k_hw_detach(ah);
 907         if (status)
 908                 *status = ecode;
 909
 910         return NULL;
 911 }
 912
 913 static void ath9k_hw_init_bb(struct ath_hw *ah,
 914                              struct ath9k_channel *chan)
 915 {
 916         u32 synthDelay;
 917
 918         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 919         if (IS_CHAN_B(chan))
 920                 synthDelay = (4 * synthDelay) / 22;
 921         else
 922                 synthDelay /= 10;
 923
 924         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 925
 926         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 927 }
 928
 929 static void ath9k_hw_init_qos(struct ath_hw *ah)
 930 {
 931         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 932         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 933
 934         REG_WRITE(ah, AR_QOS_NO_ACK,
 935                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 936                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 937                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 938
 939         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 940         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 941         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 942         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 943         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 944 }
 945
 946 static void ath9k_hw_init_pll(struct ath_hw *ah,
 947                               struct ath9k_channel *chan)
 948 {
 949         u32 pll;
 950
 951         if (AR_SREV_9100(ah)) {
 952                 if (chan && IS_CHAN_5GHZ(chan))
 953                         pll = 0x1450;
 954                 else
 955                         pll = 0x1458;
 956         } else {
 957                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 958                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 959
 960                         if (chan && IS_CHAN_HALF_RATE(chan))
 961                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 962                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 963                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 964
 965                         if (chan && IS_CHAN_5GHZ(chan)) {
 966                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
 967
 968
 969                                 if (AR_SREV_9280_20(ah)) {
 970                                         if (((chan->channel % 20) == 0)
 971                                             || ((chan->channel % 10) == 0))
 972                                                 pll = 0x2850;
 973                                         else
 974                                                 pll = 0x142c;
 975                                 }
 976                         } else {
 977                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
 978                         }
 979
 980                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 981
 982                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 983
 984                         if (chan && IS_CHAN_HALF_RATE(chan))
 985                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 986                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 987                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 988
 989                         if (chan && IS_CHAN_5GHZ(chan))
 990                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
 991                         else
 992                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
 993                 } else {
 994                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
 995
 996                         if (chan && IS_CHAN_HALF_RATE(chan))
 997                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
 998                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 999                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1000
1001                         if (chan && IS_CHAN_5GHZ(chan))
1002                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1003                         else
1004                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1005                 }
1006         }
1007         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1008
1009         udelay(RTC_PLL_SETTLE_DELAY);
1010
1011         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1012 }
1013
1014 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1015 {
1016         int rx_chainmask, tx_chainmask;
1017
1018         rx_chainmask = ah->rxchainmask;
1019         tx_chainmask = ah->txchainmask;
1020
1021         switch (rx_chainmask) {
1022         case 0x5:
1023                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1024                             AR_PHY_SWAP_ALT_CHAIN);
1025         case 0x3:
1026                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1027                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1028                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1029                         break;
1030                 }
1031         case 0x1:
1032         case 0x2:
1033         case 0x7:
1034                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1035                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1036                 break;
1037         default:
1038                 break;
1039         }
1040
1041         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1042         if (tx_chainmask == 0x5) {
1043                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1044                             AR_PHY_SWAP_ALT_CHAIN);
1045         }
1046         if (AR_SREV_9100(ah))
1047                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1048                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1049 }
1050
1051 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1052                                           enum nl80211_iftype opmode)
1053 {
1054         ah->mask_reg = AR_IMR_TXERR |
1055                 AR_IMR_TXURN |
1056                 AR_IMR_RXERR |
1057                 AR_IMR_RXORN |
1058                 AR_IMR_BCNMISC;
1059
1060         if (ah->config.intr_mitigation)
1061                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1062         else
1063                 ah->mask_reg |= AR_IMR_RXOK;
1064
1065         ah->mask_reg |= AR_IMR_TXOK;
1066
1067         if (opmode == NL80211_IFTYPE_AP)
1068                 ah->mask_reg |= AR_IMR_MIB;
1069
1070         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1071         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1072
1073         if (!AR_SREV_9100(ah)) {
1074                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1075                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1076                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1077         }
1078 }
1079
1080 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1081 {
1082         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1083                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1084                 ah->acktimeout = (u32) -1;
1085                 return false;
1086         } else {
1087                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1088                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1089                 ah->acktimeout = us;
1090                 return true;
1091         }
1092 }
1093
1094 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1095 {
1096         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1097                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1098                 ah->ctstimeout = (u32) -1;
1099                 return false;
1100         } else {
1101                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1102                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1103                 ah->ctstimeout = us;
1104                 return true;
1105         }
1106 }
1107
1108 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1109 {
1110         if (tu > 0xFFFF) {
1111                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1112                         "bad global tx timeout %u\n", tu);
1113                 ah->globaltxtimeout = (u32) -1;
1114                 return false;
1115         } else {
1116                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1117                 ah->globaltxtimeout = tu;
1118                 return true;
1119         }
1120 }
1121
1122 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1123 {
1124         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1125                 ah->misc_mode);
1126
1127         if (ah->misc_mode != 0)
1128                 REG_WRITE(ah, AR_PCU_MISC,
1129                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1130         if (ah->slottime != (u32) -1)
1131                 ath9k_hw_setslottime(ah, ah->slottime);
1132         if (ah->acktimeout != (u32) -1)
1133                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1134         if (ah->ctstimeout != (u32) -1)
1135                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1136         if (ah->globaltxtimeout != (u32) -1)
1137                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1138 }
1139
1140 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1141 {
1142         return vendorid == ATHEROS_VENDOR_ID ?
1143                 ath9k_hw_devname(devid) : NULL;
1144 }
1145
1146 void ath9k_hw_detach(struct ath_hw *ah)
1147 {
1148         if (!AR_SREV_9100(ah))
1149                 ath9k_hw_ani_detach(ah);
1150
1151         ath9k_hw_rfdetach(ah);
1152         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1153         kfree(ah);
1154 }
1155
1156 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1157 {
1158         struct ath_hw *ah = NULL;
1159
1160         switch (devid) {
1161         case AR5416_DEVID_PCI:
1162         case AR5416_DEVID_PCIE:
1163         case AR5416_AR9100_DEVID:
1164         case AR9160_DEVID_PCI:
1165         case AR9280_DEVID_PCI:
1166         case AR9280_DEVID_PCIE:
1167         case AR9285_DEVID_PCIE:
1168                 ah = ath9k_hw_do_attach(devid, sc, error);
1169                 break;
1170         default:
1171                 *error = -ENXIO;
1172                 break;
1173         }
1174
1175         return ah;
1176 }
1177
1178 /*******/
1179 /* INI */
1180 /*******/
1181
1182 static void ath9k_hw_override_ini(struct ath_hw *ah,
1183                                   struct ath9k_channel *chan)
1184 {
1185         /*
1186          * Set the RX_ABORT and RX_DIS and clear if off only after
1187          * RXE is set for MAC. This prevents frames with corrupted
1188          * descriptor status.
1189          */
1190         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1191
1192
1193         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1194             AR_SREV_9280_10_OR_LATER(ah))
1195                 return;
1196
1197         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1198 }
1199
1200 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1201                               struct ar5416_eeprom_def *pEepData,
1202                               u32 reg, u32 value)
1203 {
1204         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1205
1206         switch (ah->hw_version.devid) {
1207         case AR9280_DEVID_PCI:
1208                 if (reg == 0x7894) {
1209                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1210                                 "ini VAL: %x  EEPROM: %x\n", value,
1211                                 (pBase->version & 0xff));
1212
1213                         if ((pBase->version & 0xff) > 0x0a) {
1214                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1215                                         "PWDCLKIND: %d\n",
1216                                         pBase->pwdclkind);
1217                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1218                                 value |= AR_AN_TOP2_PWDCLKIND &
1219                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1220                         } else {
1221                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1222                                         "PWDCLKIND Earlier Rev\n");
1223                         }
1224
1225                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1226                                 "final ini VAL: %x\n", value);
1227                 }
1228                 break;
1229         }
1230
1231         return value;
1232 }
1233
1234 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1235                               struct ar5416_eeprom_def *pEepData,
1236                               u32 reg, u32 value)
1237 {
1238         if (ah->eep_map == EEP_MAP_4KBITS)
1239                 return value;
1240         else
1241                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1242 }
1243
1244 static void ath9k_olc_init(struct ath_hw *ah)
1245 {
1246         u32 i;
1247
1248         for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1249                 ah->originalGain[i] =
1250                         MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1251                                         AR_PHY_TX_GAIN);
1252         ah->PDADCdelta = 0;
1253 }
1254
1255 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1256                               struct ath9k_channel *chan)
1257 {
1258         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1259
1260         if (IS_CHAN_B(chan))
1261                 ctl |= CTL_11B;
1262         else if (IS_CHAN_G(chan))
1263                 ctl |= CTL_11G;
1264         else
1265                 ctl |= CTL_11A;
1266
1267         return ctl;
1268 }
1269
1270 static int ath9k_hw_process_ini(struct ath_hw *ah,
1271                                 struct ath9k_channel *chan,
1272                                 enum ath9k_ht_macmode macmode)
1273 {
1274         int i, regWrites = 0;
1275         struct ieee80211_channel *channel = chan->chan;
1276         u32 modesIndex, freqIndex;
1277         int status;
1278
1279         switch (chan->chanmode) {
1280         case CHANNEL_A:
1281         case CHANNEL_A_HT20:
1282                 modesIndex = 1;
1283                 freqIndex = 1;
1284                 break;
1285         case CHANNEL_A_HT40PLUS:
1286         case CHANNEL_A_HT40MINUS:
1287                 modesIndex = 2;
1288                 freqIndex = 1;
1289                 break;
1290         case CHANNEL_G:
1291         case CHANNEL_G_HT20:
1292         case CHANNEL_B:
1293                 modesIndex = 4;
1294                 freqIndex = 2;
1295                 break;
1296         case CHANNEL_G_HT40PLUS:
1297         case CHANNEL_G_HT40MINUS:
1298                 modesIndex = 3;
1299                 freqIndex = 2;
1300                 break;
1301
1302         default:
1303                 return -EINVAL;
1304         }
1305
1306         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1307         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1308         ah->eep_ops->set_addac(ah, chan);
1309
1310         if (AR_SREV_5416_22_OR_LATER(ah)) {
1311                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1312         } else {
1313                 struct ar5416IniArray temp;
1314                 u32 addacSize =
1315                         sizeof(u32) * ah->iniAddac.ia_rows *
1316                         ah->iniAddac.ia_columns;
1317
1318                 memcpy(ah->addac5416_21,
1319                        ah->iniAddac.ia_array, addacSize);
1320
1321                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1322
1323                 temp.ia_array = ah->addac5416_21;
1324                 temp.ia_columns = ah->iniAddac.ia_columns;
1325                 temp.ia_rows = ah->iniAddac.ia_rows;
1326                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1327         }
1328
1329         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1330
1331         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1332                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1333                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1334
1335                 REG_WRITE(ah, reg, val);
1336
1337                 if (reg >= 0x7800 && reg < 0x78a0
1338                     && ah->config.analog_shiftreg) {
1339                         udelay(100);
1340                 }
1341
1342                 DO_DELAY(regWrites);
1343         }
1344
1345         if (AR_SREV_9280(ah))
1346                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1347
1348         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah))
1349                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1350
1351         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1352                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1353                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1354
1355                 REG_WRITE(ah, reg, val);
1356
1357                 if (reg >= 0x7800 && reg < 0x78a0
1358                     && ah->config.analog_shiftreg) {
1359                         udelay(100);
1360                 }
1361
1362                 DO_DELAY(regWrites);
1363         }
1364
1365         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1366
1367         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1368                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1369                                 regWrites);
1370         }
1371
1372         ath9k_hw_override_ini(ah, chan);
1373         ath9k_hw_set_regs(ah, chan, macmode);
1374         ath9k_hw_init_chain_masks(ah);
1375
1376         if (OLC_FOR_AR9280_20_LATER)
1377                 ath9k_olc_init(ah);
1378
1379         status = ah->eep_ops->set_txpower(ah, chan,
1380                                   ath9k_regd_get_ctl(&ah->regulatory, chan),
1381                                   channel->max_antenna_gain * 2,
1382                                   channel->max_power * 2,
1383                                   min((u32) MAX_RATE_POWER,
1384                                       (u32) ah->regulatory.power_limit));
1385         if (status != 0) {
1386                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1387                         "Error initializing transmit power\n");
1388                 return -EIO;
1389         }
1390
1391         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1392                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1393                         "ar5416SetRfRegs failed\n");
1394                 return -EIO;
1395         }
1396
1397         return 0;
1398 }
1399
1400 /****************************************/
1401 /* Reset and Channel Switching Routines */
1402 /****************************************/
1403
1404 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1405 {
1406         u32 rfMode = 0;
1407
1408         if (chan == NULL)
1409                 return;
1410
1411         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1412                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1413
1414         if (!AR_SREV_9280_10_OR_LATER(ah))
1415                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1416                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1417
1418         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1419                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1420
1421         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1422 }
1423
1424 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1425 {
1426         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1427 }
1428
1429 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1430 {
1431         u32 regval;
1432
1433         regval = REG_READ(ah, AR_AHB_MODE);
1434         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1435
1436         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1437         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1438
1439         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1440
1441         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1442         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1443
1444         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1445
1446         if (AR_SREV_9285(ah)) {
1447                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1448                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1449         } else {
1450                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1451                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1452         }
1453 }
1454
1455 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1456 {
1457         u32 val;
1458
1459         val = REG_READ(ah, AR_STA_ID1);
1460         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1461         switch (opmode) {
1462         case NL80211_IFTYPE_AP:
1463                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1464                           | AR_STA_ID1_KSRCH_MODE);
1465                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1466                 break;
1467         case NL80211_IFTYPE_ADHOC:
1468         case NL80211_IFTYPE_MESH_POINT:
1469                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1470                           | AR_STA_ID1_KSRCH_MODE);
1471                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1472                 break;
1473         case NL80211_IFTYPE_STATION:
1474         case NL80211_IFTYPE_MONITOR:
1475                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1476                 break;
1477         }
1478 }
1479
1480 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1481                                                  u32 coef_scaled,
1482                                                  u32 *coef_mantissa,
1483                                                  u32 *coef_exponent)
1484 {
1485         u32 coef_exp, coef_man;
1486
1487         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1488                 if ((coef_scaled >> coef_exp) & 0x1)
1489                         break;
1490
1491         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1492
1493         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1494
1495         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1496         *coef_exponent = coef_exp - 16;
1497 }
1498
1499 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1500                                      struct ath9k_channel *chan)
1501 {
1502         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1503         u32 clockMhzScaled = 0x64000000;
1504         struct chan_centers centers;
1505
1506         if (IS_CHAN_HALF_RATE(chan))
1507                 clockMhzScaled = clockMhzScaled >> 1;
1508         else if (IS_CHAN_QUARTER_RATE(chan))
1509                 clockMhzScaled = clockMhzScaled >> 2;
1510
1511         ath9k_hw_get_channel_centers(ah, chan, &centers);
1512         coef_scaled = clockMhzScaled / centers.synth_center;
1513
1514         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1515                                       &ds_coef_exp);
1516
1517         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1518                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1519         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1520                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1521
1522         coef_scaled = (9 * coef_scaled) / 10;
1523
1524         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1525                                       &ds_coef_exp);
1526
1527         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1528                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1529         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1530                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1531 }
1532
1533 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1534 {
1535         u32 rst_flags;
1536         u32 tmpReg;
1537
1538         if (AR_SREV_9100(ah)) {
1539                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1540                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1541                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1542                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1543                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1544         }
1545
1546         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1547                   AR_RTC_FORCE_WAKE_ON_INT);
1548
1549         if (AR_SREV_9100(ah)) {
1550                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1551                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1552         } else {
1553                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1554                 if (tmpReg &
1555                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1556                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1557                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1558                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1559                 } else {
1560                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1561                 }
1562
1563                 rst_flags = AR_RTC_RC_MAC_WARM;
1564                 if (type == ATH9K_RESET_COLD)
1565                         rst_flags |= AR_RTC_RC_MAC_COLD;
1566         }
1567
1568         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1569         udelay(50);
1570
1571         REG_WRITE(ah, AR_RTC_RC, 0);
1572         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1573                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1574                         "RTC stuck in MAC reset\n");
1575                 return false;
1576         }
1577
1578         if (!AR_SREV_9100(ah))
1579                 REG_WRITE(ah, AR_RC, 0);
1580
1581         ath9k_hw_init_pll(ah, NULL);
1582
1583         if (AR_SREV_9100(ah))
1584                 udelay(50);
1585
1586         return true;
1587 }
1588
1589 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1590 {
1591         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1592                   AR_RTC_FORCE_WAKE_ON_INT);
1593
1594         REG_WRITE(ah, AR_RTC_RESET, 0);
1595         udelay(2);
1596         REG_WRITE(ah, AR_RTC_RESET, 1);
1597
1598         if (!ath9k_hw_wait(ah,
1599                            AR_RTC_STATUS,
1600                            AR_RTC_STATUS_M,
1601                            AR_RTC_STATUS_ON,
1602                            AH_WAIT_TIMEOUT)) {
1603                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1604                 return false;
1605         }
1606
1607         ath9k_hw_read_revisions(ah);
1608
1609         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1610 }
1611
1612 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1613 {
1614         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1615                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1616
1617         switch (type) {
1618         case ATH9K_RESET_POWER_ON:
1619                 return ath9k_hw_set_reset_power_on(ah);
1620                 break;
1621         case ATH9K_RESET_WARM:
1622         case ATH9K_RESET_COLD:
1623                 return ath9k_hw_set_reset(ah, type);
1624                 break;
1625         default:
1626                 return false;
1627         }
1628 }
1629
1630 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1631                               enum ath9k_ht_macmode macmode)
1632 {
1633         u32 phymode;
1634         u32 enableDacFifo = 0;
1635
1636         if (AR_SREV_9285_10_OR_LATER(ah))
1637                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1638                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1639
1640         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1641                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1642
1643         if (IS_CHAN_HT40(chan)) {
1644                 phymode |= AR_PHY_FC_DYN2040_EN;
1645
1646                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1647                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1648                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1649
1650                 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1651                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1652         }
1653         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1654
1655         ath9k_hw_set11nmac2040(ah, macmode);
1656
1657         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1658         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1659 }
1660
1661 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1662                                 struct ath9k_channel *chan)
1663 {
1664         if (OLC_FOR_AR9280_20_LATER) {
1665                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1666                         return false;
1667         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1668                 return false;
1669
1670         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1671                 return false;
1672
1673         ah->chip_fullsleep = false;
1674         ath9k_hw_init_pll(ah, chan);
1675         ath9k_hw_set_rfmode(ah, chan);
1676
1677         return true;
1678 }
1679
1680 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1681                                     struct ath9k_channel *chan,
1682                                     enum ath9k_ht_macmode macmode)
1683 {
1684         struct ieee80211_channel *channel = chan->chan;
1685         u32 synthDelay, qnum;
1686
1687         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1688                 if (ath9k_hw_numtxpending(ah, qnum)) {
1689                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1690                                 "Transmit frames pending on queue %d\n", qnum);
1691                         return false;
1692                 }
1693         }
1694
1695         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1696         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1697                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1698                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1699                         "Could not kill baseband RX\n");
1700                 return false;
1701         }
1702
1703         ath9k_hw_set_regs(ah, chan, macmode);
1704
1705         if (AR_SREV_9280_10_OR_LATER(ah)) {
1706                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1707                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1708                                 "Failed to set channel\n");
1709                         return false;
1710                 }
1711         } else {
1712                 if (!(ath9k_hw_set_channel(ah, chan))) {
1713                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1714                                 "Failed to set channel\n");
1715                         return false;
1716                 }
1717         }
1718
1719         if (ah->eep_ops->set_txpower(ah, chan,
1720                              ath9k_regd_get_ctl(&ah->regulatory, chan),
1721                              channel->max_antenna_gain * 2,
1722                              channel->max_power * 2,
1723                              min((u32) MAX_RATE_POWER,
1724                                  (u32) ah->regulatory.power_limit)) != 0) {
1725                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1726                         "Error initializing transmit power\n");
1727                 return false;
1728         }
1729
1730         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1731         if (IS_CHAN_B(chan))
1732                 synthDelay = (4 * synthDelay) / 22;
1733         else
1734                 synthDelay /= 10;
1735
1736         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1737
1738         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1739
1740         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1741                 ath9k_hw_set_delta_slope(ah, chan);
1742
1743         if (AR_SREV_9280_10_OR_LATER(ah))
1744                 ath9k_hw_9280_spur_mitigate(ah, chan);
1745         else
1746                 ath9k_hw_spur_mitigate(ah, chan);
1747
1748         if (!chan->oneTimeCalsDone)
1749                 chan->oneTimeCalsDone = true;
1750
1751         return true;
1752 }
1753
1754 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1755 {
1756         int bb_spur = AR_NO_SPUR;
1757         int freq;
1758         int bin, cur_bin;
1759         int bb_spur_off, spur_subchannel_sd;
1760         int spur_freq_sd;
1761         int spur_delta_phase;
1762         int denominator;
1763         int upper, lower, cur_vit_mask;
1764         int tmp, newVal;
1765         int i;
1766         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1767                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1768         };
1769         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1770                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1771         };
1772         int inc[4] = { 0, 100, 0, 0 };
1773         struct chan_centers centers;
1774
1775         int8_t mask_m[123];
1776         int8_t mask_p[123];
1777         int8_t mask_amt;
1778         int tmp_mask;
1779         int cur_bb_spur;
1780         bool is2GHz = IS_CHAN_2GHZ(chan);
1781
1782         memset(&mask_m, 0, sizeof(int8_t) * 123);
1783         memset(&mask_p, 0, sizeof(int8_t) * 123);
1784
1785         ath9k_hw_get_channel_centers(ah, chan, &centers);
1786         freq = centers.synth_center;
1787
1788         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1789         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1790                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1791
1792                 if (is2GHz)
1793                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1794                 else
1795                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1796
1797                 if (AR_NO_SPUR == cur_bb_spur)
1798                         break;
1799                 cur_bb_spur = cur_bb_spur - freq;
1800
1801                 if (IS_CHAN_HT40(chan)) {
1802                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1803                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1804                                 bb_spur = cur_bb_spur;
1805                                 break;
1806                         }
1807                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1808                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1809                         bb_spur = cur_bb_spur;
1810                         break;
1811                 }
1812         }
1813
1814         if (AR_NO_SPUR == bb_spur) {
1815                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1816                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1817                 return;
1818         } else {
1819                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1820                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1821         }
1822
1823         bin = bb_spur * 320;
1824
1825         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1826
1827         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1828                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1829                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1830                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1831         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1832
1833         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1834                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1835                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1836                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1837                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1838         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1839
1840         if (IS_CHAN_HT40(chan)) {
1841                 if (bb_spur < 0) {
1842                         spur_subchannel_sd = 1;
1843                         bb_spur_off = bb_spur + 10;
1844                 } else {
1845                         spur_subchannel_sd = 0;
1846                         bb_spur_off = bb_spur - 10;
1847                 }
1848         } else {
1849                 spur_subchannel_sd = 0;
1850                 bb_spur_off = bb_spur;
1851         }
1852
1853         if (IS_CHAN_HT40(chan))
1854                 spur_delta_phase =
1855                         ((bb_spur * 262144) /
1856                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1857         else
1858                 spur_delta_phase =
1859                         ((bb_spur * 524288) /
1860                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1861
1862         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1863         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1864
1865         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1866                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1867                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1868         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1869
1870         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1871         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1872
1873         cur_bin = -6000;
1874         upper = bin + 100;
1875         lower = bin - 100;
1876
1877         for (i = 0; i < 4; i++) {
1878                 int pilot_mask = 0;
1879                 int chan_mask = 0;
1880                 int bp = 0;
1881                 for (bp = 0; bp < 30; bp++) {
1882                         if ((cur_bin > lower) && (cur_bin < upper)) {
1883                                 pilot_mask = pilot_mask | 0x1 << bp;
1884                                 chan_mask = chan_mask | 0x1 << bp;
1885                         }
1886                         cur_bin += 100;
1887                 }
1888                 cur_bin += inc[i];
1889                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1890                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1891         }
1892
1893         cur_vit_mask = 6100;
1894         upper = bin + 120;
1895         lower = bin - 120;
1896
1897         for (i = 0; i < 123; i++) {
1898                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1899
1900                         /* workaround for gcc bug #37014 */
1901                         volatile int tmp_v = abs(cur_vit_mask - bin);
1902
1903                         if (tmp_v < 75)
1904                                 mask_amt = 1;
1905                         else
1906                                 mask_amt = 0;
1907                         if (cur_vit_mask < 0)
1908                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1909                         else
1910                                 mask_p[cur_vit_mask / 100] = mask_amt;
1911                 }
1912                 cur_vit_mask -= 100;
1913         }
1914
1915         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1916                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1917                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1918                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1919                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1920                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1921                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1922                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1923         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1924         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1925
1926         tmp_mask = (mask_m[31] << 28)
1927                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1928                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1929                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1930                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1931                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1932                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1933                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1934         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1935         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1936
1937         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1938                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1939                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1940                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1941                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1942                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1943                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1944                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1945         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1946         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1947
1948         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1949                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1950                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1951                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1952                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1953                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1954                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1955                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1956         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1957         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1958
1959         tmp_mask = (mask_p[15] << 28)
1960                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1961                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1962                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1963                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1964                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1965                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1966                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1967         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1968         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1969
1970         tmp_mask = (mask_p[30] << 28)
1971                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1972                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1973                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1974                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1975                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1976                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1977                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1978         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1979         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1980
1981         tmp_mask = (mask_p[45] << 28)
1982                 | (mask_p[44] << 26) | (mask_p[43] << 24)
1983                 | (mask_p[42] << 22) | (mask_p[41] << 20)
1984                 | (mask_p[40] << 18) | (mask_p[39] << 16)
1985                 | (mask_p[38] << 14) | (mask_p[37] << 12)
1986                 | (mask_p[36] << 10) | (mask_p[35] << 8)
1987                 | (mask_p[34] << 6) | (mask_p[33] << 4)
1988                 | (mask_p[32] << 2) | (mask_p[31] << 0);
1989         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1990         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1991
1992         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1993                 | (mask_p[59] << 26) | (mask_p[58] << 24)
1994                 | (mask_p[57] << 22) | (mask_p[56] << 20)
1995                 | (mask_p[55] << 18) | (mask_p[54] << 16)
1996                 | (mask_p[53] << 14) | (mask_p[52] << 12)
1997                 | (mask_p[51] << 10) | (mask_p[50] << 8)
1998                 | (mask_p[49] << 6) | (mask_p[48] << 4)
1999                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2000         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2001         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2002 }
2003
2004 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2005 {
2006         int bb_spur = AR_NO_SPUR;
2007         int bin, cur_bin;
2008         int spur_freq_sd;
2009         int spur_delta_phase;
2010         int denominator;
2011         int upper, lower, cur_vit_mask;
2012         int tmp, new;
2013         int i;
2014         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2015                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2016         };
2017         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2018                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2019         };
2020         int inc[4] = { 0, 100, 0, 0 };
2021
2022         int8_t mask_m[123];
2023         int8_t mask_p[123];
2024         int8_t mask_amt;
2025         int tmp_mask;
2026         int cur_bb_spur;
2027         bool is2GHz = IS_CHAN_2GHZ(chan);
2028
2029         memset(&mask_m, 0, sizeof(int8_t) * 123);
2030         memset(&mask_p, 0, sizeof(int8_t) * 123);
2031
2032         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2033                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2034                 if (AR_NO_SPUR == cur_bb_spur)
2035                         break;
2036                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2037                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2038                         bb_spur = cur_bb_spur;
2039                         break;
2040                 }
2041         }
2042
2043         if (AR_NO_SPUR == bb_spur)
2044                 return;
2045
2046         bin = bb_spur * 32;
2047
2048         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2049         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2050                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2051                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2052                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2053
2054         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2055
2056         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2057                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2058                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2059                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2060                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2061         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2062
2063         spur_delta_phase = ((bb_spur * 524288) / 100) &
2064                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2065
2066         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2067         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2068
2069         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2070                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2071                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2072         REG_WRITE(ah, AR_PHY_TIMING11, new);
2073
2074         cur_bin = -6000;
2075         upper = bin + 100;
2076         lower = bin - 100;
2077
2078         for (i = 0; i < 4; i++) {
2079                 int pilot_mask = 0;
2080                 int chan_mask = 0;
2081                 int bp = 0;
2082                 for (bp = 0; bp < 30; bp++) {
2083                         if ((cur_bin > lower) && (cur_bin < upper)) {
2084                                 pilot_mask = pilot_mask | 0x1 << bp;
2085                                 chan_mask = chan_mask | 0x1 << bp;
2086                         }
2087                         cur_bin += 100;
2088                 }
2089                 cur_bin += inc[i];
2090                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2091                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2092         }
2093
2094         cur_vit_mask = 6100;
2095         upper = bin + 120;
2096         lower = bin - 120;
2097
2098         for (i = 0; i < 123; i++) {
2099                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2100
2101                         /* workaround for gcc bug #37014 */
2102                         volatile int tmp_v = abs(cur_vit_mask - bin);
2103
2104                         if (tmp_v < 75)
2105                                 mask_amt = 1;
2106                         else
2107                                 mask_amt = 0;
2108                         if (cur_vit_mask < 0)
2109                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2110                         else
2111                                 mask_p[cur_vit_mask / 100] = mask_amt;
2112                 }
2113                 cur_vit_mask -= 100;
2114         }
2115
2116         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2117                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2118                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2119                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2120                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2121                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2122                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2123                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2124         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2125         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2126
2127         tmp_mask = (mask_m[31] << 28)
2128                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2129                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2130                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2131                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2132                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2133                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2134                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2135         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2136         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2137
2138         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2139                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2140                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2141                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2142                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2143                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2144                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2145                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2146         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2147         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2148
2149         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2150                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2151                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2152                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2153                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2154                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2155                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2156                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2157         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2158         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2159
2160         tmp_mask = (mask_p[15] << 28)
2161                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2162                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2163                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2164                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2165                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2166                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2167                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2168         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2169         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2170
2171         tmp_mask = (mask_p[30] << 28)
2172                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2173                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2174                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2175                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2176                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2177                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2178                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2179         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2180         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2181
2182         tmp_mask = (mask_p[45] << 28)
2183                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2184                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2185                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2186                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2187                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2188                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2189                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2190         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2191         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2192
2193         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2194                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2195                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2196                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2197                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2198                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2199                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2200                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2201         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2202         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2203 }
2204
2205 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2206                     bool bChannelChange)
2207 {
2208         u32 saveLedState;
2209         struct ath_softc *sc = ah->ah_sc;
2210         struct ath9k_channel *curchan = ah->curchan;
2211         u32 saveDefAntenna;
2212         u32 macStaId1;
2213         int i, rx_chainmask, r;
2214
2215         ah->extprotspacing = sc->ht_extprotspacing;
2216         ah->txchainmask = sc->tx_chainmask;
2217         ah->rxchainmask = sc->rx_chainmask;
2218
2219         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2220                 return -EIO;
2221
2222         if (curchan)
2223                 ath9k_hw_getnf(ah, curchan);
2224
2225         if (bChannelChange &&
2226             (ah->chip_fullsleep != true) &&
2227             (ah->curchan != NULL) &&
2228             (chan->channel != ah->curchan->channel) &&
2229             ((chan->channelFlags & CHANNEL_ALL) ==
2230              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2231             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2232                                    !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2233
2234                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2235                         ath9k_hw_loadnf(ah, ah->curchan);
2236                         ath9k_hw_start_nfcal(ah);
2237                         return 0;
2238                 }
2239         }
2240
2241         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2242         if (saveDefAntenna == 0)
2243                 saveDefAntenna = 1;
2244
2245         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2246
2247         saveLedState = REG_READ(ah, AR_CFG_LED) &
2248                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2249                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2250
2251         ath9k_hw_mark_phy_inactive(ah);
2252
2253         if (!ath9k_hw_chip_reset(ah, chan)) {
2254                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2255                 return -EINVAL;
2256         }
2257
2258         if (AR_SREV_9280_10_OR_LATER(ah))
2259                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2260
2261         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2262         if (r)
2263                 return r;
2264
2265         /* Setup MFP options for CCMP */
2266         if (AR_SREV_9280_20_OR_LATER(ah)) {
2267                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2268                  * frames when constructing CCMP AAD. */
2269                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2270                               0xc7ff);
2271                 ah->sw_mgmt_crypto = false;
2272         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2273                 /* Disable hardware crypto for management frames */
2274                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2275                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2276                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2277                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2278                 ah->sw_mgmt_crypto = true;
2279         } else
2280                 ah->sw_mgmt_crypto = true;
2281
2282         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2283                 ath9k_hw_set_delta_slope(ah, chan);
2284
2285         if (AR_SREV_9280_10_OR_LATER(ah))
2286                 ath9k_hw_9280_spur_mitigate(ah, chan);
2287         else
2288                 ath9k_hw_spur_mitigate(ah, chan);
2289
2290         ah->eep_ops->set_board_values(ah, chan);
2291
2292         ath9k_hw_decrease_chain_power(ah, chan);
2293
2294         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2295         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2296                   | macStaId1
2297                   | AR_STA_ID1_RTS_USE_DEF
2298                   | (ah->config.
2299                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2300                   | ah->sta_id1_defaults);
2301         ath9k_hw_set_operating_mode(ah, ah->opmode);
2302
2303         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2304         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2305
2306         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2307
2308         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2309         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2310                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2311
2312         REG_WRITE(ah, AR_ISR, ~0);
2313
2314         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2315
2316         if (AR_SREV_9280_10_OR_LATER(ah)) {
2317                 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2318                         return -EIO;
2319         } else {
2320                 if (!(ath9k_hw_set_channel(ah, chan)))
2321                         return -EIO;
2322         }
2323
2324         for (i = 0; i < AR_NUM_DCU; i++)
2325                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2326
2327         ah->intr_txqs = 0;
2328         for (i = 0; i < ah->caps.total_queues; i++)
2329                 ath9k_hw_resettxqueue(ah, i);
2330
2331         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2332         ath9k_hw_init_qos(ah);
2333
2334 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2335         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2336                 ath9k_enable_rfkill(ah);
2337 #endif
2338         ath9k_hw_init_user_settings(ah);
2339
2340         REG_WRITE(ah, AR_STA_ID1,
2341                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2342
2343         ath9k_hw_set_dma(ah);
2344
2345         REG_WRITE(ah, AR_OBS, 8);
2346
2347         if (ah->config.intr_mitigation) {
2348                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2349                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2350         }
2351
2352         ath9k_hw_init_bb(ah, chan);
2353
2354         if (!ath9k_hw_init_cal(ah, chan))
2355                 return -EIO;;
2356
2357         rx_chainmask = ah->rxchainmask;
2358         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2359                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2360                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2361         }
2362
2363         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2364
2365         if (AR_SREV_9100(ah)) {
2366                 u32 mask;
2367                 mask = REG_READ(ah, AR_CFG);
2368                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2369                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2370                                 "CFG Byte Swap Set 0x%x\n", mask);
2371                 } else {
2372                         mask =
2373                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2374                         REG_WRITE(ah, AR_CFG, mask);
2375                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2376                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2377                 }
2378         } else {
2379 #ifdef __BIG_ENDIAN
2380                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2381 #endif
2382         }
2383
2384         return 0;
2385 }
2386
2387 /************************/
2388 /* Key Cache Management */
2389 /************************/
2390
2391 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2392 {
2393         u32 keyType;
2394
2395         if (entry >= ah->caps.keycache_size) {
2396                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2397                         "keychache entry %u out of range\n", entry);
2398                 return false;
2399         }
2400
2401         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2402
2403         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2404         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2405         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2406         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2407         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2408         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2409         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2410         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2411
2412         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2413                 u16 micentry = entry + 64;
2414
2415                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2416                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2417                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2418                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2419
2420         }
2421
2422         if (ah->curchan == NULL)
2423                 return true;
2424
2425         return true;
2426 }
2427
2428 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2429 {
2430         u32 macHi, macLo;
2431
2432         if (entry >= ah->caps.keycache_size) {
2433                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2434                         "keychache entry %u out of range\n", entry);
2435                 return false;
2436         }
2437
2438         if (mac != NULL) {
2439                 macHi = (mac[5] << 8) | mac[4];
2440                 macLo = (mac[3] << 24) |
2441                         (mac[2] << 16) |
2442                         (mac[1] << 8) |
2443                         mac[0];
2444                 macLo >>= 1;
2445                 macLo |= (macHi & 1) << 31;
2446                 macHi >>= 1;
2447         } else {
2448                 macLo = macHi = 0;
2449         }
2450         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2451         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2452
2453         return true;
2454 }
2455
2456 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2457                                  const struct ath9k_keyval *k,
2458                                  const u8 *mac)
2459 {
2460         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2461         u32 key0, key1, key2, key3, key4;
2462         u32 keyType;
2463
2464         if (entry >= pCap->keycache_size) {
2465                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2466                         "keycache entry %u out of range\n", entry);
2467                 return false;
2468         }
2469
2470         switch (k->kv_type) {
2471         case ATH9K_CIPHER_AES_OCB:
2472                 keyType = AR_KEYTABLE_TYPE_AES;
2473                 break;
2474         case ATH9K_CIPHER_AES_CCM:
2475                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2476                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2477                                 "AES-CCM not supported by mac rev 0x%x\n",
2478                                 ah->hw_version.macRev);
2479                         return false;
2480                 }
2481                 keyType = AR_KEYTABLE_TYPE_CCM;
2482                 break;
2483         case ATH9K_CIPHER_TKIP:
2484                 keyType = AR_KEYTABLE_TYPE_TKIP;
2485                 if (ATH9K_IS_MIC_ENABLED(ah)
2486                     && entry + 64 >= pCap->keycache_size) {
2487                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2488                                 "entry %u inappropriate for TKIP\n", entry);
2489                         return false;
2490                 }
2491                 break;
2492         case ATH9K_CIPHER_WEP:
2493                 if (k->kv_len < LEN_WEP40) {
2494                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2495                                 "WEP key length %u too small\n", k->kv_len);
2496                         return false;
2497                 }
2498                 if (k->kv_len <= LEN_WEP40)
2499                         keyType = AR_KEYTABLE_TYPE_40;
2500                 else if (k->kv_len <= LEN_WEP104)
2501                         keyType = AR_KEYTABLE_TYPE_104;
2502                 else
2503                         keyType = AR_KEYTABLE_TYPE_128;
2504                 break;
2505         case ATH9K_CIPHER_CLR:
2506                 keyType = AR_KEYTABLE_TYPE_CLR;
2507                 break;
2508         default:
2509                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2510                         "cipher %u not supported\n", k->kv_type);
2511                 return false;
2512         }
2513
2514         key0 = get_unaligned_le32(k->kv_val + 0);
2515         key1 = get_unaligned_le16(k->kv_val + 4);
2516         key2 = get_unaligned_le32(k->kv_val + 6);
2517         key3 = get_unaligned_le16(k->kv_val + 10);
2518         key4 = get_unaligned_le32(k->kv_val + 12);
2519         if (k->kv_len <= LEN_WEP104)
2520                 key4 &= 0xff;
2521
2522         /*
2523          * Note: Key cache registers access special memory area that requires
2524          * two 32-bit writes to actually update the values in the internal
2525          * memory. Consequently, the exact order and pairs used here must be
2526          * maintained.
2527          */
2528
2529         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2530                 u16 micentry = entry + 64;
2531
2532                 /*
2533                  * Write inverted key[47:0] first to avoid Michael MIC errors
2534                  * on frames that could be sent or received at the same time.
2535                  * The correct key will be written in the end once everything
2536                  * else is ready.
2537                  */
2538                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2539                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2540
2541                 /* Write key[95:48] */
2542                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2543                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2544
2545                 /* Write key[127:96] and key type */
2546                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2547                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2548
2549                 /* Write MAC address for the entry */
2550                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2551
2552                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2553                         /*
2554                          * TKIP uses two key cache entries:
2555                          * Michael MIC TX/RX keys in the same key cache entry
2556                          * (idx = main index + 64):
2557                          * key0 [31:0] = RX key [31:0]
2558                          * key1 [15:0] = TX key [31:16]
2559                          * key1 [31:16] = reserved
2560                          * key2 [31:0] = RX key [63:32]
2561                          * key3 [15:0] = TX key [15:0]
2562                          * key3 [31:16] = reserved
2563                          * key4 [31:0] = TX key [63:32]
2564                          */
2565                         u32 mic0, mic1, mic2, mic3, mic4;
2566
2567                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2568                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2569                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2570                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2571                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2572
2573                         /* Write RX[31:0] and TX[31:16] */
2574                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2575                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2576
2577                         /* Write RX[63:32] and TX[15:0] */
2578                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2579                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2580
2581                         /* Write TX[63:32] and keyType(reserved) */
2582                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2583                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2584                                   AR_KEYTABLE_TYPE_CLR);
2585
2586                 } else {
2587                         /*
2588                          * TKIP uses four key cache entries (two for group
2589                          * keys):
2590                          * Michael MIC TX/RX keys are in different key cache
2591                          * entries (idx = main index + 64 for TX and
2592                          * main index + 32 + 96 for RX):
2593                          * key0 [31:0] = TX/RX MIC key [31:0]
2594                          * key1 [31:0] = reserved
2595                          * key2 [31:0] = TX/RX MIC key [63:32]
2596                          * key3 [31:0] = reserved
2597                          * key4 [31:0] = reserved
2598                          *
2599                          * Upper layer code will call this function separately
2600                          * for TX and RX keys when these registers offsets are
2601                          * used.
2602                          */
2603                         u32 mic0, mic2;
2604
2605                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2606                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2607
2608                         /* Write MIC key[31:0] */
2609                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2610                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2611
2612                         /* Write MIC key[63:32] */
2613                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2614                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2615
2616                         /* Write TX[63:32] and keyType(reserved) */
2617                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2618                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2619                                   AR_KEYTABLE_TYPE_CLR);
2620                 }
2621
2622                 /* MAC address registers are reserved for the MIC entry */
2623                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2624                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2625
2626                 /*
2627                  * Write the correct (un-inverted) key[47:0] last to enable
2628                  * TKIP now that all other registers are set with correct
2629                  * values.
2630                  */
2631                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2632                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2633         } else {
2634                 /* Write key[47:0] */
2635                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2636                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2637
2638                 /* Write key[95:48] */
2639                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2640                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2641
2642                 /* Write key[127:96] and key type */
2643                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2644                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2645
2646                 /* Write MAC address for the entry */
2647                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2648         }
2649
2650         return true;
2651 }
2652
2653 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2654 {
2655         if (entry < ah->caps.keycache_size) {
2656                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2657                 if (val & AR_KEYTABLE_VALID)
2658                         return true;
2659         }
2660         return false;
2661 }
2662
2663 /******************************/
2664 /* Power Management (Chipset) */
2665 /******************************/
2666
2667 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2668 {
2669         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2670         if (setChip) {
2671                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2672                             AR_RTC_FORCE_WAKE_EN);
2673                 if (!AR_SREV_9100(ah))
2674                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2675
2676                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2677                             AR_RTC_RESET_EN);
2678         }
2679 }
2680
2681 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2682 {
2683         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2684         if (setChip) {
2685                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2686
2687                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2688                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2689                                   AR_RTC_FORCE_WAKE_ON_INT);
2690                 } else {
2691                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2692                                     AR_RTC_FORCE_WAKE_EN);
2693                 }
2694         }
2695 }
2696
2697 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2698 {
2699         u32 val;
2700         int i;
2701
2702         if (setChip) {
2703                 if ((REG_READ(ah, AR_RTC_STATUS) &
2704                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2705                         if (ath9k_hw_set_reset_reg(ah,
2706                                            ATH9K_RESET_POWER_ON) != true) {
2707                                 return false;
2708                         }
2709                 }
2710                 if (AR_SREV_9100(ah))
2711                         REG_SET_BIT(ah, AR_RTC_RESET,
2712                                     AR_RTC_RESET_EN);
2713
2714                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2715                             AR_RTC_FORCE_WAKE_EN);
2716                 udelay(50);
2717
2718                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2719                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2720                         if (val == AR_RTC_STATUS_ON)
2721                                 break;
2722                         udelay(50);
2723                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2724                                     AR_RTC_FORCE_WAKE_EN);
2725                 }
2726                 if (i == 0) {
2727                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2728                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2729                         return false;
2730                 }
2731         }
2732
2733         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2734
2735         return true;
2736 }
2737
2738 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2739 {
2740         int status = true, setChip = true;
2741         static const char *modes[] = {
2742                 "AWAKE",
2743                 "FULL-SLEEP",
2744                 "NETWORK SLEEP",
2745                 "UNDEFINED"
2746         };
2747
2748         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2749                 modes[ah->power_mode], modes[mode]);
2750
2751         switch (mode) {
2752         case ATH9K_PM_AWAKE:
2753                 status = ath9k_hw_set_power_awake(ah, setChip);
2754                 break;
2755         case ATH9K_PM_FULL_SLEEP:
2756                 ath9k_set_power_sleep(ah, setChip);
2757                 ah->chip_fullsleep = true;
2758                 break;
2759         case ATH9K_PM_NETWORK_SLEEP:
2760                 ath9k_set_power_network_sleep(ah, setChip);
2761                 break;
2762         default:
2763                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2764                         "Unknown power mode %u\n", mode);
2765                 return false;
2766         }
2767         ah->power_mode = mode;
2768
2769         return status;
2770 }
2771
2772 /*
2773  * Helper for ASPM support.
2774  *
2775  * Disable PLL when in L0s as well as receiver clock when in L1.
2776  * This power saving option must be enabled through the SerDes.
2777  *
2778  * Programming the SerDes must go through the same 288 bit serial shift
2779  * register as the other analog registers.  Hence the 9 writes.
2780  */
2781 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2782 {
2783         u8 i;
2784
2785         if (ah->is_pciexpress != true)
2786                 return;
2787
2788         /* Do not touch SerDes registers */
2789         if (ah->config.pcie_powersave_enable == 2)
2790                 return;
2791
2792         /* Nothing to do on restore for 11N */
2793         if (restore)
2794                 return;
2795
2796         if (AR_SREV_9280_20_OR_LATER(ah)) {
2797                 /*
2798                  * AR9280 2.0 or later chips use SerDes values from the
2799                  * initvals.h initialized depending on chipset during
2800                  * ath9k_hw_do_attach()
2801                  */
2802                 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2803                         REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2804                                   INI_RA(&ah->iniPcieSerdes, i, 1));
2805                 }
2806         } else if (AR_SREV_9280(ah) &&
2807                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2808                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2809                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2810
2811                 /* RX shut off when elecidle is asserted */
2812                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2813                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2814                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2815
2816                 /* Shut off CLKREQ active in L1 */
2817                 if (ah->config.pcie_clock_req)
2818                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2819                 else
2820                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2821
2822                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2823                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2824                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2825
2826                 /* Load the new settings */
2827                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2828
2829         } else {
2830                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2831                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2832
2833                 /* RX shut off when elecidle is asserted */
2834                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2835                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2836                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2837
2838                 /*
2839                  * Ignore ah->ah_config.pcie_clock_req setting for
2840                  * pre-AR9280 11n
2841                  */
2842                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2843
2844                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2845                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2846                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2847
2848                 /* Load the new settings */
2849                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2850         }
2851
2852         udelay(1000);
2853
2854         /* set bit 19 to allow forcing of pcie core into L1 state */
2855         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2856
2857         /* Several PCIe massages to ensure proper behaviour */
2858         if (ah->config.pcie_waen) {
2859                 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2860         } else {
2861                 if (AR_SREV_9285(ah))
2862                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2863                 /*
2864                  * On AR9280 chips bit 22 of 0x4004 needs to be set to
2865                  * otherwise card may disappear.
2866                  */
2867                 else if (AR_SREV_9280(ah))
2868                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2869                 else
2870                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2871         }
2872 }
2873
2874 /**********************/
2875 /* Interrupt Handling */
2876 /**********************/
2877
2878 bool ath9k_hw_intrpend(struct ath_hw *ah)
2879 {
2880         u32 host_isr;
2881
2882         if (AR_SREV_9100(ah))
2883                 return true;
2884
2885         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2886         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2887                 return true;
2888
2889         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2890         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2891             && (host_isr != AR_INTR_SPURIOUS))
2892                 return true;
2893
2894         return false;
2895 }
2896
2897 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2898 {
2899         u32 isr = 0;
2900         u32 mask2 = 0;
2901         struct ath9k_hw_capabilities *pCap = &ah->caps;
2902         u32 sync_cause = 0;
2903         bool fatal_int = false;
2904
2905         if (!AR_SREV_9100(ah)) {
2906                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2907                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2908                             == AR_RTC_STATUS_ON) {
2909                                 isr = REG_READ(ah, AR_ISR);
2910                         }
2911                 }
2912
2913                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2914                         AR_INTR_SYNC_DEFAULT;
2915
2916                 *masked = 0;
2917
2918                 if (!isr && !sync_cause)
2919                         return false;
2920         } else {
2921                 *masked = 0;
2922                 isr = REG_READ(ah, AR_ISR);
2923         }
2924
2925         if (isr) {
2926                 if (isr & AR_ISR_BCNMISC) {
2927                         u32 isr2;
2928                         isr2 = REG_READ(ah, AR_ISR_S2);
2929                         if (isr2 & AR_ISR_S2_TIM)
2930                                 mask2 |= ATH9K_INT_TIM;
2931                         if (isr2 & AR_ISR_S2_DTIM)
2932                                 mask2 |= ATH9K_INT_DTIM;
2933                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2934                                 mask2 |= ATH9K_INT_DTIMSYNC;
2935                         if (isr2 & (AR_ISR_S2_CABEND))
2936                                 mask2 |= ATH9K_INT_CABEND;
2937                         if (isr2 & AR_ISR_S2_GTT)
2938                                 mask2 |= ATH9K_INT_GTT;
2939                         if (isr2 & AR_ISR_S2_CST)
2940                                 mask2 |= ATH9K_INT_CST;
2941                         if (isr2 & AR_ISR_S2_TSFOOR)
2942                                 mask2 |= ATH9K_INT_TSFOOR;
2943                 }
2944
2945                 isr = REG_READ(ah, AR_ISR_RAC);
2946                 if (isr == 0xffffffff) {
2947                         *masked = 0;
2948                         return false;
2949                 }
2950
2951                 *masked = isr & ATH9K_INT_COMMON;
2952
2953                 if (ah->config.intr_mitigation) {
2954                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2955                                 *masked |= ATH9K_INT_RX;
2956                 }
2957
2958                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2959                         *masked |= ATH9K_INT_RX;
2960                 if (isr &
2961                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2962                      AR_ISR_TXEOL)) {
2963                         u32 s0_s, s1_s;
2964
2965                         *masked |= ATH9K_INT_TX;
2966
2967                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2968                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2969                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2970
2971                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2972                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2973                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2974                 }
2975
2976                 if (isr & AR_ISR_RXORN) {
2977                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2978                                 "receive FIFO overrun interrupt\n");
2979                 }
2980
2981                 if (!AR_SREV_9100(ah)) {
2982                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2983                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2984                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2985                                         *masked |= ATH9K_INT_TIM_TIMER;
2986                         }
2987                 }
2988
2989                 *masked |= mask2;
2990         }
2991
2992         if (AR_SREV_9100(ah))
2993                 return true;
2994
2995         if (sync_cause) {
2996                 fatal_int =
2997                         (sync_cause &
2998                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2999                         ? true : false;
3000
3001                 if (fatal_int) {
3002                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3003                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3004                                         "received PCI FATAL interrupt\n");
3005                         }
3006                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3007                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3008                                         "received PCI PERR interrupt\n");
3009                         }
3010                         *masked |= ATH9K_INT_FATAL;
3011                 }
3012                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3013                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3014                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3015                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3016                         REG_WRITE(ah, AR_RC, 0);
3017                         *masked |= ATH9K_INT_FATAL;
3018                 }
3019                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3020                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3021                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3022                 }
3023
3024                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3025                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3026         }
3027
3028         return true;
3029 }
3030
3031 enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
3032 {
3033         return ah->mask_reg;
3034 }
3035
3036 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3037 {
3038         u32 omask = ah->mask_reg;
3039         u32 mask, mask2;
3040         struct ath9k_hw_capabilities *pCap = &ah->caps;
3041
3042         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3043
3044         if (omask & ATH9K_INT_GLOBAL) {
3045                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3046                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3047                 (void) REG_READ(ah, AR_IER);
3048                 if (!AR_SREV_9100(ah)) {
3049                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3050                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3051
3052                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3053                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3054                 }
3055         }
3056
3057         mask = ints & ATH9K_INT_COMMON;
3058         mask2 = 0;
3059
3060         if (ints & ATH9K_INT_TX) {
3061                 if (ah->txok_interrupt_mask)
3062                         mask |= AR_IMR_TXOK;
3063                 if (ah->txdesc_interrupt_mask)
3064                         mask |= AR_IMR_TXDESC;
3065                 if (ah->txerr_interrupt_mask)
3066                         mask |= AR_IMR_TXERR;
3067                 if (ah->txeol_interrupt_mask)
3068                         mask |= AR_IMR_TXEOL;
3069         }
3070         if (ints & ATH9K_INT_RX) {
3071                 mask |= AR_IMR_RXERR;
3072                 if (ah->config.intr_mitigation)
3073                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3074                 else
3075                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3076                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3077                         mask |= AR_IMR_GENTMR;
3078         }
3079
3080         if (ints & (ATH9K_INT_BMISC)) {
3081                 mask |= AR_IMR_BCNMISC;
3082                 if (ints & ATH9K_INT_TIM)
3083                         mask2 |= AR_IMR_S2_TIM;
3084                 if (ints & ATH9K_INT_DTIM)
3085                         mask2 |= AR_IMR_S2_DTIM;
3086                 if (ints & ATH9K_INT_DTIMSYNC)
3087                         mask2 |= AR_IMR_S2_DTIMSYNC;
3088                 if (ints & ATH9K_INT_CABEND)
3089                         mask2 |= AR_IMR_S2_CABEND;
3090                 if (ints & ATH9K_INT_TSFOOR)
3091                         mask2 |= AR_IMR_S2_TSFOOR;
3092         }
3093
3094         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3095                 mask |= AR_IMR_BCNMISC;
3096                 if (ints & ATH9K_INT_GTT)
3097                         mask2 |= AR_IMR_S2_GTT;
3098                 if (ints & ATH9K_INT_CST)
3099                         mask2 |= AR_IMR_S2_CST;
3100         }
3101
3102         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3103         REG_WRITE(ah, AR_IMR, mask);
3104         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3105                                            AR_IMR_S2_DTIM |
3106                                            AR_IMR_S2_DTIMSYNC |
3107                                            AR_IMR_S2_CABEND |
3108                                            AR_IMR_S2_CABTO |
3109                                            AR_IMR_S2_TSFOOR |
3110                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3111         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3112         ah->mask_reg = ints;
3113
3114         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3115                 if (ints & ATH9K_INT_TIM_TIMER)
3116                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3117                 else
3118                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3119         }
3120
3121         if (ints & ATH9K_INT_GLOBAL) {
3122                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3123                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3124                 if (!AR_SREV_9100(ah)) {
3125                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3126                                   AR_INTR_MAC_IRQ);
3127                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3128
3129
3130                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3131                                   AR_INTR_SYNC_DEFAULT);
3132                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3133                                   AR_INTR_SYNC_DEFAULT);
3134                 }
3135                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3136                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3137         }
3138
3139         return omask;
3140 }
3141
3142 /*******************/
3143 /* Beacon Handling */
3144 /*******************/
3145
3146 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3147 {
3148         int flags = 0;
3149
3150         ah->beacon_interval = beacon_period;
3151
3152         switch (ah->opmode) {
3153         case NL80211_IFTYPE_STATION:
3154         case NL80211_IFTYPE_MONITOR:
3155                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3156                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3157                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3158                 flags |= AR_TBTT_TIMER_EN;
3159                 break;
3160         case NL80211_IFTYPE_ADHOC:
3161         case NL80211_IFTYPE_MESH_POINT:
3162                 REG_SET_BIT(ah, AR_TXCFG,
3163                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3164                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3165                           TU_TO_USEC(next_beacon +
3166                                      (ah->atim_window ? ah->
3167                                       atim_window : 1)));
3168                 flags |= AR_NDP_TIMER_EN;
3169         case NL80211_IFTYPE_AP:
3170                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3171                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3172                           TU_TO_USEC(next_beacon -
3173                                      ah->config.
3174                                      dma_beacon_response_time));
3175                 REG_WRITE(ah, AR_NEXT_SWBA,
3176                           TU_TO_USEC(next_beacon -
3177                                      ah->config.
3178                                      sw_beacon_response_time));
3179                 flags |=
3180                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3181                 break;
3182         default:
3183                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3184                         "%s: unsupported opmode: %d\n",
3185                         __func__, ah->opmode);
3186                 return;
3187                 break;
3188         }
3189
3190         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3191         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3192         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3193         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3194
3195         beacon_period &= ~ATH9K_BEACON_ENA;
3196         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3197                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3198                 ath9k_hw_reset_tsf(ah);
3199         }
3200
3201         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3202 }
3203
3204 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3205                                     const struct ath9k_beacon_state *bs)
3206 {
3207         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3208         struct ath9k_hw_capabilities *pCap = &ah->caps;
3209
3210         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3211
3212         REG_WRITE(ah, AR_BEACON_PERIOD,
3213                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3214         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3215                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3216
3217         REG_RMW_FIELD(ah, AR_RSSI_THR,
3218                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3219
3220         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3221
3222         if (bs->bs_sleepduration > beaconintval)
3223                 beaconintval = bs->bs_sleepduration;
3224
3225         dtimperiod = bs->bs_dtimperiod;
3226         if (bs->bs_sleepduration > dtimperiod)
3227                 dtimperiod = bs->bs_sleepduration;
3228
3229         if (beaconintval == dtimperiod)
3230                 nextTbtt = bs->bs_nextdtim;
3231         else
3232                 nextTbtt = bs->bs_nexttbtt;
3233
3234         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3235         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3236         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3237         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3238
3239         REG_WRITE(ah, AR_NEXT_DTIM,
3240                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3241         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3242
3243         REG_WRITE(ah, AR_SLEEP1,
3244                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3245                   | AR_SLEEP1_ASSUME_DTIM);
3246
3247         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3248                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3249         else
3250                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3251
3252         REG_WRITE(ah, AR_SLEEP2,
3253                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3254
3255         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3256         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3257
3258         REG_SET_BIT(ah, AR_TIMER_MODE,
3259                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3260                     AR_DTIM_TIMER_EN);
3261
3262         /* TSF Out of Range Threshold */
3263         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3264 }
3265
3266 /*******************/
3267 /* HW Capabilities */
3268 /*******************/
3269
3270 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3271 {
3272         struct ath9k_hw_capabilities *pCap = &ah->caps;
3273         u16 capField = 0, eeval;
3274
3275         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3276         ah->regulatory.current_rd = eeval;
3277
3278         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3279         if (AR_SREV_9285_10_OR_LATER(ah))
3280                 eeval |= AR9285_RDEXT_DEFAULT;
3281         ah->regulatory.current_rd_ext = eeval;
3282
3283         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3284
3285         if (ah->opmode != NL80211_IFTYPE_AP &&
3286             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3287                 if (ah->regulatory.current_rd == 0x64 ||
3288                     ah->regulatory.current_rd == 0x65)
3289                         ah->regulatory.current_rd += 5;
3290                 else if (ah->regulatory.current_rd == 0x41)
3291                         ah->regulatory.current_rd = 0x43;
3292                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3293                         "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3294         }
3295
3296         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3297         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3298
3299         if (eeval & AR5416_OPFLAGS_11A) {
3300                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3301                 if (ah->config.ht_enable) {
3302                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3303                                 set_bit(ATH9K_MODE_11NA_HT20,
3304                                         pCap->wireless_modes);
3305                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3306                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3307                                         pCap->wireless_modes);
3308                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3309                                         pCap->wireless_modes);
3310                         }
3311                 }
3312         }
3313
3314         if (eeval & AR5416_OPFLAGS_11G) {
3315                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3316                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3317                 if (ah->config.ht_enable) {
3318                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3319                                 set_bit(ATH9K_MODE_11NG_HT20,
3320                                         pCap->wireless_modes);
3321                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3322                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3323                                         pCap->wireless_modes);
3324                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3325                                         pCap->wireless_modes);
3326                         }
3327                 }
3328         }
3329
3330         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3331         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3332             !(eeval & AR5416_OPFLAGS_11A))
3333                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3334         else
3335                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3336
3337         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3338                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3339
3340         pCap->low_2ghz_chan = 2312;
3341         pCap->high_2ghz_chan = 2732;
3342
3343         pCap->low_5ghz_chan = 4920;
3344         pCap->high_5ghz_chan = 6100;
3345
3346         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3347         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3348         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3349
3350         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3351         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3352         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3353
3354         if (ah->config.ht_enable)
3355                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3356         else
3357                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3358
3359         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3360         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3361         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3362         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3363
3364         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3365                 pCap->total_queues =
3366                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3367         else
3368                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3369
3370         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3371                 pCap->keycache_size =
3372                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3373         else
3374                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3375
3376         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3377         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3378
3379         if (AR_SREV_9285_10_OR_LATER(ah))
3380                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3381         else if (AR_SREV_9280_10_OR_LATER(ah))
3382                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3383         else
3384                 pCap->num_gpio_pins = AR_NUM_GPIO;
3385
3386         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3387                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3388                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3389         } else {
3390                 pCap->rts_aggr_limit = (8 * 1024);
3391         }
3392
3393         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3394
3395 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3396         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3397         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3398                 ah->rfkill_gpio =
3399                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3400                 ah->rfkill_polarity =
3401                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3402
3403                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3404         }
3405 #endif
3406
3407         if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3408             (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3409             (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3410             (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3411             (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3412             (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3413                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3414         else
3415                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3416
3417         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3418                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3419         else
3420                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3421
3422         if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3423                 pCap->reg_cap =
3424                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3425                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3426                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3427                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3428         } else {
3429                 pCap->reg_cap =
3430                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3431                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3432         }
3433
3434         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3435
3436         pCap->num_antcfg_5ghz =
3437                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3438         pCap->num_antcfg_2ghz =
3439                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3440
3441         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3442                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3443                 ah->btactive_gpio = 6;
3444                 ah->wlanactive_gpio = 5;
3445         }
3446 }
3447
3448 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3449                             u32 capability, u32 *result)
3450 {
3451         switch (type) {
3452         case ATH9K_CAP_CIPHER:
3453                 switch (capability) {
3454                 case ATH9K_CIPHER_AES_CCM:
3455                 case ATH9K_CIPHER_AES_OCB:
3456                 case ATH9K_CIPHER_TKIP:
3457                 case ATH9K_CIPHER_WEP:
3458                 case ATH9K_CIPHER_MIC:
3459                 case ATH9K_CIPHER_CLR:
3460                         return true;
3461                 default:
3462                         return false;
3463                 }
3464         case ATH9K_CAP_TKIP_MIC:
3465                 switch (capability) {
3466                 case 0:
3467                         return true;
3468                 case 1:
3469                         return (ah->sta_id1_defaults &
3470                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3471                         false;
3472                 }
3473         case ATH9K_CAP_TKIP_SPLIT:
3474                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3475                         false : true;
3476         case ATH9K_CAP_DIVERSITY:
3477                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3478                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3479                         true : false;
3480         case ATH9K_CAP_MCAST_KEYSRCH:
3481                 switch (capability) {
3482                 case 0:
3483                         return true;
3484                 case 1:
3485                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3486                                 return false;
3487                         } else {
3488                                 return (ah->sta_id1_defaults &
3489                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3490                                         false;
3491                         }
3492                 }
3493                 return false;
3494         case ATH9K_CAP_TXPOW:
3495                 switch (capability) {
3496                 case 0:
3497                         return 0;
3498                 case 1:
3499                         *result = ah->regulatory.power_limit;
3500                         return 0;
3501                 case 2:
3502                         *result = ah->regulatory.max_power_level;
3503                         return 0;
3504                 case 3:
3505                         *result = ah->regulatory.tp_scale;
3506                         return 0;
3507                 }
3508                 return false;
3509         case ATH9K_CAP_DS:
3510                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3511                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3512                         ? false : true;
3513         default:
3514                 return false;
3515         }
3516 }
3517
3518 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3519                             u32 capability, u32 setting, int *status)
3520 {
3521         u32 v;
3522
3523         switch (type) {
3524         case ATH9K_CAP_TKIP_MIC:
3525                 if (setting)
3526                         ah->sta_id1_defaults |=
3527                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3528                 else
3529                         ah->sta_id1_defaults &=
3530                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3531                 return true;
3532         case ATH9K_CAP_DIVERSITY:
3533                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3534                 if (setting)
3535                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3536                 else
3537                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3538                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3539                 return true;
3540         case ATH9K_CAP_MCAST_KEYSRCH:
3541                 if (setting)
3542                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3543                 else
3544                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3545                 return true;
3546         default:
3547                 return false;
3548         }
3549 }
3550
3551 /****************************/
3552 /* GPIO / RFKILL / Antennae */
3553 /****************************/
3554
3555 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3556                                          u32 gpio, u32 type)
3557 {
3558         int addr;
3559         u32 gpio_shift, tmp;
3560
3561         if (gpio > 11)
3562                 addr = AR_GPIO_OUTPUT_MUX3;
3563         else if (gpio > 5)
3564                 addr = AR_GPIO_OUTPUT_MUX2;
3565         else
3566                 addr = AR_GPIO_OUTPUT_MUX1;
3567
3568         gpio_shift = (gpio % 6) * 5;
3569
3570         if (AR_SREV_9280_20_OR_LATER(ah)
3571             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3572                 REG_RMW(ah, addr, (type << gpio_shift),
3573                         (0x1f << gpio_shift));
3574         } else {
3575                 tmp = REG_READ(ah, addr);
3576                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3577                 tmp &= ~(0x1f << gpio_shift);
3578                 tmp |= (type << gpio_shift);
3579                 REG_WRITE(ah, addr, tmp);
3580         }
3581 }
3582
3583 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3584 {
3585         u32 gpio_shift;
3586
3587         ASSERT(gpio < ah->caps.num_gpio_pins);
3588
3589         gpio_shift = gpio << 1;
3590
3591         REG_RMW(ah,
3592                 AR_GPIO_OE_OUT,
3593                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3594                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3595 }
3596
3597 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3598 {
3599 #define MS_REG_READ(x, y) \
3600         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3601
3602         if (gpio >= ah->caps.num_gpio_pins)
3603                 return 0xffffffff;
3604
3605         if (AR_SREV_9285_10_OR_LATER(ah))
3606                 return MS_REG_READ(AR9285, gpio) != 0;
3607         else if (AR_SREV_9280_10_OR_LATER(ah))
3608                 return MS_REG_READ(AR928X, gpio) != 0;
3609         else
3610                 return MS_REG_READ(AR, gpio) != 0;
3611 }
3612
3613 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3614                          u32 ah_signal_type)
3615 {
3616         u32 gpio_shift;
3617
3618         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3619
3620         gpio_shift = 2 * gpio;
3621
3622         REG_RMW(ah,
3623                 AR_GPIO_OE_OUT,
3624                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3625                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3626 }
3627
3628 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3629 {
3630         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3631                 AR_GPIO_BIT(gpio));
3632 }
3633
3634 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3635 void ath9k_enable_rfkill(struct ath_hw *ah)
3636 {
3637         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3638                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3639
3640         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3641                     AR_GPIO_INPUT_MUX2_RFSILENT);
3642
3643         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3644         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3645 }
3646 #endif
3647
3648 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3649 {
3650         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3651 }
3652
3653 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3654 {
3655         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3656 }
3657
3658 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3659                                enum ath9k_ant_setting settings,
3660                                struct ath9k_channel *chan,
3661                                u8 *tx_chainmask,
3662                                u8 *rx_chainmask,
3663                                u8 *antenna_cfgd)
3664 {
3665         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3666
3667         if (AR_SREV_9280(ah)) {
3668                 if (!tx_chainmask_cfg) {
3669
3670                         tx_chainmask_cfg = *tx_chainmask;
3671                         rx_chainmask_cfg = *rx_chainmask;
3672                 }
3673
3674                 switch (settings) {
3675                 case ATH9K_ANT_FIXED_A:
3676                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3677                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3678                         *antenna_cfgd = true;
3679                         break;
3680                 case ATH9K_ANT_FIXED_B:
3681                         if (ah->caps.tx_chainmask >
3682                             ATH9K_ANTENNA1_CHAINMASK) {
3683                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3684                         }
3685                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3686                         *antenna_cfgd = true;
3687                         break;
3688                 case ATH9K_ANT_VARIABLE:
3689                         *tx_chainmask = tx_chainmask_cfg;
3690                         *rx_chainmask = rx_chainmask_cfg;
3691                         *antenna_cfgd = true;
3692                         break;
3693                 default:
3694                         break;
3695                 }
3696         } else {
3697                 ah->diversity_control = settings;
3698         }
3699
3700         return true;
3701 }
3702
3703 /*********************/
3704 /* General Operation */
3705 /*********************/
3706
3707 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3708 {
3709         u32 bits = REG_READ(ah, AR_RX_FILTER);
3710         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3711
3712         if (phybits & AR_PHY_ERR_RADAR)
3713                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3714         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3715                 bits |= ATH9K_RX_FILTER_PHYERR;
3716
3717         return bits;
3718 }
3719
3720 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3721 {
3722         u32 phybits;
3723
3724         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3725         phybits = 0;
3726         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3727                 phybits |= AR_PHY_ERR_RADAR;
3728         if (bits & ATH9K_RX_FILTER_PHYERR)
3729                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3730         REG_WRITE(ah, AR_PHY_ERR, phybits);
3731
3732         if (phybits)
3733                 REG_WRITE(ah, AR_RXCFG,
3734                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3735         else
3736                 REG_WRITE(ah, AR_RXCFG,
3737                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3738 }
3739
3740 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3741 {
3742         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3743 }
3744
3745 bool ath9k_hw_disable(struct ath_hw *ah)
3746 {
3747         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3748                 return false;
3749
3750         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3751 }
3752
3753 bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3754 {
3755         struct ath9k_channel *chan = ah->curchan;
3756         struct ieee80211_channel *channel = chan->chan;
3757
3758         ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3759
3760         if (ah->eep_ops->set_txpower(ah, chan,
3761                              ath9k_regd_get_ctl(&ah->regulatory, chan),
3762                              channel->max_antenna_gain * 2,
3763                              channel->max_power * 2,
3764                              min((u32) MAX_RATE_POWER,
3765                                  (u32) ah->regulatory.power_limit)) != 0)
3766                 return false;
3767
3768         return true;
3769 }
3770
3771 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3772 {
3773         memcpy(ah->macaddr, mac, ETH_ALEN);
3774 }
3775
3776 void ath9k_hw_setopmode(struct ath_hw *ah)
3777 {
3778         ath9k_hw_set_operating_mode(ah, ah->opmode);
3779 }
3780
3781 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3782 {
3783         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3784         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3785 }
3786
3787 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3788 {
3789         REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3790         REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3791 }
3792
3793 void ath9k_hw_write_associd(struct ath_softc *sc)
3794 {
3795         REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3796         REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3797                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3798 }
3799
3800 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3801 {
3802         u64 tsf;
3803
3804         tsf = REG_READ(ah, AR_TSF_U32);
3805         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3806
3807         return tsf;
3808 }
3809
3810 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3811 {
3812         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3813         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3814 }
3815
3816 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3817 {
3818         int count;
3819
3820         count = 0;
3821         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3822                 count++;
3823                 if (count > 10) {
3824                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3825                                 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3826                         break;
3827                 }
3828                 udelay(10);
3829         }
3830         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3831 }
3832
3833 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3834 {
3835         if (setting)
3836                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3837         else
3838                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3839
3840         return true;
3841 }
3842
3843 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3844 {
3845         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3846                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3847                 ah->slottime = (u32) -1;
3848                 return false;
3849         } else {
3850                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3851                 ah->slottime = us;
3852                 return true;
3853         }
3854 }
3855
3856 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3857 {
3858         u32 macmode;
3859
3860         if (mode == ATH9K_HT_MACMODE_2040 &&
3861             !ah->config.cwm_ignore_extcca)
3862                 macmode = AR_2040_JOINED_RX_CLEAR;
3863         else
3864                 macmode = 0;
3865
3866         REG_WRITE(ah, AR_2040_MODE, macmode);
3867 }
3868
3869 /***************************/
3870 /*  Bluetooth Coexistence  */
3871 /***************************/
3872
3873 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3874 {
3875         /* connect bt_active to baseband */
3876         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3877                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3878                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3879
3880         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3881                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3882
3883         /* Set input mux for bt_active to gpio pin */
3884         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3885                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3886                         ah->btactive_gpio);
3887
3888         /* Configure the desired gpio port for input */
3889         ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3890
3891         /* Configure the desired GPIO port for TX_FRAME output */
3892         ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3893                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3894 }