2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
22 #if defined(CONFIG_DEBUG_ICEDCC)
28 mcr p14, 0, \ch, c0, c5, 0
30 #elif defined(CONFIG_CPU_XSCALE)
34 mcr p14, 0, \ch, c8, c0, 0
40 mcr p14, 0, \ch, c1, c0, 0
46 #include <mach/debug-macro.S>
52 #if defined(CONFIG_ARCH_SA1100)
54 mov \rb, #0x80000000 @ physical base address
55 #ifdef CONFIG_DEBUG_LL_SER3
56 add \rb, \rb, #0x00050000 @ Ser3
58 add \rb, \rb, #0x00010000 @ Ser1
61 #elif defined(CONFIG_ARCH_S3C2410)
64 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
85 .macro debug_reloc_start
88 kphex r6, 8 /* processor id */
90 kphex r7, 8 /* architecture id */
91 #ifdef CONFIG_CPU_CP15
93 mrc p15, 0, r0, c1, c0
94 kphex r0, 8 /* control reg */
97 kphex r5, 8 /* decompressed kernel start */
99 kphex r9, 8 /* decompressed kernel end */
101 kphex r4, 8 /* kernel execution address */
106 .macro debug_reloc_end
108 kphex r5, 8 /* end of kernel */
111 bl memdump /* dump 256 bytes at start of kernel */
115 .section ".start", #alloc, #execinstr
117 * sort out different calling conventions
121 .type start,#function
127 .word 0x016f2818 @ Magic numbers to help the loader
128 .word start @ absolute load/run zImage address
129 .word _edata @ zImage end address
130 1: mov r7, r1 @ save architecture ID
131 mov r8, r2 @ save atags pointer
133 #ifndef __ARM_ARCH_2__
135 * Booting from Angel - need to enter SVC mode and disable
136 * FIQs/IRQs (numeric definitions from angel arm.h source).
137 * We only do this if we were in user mode on entry.
139 mrs r2, cpsr @ get current mode
140 tst r2, #3 @ not user?
142 mov r0, #0x17 @ angel_SWIreason_EnterSVC
143 swi 0x123456 @ angel_SWI_ARM
145 mrs r2, cpsr @ turn off interrupts to
146 orr r2, r2, #0xc0 @ prevent angel from running
149 teqp pc, #0x0c000003 @ turn off interrupts
153 * Note that some cache flushing and other stuff may
154 * be needed here - is there an Angel SWI call for this?
158 * some architecture specific code can be inserted
159 * by the linker here, but it should preserve r7, r8, and r9.
164 ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
165 subs r0, r0, r1 @ calculate the delta offset
167 @ if delta is zero, we are
168 beq not_relocated @ running at the address we
172 * We're running at a different address. We need to fix
173 * up various pointers:
174 * r5 - zImage base address
182 #ifndef CONFIG_ZBOOT_ROM
184 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
185 * we need to fix up pointers into the BSS region.
195 * Relocate all entries in the GOT table.
197 1: ldr r1, [r6, #0] @ relocate entries in the GOT
198 add r1, r1, r0 @ table. This fixes up the
199 str r1, [r6], #4 @ C references.
205 * Relocate entries in the GOT table. We only relocate
206 * the entries that are outside the (relocated) BSS region.
208 1: ldr r1, [r6, #0] @ relocate entries in the GOT
209 cmp r1, r2 @ entry < bss_start ||
210 cmphs r3, r1 @ _end < entry
211 addlo r1, r1, r0 @ table. This fixes up the
212 str r1, [r6], #4 @ C references.
217 not_relocated: mov r0, #0
218 1: str r0, [r2], #4 @ clear bss
226 * The C runtime environment should now be setup
227 * sufficiently. Turn the cache on, set up some
228 * pointers, and start decompressing.
232 mov r1, sp @ malloc space above stack
233 add r2, sp, #0x10000 @ 64k max
236 * Check to see if we will overwrite ourselves.
237 * r4 = final kernel address
238 * r5 = start of this image
239 * r2 = end of malloc space (and therefore this image)
242 * r4 + image length <= r5 -> OK
246 sub r3, sp, r5 @ > compressed kernel size
247 add r0, r4, r3, lsl #2 @ allow for 4x expansion
251 mov r5, r2 @ decompress after malloc space
256 add r0, r0, #127 + 128 @ alignment + stack
257 bic r0, r0, #127 @ align the kernel length
259 * r0 = decompressed kernel length
261 * r4 = kernel execution address
262 * r5 = decompressed kernel start
264 * r7 = architecture ID
268 add r1, r5, r0 @ end of decompressed kernel
272 1: ldmia r2!, {r9 - r14} @ copy relocation code
273 stmia r1!, {r9 - r14}
274 ldmia r2!, {r9 - r14}
275 stmia r1!, {r9 - r14}
278 add sp, r1, #128 @ relocate the stack
281 add pc, r5, r0 @ call relocation code
284 * We're not in danger of overwriting ourselves. Do this the simple way.
286 * r4 = kernel execution address
287 * r7 = architecture ID
289 wont_overwrite: mov r0, r4
296 .word __bss_start @ r2
300 .word _got_start @ r6
302 .word user_stack+4096 @ sp
303 LC1: .word reloc_end - reloc_start
306 #ifdef CONFIG_ARCH_RPC
308 params: ldr r0, =params_phys
315 * Turn on the cache. We need to setup some page tables so that we
316 * can have both the I and D caches on.
318 * We place the page tables 16k down from the kernel execution address,
319 * and we hope that nothing else is using it. If we're using it, we
323 * r4 = kernel execution address
325 * r7 = architecture number
327 * r9 = run-time address of "start" (???)
329 * r1, r2, r3, r9, r10, r12 corrupted
330 * This routine must preserve:
334 cache_on: mov r3, #8 @ cache_on function
338 * Initialize the highest priority protection region, PR7
339 * to cover all 32bit address and cacheable and bufferable.
341 __armv4_mpu_cache_on:
342 mov r0, #0x3f @ 4G, the whole
343 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
344 mcr p15, 0, r0, c6, c7, 1
347 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
348 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
349 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
352 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
353 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
356 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
357 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
358 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
359 mrc p15, 0, r0, c1, c0, 0 @ read control reg
360 @ ...I .... ..D. WC.M
361 orr r0, r0, #0x002d @ .... .... ..1. 11.1
362 orr r0, r0, #0x1000 @ ...1 .... .... ....
364 mcr p15, 0, r0, c1, c0, 0 @ write control reg
367 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
368 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
371 __armv3_mpu_cache_on:
372 mov r0, #0x3f @ 4G, the whole
373 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
376 mcr p15, 0, r0, c2, c0, 0 @ cache on
377 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
380 mcr p15, 0, r0, c5, c0, 0 @ access permission
383 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
384 mrc p15, 0, r0, c1, c0, 0 @ read control reg
385 @ .... .... .... WC.M
386 orr r0, r0, #0x000d @ .... .... .... 11.1
388 mcr p15, 0, r0, c1, c0, 0 @ write control reg
390 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
393 __setup_mmu: sub r3, r4, #16384 @ Page directory size
394 bic r3, r3, #0xff @ Align the pointer
397 * Initialise the page tables, turning on the cacheable and bufferable
398 * bits for the RAM area only.
402 mov r9, r9, lsl #18 @ start of RAM
403 add r10, r9, #0x10000000 @ a reasonable RAM size
407 1: cmp r1, r9 @ if virt > start of RAM
408 orrhs r1, r1, #0x0c @ set cacheable, bufferable
409 cmp r1, r10 @ if virt > end of RAM
410 bichs r1, r1, #0x0c @ clear cacheable, bufferable
411 str r1, [r0], #4 @ 1:1 mapping
416 * If ever we are running from Flash, then we surely want the cache
417 * to be enabled also for our execution instance... We map 2MB of it
418 * so there is no map overlap problem for up to 1 MB compressed kernel.
419 * If the execution is in RAM then we would only be duplicating the above.
424 orr r1, r1, r2, lsl #20
425 add r0, r3, r2, lsl #2
432 __armv4_mmu_cache_on:
436 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
437 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
438 mrc p15, 0, r0, c1, c0, 0 @ read control reg
439 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
441 bl __common_mmu_cache_on
443 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
446 __armv7_mmu_cache_on:
448 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
452 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
454 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
455 mrc p15, 0, r0, c1, c0, 0 @ read control reg
456 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
457 orr r0, r0, #0x003c @ write buffer
458 orrne r0, r0, #1 @ MMU enabled
460 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
461 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
462 mcr p15, 0, r0, c1, c0, 0 @ load control register
463 mrc p15, 0, r0, c1, c0, 0 @ and read it back
465 mcr p15, 0, r0, c7, c5, 4 @ ISB
472 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
473 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
475 bl __common_mmu_cache_on
477 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
480 __common_mmu_cache_on:
482 orr r0, r0, #0x000d @ Write buffer, mmu
485 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
486 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
488 .align 5 @ cache line aligned
489 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
490 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
491 sub pc, lr, r0, lsr #32 @ properly flush pipeline
494 * All code following this line is relocatable. It is relocated by
495 * the above code to the end of the decompressed kernel image and
496 * executed there. During this time, we have no stacks.
498 * r0 = decompressed kernel length
500 * r4 = kernel execution address
501 * r5 = decompressed kernel start
503 * r7 = architecture ID
508 reloc_start: add r9, r5, r0
509 sub r9, r9, #128 @ do not copy the stack
514 ldmia r5!, {r0, r2, r3, r10 - r14} @ relocate kernel
515 stmia r1!, {r0, r2, r3, r10 - r14}
520 add sp, r1, #128 @ relocate the stack
523 call_kernel: bl cache_clean_flush
525 mov r0, #0 @ must be zero
526 mov r1, r7 @ restore architecture number
527 mov r2, r8 @ restore atags pointer
528 mov pc, r4 @ call kernel
531 * Here follow the relocatable cache support functions for the
532 * various processors. This is a generic hook for locating an
533 * entry and jumping to an instruction at the specified offset
534 * from the start of the block. Please note this is all position
544 call_cache_fn: adr r12, proc_types
545 #ifdef CONFIG_CPU_CP15
546 mrc p15, 0, r6, c0, c0 @ get processor ID
548 ldr r6, =CONFIG_PROCESSOR_ID
550 1: ldr r1, [r12, #0] @ get value
551 ldr r2, [r12, #4] @ get mask
552 eor r1, r1, r6 @ (real ^ match)
554 addeq pc, r12, r3 @ call cache function
559 * Table for cache operations. This is basically:
562 * - 'cache on' method instruction
563 * - 'cache off' method instruction
564 * - 'cache flush' method instruction
566 * We match an entry using: ((real_id ^ match) & mask) == 0
568 * Writethrough caches generally only need 'on' and 'off'
569 * methods. Writeback caches _must_ have the flush method
572 .type proc_types,#object
574 .word 0x41560600 @ ARM6/610
576 b __arm6_mmu_cache_off @ works, but slow
577 b __arm6_mmu_cache_off
579 @ b __arm6_mmu_cache_on @ untested
580 @ b __arm6_mmu_cache_off
581 @ b __armv3_mmu_cache_flush
583 .word 0x00000000 @ old ARM ID
589 .word 0x41007000 @ ARM7/710
591 b __arm7_mmu_cache_off
592 b __arm7_mmu_cache_off
595 .word 0x41807200 @ ARM720T (writethrough)
597 b __armv4_mmu_cache_on
598 b __armv4_mmu_cache_off
601 .word 0x41007400 @ ARM74x
603 b __armv3_mpu_cache_on
604 b __armv3_mpu_cache_off
605 b __armv3_mpu_cache_flush
607 .word 0x41009400 @ ARM94x
609 b __armv4_mpu_cache_on
610 b __armv4_mpu_cache_off
611 b __armv4_mpu_cache_flush
613 .word 0x00007000 @ ARM7 IDs
619 @ Everything from here on will be the new ID system.
621 .word 0x4401a100 @ sa110 / sa1100
623 b __armv4_mmu_cache_on
624 b __armv4_mmu_cache_off
625 b __armv4_mmu_cache_flush
627 .word 0x6901b110 @ sa1110
629 b __armv4_mmu_cache_on
630 b __armv4_mmu_cache_off
631 b __armv4_mmu_cache_flush
634 .word 0xff0ffff0 @ PXA935
635 b __armv4_mmu_cache_on
636 b __armv4_mmu_cache_off
637 b __armv4_mmu_cache_flush
639 .word 0x56050000 @ Feroceon
641 b __armv4_mmu_cache_on
642 b __armv4_mmu_cache_off
643 b __armv5tej_mmu_cache_flush
645 @ These match on the architecture ID
647 .word 0x00020000 @ ARMv4T
649 b __armv4_mmu_cache_on
650 b __armv4_mmu_cache_off
651 b __armv4_mmu_cache_flush
653 .word 0x00050000 @ ARMv5TE
655 b __armv4_mmu_cache_on
656 b __armv4_mmu_cache_off
657 b __armv4_mmu_cache_flush
659 .word 0x00060000 @ ARMv5TEJ
661 b __armv4_mmu_cache_on
662 b __armv4_mmu_cache_off
663 b __armv5tej_mmu_cache_flush
665 .word 0x0007b000 @ ARMv6
667 b __armv4_mmu_cache_on
668 b __armv4_mmu_cache_off
669 b __armv6_mmu_cache_flush
671 .word 0x000f0000 @ new CPU Id
673 b __armv7_mmu_cache_on
674 b __armv7_mmu_cache_off
675 b __armv7_mmu_cache_flush
677 .word 0 @ unrecognised type
683 .size proc_types, . - proc_types
686 * Turn off the Cache and MMU. ARMv3 does not support
687 * reading the control register, but ARMv4 does.
689 * On entry, r6 = processor ID
690 * On exit, r0, r1, r2, r3, r12 corrupted
691 * This routine must preserve: r4, r6, r7
694 cache_off: mov r3, #12 @ cache_off function
697 __armv4_mpu_cache_off:
698 mrc p15, 0, r0, c1, c0
700 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
702 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
703 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
704 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
707 __armv3_mpu_cache_off:
708 mrc p15, 0, r0, c1, c0
710 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
712 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
715 __armv4_mmu_cache_off:
716 mrc p15, 0, r0, c1, c0
718 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
720 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
721 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
724 __armv7_mmu_cache_off:
725 mrc p15, 0, r0, c1, c0
727 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
729 bl __armv7_mmu_cache_flush
731 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
732 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
733 mcr p15, 0, r0, c7, c10, 4 @ DSB
734 mcr p15, 0, r0, c7, c5, 4 @ ISB
737 __arm6_mmu_cache_off:
738 mov r0, #0x00000030 @ ARM6 control reg.
739 b __armv3_mmu_cache_off
741 __arm7_mmu_cache_off:
742 mov r0, #0x00000070 @ ARM7 control reg.
743 b __armv3_mmu_cache_off
745 __armv3_mmu_cache_off:
746 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
748 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
749 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
753 * Clean and flush the cache to maintain consistency.
758 * r1, r2, r3, r11, r12 corrupted
759 * This routine must preserve:
767 __armv4_mpu_cache_flush:
770 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
771 mov r1, #7 << 5 @ 8 segments
772 1: orr r3, r1, #63 << 26 @ 64 entries
773 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
774 subs r3, r3, #1 << 26
775 bcs 2b @ entries 63 to 0
777 bcs 1b @ segments 7 to 0
780 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
781 mcr p15, 0, ip, c7, c10, 4 @ drain WB
785 __armv6_mmu_cache_flush:
787 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
788 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
789 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
790 mcr p15, 0, r1, c7, c10, 4 @ drain WB
793 __armv7_mmu_cache_flush:
794 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
795 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
798 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
801 mcr p15, 0, r10, c7, c10, 5 @ DMB
802 stmfd sp!, {r0-r5, r7, r9, r11}
803 mrc p15, 1, r0, c0, c0, 1 @ read clidr
804 ands r3, r0, #0x7000000 @ extract loc from clidr
805 mov r3, r3, lsr #23 @ left align loc bit field
806 beq finished @ if loc is 0, then no need to clean
807 mov r10, #0 @ start clean at cache level 0
809 add r2, r10, r10, lsr #1 @ work out 3x current cache level
810 mov r1, r0, lsr r2 @ extract cache type bits from clidr
811 and r1, r1, #7 @ mask of the bits for current cache only
812 cmp r1, #2 @ see what cache we have at this level
813 blt skip @ skip if no cache, or just i-cache
814 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
815 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
816 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
817 and r2, r1, #7 @ extract the length of the cache lines
818 add r2, r2, #4 @ add 4 (line length offset)
820 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
821 clz r5, r4 @ find bit position of way size increment
823 ands r7, r7, r1, lsr #13 @ extract max number of the index size
825 mov r9, r4 @ create working copy of max way size
827 orr r11, r10, r9, lsl r5 @ factor way and cache number into r11
828 orr r11, r11, r7, lsl r2 @ factor index number into r11
829 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
830 subs r9, r9, #1 @ decrement the way
832 subs r7, r7, #1 @ decrement the index
835 add r10, r10, #2 @ increment cache number
839 ldmfd sp!, {r0-r5, r7, r9, r11}
840 mov r10, #0 @ swith back to cache level 0
841 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
843 mcr p15, 0, r10, c7, c10, 4 @ DSB
844 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
845 mcr p15, 0, r10, c7, c10, 4 @ DSB
846 mcr p15, 0, r10, c7, c5, 4 @ ISB
849 __armv5tej_mmu_cache_flush:
850 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
852 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
853 mcr p15, 0, r0, c7, c10, 4 @ drain WB
856 __armv4_mmu_cache_flush:
857 mov r2, #64*1024 @ default: 32K dcache size (*2)
858 mov r11, #32 @ default: 32 byte line size
859 mrc p15, 0, r3, c0, c0, 1 @ read cache type
860 teq r3, r6 @ cache ID register present?
865 mov r2, r2, lsl r1 @ base dcache size *2
866 tst r3, #1 << 14 @ test M bit
867 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
871 mov r11, r11, lsl r3 @ cache line size in bytes
873 bic r1, pc, #63 @ align to longest cache line
875 1: ldr r3, [r1], r11 @ s/w flush D cache
879 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
880 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
881 mcr p15, 0, r1, c7, c10, 4 @ drain WB
884 __armv3_mmu_cache_flush:
885 __armv3_mpu_cache_flush:
887 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
891 * Various debugging routines for printing hex characters and
892 * memory, which again must be relocatable.
895 .type phexbuf,#object
897 .size phexbuf, . - phexbuf
899 phex: adr r3, phexbuf
936 2: mov r0, r11, lsl #2
944 ldr r0, [r12, r11, lsl #2]
966 .section ".stack", "w"
967 user_stack: .space 4096