2 * linux/arch/arm/mach-realview/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/amba/bus.h>
27 #include <linux/amba/clcd.h>
28 #include <linux/clocksource.h>
29 #include <linux/clockchips.h>
31 #include <linux/smc911x.h>
32 #include <linux/ata_platform.h>
34 #include <asm/clkdev.h>
35 #include <asm/system.h>
36 #include <mach/hardware.h>
39 #include <asm/mach-types.h>
40 #include <asm/hardware/arm_timer.h>
41 #include <asm/hardware/icst307.h>
43 #include <asm/mach/arch.h>
44 #include <asm/mach/flash.h>
45 #include <asm/mach/irq.h>
46 #include <asm/mach/map.h>
47 #include <asm/mach/mmc.h>
49 #include <asm/hardware/gic.h>
54 #define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
56 /* used by entry-macro.S and platsmp.c */
57 void __iomem *gic_cpu_base_addr;
60 * This is the RealView sched_clock implementation. This has
61 * a resolution of 41.7ns, and a maximum value of about 179s.
63 unsigned long long sched_clock(void)
67 v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
74 #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
76 static int realview_flash_init(void)
80 val = __raw_readl(REALVIEW_FLASHCTRL);
81 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
82 __raw_writel(val, REALVIEW_FLASHCTRL);
87 static void realview_flash_exit(void)
91 val = __raw_readl(REALVIEW_FLASHCTRL);
92 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
93 __raw_writel(val, REALVIEW_FLASHCTRL);
96 static void realview_flash_set_vpp(int on)
100 val = __raw_readl(REALVIEW_FLASHCTRL);
102 val |= REALVIEW_FLASHPROG_FLVPPEN;
104 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
105 __raw_writel(val, REALVIEW_FLASHCTRL);
108 static struct flash_platform_data realview_flash_data = {
109 .map_name = "cfi_probe",
111 .init = realview_flash_init,
112 .exit = realview_flash_exit,
113 .set_vpp = realview_flash_set_vpp,
116 struct platform_device realview_flash_device = {
120 .platform_data = &realview_flash_data,
124 int realview_flash_register(struct resource *res, u32 num)
126 realview_flash_device.resource = res;
127 realview_flash_device.num_resources = num;
128 return platform_device_register(&realview_flash_device);
131 static struct smc911x_platdata realview_smc911x_platdata = {
132 .flags = SMC911X_USE_32BIT,
133 .irq_flags = IRQF_SHARED,
137 static struct platform_device realview_eth_device = {
143 int realview_eth_register(const char *name, struct resource *res)
146 realview_eth_device.name = name;
147 realview_eth_device.resource = res;
148 if (strcmp(realview_eth_device.name, "smc911x") == 0)
149 realview_eth_device.dev.platform_data = &realview_smc911x_platdata;
151 return platform_device_register(&realview_eth_device);
154 struct platform_device realview_usb_device = {
159 int realview_usb_register(struct resource *res)
161 realview_usb_device.resource = res;
162 return platform_device_register(&realview_usb_device);
165 static struct pata_platform_info pata_platform_data = {
169 static struct resource pata_resources[] = {
171 .start = REALVIEW_CF_BASE,
172 .end = REALVIEW_CF_BASE + 0xff,
173 .flags = IORESOURCE_MEM,
176 .start = REALVIEW_CF_BASE + 0x100,
177 .end = REALVIEW_CF_BASE + SZ_4K - 1,
178 .flags = IORESOURCE_MEM,
182 struct platform_device realview_cf_device = {
183 .name = "pata_platform",
185 .num_resources = ARRAY_SIZE(pata_resources),
186 .resource = pata_resources,
188 .platform_data = &pata_platform_data,
192 static struct resource realview_i2c_resource = {
193 .start = REALVIEW_I2C_BASE,
194 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
195 .flags = IORESOURCE_MEM,
198 struct platform_device realview_i2c_device = {
199 .name = "versatile-i2c",
202 .resource = &realview_i2c_resource,
205 static struct i2c_board_info realview_i2c_board_info[] = {
207 I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1),
212 static int __init realview_i2c_init(void)
214 return i2c_register_board_info(0, realview_i2c_board_info,
215 ARRAY_SIZE(realview_i2c_board_info));
217 arch_initcall(realview_i2c_init);
219 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
221 static unsigned int realview_mmc_status(struct device *dev)
223 struct amba_device *adev = container_of(dev, struct amba_device, dev);
226 if (adev->res.start == REALVIEW_MMCI0_BASE)
231 return readl(REALVIEW_SYSMCI) & mask;
234 struct mmc_platform_data realview_mmc0_plat_data = {
235 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
236 .status = realview_mmc_status,
239 struct mmc_platform_data realview_mmc1_plat_data = {
240 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
241 .status = realview_mmc_status,
247 static const struct icst307_params realview_oscvco_params = {
256 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
258 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
259 void __iomem *sys_osc;
262 if (machine_is_realview_pb1176())
263 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
265 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
267 val = readl(sys_osc) & ~0x7ffff;
268 val |= vco.v | (vco.r << 9) | (vco.s << 16);
270 writel(0xa05f, sys_lock);
271 writel(val, sys_osc);
275 static struct clk oscvco_clk = {
276 .params = &realview_oscvco_params,
277 .setvco = realview_oscvco_set,
281 * These are fixed clocks.
283 static struct clk ref24_clk = {
287 static struct clk_lookup lookups[] = {
318 static int __init clk_init(void)
322 for (i = 0; i < ARRAY_SIZE(lookups); i++)
323 clkdev_add(&lookups[i]);
326 arch_initcall(clk_init);
331 #define SYS_CLCD_NLCDIOON (1 << 2)
332 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
333 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
334 #define SYS_CLCD_ID_MASK (0x1f << 8)
335 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
336 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
337 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
338 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
339 #define SYS_CLCD_ID_VGA (0x1f << 8)
341 static struct clcd_panel vga = {
355 .vmode = FB_VMODE_NONINTERLACED,
359 .tim2 = TIM2_BCD | TIM2_IPC,
360 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
364 static struct clcd_panel xvga = {
378 .vmode = FB_VMODE_NONINTERLACED,
382 .tim2 = TIM2_BCD | TIM2_IPC,
383 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
387 static struct clcd_panel sanyo_3_8_in = {
389 .name = "Sanyo QVGA",
401 .vmode = FB_VMODE_NONINTERLACED,
406 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
410 static struct clcd_panel sanyo_2_5_in = {
412 .name = "Sanyo QVGA Portrait",
423 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
424 .vmode = FB_VMODE_NONINTERLACED,
428 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
429 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
433 static struct clcd_panel epson_2_2_in = {
435 .name = "Epson QCIF",
447 .vmode = FB_VMODE_NONINTERLACED,
451 .tim2 = TIM2_BCD | TIM2_IPC,
452 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
457 * Detect which LCD panel is connected, and return the appropriate
458 * clcd_panel structure. Note: we do not have any information on
459 * the required timings for the 8.4in panel, so we presently assume
462 static struct clcd_panel *realview_clcd_panel(void)
464 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
465 struct clcd_panel *vga_panel;
466 struct clcd_panel *panel;
469 if (machine_is_realview_eb())
474 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
475 if (val == SYS_CLCD_ID_SANYO_3_8)
476 panel = &sanyo_3_8_in;
477 else if (val == SYS_CLCD_ID_SANYO_2_5)
478 panel = &sanyo_2_5_in;
479 else if (val == SYS_CLCD_ID_EPSON_2_2)
480 panel = &epson_2_2_in;
481 else if (val == SYS_CLCD_ID_VGA)
484 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
493 * Disable all display connectors on the interface module.
495 static void realview_clcd_disable(struct clcd_fb *fb)
497 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
500 val = readl(sys_clcd);
501 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
502 writel(val, sys_clcd);
506 * Enable the relevant connector on the interface module.
508 static void realview_clcd_enable(struct clcd_fb *fb)
510 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
516 val = readl(sys_clcd);
517 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
518 writel(val, sys_clcd);
521 static int realview_clcd_setup(struct clcd_fb *fb)
523 unsigned long framesize;
526 if (machine_is_realview_eb())
528 framesize = 640 * 480 * 2;
531 framesize = 1024 * 768 * 2;
533 fb->panel = realview_clcd_panel();
535 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
537 if (!fb->fb.screen_base) {
538 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
542 fb->fb.fix.smem_start = dma;
543 fb->fb.fix.smem_len = framesize;
548 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
550 return dma_mmap_writecombine(&fb->dev->dev, vma,
552 fb->fb.fix.smem_start,
553 fb->fb.fix.smem_len);
556 static void realview_clcd_remove(struct clcd_fb *fb)
558 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
559 fb->fb.screen_base, fb->fb.fix.smem_start);
562 struct clcd_board clcd_plat_data = {
564 .check = clcdfb_check,
565 .decode = clcdfb_decode,
566 .disable = realview_clcd_disable,
567 .enable = realview_clcd_enable,
568 .setup = realview_clcd_setup,
569 .mmap = realview_clcd_mmap,
570 .remove = realview_clcd_remove,
574 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
576 void realview_leds_event(led_event_t ledevt)
581 local_irq_save(flags);
582 val = readl(VA_LEDS_BASE);
586 val = val & ~REALVIEW_SYS_LED0;
590 val = val | REALVIEW_SYS_LED0;
594 val = val ^ REALVIEW_SYS_LED1;
605 writel(val, VA_LEDS_BASE);
606 local_irq_restore(flags);
608 #endif /* CONFIG_LEDS */
611 * Where is the timer (VA)?
613 void __iomem *timer0_va_base;
614 void __iomem *timer1_va_base;
615 void __iomem *timer2_va_base;
616 void __iomem *timer3_va_base;
619 * How long is the timer interval?
621 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
622 #if TIMER_INTERVAL >= 0x100000
623 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
624 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
625 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
626 #elif TIMER_INTERVAL >= 0x10000
627 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
628 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
629 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
631 #define TIMER_RELOAD (TIMER_INTERVAL)
632 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
633 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
636 static void timer_set_mode(enum clock_event_mode mode,
637 struct clock_event_device *clk)
642 case CLOCK_EVT_MODE_PERIODIC:
643 writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
645 ctrl = TIMER_CTRL_PERIODIC;
646 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
648 case CLOCK_EVT_MODE_ONESHOT:
649 /* period set, and timer enabled in 'next_event' hook */
650 ctrl = TIMER_CTRL_ONESHOT;
651 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
653 case CLOCK_EVT_MODE_UNUSED:
654 case CLOCK_EVT_MODE_SHUTDOWN:
659 writel(ctrl, timer0_va_base + TIMER_CTRL);
662 static int timer_set_next_event(unsigned long evt,
663 struct clock_event_device *unused)
665 unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
667 writel(evt, timer0_va_base + TIMER_LOAD);
668 writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
673 static struct clock_event_device timer0_clockevent = {
676 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
677 .set_mode = timer_set_mode,
678 .set_next_event = timer_set_next_event,
680 .cpumask = cpu_all_mask,
683 static void __init realview_clockevents_init(unsigned int timer_irq)
685 timer0_clockevent.irq = timer_irq;
686 timer0_clockevent.mult =
687 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
688 timer0_clockevent.max_delta_ns =
689 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
690 timer0_clockevent.min_delta_ns =
691 clockevent_delta2ns(0xf, &timer0_clockevent);
693 clockevents_register_device(&timer0_clockevent);
697 * IRQ handler for the timer
699 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
701 struct clock_event_device *evt = &timer0_clockevent;
703 /* clear the interrupt */
704 writel(1, timer0_va_base + TIMER_INTCLR);
706 evt->event_handler(evt);
711 static struct irqaction realview_timer_irq = {
712 .name = "RealView Timer Tick",
713 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
714 .handler = realview_timer_interrupt,
717 static cycle_t realview_get_cycles(void)
719 return ~readl(timer3_va_base + TIMER_VALUE);
722 static struct clocksource clocksource_realview = {
725 .read = realview_get_cycles,
726 .mask = CLOCKSOURCE_MASK(32),
728 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
731 static void __init realview_clocksource_init(void)
733 /* setup timer 0 as free-running clocksource */
734 writel(0, timer3_va_base + TIMER_CTRL);
735 writel(0xffffffff, timer3_va_base + TIMER_LOAD);
736 writel(0xffffffff, timer3_va_base + TIMER_VALUE);
737 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
738 timer3_va_base + TIMER_CTRL);
740 clocksource_realview.mult =
741 clocksource_khz2mult(1000, clocksource_realview.shift);
742 clocksource_register(&clocksource_realview);
746 * Set up the clock source and clock events devices
748 void __init realview_timer_init(unsigned int timer_irq)
752 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
754 * The dummy clock device has to be registered before the main device
755 * so that the latter will broadcast the clock events
761 * set clock frequency:
762 * REALVIEW_REFCLK is 32KHz
763 * REALVIEW_TIMCLK is 1MHz
765 val = readl(__io_address(REALVIEW_SCTL_BASE));
766 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
767 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
768 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
769 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
770 __io_address(REALVIEW_SCTL_BASE));
773 * Initialise to a known state (all timers off)
775 writel(0, timer0_va_base + TIMER_CTRL);
776 writel(0, timer1_va_base + TIMER_CTRL);
777 writel(0, timer2_va_base + TIMER_CTRL);
778 writel(0, timer3_va_base + TIMER_CTRL);
781 * Make irqs happen for the system timer
783 setup_irq(timer_irq, &realview_timer_irq);
785 realview_clocksource_init();
786 realview_clockevents_init(timer_irq);