2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
55 * Knob to control our willingness to enable the local APIC.
59 static int force_enable_local_apic;
61 * APIC command line parameters
63 static int __init parse_lapic(char *arg)
65 force_enable_local_apic = 1;
68 early_param("lapic", parse_lapic);
69 /* Local APIC was disabled by the BIOS and enabled by the kernel */
70 static int enabled_via_apicbase;
75 static int apic_calibrate_pmtmr __initdata;
76 static __init int setup_apicpmtimer(char *s)
78 apic_calibrate_pmtmr = 1;
82 __setup("apicpmtimer", setup_apicpmtimer);
85 unsigned long mp_lapic_addr;
87 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
88 static int disable_apic_timer __cpuinitdata;
89 /* Local APIC timer works in C2 */
90 int local_apic_timer_c2_ok;
91 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
93 int first_system_vector = 0xfe;
95 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
98 * Debug level, exported for io_apic.c
100 unsigned int apic_verbosity;
104 /* Have we found an MP table */
105 int smp_found_config;
107 static struct resource lapic_resource = {
108 .name = "Local APIC",
109 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
112 static unsigned int calibration_result;
114 static int lapic_next_event(unsigned long delta,
115 struct clock_event_device *evt);
116 static void lapic_timer_setup(enum clock_event_mode mode,
117 struct clock_event_device *evt);
118 static void lapic_timer_broadcast(cpumask_t mask);
119 static void apic_pm_activate(void);
122 * The local apic timer can be used for any function which is CPU local.
124 static struct clock_event_device lapic_clockevent = {
126 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
127 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
129 .set_mode = lapic_timer_setup,
130 .set_next_event = lapic_next_event,
131 .broadcast = lapic_timer_broadcast,
135 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
137 static unsigned long apic_phys;
140 * Get the LAPIC version
142 static inline int lapic_get_version(void)
144 return GET_APIC_VERSION(apic_read(APIC_LVR));
148 * Check, if the APIC is integrated or a separate chip
150 static inline int lapic_is_integrated(void)
155 return APIC_INTEGRATED(lapic_get_version());
160 * Check, whether this is a modern or a first generation APIC
162 static int modern_apic(void)
164 /* AMD systems use old APIC versions, so check the CPU */
165 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
166 boot_cpu_data.x86 >= 0xf)
168 return lapic_get_version() >= 0x14;
172 * Paravirt kernels also might be using these below ops. So we still
173 * use generic apic_read()/apic_write(), which might be pointing to different
174 * ops in PARAVIRT case.
176 void xapic_wait_icr_idle(void)
178 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
182 u32 safe_xapic_wait_icr_idle(void)
189 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
193 } while (timeout++ < 1000);
198 void xapic_icr_write(u32 low, u32 id)
200 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
201 apic_write(APIC_ICR, low);
204 u64 xapic_icr_read(void)
208 icr2 = apic_read(APIC_ICR2);
209 icr1 = apic_read(APIC_ICR);
211 return icr1 | ((u64)icr2 << 32);
214 static struct apic_ops xapic_ops = {
215 .read = native_apic_mem_read,
216 .write = native_apic_mem_write,
217 .icr_read = xapic_icr_read,
218 .icr_write = xapic_icr_write,
219 .wait_icr_idle = xapic_wait_icr_idle,
220 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
223 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
224 EXPORT_SYMBOL_GPL(apic_ops);
227 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
229 void __cpuinit enable_NMI_through_LVT0(void)
233 /* unmask and set to NMI */
236 /* Level triggered for 82489DX (32bit mode) */
237 if (!lapic_is_integrated())
238 v |= APIC_LVT_LEVEL_TRIGGER;
240 apic_write(APIC_LVT0, v);
245 * get_physical_broadcast - Get number of physical broadcast IDs
247 int get_physical_broadcast(void)
249 return modern_apic() ? 0xff : 0xf;
254 * lapic_get_maxlvt - get the maximum number of local vector table entries
256 int lapic_get_maxlvt(void)
260 v = apic_read(APIC_LVR);
262 * - we always have APIC integrated on 64bit mode
263 * - 82489DXs do not report # of LVT entries
265 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
274 #define APIC_DIVISOR 1
276 #define APIC_DIVISOR 16
280 * This function sets up the local APIC timer, with a timeout of
281 * 'clocks' APIC bus clock. During calibration we actually call
282 * this function twice on the boot CPU, once with a bogus timeout
283 * value, second time for real. The other (noncalibrating) CPUs
284 * call this function only once, with the real, calibrated value.
286 * We do reads before writes even if unnecessary, to get around the
287 * P5 APIC double write bug.
289 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
291 unsigned int lvtt_value, tmp_value;
293 lvtt_value = LOCAL_TIMER_VECTOR;
295 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
296 if (!lapic_is_integrated())
297 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
300 lvtt_value |= APIC_LVT_MASKED;
302 apic_write(APIC_LVTT, lvtt_value);
307 tmp_value = apic_read(APIC_TDCR);
308 apic_write(APIC_TDCR,
309 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
313 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
317 * Setup extended LVT, AMD specific (K8, family 10h)
319 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
320 * MCE interrupts are supported. Thus MCE offset must be set to 0.
322 * If mask=1, the LVT entry does not generate interrupts while mask=0
323 * enables the vector. See also the BKDGs.
326 #define APIC_EILVT_LVTOFF_MCE 0
327 #define APIC_EILVT_LVTOFF_IBS 1
329 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
331 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
332 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
337 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
339 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
340 return APIC_EILVT_LVTOFF_MCE;
343 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
345 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
346 return APIC_EILVT_LVTOFF_IBS;
348 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
351 * Program the next event, relative to now
353 static int lapic_next_event(unsigned long delta,
354 struct clock_event_device *evt)
356 apic_write(APIC_TMICT, delta);
361 * Setup the lapic timer in periodic or oneshot mode
363 static void lapic_timer_setup(enum clock_event_mode mode,
364 struct clock_event_device *evt)
369 /* Lapic used as dummy for broadcast ? */
370 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
373 local_irq_save(flags);
376 case CLOCK_EVT_MODE_PERIODIC:
377 case CLOCK_EVT_MODE_ONESHOT:
378 __setup_APIC_LVTT(calibration_result,
379 mode != CLOCK_EVT_MODE_PERIODIC, 1);
381 case CLOCK_EVT_MODE_UNUSED:
382 case CLOCK_EVT_MODE_SHUTDOWN:
383 v = apic_read(APIC_LVTT);
384 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
385 apic_write(APIC_LVTT, v);
387 case CLOCK_EVT_MODE_RESUME:
388 /* Nothing to do here */
392 local_irq_restore(flags);
396 * Local APIC timer broadcast function
398 static void lapic_timer_broadcast(cpumask_t mask)
401 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
406 * Setup the local APIC timer for this CPU. Copy the initilized values
407 * of the boot CPU and register the clock event in the framework.
409 static void __cpuinit setup_APIC_timer(void)
411 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
413 memcpy(levt, &lapic_clockevent, sizeof(*levt));
414 levt->cpumask = cpumask_of_cpu(smp_processor_id());
416 clockevents_register_device(levt);
420 * In this functions we calibrate APIC bus clocks to the external timer.
422 * We want to do the calibration only once since we want to have local timer
423 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
426 * This was previously done by reading the PIT/HPET and waiting for a wrap
427 * around to find out, that a tick has elapsed. I have a box, where the PIT
428 * readout is broken, so it never gets out of the wait loop again. This was
429 * also reported by others.
431 * Monitoring the jiffies value is inaccurate and the clockevents
432 * infrastructure allows us to do a simple substitution of the interrupt
435 * The calibration routine also uses the pm_timer when possible, as the PIT
436 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
437 * back to normal later in the boot process).
440 #define LAPIC_CAL_LOOPS (HZ/10)
442 static __initdata int lapic_cal_loops = -1;
443 static __initdata long lapic_cal_t1, lapic_cal_t2;
444 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
445 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
446 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
449 * Temporary interrupt handler.
451 static void __init lapic_cal_handler(struct clock_event_device *dev)
453 unsigned long long tsc = 0;
454 long tapic = apic_read(APIC_TMCCT);
455 unsigned long pm = acpi_pm_read_early();
460 switch (lapic_cal_loops++) {
462 lapic_cal_t1 = tapic;
463 lapic_cal_tsc1 = tsc;
465 lapic_cal_j1 = jiffies;
468 case LAPIC_CAL_LOOPS:
469 lapic_cal_t2 = tapic;
470 lapic_cal_tsc2 = tsc;
471 if (pm < lapic_cal_pm1)
472 pm += ACPI_PM_OVRRUN;
474 lapic_cal_j2 = jiffies;
479 static int __init calibrate_APIC_clock(void)
481 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
482 const long pm_100ms = PMTMR_TICKS_PER_SEC/10;
483 const long pm_thresh = pm_100ms/100;
484 void (*real_handler)(struct clock_event_device *dev);
485 unsigned long deltaj;
487 int pm_referenced = 0;
491 /* Replace the global interrupt handler */
492 real_handler = global_clock_event->event_handler;
493 global_clock_event->event_handler = lapic_cal_handler;
496 * Setup the APIC counter to 1e9. There is no way the lapic
497 * can underflow in the 100ms detection time frame
499 __setup_APIC_LVTT(1000000000, 0, 0);
501 /* Let the interrupts run */
504 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
509 /* Restore the real event handler */
510 global_clock_event->event_handler = real_handler;
512 /* Build delta t1-t2 as apic timer counts down */
513 delta = lapic_cal_t1 - lapic_cal_t2;
514 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
516 /* Check, if the PM timer is available */
517 deltapm = lapic_cal_pm2 - lapic_cal_pm1;
518 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
524 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
526 if (deltapm > (pm_100ms - pm_thresh) &&
527 deltapm < (pm_100ms + pm_thresh)) {
528 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
530 res = (((u64) deltapm) * mult) >> 22;
531 do_div(res, 1000000);
532 printk(KERN_WARNING "APIC calibration not consistent "
533 "with PM Timer: %ldms instead of 100ms\n",
535 /* Correct the lapic counter value */
536 res = (((u64) delta) * pm_100ms);
537 do_div(res, deltapm);
538 printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
539 "%lu (%ld)\n", (unsigned long) res, delta);
545 /* Calculate the scaled math multiplication factor */
546 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
547 lapic_clockevent.shift);
548 lapic_clockevent.max_delta_ns =
549 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
550 lapic_clockevent.min_delta_ns =
551 clockevent_delta2ns(0xF, &lapic_clockevent);
553 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
555 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
556 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
557 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
561 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
562 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
564 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
565 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
568 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
570 calibration_result / (1000000 / HZ),
571 calibration_result % (1000000 / HZ));
574 * Do a sanity check on the APIC calibration result
576 if (calibration_result < (1000000 / HZ)) {
579 "APIC frequency too slow, disabling apic timer\n");
583 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
585 /* We trust the pm timer based calibration */
586 if (!pm_referenced) {
587 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
590 * Setup the apic timer manually
592 levt->event_handler = lapic_cal_handler;
593 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
594 lapic_cal_loops = -1;
596 /* Let the interrupts run */
599 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
604 /* Stop the lapic timer */
605 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
610 deltaj = lapic_cal_j2 - lapic_cal_j1;
611 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
613 /* Check, if the jiffies result is consistent */
614 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
615 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
617 levt->features |= CLOCK_EVT_FEAT_DUMMY;
621 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
623 "APIC timer disabled due to verification failure.\n");
631 * Setup the boot APIC
633 * Calibrate and verify the result.
635 void __init setup_boot_APIC_clock(void)
638 * The local apic timer can be disabled via the kernel
639 * commandline or from the CPU detection code. Register the lapic
640 * timer as a dummy clock event source on SMP systems, so the
641 * broadcast mechanism is used. On UP systems simply ignore it.
643 if (disable_apic_timer) {
644 printk(KERN_INFO "Disabling APIC timer\n");
645 /* No broadcast on UP ! */
646 if (num_possible_cpus() > 1) {
647 lapic_clockevent.mult = 1;
653 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
654 "calibrating APIC timer ...\n");
656 if (calibrate_APIC_clock()) {
657 /* No broadcast on UP ! */
658 if (num_possible_cpus() > 1)
664 * If nmi_watchdog is set to IO_APIC, we need the
665 * PIT/HPET going. Otherwise register lapic as a dummy
668 if (nmi_watchdog != NMI_IO_APIC)
669 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
671 printk(KERN_WARNING "APIC timer registered as dummy,"
672 " due to nmi_watchdog=%d!\n", nmi_watchdog);
674 /* Setup the lapic or request the broadcast */
678 void __cpuinit setup_secondary_APIC_clock(void)
684 * The guts of the apic timer interrupt
686 static void local_apic_timer_interrupt(void)
688 int cpu = smp_processor_id();
689 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
692 * Normally we should not be here till LAPIC has been initialized but
693 * in some cases like kdump, its possible that there is a pending LAPIC
694 * timer interrupt from previous kernel's context and is delivered in
695 * new kernel the moment interrupts are enabled.
697 * Interrupts are enabled early and LAPIC is setup much later, hence
698 * its possible that when we get here evt->event_handler is NULL.
699 * Check for event_handler being NULL and discard the interrupt as
702 if (!evt->event_handler) {
704 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
706 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
711 * the NMI deadlock-detector uses this.
714 add_pda(apic_timer_irqs, 1);
716 per_cpu(irq_stat, cpu).apic_timer_irqs++;
719 evt->event_handler(evt);
723 * Local APIC timer interrupt. This is the most natural way for doing
724 * local interrupts, but local timer interrupts can be emulated by
725 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
727 * [ if a single-CPU system runs an SMP kernel then we call the local
728 * interrupt as well. Thus we cannot inline the local irq ... ]
730 void smp_apic_timer_interrupt(struct pt_regs *regs)
732 struct pt_regs *old_regs = set_irq_regs(regs);
735 * NOTE! We'd better ACK the irq immediately,
736 * because timer handling can be slow.
740 * update_process_times() expects us to have done irq_enter().
741 * Besides, if we don't timer interrupts ignore the global
742 * interrupt lock, which is the WrongThing (tm) to do.
748 local_apic_timer_interrupt();
751 set_irq_regs(old_regs);
754 int setup_profiling_timer(unsigned int multiplier)
760 * Local APIC start and shutdown
764 * clear_local_APIC - shutdown the local APIC
766 * This is called, when a CPU is disabled and before rebooting, so the state of
767 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
768 * leftovers during boot.
770 void clear_local_APIC(void)
775 /* APIC hasn't been mapped yet */
779 maxlvt = lapic_get_maxlvt();
781 * Masking an LVT entry can trigger a local APIC error
782 * if the vector is zero. Mask LVTERR first to prevent this.
785 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
786 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
789 * Careful: we have to set masks only first to deassert
790 * any level-triggered sources.
792 v = apic_read(APIC_LVTT);
793 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
794 v = apic_read(APIC_LVT0);
795 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
796 v = apic_read(APIC_LVT1);
797 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
799 v = apic_read(APIC_LVTPC);
800 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
803 /* lets not touch this if we didn't frob it */
804 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
806 v = apic_read(APIC_LVTTHMR);
807 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
811 * Clean APIC state for other OSs:
813 apic_write(APIC_LVTT, APIC_LVT_MASKED);
814 apic_write(APIC_LVT0, APIC_LVT_MASKED);
815 apic_write(APIC_LVT1, APIC_LVT_MASKED);
817 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
819 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
821 /* Integrated APIC (!82489DX) ? */
822 if (lapic_is_integrated()) {
824 /* Clear ESR due to Pentium errata 3AP and 11AP */
825 apic_write(APIC_ESR, 0);
831 * disable_local_APIC - clear and disable the local APIC
833 void disable_local_APIC(void)
840 * Disable APIC (implies clearing of registers
843 value = apic_read(APIC_SPIV);
844 value &= ~APIC_SPIV_APIC_ENABLED;
845 apic_write(APIC_SPIV, value);
849 * When LAPIC was disabled by the BIOS and enabled by the kernel,
850 * restore the disabled state.
852 if (enabled_via_apicbase) {
855 rdmsr(MSR_IA32_APICBASE, l, h);
856 l &= ~MSR_IA32_APICBASE_ENABLE;
857 wrmsr(MSR_IA32_APICBASE, l, h);
863 * If Linux enabled the LAPIC against the BIOS default disable it down before
864 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
865 * not power-off. Additionally clear all LVT entries before disable_local_APIC
866 * for the case where Linux didn't enable the LAPIC.
868 void lapic_shutdown(void)
875 local_irq_save(flags);
878 if (!enabled_via_apicbase)
882 disable_local_APIC();
885 local_irq_restore(flags);
889 * This is to verify that we're looking at a real local APIC.
890 * Check these against your board if the CPUs aren't getting
891 * started for no apparent reason.
893 int __init verify_local_APIC(void)
895 unsigned int reg0, reg1;
898 * The version register is read-only in a real APIC.
900 reg0 = apic_read(APIC_LVR);
901 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
902 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
903 reg1 = apic_read(APIC_LVR);
904 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
907 * The two version reads above should print the same
908 * numbers. If the second one is different, then we
909 * poke at a non-APIC.
915 * Check if the version looks reasonably.
917 reg1 = GET_APIC_VERSION(reg0);
918 if (reg1 == 0x00 || reg1 == 0xff)
920 reg1 = lapic_get_maxlvt();
921 if (reg1 < 0x02 || reg1 == 0xff)
925 * The ID register is read/write in a real APIC.
927 reg0 = apic_read(APIC_ID);
928 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
929 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
930 reg1 = apic_read(APIC_ID);
931 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
932 apic_write(APIC_ID, reg0);
933 if (reg1 != (reg0 ^ APIC_ID_MASK))
937 * The next two are just to see if we have sane values.
938 * They're only really relevant if we're in Virtual Wire
939 * compatibility mode, but most boxes are anymore.
941 reg0 = apic_read(APIC_LVT0);
942 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
943 reg1 = apic_read(APIC_LVT1);
944 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
950 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
952 void __init sync_Arb_IDs(void)
955 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
958 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
964 apic_wait_icr_idle();
966 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
967 apic_write(APIC_ICR, APIC_DEST_ALLINC |
968 APIC_INT_LEVELTRIG | APIC_DM_INIT);
972 * An initial setup of the virtual wire mode.
974 void __init init_bsp_APIC(void)
979 * Don't do the setup now if we have a SMP BIOS as the
980 * through-I/O-APIC virtual wire mode might be active.
982 if (smp_found_config || !cpu_has_apic)
986 * Do not trust the local APIC being empty at bootup.
993 value = apic_read(APIC_SPIV);
994 value &= ~APIC_VECTOR_MASK;
995 value |= APIC_SPIV_APIC_ENABLED;
998 /* This bit is reserved on P4/Xeon and should be cleared */
999 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1000 (boot_cpu_data.x86 == 15))
1001 value &= ~APIC_SPIV_FOCUS_DISABLED;
1004 value |= APIC_SPIV_FOCUS_DISABLED;
1005 value |= SPURIOUS_APIC_VECTOR;
1006 apic_write(APIC_SPIV, value);
1009 * Set up the virtual wire mode.
1011 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1012 value = APIC_DM_NMI;
1013 if (!lapic_is_integrated()) /* 82489DX */
1014 value |= APIC_LVT_LEVEL_TRIGGER;
1015 apic_write(APIC_LVT1, value);
1018 static void __cpuinit lapic_setup_esr(void)
1020 unsigned long oldvalue, value, maxlvt;
1021 if (lapic_is_integrated() && !esr_disable) {
1024 * Something untraceable is creating bad interrupts on
1025 * secondary quads ... for the moment, just leave the
1026 * ESR disabled - we can't do anything useful with the
1027 * errors anyway - mbligh
1029 printk(KERN_INFO "Leaving ESR disabled.\n");
1033 maxlvt = lapic_get_maxlvt();
1034 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1035 apic_write(APIC_ESR, 0);
1036 oldvalue = apic_read(APIC_ESR);
1038 /* enables sending errors */
1039 value = ERROR_APIC_VECTOR;
1040 apic_write(APIC_LVTERR, value);
1042 * spec says clear errors after enabling vector.
1045 apic_write(APIC_ESR, 0);
1046 value = apic_read(APIC_ESR);
1047 if (value != oldvalue)
1048 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1049 "vector: 0x%08lx after: 0x%08lx\n",
1052 printk(KERN_INFO "No ESR for 82489DX.\n");
1058 * setup_local_APIC - setup the local APIC
1060 void __cpuinit setup_local_APIC(void)
1065 #ifdef CONFIG_X86_32
1066 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1068 apic_write(APIC_ESR, 0);
1069 apic_write(APIC_ESR, 0);
1070 apic_write(APIC_ESR, 0);
1071 apic_write(APIC_ESR, 0);
1078 * Double-check whether this APIC is really registered.
1079 * This is meaningless in clustered apic mode, so we skip it.
1081 if (!apic_id_registered())
1085 * Intel recommends to set DFR, LDR and TPR before enabling
1086 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1087 * document number 292116). So here it goes...
1092 * Set Task Priority to 'accept all'. We never change this
1095 value = apic_read(APIC_TASKPRI);
1096 value &= ~APIC_TPRI_MASK;
1097 apic_write(APIC_TASKPRI, value);
1100 * After a crash, we no longer service the interrupts and a pending
1101 * interrupt from previous kernel might still have ISR bit set.
1103 * Most probably by now CPU has serviced that pending interrupt and
1104 * it might not have done the ack_APIC_irq() because it thought,
1105 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1106 * does not clear the ISR bit and cpu thinks it has already serivced
1107 * the interrupt. Hence a vector might get locked. It was noticed
1108 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1110 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1111 value = apic_read(APIC_ISR + i*0x10);
1112 for (j = 31; j >= 0; j--) {
1119 * Now that we are all set up, enable the APIC
1121 value = apic_read(APIC_SPIV);
1122 value &= ~APIC_VECTOR_MASK;
1126 value |= APIC_SPIV_APIC_ENABLED;
1128 #ifdef CONFIG_X86_32
1130 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1131 * certain networking cards. If high frequency interrupts are
1132 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1133 * entry is masked/unmasked at a high rate as well then sooner or
1134 * later IOAPIC line gets 'stuck', no more interrupts are received
1135 * from the device. If focus CPU is disabled then the hang goes
1138 * [ This bug can be reproduced easily with a level-triggered
1139 * PCI Ne2000 networking cards and PII/PIII processors, dual
1143 * Actually disabling the focus CPU check just makes the hang less
1144 * frequent as it makes the interrupt distributon model be more
1145 * like LRU than MRU (the short-term load is more even across CPUs).
1146 * See also the comment in end_level_ioapic_irq(). --macro
1150 * - enable focus processor (bit==0)
1151 * - 64bit mode always use processor focus
1152 * so no need to set it
1154 value &= ~APIC_SPIV_FOCUS_DISABLED;
1158 * Set spurious IRQ vector
1160 value |= SPURIOUS_APIC_VECTOR;
1161 apic_write(APIC_SPIV, value);
1164 * Set up LVT0, LVT1:
1166 * set up through-local-APIC on the BP's LINT0. This is not
1167 * strictly necessary in pure symmetric-IO mode, but sometimes
1168 * we delegate interrupts to the 8259A.
1171 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1173 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1174 if (!smp_processor_id() && (pic_mode || !value)) {
1175 value = APIC_DM_EXTINT;
1176 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1177 smp_processor_id());
1179 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1180 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1181 smp_processor_id());
1183 apic_write(APIC_LVT0, value);
1186 * only the BP should see the LINT1 NMI signal, obviously.
1188 if (!smp_processor_id())
1189 value = APIC_DM_NMI;
1191 value = APIC_DM_NMI | APIC_LVT_MASKED;
1192 if (!lapic_is_integrated()) /* 82489DX */
1193 value |= APIC_LVT_LEVEL_TRIGGER;
1194 apic_write(APIC_LVT1, value);
1199 void __cpuinit end_local_APIC_setup(void)
1203 #ifdef CONFIG_X86_32
1206 /* Disable the local apic timer */
1207 value = apic_read(APIC_LVTT);
1208 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1209 apic_write(APIC_LVTT, value);
1213 setup_apic_nmi_watchdog(NULL);
1218 * Detect and initialize APIC
1220 static int __init detect_init_APIC(void)
1224 /* Disabled by kernel option? */
1228 switch (boot_cpu_data.x86_vendor) {
1229 case X86_VENDOR_AMD:
1230 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1231 (boot_cpu_data.x86 == 15))
1234 case X86_VENDOR_INTEL:
1235 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1236 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1243 if (!cpu_has_apic) {
1245 * Over-ride BIOS and try to enable the local APIC only if
1246 * "lapic" specified.
1248 if (!force_enable_local_apic) {
1249 printk(KERN_INFO "Local APIC disabled by BIOS -- "
1250 "you can enable it with \"lapic\"\n");
1254 * Some BIOSes disable the local APIC in the APIC_BASE
1255 * MSR. This can only be done in software for Intel P6 or later
1256 * and AMD K7 (Model > 1) or later.
1258 rdmsr(MSR_IA32_APICBASE, l, h);
1259 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1261 "Local APIC disabled by BIOS -- reenabling.\n");
1262 l &= ~MSR_IA32_APICBASE_BASE;
1263 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1264 wrmsr(MSR_IA32_APICBASE, l, h);
1265 enabled_via_apicbase = 1;
1269 * The APIC feature bit should now be enabled
1272 features = cpuid_edx(1);
1273 if (!(features & (1 << X86_FEATURE_APIC))) {
1274 printk(KERN_WARNING "Could not enable APIC!\n");
1277 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1278 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1280 /* The BIOS may have set up the APIC at some other address */
1281 rdmsr(MSR_IA32_APICBASE, l, h);
1282 if (l & MSR_IA32_APICBASE_ENABLE)
1283 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1285 printk(KERN_INFO "Found and enabled local APIC!\n");
1292 printk(KERN_INFO "No local APIC present or hardware disabled\n");
1296 #ifdef CONFIG_X86_64
1297 void __init early_init_lapic_mapping(void)
1299 unsigned long phys_addr;
1302 * If no local APIC can be found then go out
1303 * : it means there is no mpatable and MADT
1305 if (!smp_found_config)
1308 phys_addr = mp_lapic_addr;
1310 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1311 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1312 APIC_BASE, phys_addr);
1315 * Fetch the APIC ID of the BSP in case we have a
1316 * default configuration (or the MP table is broken).
1318 boot_cpu_physical_apicid = read_apic_id();
1323 * init_apic_mappings - initialize APIC mappings
1325 void __init init_apic_mappings(void)
1328 * If no local APIC can be found then set up a fake all
1329 * zeroes page to simulate the local APIC and another
1330 * one for the IO-APIC.
1332 if (!smp_found_config && detect_init_APIC()) {
1333 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1334 apic_phys = __pa(apic_phys);
1336 apic_phys = mp_lapic_addr;
1338 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1339 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1340 APIC_BASE, apic_phys);
1343 * Fetch the APIC ID of the BSP in case we have a
1344 * default configuration (or the MP table is broken).
1346 if (boot_cpu_physical_apicid == -1U)
1347 boot_cpu_physical_apicid = read_apic_id();
1351 * This initializes the IO-APIC and APIC hardware if this is
1354 int apic_version[MAX_APICS];
1356 int __init APIC_init_uniprocessor(void)
1358 #ifdef CONFIG_X86_64
1360 printk(KERN_INFO "Apic disabled\n");
1363 if (!cpu_has_apic) {
1365 printk(KERN_INFO "Apic disabled by BIOS\n");
1369 if (!smp_found_config && !cpu_has_apic)
1373 * Complain if the BIOS pretends there is one.
1375 if (!cpu_has_apic &&
1376 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1377 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1378 boot_cpu_physical_apicid);
1379 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1387 #ifdef CONFIG_X86_64
1388 setup_apic_routing();
1390 verify_local_APIC();
1393 #ifdef CONFIG_X86_64
1394 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1397 * Hack: In case of kdump, after a crash, kernel might be booting
1398 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1399 * might be zero if read from MP tables. Get it from LAPIC.
1401 # ifdef CONFIG_CRASH_DUMP
1402 boot_cpu_physical_apicid = read_apic_id();
1405 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1408 #ifdef CONFIG_X86_64
1410 * Now enable IO-APICs, actually call clear_IO_APIC
1411 * We need clear_IO_APIC before enabling vector on BP
1413 if (!skip_ioapic_setup && nr_ioapics)
1417 #ifdef CONFIG_X86_IO_APIC
1418 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1420 localise_nmi_watchdog();
1421 end_local_APIC_setup();
1423 #ifdef CONFIG_X86_IO_APIC
1424 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1426 # ifdef CONFIG_X86_64
1432 #ifdef CONFIG_X86_64
1433 setup_boot_APIC_clock();
1434 check_nmi_watchdog();
1443 * Local APIC interrupts
1447 * This interrupt should _never_ happen with our APIC/SMP architecture
1449 void smp_spurious_interrupt(struct pt_regs *regs)
1455 * Check if this really is a spurious interrupt and ACK it
1456 * if it is a vectored one. Just in case...
1457 * Spurious interrupts should not be ACKed.
1459 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1460 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1463 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1464 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
1465 "should never happen.\n", smp_processor_id());
1466 __get_cpu_var(irq_stat).irq_spurious_count++;
1471 * This interrupt should never happen with our APIC/SMP architecture
1473 void smp_error_interrupt(struct pt_regs *regs)
1475 unsigned long v, v1;
1478 /* First tickle the hardware, only then report what went on. -- REW */
1479 v = apic_read(APIC_ESR);
1480 apic_write(APIC_ESR, 0);
1481 v1 = apic_read(APIC_ESR);
1483 atomic_inc(&irq_err_count);
1485 /* Here is what the APIC error bits mean:
1488 2: Send accept error
1489 3: Receive accept error
1491 5: Send illegal vector
1492 6: Received illegal vector
1493 7: Illegal register address
1495 printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
1496 smp_processor_id(), v , v1);
1501 * connect_bsp_APIC - attach the APIC to the interrupt system
1503 void __init connect_bsp_APIC(void)
1505 #ifdef CONFIG_X86_32
1508 * Do not trust the local APIC being empty at bootup.
1512 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1513 * local APIC to INT and NMI lines.
1515 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1516 "enabling APIC mode.\n");
1525 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1526 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1528 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1531 void disconnect_bsp_APIC(int virt_wire_setup)
1535 #ifdef CONFIG_X86_32
1538 * Put the board back into PIC mode (has an effect only on
1539 * certain older boards). Note that APIC interrupts, including
1540 * IPIs, won't work beyond this point! The only exception are
1543 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1544 "entering PIC mode.\n");
1551 /* Go back to Virtual Wire compatibility mode */
1553 /* For the spurious interrupt use vector F, and enable it */
1554 value = apic_read(APIC_SPIV);
1555 value &= ~APIC_VECTOR_MASK;
1556 value |= APIC_SPIV_APIC_ENABLED;
1558 apic_write(APIC_SPIV, value);
1560 if (!virt_wire_setup) {
1562 * For LVT0 make it edge triggered, active high,
1563 * external and enabled
1565 value = apic_read(APIC_LVT0);
1566 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1567 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1568 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1569 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1570 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1571 apic_write(APIC_LVT0, value);
1574 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1578 * For LVT1 make it edge triggered, active high,
1581 value = apic_read(APIC_LVT1);
1582 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1583 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1584 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1585 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1586 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1587 apic_write(APIC_LVT1, value);
1590 void __cpuinit generic_processor_info(int apicid, int version)
1598 if (version == 0x0) {
1599 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
1600 "fixing up to 0x10. (tell your hw vendor)\n",
1604 apic_version[apicid] = version;
1606 if (num_processors >= NR_CPUS) {
1607 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1608 " Processor ignored.\n", NR_CPUS);
1613 cpus_complement(tmp_map, cpu_present_map);
1614 cpu = first_cpu(tmp_map);
1616 physid_set(apicid, phys_cpu_present_map);
1617 if (apicid == boot_cpu_physical_apicid) {
1619 * x86_bios_cpu_apicid is required to have processors listed
1620 * in same order as logical cpu numbers. Hence the first
1621 * entry is BSP, and so on.
1625 if (apicid > max_physical_apicid)
1626 max_physical_apicid = apicid;
1628 #ifdef CONFIG_X86_32
1630 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1631 * but we need to work other dependencies like SMP_SUSPEND etc
1632 * before this can be done without some confusion.
1633 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1634 * - Ashok Raj <ashok.raj@intel.com>
1636 if (max_physical_apicid >= 8) {
1637 switch (boot_cpu_data.x86_vendor) {
1638 case X86_VENDOR_INTEL:
1639 if (!APIC_XAPIC(version)) {
1643 /* If P4 and above fall through */
1644 case X86_VENDOR_AMD:
1650 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1651 /* are we being called early in kernel startup? */
1652 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1653 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1654 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1656 cpu_to_apicid[cpu] = apicid;
1657 bios_cpu_apicid[cpu] = apicid;
1659 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1660 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1664 cpu_set(cpu, cpu_possible_map);
1665 cpu_set(cpu, cpu_present_map);
1668 #ifdef CONFIG_X86_64
1669 int hard_smp_processor_id(void)
1671 return read_apic_id();
1682 * 'active' is true if the local APIC was enabled by us and
1683 * not the BIOS; this signifies that we are also responsible
1684 * for disabling it before entering apm/acpi suspend
1687 /* r/w apic fields */
1688 unsigned int apic_id;
1689 unsigned int apic_taskpri;
1690 unsigned int apic_ldr;
1691 unsigned int apic_dfr;
1692 unsigned int apic_spiv;
1693 unsigned int apic_lvtt;
1694 unsigned int apic_lvtpc;
1695 unsigned int apic_lvt0;
1696 unsigned int apic_lvt1;
1697 unsigned int apic_lvterr;
1698 unsigned int apic_tmict;
1699 unsigned int apic_tdcr;
1700 unsigned int apic_thmr;
1703 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1705 unsigned long flags;
1708 if (!apic_pm_state.active)
1711 maxlvt = lapic_get_maxlvt();
1713 apic_pm_state.apic_id = apic_read(APIC_ID);
1714 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1715 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1716 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1717 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1718 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1720 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1721 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1722 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1723 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1724 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1725 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1726 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1728 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1731 local_irq_save(flags);
1732 disable_local_APIC();
1733 local_irq_restore(flags);
1737 static int lapic_resume(struct sys_device *dev)
1740 unsigned long flags;
1743 if (!apic_pm_state.active)
1746 maxlvt = lapic_get_maxlvt();
1748 local_irq_save(flags);
1752 * Make sure the APICBASE points to the right address
1754 * FIXME! This will be wrong if we ever support suspend on
1755 * SMP! We'll need to do this as part of the CPU restore!
1757 rdmsr(MSR_IA32_APICBASE, l, h);
1758 l &= ~MSR_IA32_APICBASE_BASE;
1759 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1760 wrmsr(MSR_IA32_APICBASE, l, h);
1763 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1764 apic_write(APIC_ID, apic_pm_state.apic_id);
1765 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1766 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1767 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1768 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1769 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1770 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1771 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1773 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1776 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1777 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1778 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1779 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1780 apic_write(APIC_ESR, 0);
1781 apic_read(APIC_ESR);
1782 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1783 apic_write(APIC_ESR, 0);
1784 apic_read(APIC_ESR);
1786 local_irq_restore(flags);
1792 * This device has no shutdown method - fully functioning local APICs
1793 * are needed on every CPU up until machine_halt/restart/poweroff.
1796 static struct sysdev_class lapic_sysclass = {
1798 .resume = lapic_resume,
1799 .suspend = lapic_suspend,
1802 static struct sys_device device_lapic = {
1804 .cls = &lapic_sysclass,
1807 static void __cpuinit apic_pm_activate(void)
1809 apic_pm_state.active = 1;
1812 static int __init init_lapic_sysfs(void)
1818 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1820 error = sysdev_class_register(&lapic_sysclass);
1822 error = sysdev_register(&device_lapic);
1825 device_initcall(init_lapic_sysfs);
1827 #else /* CONFIG_PM */
1829 static void apic_pm_activate(void) { }
1831 #endif /* CONFIG_PM */
1833 #ifdef CONFIG_X86_64
1835 * apic_is_clustered_box() -- Check if we can expect good TSC
1837 * Thus far, the major user of this is IBM's Summit2 series:
1839 * Clustered boxes may have unsynced TSC problems if they are
1840 * multi-chassis. Use available data to take a good guess.
1841 * If in doubt, go HPET.
1843 __cpuinit int apic_is_clustered_box(void)
1845 int i, clusters, zeros;
1847 u16 *bios_cpu_apicid;
1848 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1851 * there is not this kind of box with AMD CPU yet.
1852 * Some AMD box with quadcore cpu and 8 sockets apicid
1853 * will be [4, 0x23] or [8, 0x27] could be thought to
1854 * vsmp box still need checking...
1856 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
1859 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1860 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1862 for (i = 0; i < NR_CPUS; i++) {
1863 /* are we being called early in kernel startup? */
1864 if (bios_cpu_apicid) {
1865 id = bios_cpu_apicid[i];
1867 else if (i < nr_cpu_ids) {
1869 id = per_cpu(x86_bios_cpu_apicid, i);
1876 if (id != BAD_APICID)
1877 __set_bit(APIC_CLUSTERID(id), clustermap);
1880 /* Problem: Partially populated chassis may not have CPUs in some of
1881 * the APIC clusters they have been allocated. Only present CPUs have
1882 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1883 * Since clusters are allocated sequentially, count zeros only if
1884 * they are bounded by ones.
1888 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1889 if (test_bit(i, clustermap)) {
1890 clusters += 1 + zeros;
1896 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1897 * not guaranteed to be synced between boards
1899 if (is_vsmp_box() && clusters > 1)
1903 * If clusters > 2, then should be multi-chassis.
1904 * May have to revisit this when multi-core + hyperthreaded CPUs come
1905 * out, but AFAIK this will work even for them.
1907 return (clusters > 2);
1912 * APIC command line parameters
1914 static int __init setup_disableapic(char *arg)
1917 setup_clear_cpu_cap(X86_FEATURE_APIC);
1920 early_param("disableapic", setup_disableapic);
1922 /* same as disableapic, for compatibility */
1923 static int __init setup_nolapic(char *arg)
1925 return setup_disableapic(arg);
1927 early_param("nolapic", setup_nolapic);
1929 static int __init parse_lapic_timer_c2_ok(char *arg)
1931 local_apic_timer_c2_ok = 1;
1934 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1936 static int __init parse_disable_apic_timer(char *arg)
1938 disable_apic_timer = 1;
1941 early_param("noapictimer", parse_disable_apic_timer);
1943 static int __init parse_nolapic_timer(char *arg)
1945 disable_apic_timer = 1;
1948 early_param("nolapic_timer", parse_nolapic_timer);
1950 static int __init apic_set_verbosity(char *arg)
1953 #ifdef CONFIG_X86_64
1954 skip_ioapic_setup = 0;
1961 if (strcmp("debug", arg) == 0)
1962 apic_verbosity = APIC_DEBUG;
1963 else if (strcmp("verbose", arg) == 0)
1964 apic_verbosity = APIC_VERBOSE;
1966 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
1967 " use apic=verbose or apic=debug\n", arg);
1973 early_param("apic", apic_set_verbosity);
1975 static int __init lapic_insert_resource(void)
1980 /* Put local APIC into the resource map. */
1981 lapic_resource.start = apic_phys;
1982 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1983 insert_resource(&iomem_resource, &lapic_resource);
1989 * need call insert after e820_reserve_resources()
1990 * that is using request_resource
1992 late_initcall(lapic_insert_resource);