git.oblomov.eu Git - linux-2.6/blob - drivers/net/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe_common.h"
  33 #include "ixgbe_phy.h"
  34
  35 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  42 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  45 static bool ixgbe_get_i2c_data(u32 *i2cctl);
  46 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
  47 static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
  48 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
  49 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
  50
  51 /**
  52  *  ixgbe_identify_phy_generic - Get physical layer module
  53  *  @hw: pointer to hardware structure
  54  *
  55  *  Determines the physical layer module found on the current adapter.
  56  **/
  57 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  58 {
  59         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  60         u32 phy_addr;
  61
  62         if (hw->phy.type == ixgbe_phy_unknown) {
  63                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  64                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
  65                                 hw->phy.addr = phy_addr;
  66                                 ixgbe_get_phy_id(hw);
  67                                 hw->phy.type =
  68                                         ixgbe_get_phy_type_from_id(hw->phy.id);
  69                                 status = 0;
  70                                 break;
  71                         }
  72                 }
  73         } else {
  74                 status = 0;
  75         }
  76
  77         return status;
  78 }
  79
  80 /**
  81  *  ixgbe_validate_phy_addr - Determines phy address is valid
  82  *  @hw: pointer to hardware structure
  83  *
  84  **/
  85 static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
  86 {
  87         u16 phy_id = 0;
  88         bool valid = false;
  89
  90         hw->phy.addr = phy_addr;
  91         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
  92                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
  93
  94         if (phy_id != 0xFFFF && phy_id != 0x0)
  95                 valid = true;
  96
  97         return valid;
  98 }
  99
 100 /**
 101  *  ixgbe_get_phy_id - Get the phy type
 102  *  @hw: pointer to hardware structure
 103  *
 104  **/
 105 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 106 {
 107         u32 status;
 108         u16 phy_id_high = 0;
 109         u16 phy_id_low = 0;
 110
 111         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 112                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 113                                       &phy_id_high);
 114
 115         if (status == 0) {
 116                 hw->phy.id = (u32)(phy_id_high << 16);
 117                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 118                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 119                                               &phy_id_low);
 120                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 121                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 122         }
 123         return status;
 124 }
 125
 126 /**
 127  *  ixgbe_get_phy_type_from_id - Get the phy type
 128  *  @hw: pointer to hardware structure
 129  *
 130  **/
 131 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 132 {
 133         enum ixgbe_phy_type phy_type;
 134
 135         switch (phy_id) {
 136         case TN1010_PHY_ID:
 137                 phy_type = ixgbe_phy_tn;
 138                 break;
 139         case QT2022_PHY_ID:
 140                 phy_type = ixgbe_phy_qt;
 141                 break;
 142         case ATH_PHY_ID:
 143                 phy_type = ixgbe_phy_nl;
 144                 break;
 145         default:
 146                 phy_type = ixgbe_phy_unknown;
 147                 break;
 148         }
 149
 150         return phy_type;
 151 }
 152
 153 /**
 154  *  ixgbe_reset_phy_generic - Performs a PHY reset
 155  *  @hw: pointer to hardware structure
 156  **/
 157 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 158 {
 159         /*
 160          * Perform soft PHY reset to the PHY_XS.
 161          * This will cause a soft reset to the PHY
 162          */
 163         return hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 164                                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
 165                                      IXGBE_MDIO_PHY_XS_RESET);
 166 }
 167
 168 /**
 169  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 170  *  @hw: pointer to hardware structure
 171  *  @reg_addr: 32 bit address of PHY register to read
 172  *  @phy_data: Pointer to read data from PHY register
 173  **/
 174 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 175                                u32 device_type, u16 *phy_data)
 176 {
 177         u32 command;
 178         u32 i;
 179         u32 data;
 180         s32 status = 0;
 181         u16 gssr;
 182
 183         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 184                 gssr = IXGBE_GSSR_PHY1_SM;
 185         else
 186                 gssr = IXGBE_GSSR_PHY0_SM;
 187
 188         if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
 189                 status = IXGBE_ERR_SWFW_SYNC;
 190
 191         if (status == 0) {
 192                 /* Setup and write the address cycle command */
 193                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 194                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 195                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 196                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 197
 198                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 199
 200                 /*
 201                  * Check every 10 usec to see if the address cycle completed.
 202                  * The MDI Command bit will clear when the operation is
 203                  * complete
 204                  */
 205                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 206                         udelay(10);
 207
 208                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 209
 210                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 211                                 break;
 212                 }
 213
 214                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 215                         hw_dbg(hw, "PHY address command did not complete.\n");
 216                         status = IXGBE_ERR_PHY;
 217                 }
 218
 219                 if (status == 0) {
 220                         /*
 221                          * Address cycle complete, setup and write the read
 222                          * command
 223                          */
 224                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 225                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 226                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 227                                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 228
 229                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 230
 231                         /*
 232                          * Check every 10 usec to see if the address cycle
 233                          * completed. The MDI Command bit will clear when the
 234                          * operation is complete
 235                          */
 236                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 237                                 udelay(10);
 238
 239                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 240
 241                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 242                                         break;
 243                         }
 244
 245                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 246                                 hw_dbg(hw, "PHY read command didn't complete\n");
 247                                 status = IXGBE_ERR_PHY;
 248                         } else {
 249                                 /*
 250                                  * Read operation is complete.  Get the data
 251                                  * from MSRWD
 252                                  */
 253                                 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 254                                 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 255                                 *phy_data = (u16)(data);
 256                         }
 257                 }
 258
 259                 ixgbe_release_swfw_sync(hw, gssr);
 260         }
 261
 262         return status;
 263 }
 264
 265 /**
 266  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 267  *  @hw: pointer to hardware structure
 268  *  @reg_addr: 32 bit PHY register to write
 269  *  @device_type: 5 bit device type
 270  *  @phy_data: Data to write to the PHY register
 271  **/
 272 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 273                                 u32 device_type, u16 phy_data)
 274 {
 275         u32 command;
 276         u32 i;
 277         s32 status = 0;
 278         u16 gssr;
 279
 280         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 281                 gssr = IXGBE_GSSR_PHY1_SM;
 282         else
 283                 gssr = IXGBE_GSSR_PHY0_SM;
 284
 285         if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
 286                 status = IXGBE_ERR_SWFW_SYNC;
 287
 288         if (status == 0) {
 289                 /* Put the data in the MDI single read and write data register*/
 290                 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 291
 292                 /* Setup and write the address cycle command */
 293                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 294                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 295                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 296                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 297
 298                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 299
 300                 /*
 301                  * Check every 10 usec to see if the address cycle completed.
 302                  * The MDI Command bit will clear when the operation is
 303                  * complete
 304                  */
 305                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 306                         udelay(10);
 307
 308                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 309
 310                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 311                                 break;
 312                 }
 313
 314                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 315                         hw_dbg(hw, "PHY address cmd didn't complete\n");
 316                         status = IXGBE_ERR_PHY;
 317                 }
 318
 319                 if (status == 0) {
 320                         /*
 321                          * Address cycle complete, setup and write the write
 322                          * command
 323                          */
 324                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 325                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 326                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 327                                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 328
 329                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 330
 331                         /*
 332                          * Check every 10 usec to see if the address cycle
 333                          * completed. The MDI Command bit will clear when the
 334                          * operation is complete
 335                          */
 336                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 337                                 udelay(10);
 338
 339                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 340
 341                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 342                                         break;
 343                         }
 344
 345                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 346                                 hw_dbg(hw, "PHY address cmd didn't complete\n");
 347                                 status = IXGBE_ERR_PHY;
 348                         }
 349                 }
 350
 351                 ixgbe_release_swfw_sync(hw, gssr);
 352         }
 353
 354         return status;
 355 }
 356
 357 /**
 358  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 359  *  @hw: pointer to hardware structure
 360  *
 361  *  Restart autonegotiation and PHY and waits for completion.
 362  **/
 363 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 364 {
 365         s32 status = IXGBE_NOT_IMPLEMENTED;
 366         u32 time_out;
 367         u32 max_time_out = 10;
 368         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 369
 370         /*
 371          * Set advertisement settings in PHY based on autoneg_advertised
 372          * settings. If autoneg_advertised = 0, then advertise default values
 373          * tnx devices cannot be "forced" to a autoneg 10G and fail.  But can
 374          * for a 1G.
 375          */
 376         hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
 377                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 378
 379         if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
 380                 autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */
 381         else
 382                 autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */
 383
 384         hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
 385                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 386
 387         /* Restart PHY autonegotiation and wait for completion */
 388         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 389                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 390
 391         autoneg_reg |= IXGBE_MII_RESTART;
 392
 393         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 394                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 395
 396         /* Wait for autonegotiation to finish */
 397         for (time_out = 0; time_out < max_time_out; time_out++) {
 398                 udelay(10);
 399                 /* Restart PHY autonegotiation and wait for completion */
 400                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 401                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 402                                               &autoneg_reg);
 403
 404                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 405                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
 406                         status = 0;
 407                         break;
 408                 }
 409         }
 410
 411         if (time_out == max_time_out)
 412                 status = IXGBE_ERR_LINK_SETUP;
 413
 414         return status;
 415 }
 416
 417 /**
 418  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 419  *  @hw: pointer to hardware structure
 420  *  @speed: new link speed
 421  *  @autoneg: true if autonegotiation enabled
 422  **/
 423 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 424                                        ixgbe_link_speed speed,
 425                                        bool autoneg,
 426                                        bool autoneg_wait_to_complete)
 427 {
 428
 429         /*
 430          * Clear autoneg_advertised and set new values based on input link
 431          * speed.
 432          */
 433         hw->phy.autoneg_advertised = 0;
 434
 435         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 436                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 437
 438         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 439                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 440
 441         /* Setup link based on the new speed settings */
 442         hw->phy.ops.setup_link(hw);
 443
 444         return 0;
 445 }
 446
 447 /**
 448  *  ixgbe_reset_phy_nl - Performs a PHY reset
 449  *  @hw: pointer to hardware structure
 450  **/
 451 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 452 {
 453         u16 phy_offset, control, eword, edata, block_crc;
 454         bool end_data = false;
 455         u16 list_offset, data_offset;
 456         u16 phy_data = 0;
 457         s32 ret_val = 0;
 458         u32 i;
 459
 460         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 461                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 462
 463         /* reset the PHY and poll for completion */
 464         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 465                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 466                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
 467
 468         for (i = 0; i < 100; i++) {
 469                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 470                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 471                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
 472                         break;
 473                 msleep(10);
 474         }
 475
 476         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
 477                 hw_dbg(hw, "PHY reset did not complete.\n");
 478                 ret_val = IXGBE_ERR_PHY;
 479                 goto out;
 480         }
 481
 482         /* Get init offsets */
 483         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 484                                                       &data_offset);
 485         if (ret_val != 0)
 486                 goto out;
 487
 488         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 489         data_offset++;
 490         while (!end_data) {
 491                 /*
 492                  * Read control word from PHY init contents offset
 493                  */
 494                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 495                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 496                            IXGBE_CONTROL_SHIFT_NL;
 497                 edata = eword & IXGBE_DATA_MASK_NL;
 498                 switch (control) {
 499                 case IXGBE_DELAY_NL:
 500                         data_offset++;
 501                         hw_dbg(hw, "DELAY: %d MS\n", edata);
 502                         msleep(edata);
 503                         break;
 504                 case IXGBE_DATA_NL:
 505                         hw_dbg(hw, "DATA:  \n");
 506                         data_offset++;
 507                         hw->eeprom.ops.read(hw, data_offset++,
 508                                             &phy_offset);
 509                         for (i = 0; i < edata; i++) {
 510                                 hw->eeprom.ops.read(hw, data_offset, &eword);
 511                                 hw->phy.ops.write_reg(hw, phy_offset,
 512                                                       IXGBE_TWINAX_DEV, eword);
 513                                 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
 514                                        phy_offset);
 515                                 data_offset++;
 516                                 phy_offset++;
 517                         }
 518                         break;
 519                 case IXGBE_CONTROL_NL:
 520                         data_offset++;
 521                         hw_dbg(hw, "CONTROL: \n");
 522                         if (edata == IXGBE_CONTROL_EOL_NL) {
 523                                 hw_dbg(hw, "EOL\n");
 524                                 end_data = true;
 525                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 526                                 hw_dbg(hw, "SOL\n");
 527                         } else {
 528                                 hw_dbg(hw, "Bad control value\n");
 529                                 ret_val = IXGBE_ERR_PHY;
 530                                 goto out;
 531                         }
 532                         break;
 533                 default:
 534                         hw_dbg(hw, "Bad control type\n");
 535                         ret_val = IXGBE_ERR_PHY;
 536                         goto out;
 537                 }
 538         }
 539
 540 out:
 541         return ret_val;
 542 }
 543
 544 /**
 545  *  ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns
 546  *                                      the PHY type.
 547  *  @hw: pointer to hardware structure
 548  *
 549  *  Searches for and indentifies the SFP module.  Assings appropriate PHY type.
 550  **/
 551 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 552 {
 553         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 554         u32 vendor_oui = 0;
 555         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
 556         u8 identifier = 0;
 557         u8 comp_codes_1g = 0;
 558         u8 comp_codes_10g = 0;
 559         u8 oui_bytes[3] = {0, 0, 0};
 560         u8 transmission_media = 0;
 561         u16 enforce_sfp = 0;
 562
 563         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
 564                                              &identifier);
 565
 566         if (status == IXGBE_ERR_SFP_NOT_PRESENT) {
 567                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 568                 goto out;
 569         }
 570
 571         if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
 572                 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
 573                                             &comp_codes_1g);
 574                 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
 575                                             &comp_codes_10g);
 576                 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_TRANSMISSION_MEDIA,
 577                                             &transmission_media);
 578
 579                 /* ID Module
 580                  * =========
 581                  * 0    SFP_DA_CU
 582                  * 1    SFP_SR
 583                  * 2    SFP_LR
 584                  * 3    SFP_DA_CORE0 - 82599-specific
 585                  * 4    SFP_DA_CORE1 - 82599-specific
 586                  * 5    SFP_SR/LR_CORE0 - 82599-specific
 587                  * 6    SFP_SR/LR_CORE1 - 82599-specific
 588                  */
 589                 if (hw->mac.type == ixgbe_mac_82598EB) {
 590                         if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
 591                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
 592                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 593                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
 594                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
 595                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
 596                         else
 597                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 598                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
 599                         if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
 600                                 if (hw->bus.lan_id == 0)
 601                                         hw->phy.sfp_type =
 602                                                      ixgbe_sfp_type_da_cu_core0;
 603                                 else
 604                                         hw->phy.sfp_type =
 605                                                      ixgbe_sfp_type_da_cu_core1;
 606                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 607                                 if (hw->bus.lan_id == 0)
 608                                         hw->phy.sfp_type =
 609                                                       ixgbe_sfp_type_srlr_core0;
 610                                 else
 611                                         hw->phy.sfp_type =
 612                                                       ixgbe_sfp_type_srlr_core1;
 613                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
 614                                 if (hw->bus.lan_id == 0)
 615                                         hw->phy.sfp_type =
 616                                                       ixgbe_sfp_type_srlr_core0;
 617                                 else
 618                                         hw->phy.sfp_type =
 619                                                       ixgbe_sfp_type_srlr_core1;
 620                         else
 621                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 622                 }
 623
 624                 if (hw->phy.sfp_type != stored_sfp_type)
 625                         hw->phy.sfp_setup_needed = true;
 626
 627                 /* Determine if the SFP+ PHY is dual speed or not. */
 628                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
 629                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
 630                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
 631                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
 632                         hw->phy.multispeed_fiber = true;
 633
 634                 /* Determine PHY vendor */
 635                 if (hw->phy.type != ixgbe_phy_nl) {
 636                         hw->phy.id = identifier;
 637                         hw->phy.ops.read_i2c_eeprom(hw,
 638                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
 639                                                     &oui_bytes[0]);
 640                         hw->phy.ops.read_i2c_eeprom(hw,
 641                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
 642                                                     &oui_bytes[1]);
 643                         hw->phy.ops.read_i2c_eeprom(hw,
 644                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
 645                                                     &oui_bytes[2]);
 646
 647                         vendor_oui =
 648                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
 649                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
 650                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
 651
 652                         switch (vendor_oui) {
 653                         case IXGBE_SFF_VENDOR_OUI_TYCO:
 654                                 if (transmission_media &
 655                                     IXGBE_SFF_TWIN_AX_CAPABLE)
 656                                         hw->phy.type = ixgbe_phy_tw_tyco;
 657                                 break;
 658                         case IXGBE_SFF_VENDOR_OUI_FTL:
 659                                 hw->phy.type = ixgbe_phy_sfp_ftl;
 660                                 break;
 661                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
 662                                 hw->phy.type = ixgbe_phy_sfp_avago;
 663                                 break;
 664                         case IXGBE_SFF_VENDOR_OUI_INTEL:
 665                                 hw->phy.type = ixgbe_phy_sfp_intel;
 666                                 break;
 667                         default:
 668                                 if (transmission_media &
 669                                     IXGBE_SFF_TWIN_AX_CAPABLE)
 670                                         hw->phy.type = ixgbe_phy_tw_unknown;
 671                                 else
 672                                         hw->phy.type = ixgbe_phy_sfp_unknown;
 673                                 break;
 674                         }
 675                 }
 676
 677                 /* All DA cables are supported */
 678                 if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE) {
 679                         status = 0;
 680                         goto out;
 681                 }
 682
 683                 /* 1G SFP modules are not supported */
 684                 if (comp_codes_10g == 0) {
 685                         hw->phy.type = ixgbe_phy_sfp_unsupported;
 686                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 687                         goto out;
 688                 }
 689
 690                 /* Anything else 82598-based is supported */
 691                 if (hw->mac.type == ixgbe_mac_82598EB) {
 692                         status = 0;
 693                         goto out;
 694                 }
 695
 696                 /* This is guaranteed to be 82599, no need to check for NULL */
 697                 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
 698                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
 699                         /* Make sure we're a supported PHY type */
 700                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
 701                                 status = 0;
 702                         } else {
 703                                 hw_dbg(hw, "SFP+ module not supported\n");
 704                                 hw->phy.type = ixgbe_phy_sfp_unsupported;
 705                                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 706                         }
 707                 } else {
 708                         status = 0;
 709                 }
 710         }
 711
 712 out:
 713         return status;
 714 }
 715
 716 /**
 717  *  ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see
 718  *  if it supports a given SFP+ module type, if so it returns the offsets to the
 719  *  phy init sequence block.
 720  *  @hw: pointer to hardware structure
 721  *  @list_offset: offset to the SFP ID list
 722  *  @data_offset: offset to the SFP data block
 723  **/
 724 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
 725                                         u16 *list_offset,
 726                                         u16 *data_offset)
 727 {
 728         u16 sfp_id;
 729
 730         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
 731                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 732
 733         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
 734                 return IXGBE_ERR_SFP_NOT_PRESENT;
 735
 736         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
 737             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
 738                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 739
 740         /* Read offset to PHY init contents */
 741         hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
 742
 743         if ((!*list_offset) || (*list_offset == 0xFFFF))
 744                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
 745
 746         /* Shift offset to first ID word */
 747         (*list_offset)++;
 748
 749         /*
 750          * Find the matching SFP ID in the EEPROM
 751          * and program the init sequence
 752          */
 753         hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
 754
 755         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
 756                 if (sfp_id == hw->phy.sfp_type) {
 757                         (*list_offset)++;
 758                         hw->eeprom.ops.read(hw, *list_offset, data_offset);
 759                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
 760                                 hw_dbg(hw, "SFP+ module not supported\n");
 761                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 762                         } else {
 763                                 break;
 764                         }
 765                 } else {
 766                         (*list_offset) += 2;
 767                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
 768                                 return IXGBE_ERR_PHY;
 769                 }
 770         }
 771
 772         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
 773                 hw_dbg(hw, "No matching SFP+ module found\n");
 774                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 775         }
 776
 777         return 0;
 778 }
 779
 780 /**
 781  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
 782  *  @hw: pointer to hardware structure
 783  *  @byte_offset: EEPROM byte offset to read
 784  *  @eeprom_data: value read
 785  *
 786  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
 787  **/
 788 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 789                                   u8 *eeprom_data)
 790 {
 791         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
 792                                          IXGBE_I2C_EEPROM_DEV_ADDR,
 793                                          eeprom_data);
 794 }
 795
 796 /**
 797  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
 798  *  @hw: pointer to hardware structure
 799  *  @byte_offset: EEPROM byte offset to write
 800  *  @eeprom_data: value to write
 801  *
 802  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
 803  **/
 804 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 805                                    u8 eeprom_data)
 806 {
 807         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
 808                                           IXGBE_I2C_EEPROM_DEV_ADDR,
 809                                           eeprom_data);
 810 }
 811
 812 /**
 813  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
 814  *  @hw: pointer to hardware structure
 815  *  @byte_offset: byte offset to read
 816  *  @data: value read
 817  *
 818  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
 819  *  a specified deivce address.
 820  **/
 821 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 822                                 u8 dev_addr, u8 *data)
 823 {
 824         s32 status = 0;
 825         u32 max_retry = 1;
 826         u32 retry = 0;
 827         bool nack = 1;
 828
 829         do {
 830                 ixgbe_i2c_start(hw);
 831
 832                 /* Device Address and write indication */
 833                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
 834                 if (status != 0)
 835                         goto fail;
 836
 837                 status = ixgbe_get_i2c_ack(hw);
 838                 if (status != 0)
 839                         goto fail;
 840
 841                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
 842                 if (status != 0)
 843                         goto fail;
 844
 845                 status = ixgbe_get_i2c_ack(hw);
 846                 if (status != 0)
 847                         goto fail;
 848
 849                 ixgbe_i2c_start(hw);
 850
 851                 /* Device Address and read indication */
 852                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
 853                 if (status != 0)
 854                         goto fail;
 855
 856                 status = ixgbe_get_i2c_ack(hw);
 857                 if (status != 0)
 858                         goto fail;
 859
 860                 status = ixgbe_clock_in_i2c_byte(hw, data);
 861                 if (status != 0)
 862                         goto fail;
 863
 864                 status = ixgbe_clock_out_i2c_bit(hw, nack);
 865                 if (status != 0)
 866                         goto fail;
 867
 868                 ixgbe_i2c_stop(hw);
 869                 break;
 870
 871 fail:
 872                 ixgbe_i2c_bus_clear(hw);
 873                 retry++;
 874                 if (retry < max_retry)
 875                         hw_dbg(hw, "I2C byte read error - Retrying.\n");
 876                 else
 877                         hw_dbg(hw, "I2C byte read error.\n");
 878
 879         } while (retry < max_retry);
 880
 881         return status;
 882 }
 883
 884 /**
 885  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
 886  *  @hw: pointer to hardware structure
 887  *  @byte_offset: byte offset to write
 888  *  @data: value to write
 889  *
 890  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
 891  *  a specified device address.
 892  **/
 893 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 894                                  u8 dev_addr, u8 data)
 895 {
 896         s32 status = 0;
 897         u32 max_retry = 1;
 898         u32 retry = 0;
 899
 900         do {
 901                 ixgbe_i2c_start(hw);
 902
 903                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
 904                 if (status != 0)
 905                         goto fail;
 906
 907                 status = ixgbe_get_i2c_ack(hw);
 908                 if (status != 0)
 909                         goto fail;
 910
 911                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
 912                 if (status != 0)
 913                         goto fail;
 914
 915                 status = ixgbe_get_i2c_ack(hw);
 916                 if (status != 0)
 917                         goto fail;
 918
 919                 status = ixgbe_clock_out_i2c_byte(hw, data);
 920                 if (status != 0)
 921                         goto fail;
 922
 923                 status = ixgbe_get_i2c_ack(hw);
 924                 if (status != 0)
 925                         goto fail;
 926
 927                 ixgbe_i2c_stop(hw);
 928                 break;
 929
 930 fail:
 931                 ixgbe_i2c_bus_clear(hw);
 932                 retry++;
 933                 if (retry < max_retry)
 934                         hw_dbg(hw, "I2C byte write error - Retrying.\n");
 935                 else
 936                         hw_dbg(hw, "I2C byte write error.\n");
 937         } while (retry < max_retry);
 938
 939         return status;
 940 }
 941
 942 /**
 943  *  ixgbe_i2c_start - Sets I2C start condition
 944  *  @hw: pointer to hardware structure
 945  *
 946  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
 947  **/
 948 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
 949 {
 950         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
 951
 952         /* Start condition must begin with data and clock high */
 953         ixgbe_set_i2c_data(hw, &i2cctl, 1);
 954         ixgbe_raise_i2c_clk(hw, &i2cctl);
 955
 956         /* Setup time for start condition (4.7us) */
 957         udelay(IXGBE_I2C_T_SU_STA);
 958
 959         ixgbe_set_i2c_data(hw, &i2cctl, 0);
 960
 961         /* Hold time for start condition (4us) */
 962         udelay(IXGBE_I2C_T_HD_STA);
 963
 964         ixgbe_lower_i2c_clk(hw, &i2cctl);
 965
 966         /* Minimum low period of clock is 4.7 us */
 967         udelay(IXGBE_I2C_T_LOW);
 968
 969 }
 970
 971 /**
 972  *  ixgbe_i2c_stop - Sets I2C stop condition
 973  *  @hw: pointer to hardware structure
 974  *
 975  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
 976  **/
 977 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
 978 {
 979         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
 980
 981         /* Stop condition must begin with data low and clock high */
 982         ixgbe_set_i2c_data(hw, &i2cctl, 0);
 983         ixgbe_raise_i2c_clk(hw, &i2cctl);
 984
 985         /* Setup time for stop condition (4us) */
 986         udelay(IXGBE_I2C_T_SU_STO);
 987
 988         ixgbe_set_i2c_data(hw, &i2cctl, 1);
 989
 990         /* bus free time between stop and start (4.7us)*/
 991         udelay(IXGBE_I2C_T_BUF);
 992 }
 993
 994 /**
 995  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
 996  *  @hw: pointer to hardware structure
 997  *  @data: data byte to clock in
 998  *
 999  *  Clocks in one byte data via I2C data/clock
1000  **/
1001 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1002 {
1003         s32 status = 0;
1004         s32 i;
1005         bool bit = 0;
1006
1007         for (i = 7; i >= 0; i--) {
1008                 status = ixgbe_clock_in_i2c_bit(hw, &bit);
1009                 *data |= bit << i;
1010
1011                 if (status != 0)
1012                         break;
1013         }
1014
1015         return status;
1016 }
1017
1018 /**
1019  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1020  *  @hw: pointer to hardware structure
1021  *  @data: data byte clocked out
1022  *
1023  *  Clocks out one byte data via I2C data/clock
1024  **/
1025 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1026 {
1027         s32 status = 0;
1028         s32 i;
1029         u32 i2cctl;
1030         bool bit = 0;
1031
1032         for (i = 7; i >= 0; i--) {
1033                 bit = (data >> i) & 0x1;
1034                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1035
1036                 if (status != 0)
1037                         break;
1038         }
1039
1040         /* Release SDA line (set high) */
1041         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1042         i2cctl |= IXGBE_I2C_DATA_OUT;
1043         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1044
1045         return status;
1046 }
1047
1048 /**
1049  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1050  *  @hw: pointer to hardware structure
1051  *
1052  *  Clocks in/out one bit via I2C data/clock
1053  **/
1054 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1055 {
1056         s32 status;
1057         u32 i = 0;
1058         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1059         u32 timeout = 10;
1060         bool ack = 1;
1061
1062         status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1063
1064         if (status != 0)
1065                 goto out;
1066
1067         /* Minimum high period of clock is 4us */
1068         udelay(IXGBE_I2C_T_HIGH);
1069
1070         /* Poll for ACK.  Note that ACK in I2C spec is
1071          * transition from 1 to 0 */
1072         for (i = 0; i < timeout; i++) {
1073                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1074                 ack = ixgbe_get_i2c_data(&i2cctl);
1075
1076                 udelay(1);
1077                 if (ack == 0)
1078                         break;
1079         }
1080
1081         if (ack == 1) {
1082                 hw_dbg(hw, "I2C ack was not received.\n");
1083                 status = IXGBE_ERR_I2C;
1084         }
1085
1086         ixgbe_lower_i2c_clk(hw, &i2cctl);
1087
1088         /* Minimum low period of clock is 4.7 us */
1089         udelay(IXGBE_I2C_T_LOW);
1090
1091 out:
1092         return status;
1093 }
1094
1095 /**
1096  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1097  *  @hw: pointer to hardware structure
1098  *  @data: read data value
1099  *
1100  *  Clocks in one bit via I2C data/clock
1101  **/
1102 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1103 {
1104         s32 status;
1105         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1106
1107         status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1108
1109         /* Minimum high period of clock is 4us */
1110         udelay(IXGBE_I2C_T_HIGH);
1111
1112         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1113         *data = ixgbe_get_i2c_data(&i2cctl);
1114
1115         ixgbe_lower_i2c_clk(hw, &i2cctl);
1116
1117         /* Minimum low period of clock is 4.7 us */
1118         udelay(IXGBE_I2C_T_LOW);
1119
1120         return status;
1121 }
1122
1123 /**
1124  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1125  *  @hw: pointer to hardware structure
1126  *  @data: data value to write
1127  *
1128  *  Clocks out one bit via I2C data/clock
1129  **/
1130 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1131 {
1132         s32 status;
1133         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1134
1135         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1136         if (status == 0) {
1137                 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1138
1139                 /* Minimum high period of clock is 4us */
1140                 udelay(IXGBE_I2C_T_HIGH);
1141
1142                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1143
1144                 /* Minimum low period of clock is 4.7 us.
1145                  * This also takes care of the data hold time.
1146                  */
1147                 udelay(IXGBE_I2C_T_LOW);
1148         } else {
1149                 status = IXGBE_ERR_I2C;
1150                 hw_dbg(hw, "I2C data was not set to %X\n", data);
1151         }
1152
1153         return status;
1154 }
1155 /**
1156  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1157  *  @hw: pointer to hardware structure
1158  *  @i2cctl: Current value of I2CCTL register
1159  *
1160  *  Raises the I2C clock line '0'->'1'
1161  **/
1162 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1163 {
1164         s32 status = 0;
1165
1166         *i2cctl |= IXGBE_I2C_CLK_OUT;
1167
1168         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1169
1170         /* SCL rise time (1000ns) */
1171         udelay(IXGBE_I2C_T_RISE);
1172
1173         return status;
1174 }
1175
1176 /**
1177  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1178  *  @hw: pointer to hardware structure
1179  *  @i2cctl: Current value of I2CCTL register
1180  *
1181  *  Lowers the I2C clock line '1'->'0'
1182  **/
1183 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1184 {
1185
1186         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1187
1188         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1189
1190         /* SCL fall time (300ns) */
1191         udelay(IXGBE_I2C_T_FALL);
1192 }
1193
1194 /**
1195  *  ixgbe_set_i2c_data - Sets the I2C data bit
1196  *  @hw: pointer to hardware structure
1197  *  @i2cctl: Current value of I2CCTL register
1198  *  @data: I2C data value (0 or 1) to set
1199  *
1200  *  Sets the I2C data bit
1201  **/
1202 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1203 {
1204         s32 status = 0;
1205
1206         if (data)
1207                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1208         else
1209                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1210
1211         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1212
1213         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1214         udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1215
1216         /* Verify data was set correctly */
1217         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1218         if (data != ixgbe_get_i2c_data(i2cctl)) {
1219                 status = IXGBE_ERR_I2C;
1220                 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1221         }
1222
1223         return status;
1224 }
1225
1226 /**
1227  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1228  *  @hw: pointer to hardware structure
1229  *  @i2cctl: Current value of I2CCTL register
1230  *
1231  *  Returns the I2C data bit value
1232  **/
1233 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1234 {
1235         bool data;
1236
1237         if (*i2cctl & IXGBE_I2C_DATA_IN)
1238                 data = 1;
1239         else
1240                 data = 0;
1241
1242         return data;
1243 }
1244
1245 /**
1246  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1247  *  @hw: pointer to hardware structure
1248  *
1249  *  Clears the I2C bus by sending nine clock pulses.
1250  *  Used when data line is stuck low.
1251  **/
1252 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1253 {
1254         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1255         u32 i;
1256
1257         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1258
1259         for (i = 0; i < 9; i++) {
1260                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1261
1262                 /* Min high period of clock is 4us */
1263                 udelay(IXGBE_I2C_T_HIGH);
1264
1265                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1266
1267                 /* Min low period of clock is 4.7us*/
1268                 udelay(IXGBE_I2C_T_LOW);
1269         }
1270
1271         /* Put the i2c bus back to default state */
1272         ixgbe_i2c_stop(hw);
1273 }
1274
1275 /**
1276  *  ixgbe_check_phy_link_tnx - Determine link and speed status
1277  *  @hw: pointer to hardware structure
1278  *
1279  *  Reads the VS1 register to determine if link is up and the current speed for
1280  *  the PHY.
1281  **/
1282 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1283                              bool *link_up)
1284 {
1285         s32 status = 0;
1286         u32 time_out;
1287         u32 max_time_out = 10;
1288         u16 phy_link = 0;
1289         u16 phy_speed = 0;
1290         u16 phy_data = 0;
1291
1292         /* Initialize speed and link to default case */
1293         *link_up = false;
1294         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1295
1296         /*
1297          * Check current speed and link status of the PHY register.
1298          * This is a vendor specific register and may have to
1299          * be changed for other copper PHYs.
1300          */
1301         for (time_out = 0; time_out < max_time_out; time_out++) {
1302                 udelay(10);
1303                 status = hw->phy.ops.read_reg(hw,
1304                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1305                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1306                                         &phy_data);
1307                 phy_link = phy_data &
1308                            IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1309                 phy_speed = phy_data &
1310                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1311                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1312                         *link_up = true;
1313                         if (phy_speed ==
1314                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1315                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1316                         break;
1317                 }
1318         }
1319
1320         return status;
1321 }
1322
1323 /**
1324  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1325  *  @hw: pointer to hardware structure
1326  *  @firmware_version: pointer to the PHY Firmware Version
1327  **/
1328 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1329                                        u16 *firmware_version)
1330 {
1331         s32 status = 0;
1332
1333         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1334                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1335                                       firmware_version);
1336
1337         return status;
1338 }
1339