2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes
15 * it to save wrong values... Be aware!
18 #include <asm/memory.h>
20 #include <asm/vfpmacros.h>
21 #include <asm/arch/entry-macro.S>
22 #include <asm/thread_notify.h>
24 #include "entry-header.S"
27 * Interrupt handling. Preserves r7, r8, r9
30 get_irqnr_preamble r5, lr
31 1: get_irqnr_and_base r0, r6, r5, lr
34 @ routine called with r0 = irq number, r1 = struct pt_regs *
43 * this macro assumes that irqstat (r6) and base (r5) are
44 * preserved from get_irqnr_and_base above
46 test_for_ipi r0, r6, r5, lr
51 #ifdef CONFIG_LOCAL_TIMERS
52 test_for_ltirq r0, r6, r5, lr
62 * Invalid mode handlers
64 .macro inv_entry, reason
65 sub sp, sp, #S_FRAME_SIZE
71 inv_entry BAD_PREFETCH
83 inv_entry BAD_UNDEFINSTR
86 @ XXX fall through to common_invalid
90 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
96 add r0, sp, #S_PC @ here for interlock avoidance
97 mov r7, #-1 @ "" "" "" ""
98 str r4, [sp] @ save preserved r0
99 stmia r0, {r5 - r7} @ lr_<exception>,
100 @ cpsr_<exception>, "old_r0"
109 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
110 #define SPFIX(code...) code
112 #define SPFIX(code...)
116 sub sp, sp, #S_FRAME_SIZE
118 SPFIX( bicne sp, sp, #4 )
122 add r5, sp, #S_SP @ here for interlock avoidance
123 mov r4, #-1 @ "" "" "" ""
124 add r0, sp, #S_FRAME_SIZE @ "" "" "" ""
125 SPFIX( addne r0, r0, #4 )
126 str r1, [sp] @ save the "real" r0 copied
127 @ from the exception stack
132 @ We are now ready to fill in the remaining blanks on the stack:
136 @ r2 - lr_<exception>, already fixed up for correct return/restart
137 @ r3 - spsr_<exception>
138 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
148 @ get ready to re-enable interrupts if appropriate
152 biceq r9, r9, #PSR_I_BIT
155 @ Call the processor-specific abort handler:
157 @ r2 - aborted context pc
158 @ r3 - aborted context cpsr
160 @ The abort handler must return the aborted address in r0, and
161 @ the fault status register in r1. r9 must be preserved.
172 @ set desired IRQ state, then call main handler
179 @ IRQs off again before pulling preserved data off the stack
184 @ restore SPSR and restart the instruction
188 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
194 #ifdef CONFIG_TRACE_IRQFLAGS
195 bl trace_hardirqs_off
197 #ifdef CONFIG_PREEMPT
199 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
200 add r7, r8, #1 @ increment it
201 str r7, [tsk, #TI_PREEMPT]
205 #ifdef CONFIG_PREEMPT
206 ldr r0, [tsk, #TI_FLAGS] @ get flags
207 tst r0, #_TIF_NEED_RESCHED
210 ldr r0, [tsk, #TI_PREEMPT] @ read preempt value
211 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
213 strne r0, [r0, -r0] @ bug()
215 ldr r0, [sp, #S_PSR] @ irqs are already disabled
217 #ifdef CONFIG_TRACE_IRQFLAGS
219 bleq trace_hardirqs_on
221 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
225 #ifdef CONFIG_PREEMPT
227 teq r8, #0 @ was preempt count = 0
228 ldreq r6, .LCirq_stat
230 ldr r0, [r6, #4] @ local_irq_count
231 ldr r1, [r6, #8] @ local_bh_count
234 mov r7, #0 @ preempt_schedule_irq
235 str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0
236 1: bl preempt_schedule_irq @ irq en/disable is done inside
237 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
238 tst r0, #_TIF_NEED_RESCHED
239 beq preempt_return @ go again
248 @ call emulation code, which returns using r9 if it has emulated
249 @ the instruction, or the more conventional lr if we are to treat
250 @ this as a real undefined instruction
258 mov r0, sp @ struct pt_regs *regs
262 @ IRQs off again before pulling preserved data off the stack
267 @ restore SPSR and restart the instruction
269 ldr lr, [sp, #S_PSR] @ Get SVC cpsr
271 ldmia sp, {r0 - pc}^ @ Restore SVC registers
278 @ re-enable interrupts if appropriate
282 biceq r9, r9, #PSR_I_BIT
286 @ set args, then call main handler
288 @ r0 - address of faulting instruction
289 @ r1 - pointer to registers on stack
291 mov r0, r2 @ address (pc)
293 bl do_PrefetchAbort @ call abort handler
296 @ IRQs off again before pulling preserved data off the stack
301 @ restore SPSR and restart the instruction
305 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
316 #ifdef CONFIG_PREEMPT
324 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
327 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
328 #error "sizeof(struct pt_regs) must be a multiple of 8"
332 sub sp, sp, #S_FRAME_SIZE
336 add r0, sp, #S_PC @ here for interlock avoidance
337 mov r4, #-1 @ "" "" "" ""
339 str r1, [sp] @ save the "real" r0 copied
340 @ from the exception stack
342 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
344 #warning "NPTL on non MMU needs fixing"
346 @ make sure our user space atomic helper is aborted
348 bichs r3, r3, #PSR_Z_BIT
353 @ We are now ready to fill in the remaining blanks on the stack:
355 @ r2 - lr_<exception>, already fixed up for correct return/restart
356 @ r3 - spsr_<exception>
357 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
359 @ Also, separately save sp_usr and lr_usr
365 @ Enable the alignment trap while in kernel mode
370 @ Clear FP to mark the first stack frame
380 @ Call the processor-specific abort handler:
382 @ r2 - aborted context pc
383 @ r3 - aborted context cpsr
385 @ The abort handler must return the aborted address in r0, and
386 @ the fault status register in r1.
397 @ IRQs on, then call the main handler
401 adr lr, ret_from_exception
408 #ifdef CONFIG_TRACE_IRQFLAGS
409 bl trace_hardirqs_off
412 #ifdef CONFIG_PREEMPT
413 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
414 add r7, r8, #1 @ increment it
415 str r7, [tsk, #TI_PREEMPT]
419 #ifdef CONFIG_PREEMPT
420 ldr r0, [tsk, #TI_PREEMPT]
421 str r8, [tsk, #TI_PREEMPT]
425 #ifdef CONFIG_TRACE_IRQFLAGS
438 tst r3, #PSR_T_BIT @ Thumb mode?
439 bne __und_usr_unknown @ ignore FP
443 @ fall through to the emulation code, which returns using r9 if
444 @ it has emulated the instruction, or the more conventional lr
445 @ if we are to treat this as a real undefined instruction
450 adr r9, ret_from_exception
451 adr lr, __und_usr_unknown
453 @ fallthrough to call_fpe
457 * The out of line fixup for the ldrt above.
459 .section .fixup, "ax"
462 .section __ex_table,"a"
467 * Check whether the instruction is a co-processor instruction.
468 * If yes, we need to call the relevant co-processor handler.
470 * Note that we don't do a full check here for the co-processor
471 * instructions; all instructions with bit 27 set are well
472 * defined. The only instructions that should fault are the
473 * co-processor instructions. However, we have to watch out
474 * for the ARM6/ARM7 SWI bug.
476 * Emulators may wish to make use of the following registers:
477 * r0 = instruction opcode.
479 * r9 = normal "successful" return address
480 * r10 = this threads thread_info structure.
481 * lr = unrecognised instruction return address
484 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
485 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
486 and r8, r0, #0x0f000000 @ mask out op-code bits
487 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
490 get_thread_info r10 @ get current thread
491 and r8, r0, #0x00000f00 @ mask out CP number
493 add r6, r10, #TI_USED_CP
494 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[]
496 @ Test if we need to give access to iWMMXt coprocessors
497 ldr r5, [r10, #TI_FLAGS]
498 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
499 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
500 bcs iwmmxt_task_enable
502 add pc, pc, r8, lsr #6
506 b do_fpe @ CP#1 (FPE)
507 b do_fpe @ CP#2 (FPE)
510 b crunch_task_enable @ CP#4 (MaverickCrunch)
511 b crunch_task_enable @ CP#5 (MaverickCrunch)
512 b crunch_task_enable @ CP#6 (MaverickCrunch)
522 b do_vfp @ CP#10 (VFP)
523 b do_vfp @ CP#11 (VFP)
525 mov pc, lr @ CP#10 (VFP)
526 mov pc, lr @ CP#11 (VFP)
530 mov pc, lr @ CP#14 (Debug)
531 mov pc, lr @ CP#15 (Control)
536 add r10, r10, #TI_FPSTATE @ r10 = workspace
537 ldr pc, [r4] @ Call FP module USR entry point
540 * The FP module is called with these registers set:
543 * r9 = normal "successful" return address
545 * lr = unrecognised FP instruction return address
557 adr lr, ret_from_exception
564 enable_irq @ Enable interrupts
565 mov r0, r2 @ address (pc)
567 bl do_PrefetchAbort @ call abort handler
570 * This is the return code to user mode for abort handlers
572 ENTRY(ret_from_exception)
578 * Register switch for ARMv3 and ARMv4 processors
579 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
580 * previous and next are guaranteed not to be the same.
583 add ip, r1, #TI_CPU_SAVE
584 ldr r3, [r2, #TI_TP_VALUE]
585 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack
587 ldr r6, [r2, #TI_CPU_DOMAIN]
589 #if __LINUX_ARM_ARCH__ >= 6
590 #ifdef CONFIG_CPU_32v6K
593 strex r5, r4, [ip] @ Clear exclusive monitor
596 #if defined(CONFIG_HAS_TLS_REG)
597 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
598 #elif !defined(CONFIG_TLS_REG_EMUL)
600 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
603 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
606 add r4, r2, #TI_CPU_SAVE
607 ldr r0, =thread_notify_head
608 mov r1, #THREAD_NOTIFY_SWITCH
609 bl atomic_notifier_call_chain
611 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
618 * These are segment of kernel provided user code reachable from user space
619 * at a fixed address in kernel memory. This is used to provide user space
620 * with some operations which require kernel help because of unimplemented
621 * native feature and/or instructions in many ARM CPUs. The idea is for
622 * this code to be executed directly in user mode for best efficiency but
623 * which is too intimate with the kernel counter part to be left to user
624 * libraries. In fact this code might even differ from one CPU to another
625 * depending on the available instruction set and restrictions like on
626 * SMP systems. In other words, the kernel reserves the right to change
627 * this code as needed without warning. Only the entry points and their
628 * results are guaranteed to be stable.
630 * Each segment is 32-byte aligned and will be moved to the top of the high
631 * vector page. New segments (if ever needed) must be added in front of
632 * existing ones. This mechanism should be used only for things that are
633 * really small and justified, and not be abused freely.
635 * User space is expected to implement those things inline when optimizing
636 * for a processor that has the necessary native support, but only if such
637 * resulting binaries are already to be incompatible with earlier ARM
638 * processors due to the use of unsupported instructions other than what
639 * is provided here. In other words don't make binaries unable to run on
640 * earlier processors just for the sake of not using these kernel helpers
641 * if your compiled code is not going to use the new instructions for other
646 #ifdef CONFIG_ARM_THUMB
654 .globl __kuser_helper_start
655 __kuser_helper_start:
658 * Reference prototype:
660 * void __kernel_memory_barrier(void)
664 * lr = return address
672 * the Z flag might be lost
674 * Definition and user space usage example:
676 * typedef void (__kernel_dmb_t)(void);
677 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
679 * Apply any needed memory barrier to preserve consistency with data modified
680 * manually and __kuser_cmpxchg usage.
682 * This could be used as follows:
684 * #define __kernel_dmb() \
685 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
686 * : : : "r0", "lr","cc" )
689 __kuser_memory_barrier: @ 0xffff0fa0
691 #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP)
692 mcr p15, 0, r0, c7, c10, 5 @ dmb
699 * Reference prototype:
701 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
708 * lr = return address
712 * r0 = returned value (zero or non-zero)
713 * C flag = set if r0 == 0, clear if r0 != 0
719 * Definition and user space usage example:
721 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
722 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
724 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
725 * Return zero if *ptr was changed or non-zero if no exchange happened.
726 * The C flag is also set if *ptr was changed to allow for assembly
727 * optimization in the calling code.
731 * - This routine already includes memory barriers as needed.
733 * - A failure might be transient, i.e. it is possible, although unlikely,
734 * that "failure" be returned even if *ptr == oldval.
736 * For example, a user space atomic_add implementation could look like this:
738 * #define atomic_add(ptr, val) \
739 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
740 * register unsigned int __result asm("r1"); \
742 * "1: @ atomic_add\n\t" \
743 * "ldr r0, [r2]\n\t" \
744 * "mov r3, #0xffff0fff\n\t" \
745 * "add lr, pc, #4\n\t" \
746 * "add r1, r0, %2\n\t" \
747 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
749 * : "=&r" (__result) \
750 * : "r" (__ptr), "rIL" (val) \
751 * : "r0","r3","ip","lr","cc","memory" ); \
755 __kuser_cmpxchg: @ 0xffff0fc0
757 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
760 * Poor you. No fast solution possible...
761 * The kernel itself must perform the operation.
762 * A special ghost syscall is used for that (see traps.c).
765 mov r7, #0xff00 @ 0xfff0 into r7 for EABI
770 #elif __LINUX_ARM_ARCH__ < 6
773 * Theory of operation:
775 * We set the Z flag before loading oldval. If ever an exception
776 * occurs we can not be sure the loaded value will still be the same
777 * when the exception returns, therefore the user exception handler
778 * will clear the Z flag whenever the interrupted user code was
779 * actually from the kernel address space (see the usr_entry macro).
781 * The post-increment on the str is used to prevent a race with an
782 * exception happening just after the str instruction which would
783 * clear the Z flag although the exchange was done.
786 teq ip, ip @ set Z flag
787 ldr ip, [r2] @ load current val
788 add r3, r2, #1 @ prepare store ptr
789 teqeq ip, r0 @ compare with oldval if still allowed
790 streq r1, [r3, #-1]! @ store newval if still allowed
791 subs r0, r2, r3 @ if r2 == r3 the str occured
793 #warning "NPTL on non MMU needs fixing"
802 mcr p15, 0, r0, c7, c10, 5 @ dmb
809 mcr p15, 0, r0, c7, c10, 5 @ dmb
818 * Reference prototype:
820 * int __kernel_get_tls(void)
824 * lr = return address
832 * the Z flag might be lost
834 * Definition and user space usage example:
836 * typedef int (__kernel_get_tls_t)(void);
837 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
839 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
841 * This could be used as follows:
843 * #define __kernel_get_tls() \
844 * ({ register unsigned int __val asm("r0"); \
845 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
846 * : "=r" (__val) : : "lr","cc" ); \
850 __kuser_get_tls: @ 0xffff0fe0
852 #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
853 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
855 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
860 .word 0 @ pad up to __kuser_helper_version
864 * Reference declaration:
866 * extern unsigned int __kernel_helper_version;
868 * Definition and user space usage example:
870 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
872 * User space may read this to determine the curent number of helpers
876 __kuser_helper_version: @ 0xffff0ffc
877 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
879 .globl __kuser_helper_end
886 * This code is copied to 0xffff0200 so we can use branches in the
887 * vectors, rather than ldr's. Note that this code must not
888 * exceed 0x300 bytes.
890 * Common stub entry macro:
891 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
893 * SP points to a minimal amount of processor-private memory, the address
894 * of which is copied into r0 for the mode specific abort handler.
896 .macro vector_stub, name, mode, correction=0
901 sub lr, lr, #\correction
905 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
908 stmia sp, {r0, lr} @ save r0, lr
910 str lr, [sp, #8] @ save spsr
913 @ Prepare for SVC32 mode. IRQs remain disabled.
916 eor r0, r0, #(\mode ^ SVC_MODE)
920 @ the branch table must immediately follow this code
924 ldr lr, [pc, lr, lsl #2]
925 movs pc, lr @ branch to handler in SVC mode
931 * Interrupt dispatcher
933 vector_stub irq, IRQ_MODE, 4
935 .long __irq_usr @ 0 (USR_26 / USR_32)
936 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
937 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
938 .long __irq_svc @ 3 (SVC_26 / SVC_32)
939 .long __irq_invalid @ 4
940 .long __irq_invalid @ 5
941 .long __irq_invalid @ 6
942 .long __irq_invalid @ 7
943 .long __irq_invalid @ 8
944 .long __irq_invalid @ 9
945 .long __irq_invalid @ a
946 .long __irq_invalid @ b
947 .long __irq_invalid @ c
948 .long __irq_invalid @ d
949 .long __irq_invalid @ e
950 .long __irq_invalid @ f
953 * Data abort dispatcher
954 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
956 vector_stub dabt, ABT_MODE, 8
958 .long __dabt_usr @ 0 (USR_26 / USR_32)
959 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
960 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
961 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
962 .long __dabt_invalid @ 4
963 .long __dabt_invalid @ 5
964 .long __dabt_invalid @ 6
965 .long __dabt_invalid @ 7
966 .long __dabt_invalid @ 8
967 .long __dabt_invalid @ 9
968 .long __dabt_invalid @ a
969 .long __dabt_invalid @ b
970 .long __dabt_invalid @ c
971 .long __dabt_invalid @ d
972 .long __dabt_invalid @ e
973 .long __dabt_invalid @ f
976 * Prefetch abort dispatcher
977 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
979 vector_stub pabt, ABT_MODE, 4
981 .long __pabt_usr @ 0 (USR_26 / USR_32)
982 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
983 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
984 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
985 .long __pabt_invalid @ 4
986 .long __pabt_invalid @ 5
987 .long __pabt_invalid @ 6
988 .long __pabt_invalid @ 7
989 .long __pabt_invalid @ 8
990 .long __pabt_invalid @ 9
991 .long __pabt_invalid @ a
992 .long __pabt_invalid @ b
993 .long __pabt_invalid @ c
994 .long __pabt_invalid @ d
995 .long __pabt_invalid @ e
996 .long __pabt_invalid @ f
999 * Undef instr entry dispatcher
1000 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1002 vector_stub und, UND_MODE
1004 .long __und_usr @ 0 (USR_26 / USR_32)
1005 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1006 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1007 .long __und_svc @ 3 (SVC_26 / SVC_32)
1008 .long __und_invalid @ 4
1009 .long __und_invalid @ 5
1010 .long __und_invalid @ 6
1011 .long __und_invalid @ 7
1012 .long __und_invalid @ 8
1013 .long __und_invalid @ 9
1014 .long __und_invalid @ a
1015 .long __und_invalid @ b
1016 .long __und_invalid @ c
1017 .long __und_invalid @ d
1018 .long __und_invalid @ e
1019 .long __und_invalid @ f
1023 /*=============================================================================
1025 *-----------------------------------------------------------------------------
1026 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1027 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1028 * Basically to switch modes, we *HAVE* to clobber one register... brain
1029 * damage alert! I don't think that we can execute any code in here in any
1030 * other mode than FIQ... Ok you can switch to another mode, but you can't
1031 * get out of that mode without clobbering one register.
1037 /*=============================================================================
1038 * Address exception handler
1039 *-----------------------------------------------------------------------------
1040 * These aren't too critical.
1041 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1048 * We group all the following data together to optimise
1049 * for CPUs with separate I & D caches.
1059 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1061 .globl __vectors_start
1064 b vector_und + stubs_offset
1065 ldr pc, .LCvswi + stubs_offset
1066 b vector_pabt + stubs_offset
1067 b vector_dabt + stubs_offset
1068 b vector_addrexcptn + stubs_offset
1069 b vector_irq + stubs_offset
1070 b vector_fiq + stubs_offset
1072 .globl __vectors_end
1078 .globl cr_no_alignment
projects / linux-2.6 / blob