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   1 /*
   2  * DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves
   3  * the minimum state necessary that allows us to turn psr.ic back
   4  * on.
   5  *
   6  * Assumed state upon entry:
   7  *      psr.ic: off
   8  *      r31:    contains saved predicates (pr)
   9  *
  10  * Upon exit, the state is as follows:
  11  *      psr.ic: off
  12  *       r2 = points to &pt_regs.r16
  13  *       r8 = contents of ar.ccv
  14  *       r9 = contents of ar.csd
  15  *      r10 = contents of ar.ssd
  16  *      r11 = FPSR_DEFAULT
  17  *      r12 = kernel sp (kernel virtual address)
  18  *      r13 = points to current task_struct (kernel virtual address)
  19  *      p15 = TRUE if psr.i is set in cr.ipsr
  20  *      predicate registers (other than p2, p3, and p15), b6, r3, r14, r15:
  21  *              preserved
  22  * CONFIG_XEN note: p6/p7 are not preserved
  23  *
  24  * Note that psr.ic is NOT turned on by this macro.  This is so that
  25  * we can pass interruption state as arguments to a handler.
  26  */
  27 #define XEN_DO_SAVE_MIN(__COVER,SAVE_IFS,EXTRA,WORKAROUND)                                      \
  28         mov r16=IA64_KR(CURRENT);       /* M */                                                 \
  29         mov r27=ar.rsc;                 /* M */                                                 \
  30         mov r20=r1;                     /* A */                                                 \
  31         mov r25=ar.unat;                /* M */                                                 \
  32         MOV_FROM_IPSR(p0,r29);          /* M */                                                 \
  33         MOV_FROM_IIP(r28);              /* M */                                                 \
  34         mov r21=ar.fpsr;                /* M */                                                 \
  35         mov r26=ar.pfs;                 /* I */                                                 \
  36         __COVER;                        /* B;; (or nothing) */                                  \
  37         adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16;                                         \
  38         ;;                                                                                      \
  39         ld1 r17=[r16];                          /* load current->thread.on_ustack flag */       \
  40         st1 [r16]=r0;                           /* clear current->thread.on_ustack flag */      \
  41         adds r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16                                          \
  42         /* switch from user to kernel RBS: */                                                   \
  43         ;;                                                                                      \
  44         invala;                         /* M */                                                 \
  45         /* SAVE_IFS;*/ /* see xen special handling below */                                     \
  46         cmp.eq pKStk,pUStk=r0,r17;              /* are we in kernel mode already? */            \
  47         ;;                                                                                      \
  48 (pUStk) mov ar.rsc=0;           /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */     \
  49         ;;                                                                                      \
  50 (pUStk) mov.m r24=ar.rnat;                                                                      \
  51 (pUStk) addl r22=IA64_RBS_OFFSET,r1;                    /* compute base of RBS */               \
  52 (pKStk) mov r1=sp;                                      /* get sp  */                           \
  53         ;;                                                                                      \
  54 (pUStk) lfetch.fault.excl.nt1 [r22];                                                            \
  55 (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1;   /* compute base of memory stack */      \
  56 (pUStk) mov r23=ar.bspstore;                            /* save ar.bspstore */                  \
  57         ;;                                                                                      \
  58 (pUStk) mov ar.bspstore=r22;                            /* switch to kernel RBS */              \
  59 (pKStk) addl r1=-IA64_PT_REGS_SIZE,r1;                  /* if in kernel mode, use sp (r12) */   \
  60         ;;                                                                                      \
  61 (pUStk) mov r18=ar.bsp;                                                                         \
  62 (pUStk) mov ar.rsc=0x3;         /* set eager mode, pl 0, little-endian, loadrs=0 */             \
  63         adds r17=2*L1_CACHE_BYTES,r1;           /* really: biggest cache-line size */           \
  64         adds r16=PT(CR_IPSR),r1;                                                                \
  65         ;;                                                                                      \
  66         lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES;                                             \
  67         st8 [r16]=r29;          /* save cr.ipsr */                                              \
  68         ;;                                                                                      \
  69         lfetch.fault.excl.nt1 [r17];                                                            \
  70         tbit.nz p15,p0=r29,IA64_PSR_I_BIT;                                                      \
  71         mov r29=b0                                                                              \
  72         ;;                                                                                      \
  73         WORKAROUND;                                                                             \
  74         adds r16=PT(R8),r1;     /* initialize first base pointer */                             \
  75         adds r17=PT(R9),r1;     /* initialize second base pointer */                            \
  76 (pKStk) mov r18=r0;             /* make sure r18 isn't NaT */                                   \
  77         ;;                                                                                      \
  78 .mem.offset 0,0; st8.spill [r16]=r8,16;                                                         \
  79 .mem.offset 8,0; st8.spill [r17]=r9,16;                                                         \
  80         ;;                                                                                      \
  81 .mem.offset 0,0; st8.spill [r16]=r10,24;                                                        \
  82         movl r8=XSI_PRECOVER_IFS;                                                               \
  83 .mem.offset 8,0; st8.spill [r17]=r11,24;                                                        \
  84         ;;                                                                                      \
  85         /* xen special handling for possibly lazy cover */                                      \
  86         /* SAVE_MIN case in dispatch_ia32_handler: mov r30=r0 */                                \
  87         ld8 r30=[r8];                                                                           \
  88 (pUStk) sub r18=r18,r22;        /* r18=RSE.ndirty*8 */                                          \
  89         st8 [r16]=r28,16;       /* save cr.iip */                                               \
  90         ;;                                                                                      \
  91         st8 [r17]=r30,16;       /* save cr.ifs */                                               \
  92         mov r8=ar.ccv;                                                                          \
  93         mov r9=ar.csd;                                                                          \
  94         mov r10=ar.ssd;                                                                         \
  95         movl r11=FPSR_DEFAULT;   /* L-unit */                                                   \
  96         ;;                                                                                      \
  97         st8 [r16]=r25,16;       /* save ar.unat */                                              \
  98         st8 [r17]=r26,16;       /* save ar.pfs */                                               \
  99         shl r18=r18,16;         /* compute ar.rsc to be used for "loadrs" */                    \
 100         ;;                                                                                      \
 101         st8 [r16]=r27,16;       /* save ar.rsc */                                               \
 102 (pUStk) st8 [r17]=r24,16;       /* save ar.rnat */                                              \
 103 (pKStk) adds r17=16,r17;        /* skip over ar_rnat field */                                   \
 104         ;;                      /* avoid RAW on r16 & r17 */                                    \
 105 (pUStk) st8 [r16]=r23,16;       /* save ar.bspstore */                                          \
 106         st8 [r17]=r31,16;       /* save predicates */                                           \
 107 (pKStk) adds r16=16,r16;        /* skip over ar_bspstore field */                               \
 108         ;;                                                                                      \
 109         st8 [r16]=r29,16;       /* save b0 */                                                   \
 110         st8 [r17]=r18,16;       /* save ar.rsc value for "loadrs" */                            \
 111         cmp.eq pNonSys,pSys=r0,r0       /* initialize pSys=0, pNonSys=1 */                      \
 112         ;;                                                                                      \
 113 .mem.offset 0,0; st8.spill [r16]=r20,16;        /* save original r1 */                          \
 114 .mem.offset 8,0; st8.spill [r17]=r12,16;                                                        \
 115         adds r12=-16,r1;        /* switch to kernel memory stack (with 16 bytes of scratch) */  \
 116         ;;                                                                                      \
 117 .mem.offset 0,0; st8.spill [r16]=r13,16;                                                        \
 118 .mem.offset 8,0; st8.spill [r17]=r21,16;        /* save ar.fpsr */                              \
 119         mov r13=IA64_KR(CURRENT);       /* establish `current' */                               \
 120         ;;                                                                                      \
 121 .mem.offset 0,0; st8.spill [r16]=r15,16;                                                        \
 122 .mem.offset 8,0; st8.spill [r17]=r14,16;                                                        \
 123         ;;                                                                                      \
 124 .mem.offset 0,0; st8.spill [r16]=r2,16;                                                         \
 125 .mem.offset 8,0; st8.spill [r17]=r3,16;                                                         \
 126         ACCOUNT_GET_STAMP                                                                       \
 127         adds r2=IA64_PT_REGS_R16_OFFSET,r1;                                                     \
 128         ;;                                                                                      \
 129         EXTRA;                                                                                  \
 130         movl r1=__gp;           /* establish kernel global pointer */                           \
 131         ;;                                                                                      \
 132         ACCOUNT_SYS_ENTER                                                                       \
 133         BSW_1(r3,r14);  /* switch back to bank 1 (must be last in insn group) */                \
 134         ;;