2 * pata_hpt3x3 - HPT3x3 driver
3 * (c) Copyright 2005-2006 Red Hat
5 * Was pata_hpt34x but the naming was confusing as it supported the
6 * 343 and 363 so it has been renamed.
9 * linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
12 * May be copied or modified under the terms of the GNU General Public
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/blkdev.h>
21 #include <linux/delay.h>
22 #include <scsi/scsi_host.h>
23 #include <linux/libata.h>
25 #define DRV_NAME "pata_hpt3x3"
26 #define DRV_VERSION "0.5.3"
29 * hpt3x3_set_piomode - PIO setup
31 * @adev: device on the interface
33 * Set our PIO requirements. This is fairly simple on the HPT3x3 as
34 * all we have to do is clear the MWDMA and UDMA bits then load the
38 static void hpt3x3_set_piomode(struct ata_port *ap, struct ata_device *adev)
40 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
42 int dn = 2 * ap->port_no + adev->devno;
44 pci_read_config_dword(pdev, 0x44, &r1);
45 pci_read_config_dword(pdev, 0x48, &r2);
46 /* Load the PIO timing number */
47 r1 &= ~(7 << (3 * dn));
48 r1 |= (adev->pio_mode - XFER_PIO_0) << (3 * dn);
49 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
51 pci_write_config_dword(pdev, 0x44, r1);
52 pci_write_config_dword(pdev, 0x48, r2);
56 * hpt3x3_set_dmamode - DMA timing setup
58 * @adev: Device being configured
60 * Set up the channel for MWDMA or UDMA modes. Much the same as with
61 * PIO, load the mode number and then set MWDMA or UDMA flag.
63 * 0x44 : bit 0-2 master mode, 3-5 slave mode, etc
64 * 0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
67 static void hpt3x3_set_dmamode(struct ata_port *ap, struct ata_device *adev)
69 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
71 int dn = 2 * ap->port_no + adev->devno;
72 int mode_num = adev->dma_mode & 0x0F;
74 pci_read_config_dword(pdev, 0x44, &r1);
75 pci_read_config_dword(pdev, 0x48, &r2);
76 /* Load the timing number */
77 r1 &= ~(7 << (3 * dn));
78 r1 |= (mode_num << (3 * dn));
79 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
81 if (adev->dma_mode >= XFER_UDMA_0)
82 r2 |= (0x10 << dn); /* Ultra mode */
84 r2 |= (0x01 << dn); /* MWDMA */
86 pci_write_config_dword(pdev, 0x44, r1);
87 pci_write_config_dword(pdev, 0x48, r2);
91 * hpt3x3_atapi_dma - ATAPI DMA check
94 * Just say no - we don't do ATAPI DMA
97 static int hpt3x3_atapi_dma(struct ata_queued_cmd *qc)
102 static struct scsi_host_template hpt3x3_sht = {
103 .module = THIS_MODULE,
105 .ioctl = ata_scsi_ioctl,
106 .queuecommand = ata_scsi_queuecmd,
107 .can_queue = ATA_DEF_QUEUE,
108 .this_id = ATA_SHT_THIS_ID,
109 .sg_tablesize = LIBATA_MAX_PRD,
110 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
111 .emulated = ATA_SHT_EMULATED,
112 .use_clustering = ATA_SHT_USE_CLUSTERING,
113 .proc_name = DRV_NAME,
114 .dma_boundary = ATA_DMA_BOUNDARY,
115 .slave_configure = ata_scsi_slave_config,
116 .slave_destroy = ata_scsi_slave_destroy,
117 .bios_param = ata_std_bios_param,
120 static struct ata_port_operations hpt3x3_port_ops = {
121 .port_disable = ata_port_disable,
122 .set_piomode = hpt3x3_set_piomode,
123 .mode_filter = ata_pci_default_filter,
125 .tf_load = ata_tf_load,
126 .tf_read = ata_tf_read,
127 .check_status = ata_check_status,
128 .exec_command = ata_exec_command,
129 .dev_select = ata_std_dev_select,
131 .freeze = ata_bmdma_freeze,
132 .thaw = ata_bmdma_thaw,
133 .error_handler = ata_bmdma_error_handler,
134 .post_internal_cmd = ata_bmdma_post_internal_cmd,
135 .cable_detect = ata_cable_40wire,
137 .bmdma_setup = ata_bmdma_setup,
138 .bmdma_start = ata_bmdma_start,
139 .bmdma_stop = ata_bmdma_stop,
140 .bmdma_status = ata_bmdma_status,
141 .check_atapi_dma= hpt3x3_atapi_dma,
143 .qc_prep = ata_qc_prep,
144 .qc_issue = ata_qc_issue_prot,
146 .data_xfer = ata_data_xfer,
148 .irq_handler = ata_interrupt,
149 .irq_clear = ata_bmdma_irq_clear,
150 .irq_on = ata_irq_on,
151 .irq_ack = ata_irq_ack,
153 .port_start = ata_port_start,
157 * hpt3x3_init_chipset - chip setup
160 * Perform the setup required at boot and on resume.
163 static void hpt3x3_init_chipset(struct pci_dev *dev)
166 /* Initialize the board */
167 pci_write_config_word(dev, 0x80, 0x00);
168 /* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */
169 pci_read_config_word(dev, PCI_COMMAND, &cmd);
170 if (cmd & PCI_COMMAND_MEMORY)
171 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
173 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
177 * hpt3x3_init_one - Initialise an HPT343/363
179 * @id: Entry in match table
181 * Perform basic initialisation. We set the device up so we access all
182 * ports via BAR4. This is neccessary to work around errata.
185 static int hpt3x3_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
187 static int printed_version;
188 static const struct ata_port_info info = {
190 .flags = ATA_FLAG_SLAVE_POSS,
192 #if defined(CONFIG_PATA_HPT3X3_DMA)
193 /* Further debug needed */
197 .port_ops = &hpt3x3_port_ops
199 /* Register offsets of taskfiles in BAR4 area */
200 static const u8 offset_cmd[2] = { 0x20, 0x28 };
201 static const u8 offset_ctl[2] = { 0x36, 0x3E };
202 const struct ata_port_info *ppi[] = { &info, NULL };
203 struct ata_host *host;
207 hpt3x3_init_chipset(pdev);
209 if (!printed_version++)
210 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
212 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
215 /* acquire resources and fill host */
216 rc = pcim_enable_device(pdev);
220 /* Everything is relative to BAR4 if we set up this way */
221 rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME);
223 pcim_pin_device(pdev);
226 host->iomap = pcim_iomap_table(pdev);
227 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
230 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
234 base = host->iomap[4]; /* Bus mastering base */
236 for (i = 0; i < host->n_ports; i++) {
237 struct ata_ioports *ioaddr = &host->ports[i]->ioaddr;
239 ioaddr->cmd_addr = base + offset_cmd[i];
240 ioaddr->altstatus_addr =
241 ioaddr->ctl_addr = base + offset_ctl[i];
242 ioaddr->scr_addr = NULL;
243 ata_std_ports(ioaddr);
244 ioaddr->bmdma_addr = base + 8 * i;
246 pci_set_master(pdev);
247 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
252 static int hpt3x3_reinit_one(struct pci_dev *dev)
254 hpt3x3_init_chipset(dev);
255 return ata_pci_device_resume(dev);
259 static const struct pci_device_id hpt3x3[] = {
260 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), },
265 static struct pci_driver hpt3x3_pci_driver = {
268 .probe = hpt3x3_init_one,
269 .remove = ata_pci_remove_one,
271 .suspend = ata_pci_device_suspend,
272 .resume = hpt3x3_reinit_one,
276 static int __init hpt3x3_init(void)
278 return pci_register_driver(&hpt3x3_pci_driver);
282 static void __exit hpt3x3_exit(void)
284 pci_unregister_driver(&hpt3x3_pci_driver);
288 MODULE_AUTHOR("Alan Cox");
289 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363");
290 MODULE_LICENSE("GPL");
291 MODULE_DEVICE_TABLE(pci, hpt3x3);
292 MODULE_VERSION(DRV_VERSION);
294 module_init(hpt3x3_init);
295 module_exit(hpt3x3_exit);