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   1 /*
   2  *
   3  * arch/arm/mach-u300/timer.c
   4  *
   5  *
   6  * Copyright (C) 2007-2009 ST-Ericsson AB
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Timer COH 901 328, runs the OS timer interrupt.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/interrupt.h>
  12 #include <linux/time.h>
  13 #include <linux/timex.h>
  14 #include <linux/clockchips.h>
  15 #include <linux/clocksource.h>
  16 #include <linux/types.h>
  17 #include <linux/io.h>
  18
  19 #include <mach/hardware.h>
  20
  21 /* Generic stuff */
  22 #include <asm/mach/map.h>
  23 #include <asm/mach/time.h>
  24 #include <asm/mach/irq.h>
  25
  26 #include "clock.h"
  27
  28 /*
  29  * APP side special timer registers
  30  * This timer contains four timers which can fire an interrupt each.
  31  * OS (operating system) timer @ 32768 Hz
  32  * DD (device driver) timer @ 1 kHz
  33  * GP1 (general purpose 1) timer @ 1MHz
  34  * GP2 (general purpose 2) timer @ 1MHz
  35  */
  36
  37 /* Reset OS Timer 32bit (-/W) */
  38 #define U300_TIMER_APP_ROST                                     (0x0000)
  39 #define U300_TIMER_APP_ROST_TIMER_RESET                         (0x00000000)
  40 /* Enable OS Timer 32bit (-/W) */
  41 #define U300_TIMER_APP_EOST                                     (0x0004)
  42 #define U300_TIMER_APP_EOST_TIMER_ENABLE                        (0x00000000)
  43 /* Disable OS Timer 32bit (-/W) */
  44 #define U300_TIMER_APP_DOST                                     (0x0008)
  45 #define U300_TIMER_APP_DOST_TIMER_DISABLE                       (0x00000000)
  46 /* OS Timer Mode Register 32bit (-/W) */
  47 #define U300_TIMER_APP_SOSTM                                    (0x000c)
  48 #define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS                    (0x00000000)
  49 #define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT                      (0x00000001)
  50 /* OS Timer Status Register 32bit (R/-) */
  51 #define U300_TIMER_APP_OSTS                                     (0x0010)
  52 #define U300_TIMER_APP_OSTS_TIMER_STATE_MASK                    (0x0000000F)
  53 #define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE                    (0x00000001)
  54 #define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE                  (0x00000002)
  55 #define U300_TIMER_APP_OSTS_ENABLE_IND                          (0x00000010)
  56 #define U300_TIMER_APP_OSTS_MODE_MASK                           (0x00000020)
  57 #define U300_TIMER_APP_OSTS_MODE_CONTINUOUS                     (0x00000000)
  58 #define U300_TIMER_APP_OSTS_MODE_ONE_SHOT                       (0x00000020)
  59 #define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND                     (0x00000040)
  60 #define U300_TIMER_APP_OSTS_IRQ_PENDING_IND                     (0x00000080)
  61 /* OS Timer Current Count Register 32bit (R/-) */
  62 #define U300_TIMER_APP_OSTCC                                    (0x0014)
  63 /* OS Timer Terminal Count Register 32bit (R/W) */
  64 #define U300_TIMER_APP_OSTTC                                    (0x0018)
  65 /* OS Timer Interrupt Enable Register 32bit (-/W) */
  66 #define U300_TIMER_APP_OSTIE                                    (0x001c)
  67 #define U300_TIMER_APP_OSTIE_IRQ_DISABLE                        (0x00000000)
  68 #define U300_TIMER_APP_OSTIE_IRQ_ENABLE                         (0x00000001)
  69 /* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
  70 #define U300_TIMER_APP_OSTIA                                    (0x0020)
  71 #define U300_TIMER_APP_OSTIA_IRQ_ACK                            (0x00000080)
  72
  73 /* Reset DD Timer 32bit (-/W) */
  74 #define U300_TIMER_APP_RDDT                                     (0x0040)
  75 #define U300_TIMER_APP_RDDT_TIMER_RESET                         (0x00000000)
  76 /* Enable DD Timer 32bit (-/W) */
  77 #define U300_TIMER_APP_EDDT                                     (0x0044)
  78 #define U300_TIMER_APP_EDDT_TIMER_ENABLE                        (0x00000000)
  79 /* Disable DD Timer 32bit (-/W) */
  80 #define U300_TIMER_APP_DDDT                                     (0x0048)
  81 #define U300_TIMER_APP_DDDT_TIMER_DISABLE                       (0x00000000)
  82 /* DD Timer Mode Register 32bit (-/W) */
  83 #define U300_TIMER_APP_SDDTM                                    (0x004c)
  84 #define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS                    (0x00000000)
  85 #define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT                      (0x00000001)
  86 /* DD Timer Status Register 32bit (R/-) */
  87 #define U300_TIMER_APP_DDTS                                     (0x0050)
  88 #define U300_TIMER_APP_DDTS_TIMER_STATE_MASK                    (0x0000000F)
  89 #define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE                    (0x00000001)
  90 #define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE                  (0x00000002)
  91 #define U300_TIMER_APP_DDTS_ENABLE_IND                          (0x00000010)
  92 #define U300_TIMER_APP_DDTS_MODE_MASK                           (0x00000020)
  93 #define U300_TIMER_APP_DDTS_MODE_CONTINUOUS                     (0x00000000)
  94 #define U300_TIMER_APP_DDTS_MODE_ONE_SHOT                       (0x00000020)
  95 #define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND                     (0x00000040)
  96 #define U300_TIMER_APP_DDTS_IRQ_PENDING_IND                     (0x00000080)
  97 /* DD Timer Current Count Register 32bit (R/-) */
  98 #define U300_TIMER_APP_DDTCC                                    (0x0054)
  99 /* DD Timer Terminal Count Register 32bit (R/W) */
 100 #define U300_TIMER_APP_DDTTC                                    (0x0058)
 101 /* DD Timer Interrupt Enable Register 32bit (-/W) */
 102 #define U300_TIMER_APP_DDTIE                                    (0x005c)
 103 #define U300_TIMER_APP_DDTIE_IRQ_DISABLE                        (0x00000000)
 104 #define U300_TIMER_APP_DDTIE_IRQ_ENABLE                         (0x00000001)
 105 /* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
 106 #define U300_TIMER_APP_DDTIA                                    (0x0060)
 107 #define U300_TIMER_APP_DDTIA_IRQ_ACK                            (0x00000080)
 108
 109 /* Reset GP1 Timer 32bit (-/W) */
 110 #define U300_TIMER_APP_RGPT1                                    (0x0080)
 111 #define U300_TIMER_APP_RGPT1_TIMER_RESET                        (0x00000000)
 112 /* Enable GP1 Timer 32bit (-/W) */
 113 #define U300_TIMER_APP_EGPT1                                    (0x0084)
 114 #define U300_TIMER_APP_EGPT1_TIMER_ENABLE                       (0x00000000)
 115 /* Disable GP1 Timer 32bit (-/W) */
 116 #define U300_TIMER_APP_DGPT1                                    (0x0088)
 117 #define U300_TIMER_APP_DGPT1_TIMER_DISABLE                      (0x00000000)
 118 /* GP1 Timer Mode Register 32bit (-/W) */
 119 #define U300_TIMER_APP_SGPT1M                                   (0x008c)
 120 #define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS                   (0x00000000)
 121 #define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT                     (0x00000001)
 122 /* GP1 Timer Status Register 32bit (R/-) */
 123 #define U300_TIMER_APP_GPT1S                                    (0x0090)
 124 #define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK                   (0x0000000F)
 125 #define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE                   (0x00000001)
 126 #define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE                 (0x00000002)
 127 #define U300_TIMER_APP_GPT1S_ENABLE_IND                         (0x00000010)
 128 #define U300_TIMER_APP_GPT1S_MODE_MASK                          (0x00000020)
 129 #define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS                    (0x00000000)
 130 #define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT                      (0x00000020)
 131 #define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND                    (0x00000040)
 132 #define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND                    (0x00000080)
 133 /* GP1 Timer Current Count Register 32bit (R/-) */
 134 #define U300_TIMER_APP_GPT1CC                                   (0x0094)
 135 /* GP1 Timer Terminal Count Register 32bit (R/W) */
 136 #define U300_TIMER_APP_GPT1TC                                   (0x0098)
 137 /* GP1 Timer Interrupt Enable Register 32bit (-/W) */
 138 #define U300_TIMER_APP_GPT1IE                                   (0x009c)
 139 #define U300_TIMER_APP_GPT1IE_IRQ_DISABLE                       (0x00000000)
 140 #define U300_TIMER_APP_GPT1IE_IRQ_ENABLE                        (0x00000001)
 141 /* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
 142 #define U300_TIMER_APP_GPT1IA                                   (0x00a0)
 143 #define U300_TIMER_APP_GPT1IA_IRQ_ACK                           (0x00000080)
 144
 145 /* Reset GP2 Timer 32bit (-/W) */
 146 #define U300_TIMER_APP_RGPT2                                    (0x00c0)
 147 #define U300_TIMER_APP_RGPT2_TIMER_RESET                        (0x00000000)
 148 /* Enable GP2 Timer 32bit (-/W) */
 149 #define U300_TIMER_APP_EGPT2                                    (0x00c4)
 150 #define U300_TIMER_APP_EGPT2_TIMER_ENABLE                       (0x00000000)
 151 /* Disable GP2 Timer 32bit (-/W) */
 152 #define U300_TIMER_APP_DGPT2                                    (0x00c8)
 153 #define U300_TIMER_APP_DGPT2_TIMER_DISABLE                      (0x00000000)
 154 /* GP2 Timer Mode Register 32bit (-/W) */
 155 #define U300_TIMER_APP_SGPT2M                                   (0x00cc)
 156 #define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS                   (0x00000000)
 157 #define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT                     (0x00000001)
 158 /* GP2 Timer Status Register 32bit (R/-) */
 159 #define U300_TIMER_APP_GPT2S                                    (0x00d0)
 160 #define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK                   (0x0000000F)
 161 #define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE                   (0x00000001)
 162 #define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE                 (0x00000002)
 163 #define U300_TIMER_APP_GPT2S_ENABLE_IND                         (0x00000010)
 164 #define U300_TIMER_APP_GPT2S_MODE_MASK                          (0x00000020)
 165 #define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS                    (0x00000000)
 166 #define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT                      (0x00000020)
 167 #define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND                    (0x00000040)
 168 #define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND                    (0x00000080)
 169 /* GP2 Timer Current Count Register 32bit (R/-) */
 170 #define U300_TIMER_APP_GPT2CC                                   (0x00d4)
 171 /* GP2 Timer Terminal Count Register 32bit (R/W) */
 172 #define U300_TIMER_APP_GPT2TC                                   (0x00d8)
 173 /* GP2 Timer Interrupt Enable Register 32bit (-/W) */
 174 #define U300_TIMER_APP_GPT2IE                                   (0x00dc)
 175 #define U300_TIMER_APP_GPT2IE_IRQ_DISABLE                       (0x00000000)
 176 #define U300_TIMER_APP_GPT2IE_IRQ_ENABLE                        (0x00000001)
 177 /* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
 178 #define U300_TIMER_APP_GPT2IA                                   (0x00e0)
 179 #define U300_TIMER_APP_GPT2IA_IRQ_ACK                           (0x00000080)
 180
 181 /* Clock request control register - all four timers */
 182 #define U300_TIMER_APP_CRC                                      (0x100)
 183 #define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE                 (0x00000001)
 184
 185 #define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
 186 #define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
 187
 188 /*
 189  * The u300_set_mode() function is always called first, if we
 190  * have oneshot timer active, the oneshot scheduling function
 191  * u300_set_next_event() is called immediately after.
 192  */
 193 static void u300_set_mode(enum clock_event_mode mode,
 194                           struct clock_event_device *evt)
 195 {
 196         switch (mode) {
 197         case CLOCK_EVT_MODE_PERIODIC:
 198                 /* Disable interrupts on GPT1 */
 199                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 200                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 201                 /* Disable GP1 while we're reprogramming it. */
 202                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 203                        U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
 204                 /*
 205                  * Set the periodic mode to a certain number of ticks per
 206                  * jiffy.
 207                  */
 208                 writel(TICKS_PER_JIFFY,
 209                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
 210                 /*
 211                  * Set continuous mode, so the timer keeps triggering
 212                  * interrupts.
 213                  */
 214                 writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
 215                        U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
 216                 /* Enable timer interrupts */
 217                 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 218                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 219                 /* Then enable the OS timer again */
 220                 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 221                        U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
 222                 break;
 223         case CLOCK_EVT_MODE_ONESHOT:
 224                 /* Just break; here? */
 225                 /*
 226                  * The actual event will be programmed by the next event hook,
 227                  * so we just set a dummy value somewhere at the end of the
 228                  * universe here.
 229                  */
 230                 /* Disable interrupts on GPT1 */
 231                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 232                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 233                 /* Disable GP1 while we're reprogramming it. */
 234                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 235                        U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
 236                 /*
 237                  * Expire far in the future, u300_set_next_event() will be
 238                  * called soon...
 239                  */
 240                 writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
 241                 /* We run one shot per tick here! */
 242                 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
 243                        U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
 244                 /* Enable interrupts for this timer */
 245                 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 246                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 247                 /* Enable timer */
 248                 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 249                        U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
 250                 break;
 251         case CLOCK_EVT_MODE_UNUSED:
 252         case CLOCK_EVT_MODE_SHUTDOWN:
 253                 /* Disable interrupts on GP1 */
 254                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 255                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 256                 /* Disable GP1 */
 257                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 258                        U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
 259                 break;
 260         case CLOCK_EVT_MODE_RESUME:
 261                 /* Ignore this call */
 262                 break;
 263         }
 264 }
 265
 266 /*
 267  * The app timer in one shot mode obviously has to be reprogrammed
 268  * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
 269  * the interrupt disable + timer disable commands with a reset command,
 270  * it will fail miserably. Apparently (and I found this the hard way)
 271  * the timer is very sensitive to the instruction order, though you don't
 272  * get that impression from the data sheet.
 273  */
 274 static int u300_set_next_event(unsigned long cycles,
 275                                struct clock_event_device *evt)
 276
 277 {
 278         /* Disable interrupts on GPT1 */
 279         writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 280                U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 281         /* Disable GP1 while we're reprogramming it. */
 282         writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 283                U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
 284         /* Reset the General Purpose timer 1. */
 285         writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
 286                U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
 287         /* IRQ in n * cycles */
 288         writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
 289         /*
 290          * We run one shot per tick here! (This is necessary to reconfigure,
 291          * the timer will tilt if you don't!)
 292          */
 293         writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
 294                U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
 295         /* Enable timer interrupts */
 296         writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 297                U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 298         /* Then enable the OS timer again */
 299         writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 300                U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
 301         return 0;
 302 }
 303
 304
 305 /* Use general purpose timer 1 as clock event */
 306 static struct clock_event_device clockevent_u300_1mhz = {
 307         .name           = "GPT1",
 308         .rating         = 300, /* Reasonably fast and accurate clock event */
 309         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 310         /* 22 calculated using the algorithm in arch/mips/kernel/time.c */
 311         .shift          = 22,
 312         .set_next_event = u300_set_next_event,
 313         .set_mode       = u300_set_mode,
 314 };
 315
 316 /* Clock event timer interrupt handler */
 317 static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
 318 {
 319         struct clock_event_device *evt = &clockevent_u300_1mhz;
 320         /* ACK/Clear timer IRQ for the APP GPT1 Timer */
 321         writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
 322                 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA);
 323         evt->event_handler(evt);
 324         return IRQ_HANDLED;
 325 }
 326
 327 static struct irqaction u300_timer_irq = {
 328         .name           = "U300 Timer Tick",
 329         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 330         .handler        = u300_timer_interrupt,
 331 };
 332
 333 /* Use general purpose timer 2 as clock source */
 334 static cycle_t u300_get_cycles(struct clocksource *cs)
 335 {
 336         return (cycles_t) readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
 337 }
 338
 339 static struct clocksource clocksource_u300_1mhz = {
 340         .name           = "GPT2",
 341         .rating         = 300, /* Reasonably fast and accurate clock source */
 342         .read           = u300_get_cycles,
 343         .mask           = CLOCKSOURCE_MASK(32), /* 32 bits */
 344         /* 22 calculated using the algorithm in arch/mips/kernel/time.c */
 345         .shift          = 22,
 346         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 347 };
 348
 349
 350 /*
 351  * This sets up the system timers, clock source and clock event.
 352  */
 353 static void __init u300_timer_init(void)
 354 {
 355         u300_enable_timer_clock();
 356         /*
 357          * Disable the "OS" and "DD" timers - these are designed for Symbian!
 358          * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
 359          */
 360         writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
 361                 U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
 362         writel(U300_TIMER_APP_ROST_TIMER_RESET,
 363                 U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
 364         writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
 365                 U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
 366         writel(U300_TIMER_APP_RDDT_TIMER_RESET,
 367                 U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
 368         writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
 369                 U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
 370
 371         /* Reset the General Purpose timer 1. */
 372         writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
 373                 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
 374
 375         /* Set up the IRQ handler */
 376         setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
 377
 378         /* Reset the General Purpose timer 2 */
 379         writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
 380                 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
 381         /* Set this timer to run around forever */
 382         writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
 383         /* Set continuous mode so it wraps around */
 384         writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
 385                U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
 386         /* Disable timer interrupts */
 387         writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
 388                 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
 389         /* Then enable the GP2 timer to use as a free running us counter */
 390         writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
 391                 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
 392
 393         /* This is a pure microsecond clock source */
 394         clocksource_u300_1mhz.mult =
 395                 clocksource_khz2mult(1000, clocksource_u300_1mhz.shift);
 396         if (clocksource_register(&clocksource_u300_1mhz))
 397                 printk(KERN_ERR "timer: failed to initialize clock "
 398                        "source %s\n", clocksource_u300_1mhz.name);
 399
 400         clockevent_u300_1mhz.mult =
 401                 div_sc(1000000, NSEC_PER_SEC, clockevent_u300_1mhz.shift);
 402         /* 32bit counter, so 32bits delta is max */
 403         clockevent_u300_1mhz.max_delta_ns =
 404                 clockevent_delta2ns(0xffffffff, &clockevent_u300_1mhz);
 405         /* This timer is slow enough to set for 1 cycle == 1 MHz */
 406         clockevent_u300_1mhz.min_delta_ns =
 407                 clockevent_delta2ns(1, &clockevent_u300_1mhz);
 408         clockevent_u300_1mhz.cpumask = cpumask_of(0);
 409         clockevents_register_device(&clockevent_u300_1mhz);
 410         /*
 411          * TODO: init and register the rest of the timers too, they can be
 412          * used by hrtimers!
 413          */
 414 }
 415
 416 /*
 417  * Very simple system timer that only register the clock event and
 418  * clock source.
 419  */
 420 struct sys_timer u300_timer = {
 421         .init           = u300_timer_init,
 422 };