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   1 /*
   2  * cpu.h: Values of the PRId register used to match up
   3  *        various MIPS cpu types.
   4  *
   5  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
   6  * Copyright (C) 2004  Maciej W. Rozycki
   7  */
   8 #ifndef _ASM_CPU_H
   9 #define _ASM_CPU_H
  10
  11 /* Assigned Company values for bits 23:16 of the PRId Register
  12    (CP0 register 15, select 0).  As of the MIPS32 and MIPS64 specs from
  13    MTI, the PRId register is defined in this (backwards compatible)
  14    way:
  15
  16   +----------------+----------------+----------------+----------------+
  17   | Company Options| Company ID     | Processor ID   | Revision       |
  18   +----------------+----------------+----------------+----------------+
  19    31            24 23            16 15             8 7
  20
  21    I don't have docs for all the previous processors, but my impression is
  22    that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
  23    spec.
  24 */
  25
  26 #define PRID_COMP_LEGACY        0x000000
  27 #define PRID_COMP_MIPS          0x010000
  28 #define PRID_COMP_BROADCOM      0x020000
  29 #define PRID_COMP_ALCHEMY       0x030000
  30 #define PRID_COMP_SIBYTE        0x040000
  31 #define PRID_COMP_SANDCRAFT     0x050000
  32 #define PRID_COMP_PHILIPS       0x060000
  33 #define PRID_COMP_TOSHIBA       0x070000
  34 #define PRID_COMP_LSI           0x080000
  35 #define PRID_COMP_LEXRA         0x0b0000
  36
  37
  38 /*
  39  * Assigned values for the product ID register.  In order to detect a
  40  * certain CPU type exactly eventually additional registers may need to
  41  * be examined.  These are valid when 23:16 == PRID_COMP_LEGACY
  42  */
  43 #define PRID_IMP_R2000          0x0100
  44 #define PRID_IMP_AU1_REV1       0x0100
  45 #define PRID_IMP_AU1_REV2       0x0200
  46 #define PRID_IMP_R3000          0x0200          /* Same as R2000A  */
  47 #define PRID_IMP_R6000          0x0300          /* Same as R3000A  */
  48 #define PRID_IMP_R4000          0x0400
  49 #define PRID_IMP_R6000A         0x0600
  50 #define PRID_IMP_R10000         0x0900
  51 #define PRID_IMP_R4300          0x0b00
  52 #define PRID_IMP_VR41XX         0x0c00
  53 #define PRID_IMP_R12000         0x0e00
  54 #define PRID_IMP_R14000         0x0f00
  55 #define PRID_IMP_R8000          0x1000
  56 #define PRID_IMP_PR4450         0x1200
  57 #define PRID_IMP_R4600          0x2000
  58 #define PRID_IMP_R4700          0x2100
  59 #define PRID_IMP_TX39           0x2200
  60 #define PRID_IMP_R4640          0x2200
  61 #define PRID_IMP_R4650          0x2200          /* Same as R4640 */
  62 #define PRID_IMP_R5000          0x2300
  63 #define PRID_IMP_TX49           0x2d00
  64 #define PRID_IMP_SONIC          0x2400
  65 #define PRID_IMP_MAGIC          0x2500
  66 #define PRID_IMP_RM7000         0x2700
  67 #define PRID_IMP_NEVADA         0x2800          /* RM5260 ??? */
  68 #define PRID_IMP_RM9000         0x3400
  69 #define PRID_IMP_R5432          0x5400
  70 #define PRID_IMP_R5500          0x5500
  71
  72 #define PRID_IMP_UNKNOWN        0xff00
  73
  74 /*
  75  * These are the PRID's for when 23:16 == PRID_COMP_MIPS
  76  */
  77
  78 #define PRID_IMP_4KC            0x8000
  79 #define PRID_IMP_5KC            0x8100
  80 #define PRID_IMP_20KC           0x8200
  81 #define PRID_IMP_4KEC           0x8400
  82 #define PRID_IMP_4KSC           0x8600
  83 #define PRID_IMP_25KF           0x8800
  84 #define PRID_IMP_5KE            0x8900
  85 #define PRID_IMP_4KECR2         0x9000
  86 #define PRID_IMP_4KEMPR2        0x9100
  87 #define PRID_IMP_4KSD           0x9200
  88 #define PRID_IMP_24K            0x9300
  89 #define PRID_IMP_34K            0x9500
  90 #define PRID_IMP_24KE           0x9600
  91 #define PRID_IMP_74K            0x9700
  92 #define PRID_IMP_LOONGSON1      0x4200
  93 #define PRID_IMP_LOONGSON2      0x6300
  94
  95 /*
  96  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
  97  */
  98
  99 #define PRID_IMP_SB1            0x0100
 100 #define PRID_IMP_SB1A           0x1100
 101
 102 /*
 103  * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
 104  */
 105
 106 #define PRID_IMP_SR71000        0x0400
 107
 108 /*
 109  * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
 110  */
 111
 112 #define PRID_IMP_BCM4710        0x4000
 113 #define PRID_IMP_BCM3302        0x9000
 114
 115 /*
 116  * Definitions for 7:0 on legacy processors
 117  */
 118
 119 #define PRID_REV_MASK           0x00ff
 120
 121 #define PRID_REV_TX4927         0x0022
 122 #define PRID_REV_TX4937         0x0030
 123 #define PRID_REV_R4400          0x0040
 124 #define PRID_REV_R3000A         0x0030
 125 #define PRID_REV_R3000          0x0020
 126 #define PRID_REV_R2000A         0x0010
 127 #define PRID_REV_TX3912         0x0010
 128 #define PRID_REV_TX3922         0x0030
 129 #define PRID_REV_TX3927         0x0040
 130 #define PRID_REV_VR4111         0x0050
 131 #define PRID_REV_VR4181         0x0050  /* Same as VR4111 */
 132 #define PRID_REV_VR4121         0x0060
 133 #define PRID_REV_VR4122         0x0070
 134 #define PRID_REV_VR4181A        0x0070  /* Same as VR4122 */
 135 #define PRID_REV_VR4130         0x0080
 136 #define PRID_REV_34K_V1_0_2     0x0022
 137
 138 /*
 139  * Older processors used to encode processor version and revision in two
 140  * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
 141  * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
 142  * the patch number.  *ARGH*
 143  */
 144 #define PRID_REV_ENCODE_44(ver, rev)                                    \
 145         ((ver) << 4 | (rev))
 146 #define PRID_REV_ENCODE_332(ver, rev, patch)                            \
 147         ((ver) << 5 | (rev) << 2 | (patch))
 148
 149 /*
 150  * FPU implementation/revision register (CP1 control register 0).
 151  *
 152  * +---------------------------------+----------------+----------------+
 153  * | 0                               | Implementation | Revision       |
 154  * +---------------------------------+----------------+----------------+
 155  *  31                             16 15             8 7              0
 156  */
 157
 158 #define FPIR_IMP_NONE           0x0000
 159
 160 enum cpu_type_enum {
 161         CPU_UNKNOWN,
 162
 163         /*
 164          * R2000 class processors
 165          */
 166         CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
 167         CPU_R3081, CPU_R3081E,
 168
 169         /*
 170          * R6000 class processors
 171          */
 172         CPU_R6000, CPU_R6000A,
 173
 174         /*
 175          * R4000 class processors
 176          */
 177         CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
 178         CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
 179         CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432,
 180         CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
 181         CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
 182         CPU_SR71000, CPU_RM9000, CPU_TX49XX,
 183
 184         /*
 185          * R8000 class processors
 186          */
 187         CPU_R8000,
 188
 189         /*
 190          * TX3900 class processors
 191          */
 192         CPU_TX3912, CPU_TX3922, CPU_TX3927,
 193
 194         /*
 195          * MIPS32 class processors
 196          */
 197         CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000,
 198         CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, CPU_AU1550,
 199         CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
 200
 201         /*
 202          * MIPS64 class processors
 203          */
 204         CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
 205
 206         CPU_LAST
 207 };
 208
 209
 210 /*
 211  * ISA Level encodings
 212  *
 213  */
 214 #define MIPS_CPU_ISA_I          0x00000001
 215 #define MIPS_CPU_ISA_II         0x00000002
 216 #define MIPS_CPU_ISA_III        0x00000004
 217 #define MIPS_CPU_ISA_IV         0x00000008
 218 #define MIPS_CPU_ISA_V          0x00000010
 219 #define MIPS_CPU_ISA_M32R1      0x00000020
 220 #define MIPS_CPU_ISA_M32R2      0x00000040
 221 #define MIPS_CPU_ISA_M64R1      0x00000080
 222 #define MIPS_CPU_ISA_M64R2      0x00000100
 223
 224 #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
 225         MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
 226 #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
 227         MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
 228
 229 /*
 230  * CPU Option encodings
 231  */
 232 #define MIPS_CPU_TLB            0x00000001 /* CPU has TLB */
 233 #define MIPS_CPU_4KEX           0x00000002 /* "R4K" exception model */
 234 #define MIPS_CPU_3K_CACHE       0x00000004 /* R3000-style caches */
 235 #define MIPS_CPU_4K_CACHE       0x00000008 /* R4000-style caches */
 236 #define MIPS_CPU_TX39_CACHE     0x00000010 /* TX3900-style caches */
 237 #define MIPS_CPU_FPU            0x00000020 /* CPU has FPU */
 238 #define MIPS_CPU_32FPR          0x00000040 /* 32 dbl. prec. FP registers */
 239 #define MIPS_CPU_COUNTER        0x00000080 /* Cycle count/compare */
 240 #define MIPS_CPU_WATCH          0x00000100 /* watchpoint registers */
 241 #define MIPS_CPU_DIVEC          0x00000200 /* dedicated interrupt vector */
 242 #define MIPS_CPU_VCE            0x00000400 /* virt. coherence conflict possible */
 243 #define MIPS_CPU_CACHE_CDEX_P   0x00000800 /* Create_Dirty_Exclusive CACHE op */
 244 #define MIPS_CPU_CACHE_CDEX_S   0x00001000 /* ... same for seconary cache ... */
 245 #define MIPS_CPU_MCHECK         0x00002000 /* Machine check exception */
 246 #define MIPS_CPU_EJTAG          0x00004000 /* EJTAG exception */
 247 #define MIPS_CPU_NOFPUEX        0x00008000 /* no FPU exception */
 248 #define MIPS_CPU_LLSC           0x00010000 /* CPU has ll/sc instructions */
 249 #define MIPS_CPU_INCLUSIVE_CACHES       0x00020000 /* P-cache subset enforced */
 250 #define MIPS_CPU_PREFETCH       0x00040000 /* CPU has usable prefetch */
 251 #define MIPS_CPU_VINT           0x00080000 /* CPU supports MIPSR2 vectored interrupts */
 252 #define MIPS_CPU_VEIC           0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
 253 #define MIPS_CPU_ULRI           0x00200000 /* CPU has ULRI feature */
 254
 255 /*
 256  * CPU ASE encodings
 257  */
 258 #define MIPS_ASE_MIPS16         0x00000001 /* code compression */
 259 #define MIPS_ASE_MDMX           0x00000002 /* MIPS digital media extension */
 260 #define MIPS_ASE_MIPS3D         0x00000004 /* MIPS-3D */
 261 #define MIPS_ASE_SMARTMIPS      0x00000008 /* SmartMIPS */
 262 #define MIPS_ASE_DSP            0x00000010 /* Signal Processing ASE */
 263 #define MIPS_ASE_MIPSMT         0x00000020 /* CPU supports MIPS MT */
 264
 265
 266 #endif /* _ASM_CPU_H */