Merge branch 'avr32-arch' of git://git.kernel.org/pub/scm/linux/kernel/git/hskinnemoe...
[linux-2.6] / arch / powerpc / boot / dts / mpc8568mds.dts
1 /*
2  * MPC8568E MDS Device Tree Source
3  *
4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12 /dts-v1/;
13
14 / {
15         model = "MPC8568EMDS";
16         compatible = "MPC8568EMDS", "MPC85xxMDS";
17         #address-cells = <1>;
18         #size-cells = <1>;
19
20         aliases {
21                 ethernet0 = &enet0;
22                 ethernet1 = &enet1;
23                 ethernet2 = &enet2;
24                 ethernet3 = &enet3;
25                 serial0 = &serial0;
26                 serial1 = &serial1;
27                 pci0 = &pci0;
28                 pci1 = &pci1;
29         };
30
31         cpus {
32                 #address-cells = <1>;
33                 #size-cells = <0>;
34
35                 PowerPC,8568@0 {
36                         device_type = "cpu";
37                         reg = <0x0>;
38                         d-cache-line-size = <32>;       // 32 bytes
39                         i-cache-line-size = <32>;       // 32 bytes
40                         d-cache-size = <0x8000>;                // L1, 32K
41                         i-cache-size = <0x8000>;                // L1, 32K
42                         timebase-frequency = <0>;
43                         bus-frequency = <0>;
44                         clock-frequency = <0>;
45                         next-level-cache = <&L2>;
46                 };
47         };
48
49         memory {
50                 device_type = "memory";
51                 reg = <0x0 0x10000000>;
52         };
53
54         bcsr@f8000000 {
55                 compatible = "fsl,mpc8568mds-bcsr";
56                 reg = <0xf8000000 0x8000>;
57         };
58
59         soc8568@e0000000 {
60                 #address-cells = <1>;
61                 #size-cells = <1>;
62                 device_type = "soc";
63                 compatible = "simple-bus";
64                 ranges = <0x0 0xe0000000 0x100000>;
65                 reg = <0xe0000000 0x1000>;
66                 bus-frequency = <0>;
67
68                 memory-controller@2000 {
69                         compatible = "fsl,8568-memory-controller";
70                         reg = <0x2000 0x1000>;
71                         interrupt-parent = <&mpic>;
72                         interrupts = <18 2>;
73                 };
74
75                 L2: l2-cache-controller@20000 {
76                         compatible = "fsl,8568-l2-cache-controller";
77                         reg = <0x20000 0x1000>;
78                         cache-line-size = <32>; // 32 bytes
79                         cache-size = <0x80000>; // L2, 512K
80                         interrupt-parent = <&mpic>;
81                         interrupts = <16 2>;
82                 };
83
84                 i2c@3000 {
85                         #address-cells = <1>;
86                         #size-cells = <0>;
87                         cell-index = <0>;
88                         compatible = "fsl-i2c";
89                         reg = <0x3000 0x100>;
90                         interrupts = <43 2>;
91                         interrupt-parent = <&mpic>;
92                         dfsrr;
93
94                         rtc@68 {
95                                 compatible = "dallas,ds1374";
96                                 reg = <0x68>;
97                         };
98                 };
99
100                 i2c@3100 {
101                         #address-cells = <1>;
102                         #size-cells = <0>;
103                         cell-index = <1>;
104                         compatible = "fsl-i2c";
105                         reg = <0x3100 0x100>;
106                         interrupts = <43 2>;
107                         interrupt-parent = <&mpic>;
108                         dfsrr;
109                 };
110
111                 dma@21300 {
112                         #address-cells = <1>;
113                         #size-cells = <1>;
114                         compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma";
115                         reg = <0x21300 0x4>;
116                         ranges = <0x0 0x21100 0x200>;
117                         cell-index = <0>;
118                         dma-channel@0 {
119                                 compatible = "fsl,mpc8568-dma-channel",
120                                                 "fsl,eloplus-dma-channel";
121                                 reg = <0x0 0x80>;
122                                 cell-index = <0>;
123                                 interrupt-parent = <&mpic>;
124                                 interrupts = <20 2>;
125                         };
126                         dma-channel@80 {
127                                 compatible = "fsl,mpc8568-dma-channel",
128                                                 "fsl,eloplus-dma-channel";
129                                 reg = <0x80 0x80>;
130                                 cell-index = <1>;
131                                 interrupt-parent = <&mpic>;
132                                 interrupts = <21 2>;
133                         };
134                         dma-channel@100 {
135                                 compatible = "fsl,mpc8568-dma-channel",
136                                                 "fsl,eloplus-dma-channel";
137                                 reg = <0x100 0x80>;
138                                 cell-index = <2>;
139                                 interrupt-parent = <&mpic>;
140                                 interrupts = <22 2>;
141                         };
142                         dma-channel@180 {
143                                 compatible = "fsl,mpc8568-dma-channel",
144                                                 "fsl,eloplus-dma-channel";
145                                 reg = <0x180 0x80>;
146                                 cell-index = <3>;
147                                 interrupt-parent = <&mpic>;
148                                 interrupts = <23 2>;
149                         };
150                 };
151
152                 enet0: ethernet@24000 {
153                         #address-cells = <1>;
154                         #size-cells = <1>;
155                         cell-index = <0>;
156                         device_type = "network";
157                         model = "eTSEC";
158                         compatible = "gianfar";
159                         reg = <0x24000 0x1000>;
160                         ranges = <0x0 0x24000 0x1000>;
161                         local-mac-address = [ 00 00 00 00 00 00 ];
162                         interrupts = <29 2 30 2 34 2>;
163                         interrupt-parent = <&mpic>;
164                         tbi-handle = <&tbi0>;
165                         phy-handle = <&phy2>;
166
167                         mdio@520 {
168                                 #address-cells = <1>;
169                                 #size-cells = <0>;
170                                 compatible = "fsl,gianfar-mdio";
171                                 reg = <0x520 0x20>;
172
173                                 phy0: ethernet-phy@7 {
174                                         interrupt-parent = <&mpic>;
175                                         interrupts = <1 1>;
176                                         reg = <0x7>;
177                                         device_type = "ethernet-phy";
178                                 };
179                                 phy1: ethernet-phy@1 {
180                                         interrupt-parent = <&mpic>;
181                                         interrupts = <2 1>;
182                                         reg = <0x1>;
183                                         device_type = "ethernet-phy";
184                                 };
185                                 phy2: ethernet-phy@2 {
186                                         interrupt-parent = <&mpic>;
187                                         interrupts = <1 1>;
188                                         reg = <0x2>;
189                                         device_type = "ethernet-phy";
190                                 };
191                                 phy3: ethernet-phy@3 {
192                                         interrupt-parent = <&mpic>;
193                                         interrupts = <2 1>;
194                                         reg = <0x3>;
195                                         device_type = "ethernet-phy";
196                                 };
197                                 tbi0: tbi-phy@11 {
198                                         reg = <0x11>;
199                                         device_type = "tbi-phy";
200                                 };
201                         };
202                 };
203
204                 enet1: ethernet@25000 {
205                         #address-cells = <1>;
206                         #size-cells = <1>;
207                         cell-index = <1>;
208                         device_type = "network";
209                         model = "eTSEC";
210                         compatible = "gianfar";
211                         reg = <0x25000 0x1000>;
212                         ranges = <0x0 0x25000 0x1000>;
213                         local-mac-address = [ 00 00 00 00 00 00 ];
214                         interrupts = <35 2 36 2 40 2>;
215                         interrupt-parent = <&mpic>;
216                         tbi-handle = <&tbi1>;
217                         phy-handle = <&phy3>;
218
219                         mdio@520 {
220                                 #address-cells = <1>;
221                                 #size-cells = <0>;
222                                 compatible = "fsl,gianfar-tbi";
223                                 reg = <0x520 0x20>;
224
225                                 tbi1: tbi-phy@11 {
226                                         reg = <0x11>;
227                                         device_type = "tbi-phy";
228                                 };
229                         };
230                 };
231
232                 serial0: serial@4500 {
233                         cell-index = <0>;
234                         device_type = "serial";
235                         compatible = "ns16550";
236                         reg = <0x4500 0x100>;
237                         clock-frequency = <0>;
238                         interrupts = <42 2>;
239                         interrupt-parent = <&mpic>;
240                 };
241
242                 global-utilities@e0000 {        //global utilities block
243                         compatible = "fsl,mpc8548-guts";
244                         reg = <0xe0000 0x1000>;
245                         fsl,has-rstcr;
246                 };
247
248                 serial1: serial@4600 {
249                         cell-index = <1>;
250                         device_type = "serial";
251                         compatible = "ns16550";
252                         reg = <0x4600 0x100>;
253                         clock-frequency = <0>;
254                         interrupts = <42 2>;
255                         interrupt-parent = <&mpic>;
256                 };
257
258                 crypto@30000 {
259                         compatible = "fsl,sec2.1", "fsl,sec2.0";
260                         reg = <0x30000 0x10000>;
261                         interrupts = <45 2>;
262                         interrupt-parent = <&mpic>;
263                         fsl,num-channels = <4>;
264                         fsl,channel-fifo-len = <24>;
265                         fsl,exec-units-mask = <0xfe>;
266                         fsl,descriptor-types-mask = <0x12b0ebf>;
267                 };
268
269                 mpic: pic@40000 {
270                         interrupt-controller;
271                         #address-cells = <0>;
272                         #interrupt-cells = <2>;
273                         reg = <0x40000 0x40000>;
274                         compatible = "chrp,open-pic";
275                         device_type = "open-pic";
276                 };
277
278                 par_io@e0100 {
279                         reg = <0xe0100 0x100>;
280                         device_type = "par_io";
281                         num-ports = <7>;
282
283                         pio1: ucc_pin@01 {
284                                 pio-map = <
285                         /* port  pin  dir  open_drain  assignment  has_irq */
286                                         0x4  0xa  0x1  0x0  0x2  0x0    /* TxD0 */
287                                         0x4  0x9  0x1  0x0  0x2  0x0    /* TxD1 */
288                                         0x4  0x8  0x1  0x0  0x2  0x0    /* TxD2 */
289                                         0x4  0x7  0x1  0x0  0x2  0x0    /* TxD3 */
290                                         0x4  0x17  0x1  0x0  0x2  0x0   /* TxD4 */
291                                         0x4  0x16  0x1  0x0  0x2  0x0   /* TxD5 */
292                                         0x4  0x15  0x1  0x0  0x2  0x0   /* TxD6 */
293                                         0x4  0x14  0x1  0x0  0x2  0x0   /* TxD7 */
294                                         0x4  0xf  0x2  0x0  0x2  0x0    /* RxD0 */
295                                         0x4  0xe  0x2  0x0  0x2  0x0    /* RxD1 */
296                                         0x4  0xd  0x2  0x0  0x2  0x0    /* RxD2 */
297                                         0x4  0xc  0x2  0x0  0x2  0x0    /* RxD3 */
298                                         0x4  0x1d  0x2  0x0  0x2  0x0   /* RxD4 */
299                                         0x4  0x1c  0x2  0x0  0x2  0x0   /* RxD5 */
300                                         0x4  0x1b  0x2  0x0  0x2  0x0   /* RxD6 */
301                                         0x4  0x1a  0x2  0x0  0x2  0x0   /* RxD7 */
302                                         0x4  0xb  0x1  0x0  0x2  0x0    /* TX_EN */
303                                         0x4  0x18  0x1  0x0  0x2  0x0   /* TX_ER */
304                                         0x4  0x10  0x2  0x0  0x2  0x0   /* RX_DV */
305                                         0x4  0x1e  0x2  0x0  0x2  0x0   /* RX_ER */
306                                         0x4  0x11  0x2  0x0  0x2  0x0   /* RX_CLK */
307                                         0x4  0x13  0x1  0x0  0x2  0x0   /* GTX_CLK */
308                                         0x1  0x1f  0x2  0x0  0x3  0x0>; /* GTX125 */
309                         };
310
311                         pio2: ucc_pin@02 {
312                                 pio-map = <
313                         /* port  pin  dir  open_drain  assignment  has_irq */
314                                         0x5  0xa 0x1  0x0  0x2  0x0   /* TxD0 */
315                                         0x5  0x9 0x1  0x0  0x2  0x0   /* TxD1 */
316                                         0x5  0x8 0x1  0x0  0x2  0x0   /* TxD2 */
317                                         0x5  0x7 0x1  0x0  0x2  0x0   /* TxD3 */
318                                         0x5  0x17 0x1  0x0  0x2  0x0   /* TxD4 */
319                                         0x5  0x16 0x1  0x0  0x2  0x0   /* TxD5 */
320                                         0x5  0x15 0x1  0x0  0x2  0x0   /* TxD6 */
321                                         0x5  0x14 0x1  0x0  0x2  0x0   /* TxD7 */
322                                         0x5  0xf 0x2  0x0  0x2  0x0   /* RxD0 */
323                                         0x5  0xe 0x2  0x0  0x2  0x0   /* RxD1 */
324                                         0x5  0xd 0x2  0x0  0x2  0x0   /* RxD2 */
325                                         0x5  0xc 0x2  0x0  0x2  0x0   /* RxD3 */
326                                         0x5  0x1d 0x2  0x0  0x2  0x0   /* RxD4 */
327                                         0x5  0x1c 0x2  0x0  0x2  0x0   /* RxD5 */
328                                         0x5  0x1b 0x2  0x0  0x2  0x0   /* RxD6 */
329                                         0x5  0x1a 0x2  0x0  0x2  0x0   /* RxD7 */
330                                         0x5  0xb 0x1  0x0  0x2  0x0   /* TX_EN */
331                                         0x5  0x18 0x1  0x0  0x2  0x0   /* TX_ER */
332                                         0x5  0x10 0x2  0x0  0x2  0x0   /* RX_DV */
333                                         0x5  0x1e 0x2  0x0  0x2  0x0   /* RX_ER */
334                                         0x5  0x11 0x2  0x0  0x2  0x0   /* RX_CLK */
335                                         0x5  0x13 0x1  0x0  0x2  0x0   /* GTX_CLK */
336                                         0x1  0x1f 0x2  0x0  0x3  0x0   /* GTX125 */
337                                         0x4  0x6 0x3  0x0  0x2  0x0   /* MDIO */
338                                         0x4  0x5 0x1  0x0  0x2  0x0>; /* MDC */
339                         };
340                 };
341         };
342
343         qe@e0080000 {
344                 #address-cells = <1>;
345                 #size-cells = <1>;
346                 device_type = "qe";
347                 compatible = "fsl,qe";
348                 ranges = <0x0 0xe0080000 0x40000>;
349                 reg = <0xe0080000 0x480>;
350                 brg-frequency = <0>;
351                 bus-frequency = <396000000>;
352
353                 muram@10000 {
354                         #address-cells = <1>;
355                         #size-cells = <1>;
356                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
357                         ranges = <0x0 0x10000 0x10000>;
358
359                         data-only@0 {
360                                 compatible = "fsl,qe-muram-data",
361                                              "fsl,cpm-muram-data";
362                                 reg = <0x0 0x10000>;
363                         };
364                 };
365
366                 spi@4c0 {
367                         cell-index = <0>;
368                         compatible = "fsl,spi";
369                         reg = <0x4c0 0x40>;
370                         interrupts = <2>;
371                         interrupt-parent = <&qeic>;
372                         mode = "cpu";
373                 };
374
375                 spi@500 {
376                         cell-index = <1>;
377                         compatible = "fsl,spi";
378                         reg = <0x500 0x40>;
379                         interrupts = <1>;
380                         interrupt-parent = <&qeic>;
381                         mode = "cpu";
382                 };
383
384                 enet2: ucc@2000 {
385                         device_type = "network";
386                         compatible = "ucc_geth";
387                         cell-index = <1>;
388                         reg = <0x2000 0x200>;
389                         interrupts = <32>;
390                         interrupt-parent = <&qeic>;
391                         local-mac-address = [ 00 00 00 00 00 00 ];
392                         rx-clock-name = "none";
393                         tx-clock-name = "clk16";
394                         pio-handle = <&pio1>;
395                         phy-handle = <&phy0>;
396                         phy-connection-type = "rgmii-id";
397                 };
398
399                 enet3: ucc@3000 {
400                         device_type = "network";
401                         compatible = "ucc_geth";
402                         cell-index = <2>;
403                         reg = <0x3000 0x200>;
404                         interrupts = <33>;
405                         interrupt-parent = <&qeic>;
406                         local-mac-address = [ 00 00 00 00 00 00 ];
407                         rx-clock-name = "none";
408                         tx-clock-name = "clk16";
409                         pio-handle = <&pio2>;
410                         phy-handle = <&phy1>;
411                         phy-connection-type = "rgmii-id";
412                 };
413
414                 mdio@2120 {
415                         #address-cells = <1>;
416                         #size-cells = <0>;
417                         reg = <0x2120 0x18>;
418                         compatible = "fsl,ucc-mdio";
419
420                         /* These are the same PHYs as on
421                          * gianfar's MDIO bus */
422                         qe_phy0: ethernet-phy@07 {
423                                 interrupt-parent = <&mpic>;
424                                 interrupts = <1 1>;
425                                 reg = <0x7>;
426                                 device_type = "ethernet-phy";
427                         };
428                         qe_phy1: ethernet-phy@01 {
429                                 interrupt-parent = <&mpic>;
430                                 interrupts = <2 1>;
431                                 reg = <0x1>;
432                                 device_type = "ethernet-phy";
433                         };
434                         qe_phy2: ethernet-phy@02 {
435                                 interrupt-parent = <&mpic>;
436                                 interrupts = <1 1>;
437                                 reg = <0x2>;
438                                 device_type = "ethernet-phy";
439                         };
440                         qe_phy3: ethernet-phy@03 {
441                                 interrupt-parent = <&mpic>;
442                                 interrupts = <2 1>;
443                                 reg = <0x3>;
444                                 device_type = "ethernet-phy";
445                         };
446                 };
447
448                 qeic: interrupt-controller@80 {
449                         interrupt-controller;
450                         compatible = "fsl,qe-ic";
451                         #address-cells = <0>;
452                         #interrupt-cells = <1>;
453                         reg = <0x80 0x80>;
454                         big-endian;
455                         interrupts = <46 2 46 2>; //high:30 low:30
456                         interrupt-parent = <&mpic>;
457                 };
458
459         };
460
461         pci0: pci@e0008000 {
462                 cell-index = <0>;
463                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
464                 interrupt-map = <
465                         /* IDSEL 0x12 AD18 */
466                         0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
467                         0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
468                         0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
469                         0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
470
471                         /* IDSEL 0x13 AD19 */
472                         0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
473                         0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
474                         0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
475                         0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
476
477                 interrupt-parent = <&mpic>;
478                 interrupts = <24 2>;
479                 bus-range = <0 255>;
480                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
481                           0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
482                 clock-frequency = <66666666>;
483                 #interrupt-cells = <1>;
484                 #size-cells = <2>;
485                 #address-cells = <3>;
486                 reg = <0xe0008000 0x1000>;
487                 compatible = "fsl,mpc8540-pci";
488                 device_type = "pci";
489         };
490
491         /* PCI Express */
492         pci1: pcie@e000a000 {
493                 cell-index = <2>;
494                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
495                 interrupt-map = <
496
497                         /* IDSEL 0x0 (PEX) */
498                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
499                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
500                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
501                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
502
503                 interrupt-parent = <&mpic>;
504                 interrupts = <26 2>;
505                 bus-range = <0 255>;
506                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
507                           0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
508                 clock-frequency = <33333333>;
509                 #interrupt-cells = <1>;
510                 #size-cells = <2>;
511                 #address-cells = <3>;
512                 reg = <0xe000a000 0x1000>;
513                 compatible = "fsl,mpc8548-pcie";
514                 device_type = "pci";
515                 pcie@0 {
516                         reg = <0x0 0x0 0x0 0x0 0x0>;
517                         #size-cells = <2>;
518                         #address-cells = <3>;
519                         device_type = "pci";
520                         ranges = <0x2000000 0x0 0xa0000000
521                                   0x2000000 0x0 0xa0000000
522                                   0x0 0x10000000
523
524                                   0x1000000 0x0 0x0
525                                   0x1000000 0x0 0x0
526                                   0x0 0x800000>;
527                 };
528         };
529 };