4 * @brief ME-8100 digital input subdevice instance.
5 * @note Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de)
6 * @author Guenter Gebhardt
7 * @author Krzysztof Gantzke (k.gantzke@meilhaus.de)
11 * Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de)
13 * This file is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
35 #include <linux/module.h>
37 #include <linux/slab.h>
38 #include <linux/spinlock.h>
40 #include <linux/types.h>
41 #include <linux/interrupt.h>
43 #include "medefines.h"
48 #include "meplx_reg.h"
49 #include "me8100_reg.h"
50 #include "me8100_di_reg.h"
51 #include "me8100_di.h"
61 static int me8100_di_io_reset_subdevice(struct me_subdevice *subdevice,
62 struct file *filep, int flags)
64 me8100_di_subdevice_t *instance;
66 unsigned long cpu_flags;
68 PDEBUG("executed.\n");
70 instance = (me8100_di_subdevice_t *) subdevice;
73 PERROR("Invalid flag specified.\n");
74 return ME_ERRNO_INVALID_FLAGS;
79 spin_lock_irqsave(&instance->subdevice_lock, cpu_flags);
80 spin_lock(instance->ctrl_reg_lock);
81 ctrl = inw(instance->ctrl_reg);
82 ctrl &= ~(ME8100_DIO_CTRL_BIT_INTB_1 | ME8100_DIO_CTRL_BIT_INTB_0);
83 outw(ctrl, instance->ctrl_reg);
84 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
85 instance->ctrl_reg - instance->reg_base, ctrl);
86 spin_unlock(instance->ctrl_reg_lock);
88 outw(0, instance->mask_reg);
89 PDEBUG_REG("mask_reg outw(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
90 instance->mask_reg - instance->reg_base, 0);
91 outw(0, instance->pattern_reg);
92 PDEBUG_REG("pattern_reg outw(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
93 instance->pattern_reg - instance->reg_base, 0);
95 instance->irq_count = 0;
96 instance->filtering_flag = 0;
97 spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);
99 outl(PLX_INTCSR_LOCAL_INT1_EN |
100 PLX_INTCSR_LOCAL_INT1_POL |
101 PLX_INTCSR_LOCAL_INT2_EN |
102 PLX_INTCSR_LOCAL_INT2_POL |
103 PLX_INTCSR_PCI_INT_EN, instance->irq_status_reg);
104 PDEBUG_REG("plx:irq_status_reg outl(0x%lX)=0x%x\n",
105 instance->irq_status_reg,
106 PLX_INTCSR_LOCAL_INT1_EN | PLX_INTCSR_LOCAL_INT1_POL |
107 PLX_INTCSR_LOCAL_INT2_EN | PLX_INTCSR_LOCAL_INT2_POL |
108 PLX_INTCSR_PCI_INT_EN);
110 wake_up_interruptible_all(&instance->wait_queue);
113 return ME_ERRNO_SUCCESS;
116 static int me8100_di_io_irq_start(me_subdevice_t *subdevice,
120 int irq_edge, int irq_arg, int flags)
122 me8100_di_subdevice_t *instance;
123 int err = ME_ERRNO_SUCCESS;
125 unsigned long cpu_flags;
127 PDEBUG("executed.\n");
129 instance = (me8100_di_subdevice_t *) subdevice;
131 if (irq_source == ME_IRQ_SOURCE_DIO_PATTERN) {
133 ~(ME_IO_IRQ_START_PATTERN_FILTERING |
134 ME_IO_IRQ_START_DIO_WORD)) {
135 PERROR("Invalid flag specified.\n");
136 return ME_ERRNO_INVALID_FLAGS;
139 if (irq_edge != ME_IRQ_EDGE_NOT_USED) {
140 PERROR("Invalid irq edge specified.\n");
141 return ME_ERRNO_INVALID_IRQ_EDGE;
143 } else if (irq_source == ME_IRQ_SOURCE_DIO_MASK) {
145 ~(ME_IO_IRQ_START_EXTENDED_STATUS |
146 ME_IO_IRQ_START_DIO_WORD)) {
147 PERROR("Invalid flag specified.\n");
148 return ME_ERRNO_INVALID_FLAGS;
151 if (irq_edge != ME_IRQ_EDGE_ANY) {
152 PERROR("Invalid irq edge specified.\n");
153 return ME_ERRNO_INVALID_IRQ_EDGE;
156 if (!(irq_arg & 0xFFFF)) {
157 PERROR("No mask specified.\n");
158 return ME_ERRNO_INVALID_IRQ_ARG;
161 PERROR("Invalid irq source specified.\n");
162 return ME_ERRNO_INVALID_IRQ_SOURCE;
166 PERROR("Invalid channel specified.\n");
167 return ME_ERRNO_INVALID_CHANNEL;
172 spin_lock_irqsave(&instance->subdevice_lock, cpu_flags);
173 if (irq_source == ME_IRQ_SOURCE_DIO_PATTERN) {
174 outw(irq_arg, instance->pattern_reg);
175 instance->compare_value = irq_arg;
176 instance->filtering_flag =
177 (flags & ME_IO_IRQ_START_PATTERN_FILTERING) ? 1 : 0;
179 if (irq_source == ME_IRQ_SOURCE_DIO_MASK) {
180 outw(irq_arg, instance->mask_reg);
183 spin_lock(instance->ctrl_reg_lock);
184 ctrl = inw(instance->ctrl_reg);
185 ctrl |= ME8100_DIO_CTRL_BIT_INTB_0;
186 if (irq_source == ME_IRQ_SOURCE_DIO_PATTERN) {
187 ctrl &= ~ME8100_DIO_CTRL_BIT_INTB_1;
190 if (irq_source == ME_IRQ_SOURCE_DIO_MASK) {
191 ctrl |= ME8100_DIO_CTRL_BIT_INTB_1;
193 outw(ctrl, instance->ctrl_reg);
194 PDEBUG_REG("ctrl_reg outw(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
195 instance->ctrl_reg - instance->reg_base, ctrl);
196 spin_unlock(instance->ctrl_reg_lock);
199 instance->status_value = 0;
200 instance->status_value_edges = 0;
201 instance->line_value = inw(instance->port_reg);
202 instance->status_flag = flags & ME_IO_IRQ_START_EXTENDED_STATUS;
203 spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);
210 static int me8100_di_io_irq_wait(me_subdevice_t *subdevice,
214 int *value, int time_out, int flags)
216 me8100_di_subdevice_t *instance;
217 int err = ME_ERRNO_SUCCESS;
219 unsigned long cpu_flags;
222 PDEBUG("executed.\n");
223 PDEVELOP("PID: %d.\n", current->pid);
225 instance = (me8100_di_subdevice_t *) subdevice;
228 ~(ME_IO_IRQ_WAIT_NORMAL_STATUS | ME_IO_IRQ_WAIT_EXTENDED_STATUS)) {
229 PERROR("Invalid flag specified.\n");
230 return ME_ERRNO_INVALID_FLAGS;
234 PERROR("Invalid channel specified.\n");
235 return ME_ERRNO_INVALID_CHANNEL;
239 PERROR("Invalid time_out specified.\n");
240 return ME_ERRNO_INVALID_TIMEOUT;
244 t = (time_out * HZ) / 1000;
252 if (instance->rised <= 0) {
254 count = instance->irq_count;
257 t = wait_event_interruptible_timeout(instance->
265 // t = wait_event_interruptible_timeout(instance->wait_queue, (instance->rised != 0), t);
267 PERROR("Wait on interrupt timed out.\n");
268 err = ME_ERRNO_TIMEOUT;
271 wait_event_interruptible(instance->wait_queue,
272 ((count != instance->irq_count)
273 || (instance->rised < 0)));
274 // wait_event_interruptible(instance->wait_queue, (instance->rised != 0));
277 if (instance->rised < 0) {
278 PERROR("Wait on interrupt aborted by user.\n");
279 err = ME_ERRNO_CANCELLED;
283 if (signal_pending(current)) {
284 PERROR("Wait on interrupt aborted by signal.\n");
285 err = ME_ERRNO_SIGNAL;
288 spin_lock_irqsave(&instance->subdevice_lock, cpu_flags);
289 *irq_count = instance->irq_count;
291 if (flags & ME_IO_IRQ_WAIT_NORMAL_STATUS) {
292 *value = instance->status_value;
293 } else if (flags & ME_IO_IRQ_WAIT_EXTENDED_STATUS) {
294 *value = instance->status_value_edges;
295 } else { // Use default
296 if (!instance->status_flag) {
297 *value = instance->status_value;
299 *value = instance->status_value_edges;
304 instance->status_value = 0;
305 instance->status_value_edges = 0;
310 spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);
317 static int me8100_di_io_irq_stop(me_subdevice_t *subdevice,
318 struct file *filep, int channel, int flags)
320 me8100_di_subdevice_t *instance;
322 unsigned long cpu_flags;
324 PDEBUG("executed.\n");
326 instance = (me8100_di_subdevice_t *) subdevice;
329 PERROR("Invalid flag specified.\n");
330 return ME_ERRNO_INVALID_FLAGS;
334 PERROR("Invalid channel specified.\n");
335 return ME_ERRNO_INVALID_CHANNEL;
340 spin_lock_irqsave(&instance->subdevice_lock, cpu_flags);
341 spin_lock(instance->ctrl_reg_lock);
342 ctrl = inw(instance->ctrl_reg);
343 ctrl &= ~(ME8100_DIO_CTRL_BIT_INTB_1 | ME8100_DIO_CTRL_BIT_INTB_0);
344 outw(ctrl, instance->ctrl_reg);
345 PDEBUG_REG("ctrl_reg outw(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
346 instance->ctrl_reg - instance->reg_base, ctrl);
347 spin_unlock(instance->ctrl_reg_lock);
348 instance->rised = -1;
349 instance->status_value = 0;
350 instance->status_value_edges = 0;
351 instance->filtering_flag = 0;
352 spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);
353 wake_up_interruptible_all(&instance->wait_queue);
357 return ME_ERRNO_SUCCESS;
360 static int me8100_di_io_single_config(me_subdevice_t *subdevice,
366 int trig_type, int trig_edge, int flags)
368 me8100_di_subdevice_t *instance;
369 int err = ME_ERRNO_SUCCESS;
371 PDEBUG("executed.\n");
373 instance = (me8100_di_subdevice_t *) subdevice;
377 spin_lock(&instance->subdevice_lock);
380 case ME_IO_SINGLE_CONFIG_NO_FLAGS:
381 case ME_IO_SINGLE_CONFIG_DIO_WORD:
383 if (single_config == ME_SINGLE_CONFIG_DIO_INPUT) {
386 ("Invalid port configuration specified.\n");
387 err = ME_ERRNO_INVALID_SINGLE_CONFIG;
390 PERROR("Invalid channel number.\n");
391 err = ME_ERRNO_INVALID_CHANNEL;
396 PERROR("Invalid flags specified.\n");
397 err = ME_ERRNO_INVALID_FLAGS;
400 spin_unlock(&instance->subdevice_lock);
407 static int me8100_di_io_single_read(me_subdevice_t *subdevice,
410 int *value, int time_out, int flags)
412 me8100_di_subdevice_t *instance;
413 int err = ME_ERRNO_SUCCESS;
415 PDEBUG("executed.\n");
417 instance = (me8100_di_subdevice_t *) subdevice;
421 spin_lock(&instance->subdevice_lock);
425 case ME_IO_SINGLE_TYPE_DIO_BIT:
426 if ((channel >= 0) && (channel < 16)) {
427 *value = inw(instance->port_reg) & (0x1 << channel);
429 PERROR("Invalid bit number specified.\n");
430 err = ME_ERRNO_INVALID_CHANNEL;
434 case ME_IO_SINGLE_TYPE_DIO_BYTE:
436 *value = inw(instance->port_reg) & 0xFF;
437 } else if (channel == 1) {
438 *value = (inw(instance->port_reg) >> 8) & 0xFF;
440 PERROR("Invalid byte number specified.\n");
441 err = ME_ERRNO_INVALID_CHANNEL;
445 case ME_IO_SINGLE_NO_FLAGS:
446 case ME_IO_SINGLE_TYPE_DIO_WORD:
448 *value = inw(instance->port_reg);
450 PERROR("Invalid word number specified.\n");
451 err = ME_ERRNO_INVALID_CHANNEL;
457 PERROR("Invalid flags specified.\n");
458 err = ME_ERRNO_INVALID_FLAGS;
461 spin_unlock(&instance->subdevice_lock);
468 static int me8100_di_query_number_channels(me_subdevice_t *subdevice,
471 PDEBUG("executed.\n");
473 return ME_ERRNO_SUCCESS;
476 static int me8100_di_query_subdevice_type(me_subdevice_t *subdevice,
477 int *type, int *subtype)
479 PDEBUG("executed.\n");
481 *subtype = ME_SUBTYPE_SINGLE;
482 return ME_ERRNO_SUCCESS;
485 static int me8100_di_query_subdevice_caps(me_subdevice_t *subdevice, int *caps)
487 PDEBUG("executed.\n");
488 *caps = ME_CAPS_DIO_BIT_PATTERN_IRQ | ME_CAPS_DIO_BIT_MASK_IRQ_EDGE_ANY;
489 return ME_ERRNO_SUCCESS;
492 static void me8100_di_destructor(struct me_subdevice *subdevice)
494 me8100_di_subdevice_t *instance;
496 PDEBUG("executed.\n");
498 instance = (me8100_di_subdevice_t *) subdevice;
500 free_irq(instance->irq, (void *)instance);
501 me_subdevice_deinit(&instance->base);
505 static irqreturn_t me8100_isr(int irq, void *dev_id)
507 me8100_di_subdevice_t *instance;
511 uint16_t line_value = 0;
513 uint32_t status_val = 0;
515 PDEBUG("executed.\n");
517 instance = (me8100_di_subdevice_t *) dev_id;
519 if (irq != instance->irq) {
520 PERROR("Incorrect interrupt num: %d.\n", irq);
524 icsr = inl(instance->irq_status_reg);
525 if (instance->di_idx == 0) {
528 (PLX_INTCSR_LOCAL_INT1_STATE | PLX_INTCSR_PCI_INT_EN |
529 PLX_INTCSR_LOCAL_INT1_EN)) !=
530 (PLX_INTCSR_LOCAL_INT1_STATE | PLX_INTCSR_PCI_INT_EN |
531 PLX_INTCSR_LOCAL_INT1_EN)) {
533 ("%ld Shared interrupt. %s(): idx=0 plx:irq_status_reg=0x%04X\n",
534 jiffies, __func__, icsr);
537 } else if (instance->di_idx == 1) {
539 (PLX_INTCSR_LOCAL_INT2_STATE | PLX_INTCSR_PCI_INT_EN |
540 PLX_INTCSR_LOCAL_INT2_EN)) !=
541 (PLX_INTCSR_LOCAL_INT2_STATE | PLX_INTCSR_PCI_INT_EN |
542 PLX_INTCSR_LOCAL_INT2_EN)) {
544 ("%ld Shared interrupt. %s(): idx=1 plx:irq_status_reg=0x%04X\n",
545 jiffies, __func__, icsr);
549 PERROR("%s():Wrong interrupt idx=%d csr=0x%X.\n", __func__,
550 instance->di_idx, icsr);
554 PDEBUG("me8100_isr():Interrupt from idx=%d occured.\n",
556 spin_lock(&instance->subdevice_lock);
557 inw(instance->irq_reset_reg);
558 line_value = inw(instance->port_reg);
560 irq_status = instance->line_value ^ line_value;
562 // Make extended information.
563 status_val |= (0x00FF & (~(uint16_t) instance->line_value & line_value)) << 16; //Raise
564 status_val |= (0x00FF & ((uint16_t) instance->line_value & ~line_value)); //Fall
566 instance->line_value = line_value;
568 if (instance->rised == 0) {
569 instance->status_value = irq_status;
570 instance->status_value_edges = status_val;
572 instance->status_value |= irq_status;
573 instance->status_value_edges |= status_val;
576 if (instance->filtering_flag) { // For compare mode only.
577 if (instance->compare_value == instance->line_value) {
579 instance->irq_count++;
583 instance->irq_count++;
586 spin_unlock(&instance->subdevice_lock);
587 wake_up_interruptible_all(&instance->wait_queue);
592 me8100_di_subdevice_t *me8100_di_constructor(uint32_t me8100_reg_base,
593 uint32_t plx_reg_base,
596 spinlock_t *ctrl_reg_lock)
598 me8100_di_subdevice_t *subdevice;
601 PDEBUG("executed.\n");
603 /* Allocate memory for subdevice instance */
604 subdevice = kmalloc(sizeof(me8100_di_subdevice_t), GFP_KERNEL);
607 PERROR("Cannot get memory for subdevice instance.\n");
611 memset(subdevice, 0, sizeof(me8100_di_subdevice_t));
613 /* Initialize subdevice base class */
614 err = me_subdevice_init(&subdevice->base);
617 PERROR("Cannot initialize subdevice base class instance.\n");
621 // Initialize spin locks.
622 spin_lock_init(&subdevice->subdevice_lock);
624 subdevice->ctrl_reg_lock = ctrl_reg_lock;
626 /* Save the subdevice index. */
627 subdevice->di_idx = di_idx;
629 /* Initialize wait queue */
630 init_waitqueue_head(&subdevice->wait_queue);
632 /* Register interrupt service routine. */
633 subdevice->irq = irq;
634 err = request_irq(subdevice->irq, me8100_isr,
635 IRQF_DISABLED | IRQF_SHARED,
636 ME8100_NAME, (void *)subdevice);
639 PERROR("Cannot initialize subdevice base class instance.\n");
643 PINFO("Registered irq=%d.\n", subdevice->irq);
645 /* Initialize the registers */
646 subdevice->ctrl_reg =
647 me8100_reg_base + ME8100_CTRL_REG_A + di_idx * ME8100_REG_OFFSET;
648 subdevice->port_reg =
649 me8100_reg_base + ME8100_DI_REG_A + di_idx * ME8100_REG_OFFSET;
650 subdevice->mask_reg =
651 me8100_reg_base + ME8100_MASK_REG_A + di_idx * ME8100_REG_OFFSET;
652 subdevice->pattern_reg =
653 me8100_reg_base + ME8100_PATTERN_REG_A + di_idx * ME8100_REG_OFFSET;
654 subdevice->din_int_reg =
655 me8100_reg_base + ME8100_INT_DI_REG_A + di_idx * ME8100_REG_OFFSET;
656 subdevice->irq_reset_reg =
657 me8100_reg_base + ME8100_RES_INT_REG_A + di_idx * ME8100_REG_OFFSET;
658 subdevice->irq_status_reg = plx_reg_base + PLX_INTCSR;
659 #ifdef MEDEBUG_DEBUG_REG
660 subdevice->reg_base = me8100_reg_base;
663 /* Overload base class methods. */
664 subdevice->base.me_subdevice_io_irq_start = me8100_di_io_irq_start;
665 subdevice->base.me_subdevice_io_irq_wait = me8100_di_io_irq_wait;
666 subdevice->base.me_subdevice_io_irq_stop = me8100_di_io_irq_stop;
667 subdevice->base.me_subdevice_io_reset_subdevice =
668 me8100_di_io_reset_subdevice;
669 subdevice->base.me_subdevice_io_single_config =
670 me8100_di_io_single_config;
671 subdevice->base.me_subdevice_io_single_read = me8100_di_io_single_read;
672 subdevice->base.me_subdevice_query_number_channels =
673 me8100_di_query_number_channels;
674 subdevice->base.me_subdevice_query_subdevice_type =
675 me8100_di_query_subdevice_type;
676 subdevice->base.me_subdevice_query_subdevice_caps =
677 me8100_di_query_subdevice_caps;
678 subdevice->base.me_subdevice_destructor = me8100_di_destructor;
680 subdevice->rised = 0;
681 subdevice->irq_count = 0;