git.oblomov.eu Git - linux-2.6/blob - drivers/scsi/qla2xxx/qla_sup.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2005 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8
   9 #include <linux/delay.h>
  10 #include <linux/vmalloc.h>
  11 #include <asm/uaccess.h>
  12
  13 static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
  14 static void qla2x00_nv_deselect(scsi_qla_host_t *);
  15 static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
  16
  17 /*
  18  * NVRAM support routines
  19  */
  20
  21 /**
  22  * qla2x00_lock_nvram_access() -
  23  * @ha: HA context
  24  */
  25 static void
  26 qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
  27 {
  28         uint16_t data;
  29         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  30
  31         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  32                 data = RD_REG_WORD(&reg->nvram);
  33                 while (data & NVR_BUSY) {
  34                         udelay(100);
  35                         data = RD_REG_WORD(&reg->nvram);
  36                 }
  37
  38                 /* Lock resource */
  39                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  40                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  41                 udelay(5);
  42                 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  43                 while ((data & BIT_0) == 0) {
  44                         /* Lock failed */
  45                         udelay(100);
  46                         WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  47                         RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  48                         udelay(5);
  49                         data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  50                 }
  51         }
  52 }
  53
  54 /**
  55  * qla2x00_unlock_nvram_access() -
  56  * @ha: HA context
  57  */
  58 static void
  59 qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
  60 {
  61         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  62
  63         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  64                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
  65                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  66         }
  67 }
  68
  69 /**
  70  * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
  71  *      request routine to get the word from NVRAM.
  72  * @ha: HA context
  73  * @addr: Address in NVRAM to read
  74  *
  75  * Returns the word read from nvram @addr.
  76  */
  77 static uint16_t
  78 qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
  79 {
  80         uint16_t        data;
  81         uint32_t        nv_cmd;
  82
  83         nv_cmd = addr << 16;
  84         nv_cmd |= NV_READ_OP;
  85         data = qla2x00_nvram_request(ha, nv_cmd);
  86
  87         return (data);
  88 }
  89
  90 /**
  91  * qla2x00_write_nvram_word() - Write NVRAM data.
  92  * @ha: HA context
  93  * @addr: Address in NVRAM to write
  94  * @data: word to program
  95  */
  96 static void
  97 qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
  98 {
  99         int count;
 100         uint16_t word;
 101         uint32_t nv_cmd, wait_cnt;
 102         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 103
 104         qla2x00_nv_write(ha, NVR_DATA_OUT);
 105         qla2x00_nv_write(ha, 0);
 106         qla2x00_nv_write(ha, 0);
 107
 108         for (word = 0; word < 8; word++)
 109                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 110
 111         qla2x00_nv_deselect(ha);
 112
 113         /* Write data */
 114         nv_cmd = (addr << 16) | NV_WRITE_OP;
 115         nv_cmd |= data;
 116         nv_cmd <<= 5;
 117         for (count = 0; count < 27; count++) {
 118                 if (nv_cmd & BIT_31)
 119                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 120                 else
 121                         qla2x00_nv_write(ha, 0);
 122
 123                 nv_cmd <<= 1;
 124         }
 125
 126         qla2x00_nv_deselect(ha);
 127
 128         /* Wait for NVRAM to become ready */
 129         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 130         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 131         wait_cnt = NVR_WAIT_CNT;
 132         do {
 133                 if (!--wait_cnt) {
 134                         DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
 135                             __func__, ha->host_no));
 136                         break;
 137                 }
 138                 NVRAM_DELAY();
 139                 word = RD_REG_WORD(&reg->nvram);
 140         } while ((word & NVR_DATA_IN) == 0);
 141
 142         qla2x00_nv_deselect(ha);
 143
 144         /* Disable writes */
 145         qla2x00_nv_write(ha, NVR_DATA_OUT);
 146         for (count = 0; count < 10; count++)
 147                 qla2x00_nv_write(ha, 0);
 148
 149         qla2x00_nv_deselect(ha);
 150 }
 151
 152 static int
 153 qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
 154     uint32_t tmo)
 155 {
 156         int ret, count;
 157         uint16_t word;
 158         uint32_t nv_cmd;
 159         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 160
 161         ret = QLA_SUCCESS;
 162
 163         qla2x00_nv_write(ha, NVR_DATA_OUT);
 164         qla2x00_nv_write(ha, 0);
 165         qla2x00_nv_write(ha, 0);
 166
 167         for (word = 0; word < 8; word++)
 168                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 169
 170         qla2x00_nv_deselect(ha);
 171
 172         /* Write data */
 173         nv_cmd = (addr << 16) | NV_WRITE_OP;
 174         nv_cmd |= data;
 175         nv_cmd <<= 5;
 176         for (count = 0; count < 27; count++) {
 177                 if (nv_cmd & BIT_31)
 178                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 179                 else
 180                         qla2x00_nv_write(ha, 0);
 181
 182                 nv_cmd <<= 1;
 183         }
 184
 185         qla2x00_nv_deselect(ha);
 186
 187         /* Wait for NVRAM to become ready */
 188         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 189         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 190         do {
 191                 NVRAM_DELAY();
 192                 word = RD_REG_WORD(&reg->nvram);
 193                 if (!--tmo) {
 194                         ret = QLA_FUNCTION_FAILED;
 195                         break;
 196                 }
 197         } while ((word & NVR_DATA_IN) == 0);
 198
 199         qla2x00_nv_deselect(ha);
 200
 201         /* Disable writes */
 202         qla2x00_nv_write(ha, NVR_DATA_OUT);
 203         for (count = 0; count < 10; count++)
 204                 qla2x00_nv_write(ha, 0);
 205
 206         qla2x00_nv_deselect(ha);
 207
 208         return ret;
 209 }
 210
 211 /**
 212  * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
 213  *      NVRAM.
 214  * @ha: HA context
 215  * @nv_cmd: NVRAM command
 216  *
 217  * Bit definitions for NVRAM command:
 218  *
 219  *      Bit 26     = start bit
 220  *      Bit 25, 24 = opcode
 221  *      Bit 23-16  = address
 222  *      Bit 15-0   = write data
 223  *
 224  * Returns the word read from nvram @addr.
 225  */
 226 static uint16_t
 227 qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
 228 {
 229         uint8_t         cnt;
 230         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 231         uint16_t        data = 0;
 232         uint16_t        reg_data;
 233
 234         /* Send command to NVRAM. */
 235         nv_cmd <<= 5;
 236         for (cnt = 0; cnt < 11; cnt++) {
 237                 if (nv_cmd & BIT_31)
 238                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 239                 else
 240                         qla2x00_nv_write(ha, 0);
 241                 nv_cmd <<= 1;
 242         }
 243
 244         /* Read data from NVRAM. */
 245         for (cnt = 0; cnt < 16; cnt++) {
 246                 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
 247                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 248                 NVRAM_DELAY();
 249                 data <<= 1;
 250                 reg_data = RD_REG_WORD(&reg->nvram);
 251                 if (reg_data & NVR_DATA_IN)
 252                         data |= BIT_0;
 253                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 254                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 255                 NVRAM_DELAY();
 256         }
 257
 258         /* Deselect chip. */
 259         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 260         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 261         NVRAM_DELAY();
 262
 263         return (data);
 264 }
 265
 266 /**
 267  * qla2x00_nv_write() - Clean NVRAM operations.
 268  * @ha: HA context
 269  */
 270 static void
 271 qla2x00_nv_deselect(scsi_qla_host_t *ha)
 272 {
 273         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 274
 275         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 276         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 277         NVRAM_DELAY();
 278 }
 279
 280 /**
 281  * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
 282  * @ha: HA context
 283  * @data: Serial interface selector
 284  */
 285 static void
 286 qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
 287 {
 288         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 289
 290         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
 291         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 292         NVRAM_DELAY();
 293         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT| NVR_CLOCK |
 294             NVR_WRT_ENABLE);
 295         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 296         NVRAM_DELAY();
 297         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
 298         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 299         NVRAM_DELAY();
 300 }
 301
 302 /**
 303  * qla2x00_clear_nvram_protection() -
 304  * @ha: HA context
 305  */
 306 static int
 307 qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
 308 {
 309         int ret, stat;
 310         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 311         uint32_t word, wait_cnt;
 312         uint16_t wprot, wprot_old;
 313
 314         /* Clear NVRAM write protection. */
 315         ret = QLA_FUNCTION_FAILED;
 316
 317         wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 318         stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
 319             __constant_cpu_to_le16(0x1234), 100000);
 320         wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 321         if (stat != QLA_SUCCESS || wprot != 0x1234) {
 322                 /* Write enable. */
 323                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 324                 qla2x00_nv_write(ha, 0);
 325                 qla2x00_nv_write(ha, 0);
 326                 for (word = 0; word < 8; word++)
 327                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 328
 329                 qla2x00_nv_deselect(ha);
 330
 331                 /* Enable protection register. */
 332                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 333                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 334                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 335                 for (word = 0; word < 8; word++)
 336                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 337
 338                 qla2x00_nv_deselect(ha);
 339
 340                 /* Clear protection register (ffff is cleared). */
 341                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 342                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 343                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 344                 for (word = 0; word < 8; word++)
 345                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 346
 347                 qla2x00_nv_deselect(ha);
 348
 349                 /* Wait for NVRAM to become ready. */
 350                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 351                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 352                 wait_cnt = NVR_WAIT_CNT;
 353                 do {
 354                         if (!--wait_cnt) {
 355                                 DEBUG9_10(printk("%s(%ld): NVRAM didn't go "
 356                                     "ready...\n", __func__,
 357                                     ha->host_no));
 358                                 break;
 359                         }
 360                         NVRAM_DELAY();
 361                         word = RD_REG_WORD(&reg->nvram);
 362                 } while ((word & NVR_DATA_IN) == 0);
 363
 364                 if (wait_cnt)
 365                         ret = QLA_SUCCESS;
 366         } else
 367                 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
 368
 369         return ret;
 370 }
 371
 372 static void
 373 qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
 374 {
 375         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 376         uint32_t word, wait_cnt;
 377
 378         if (stat != QLA_SUCCESS)
 379                 return;
 380
 381         /* Set NVRAM write protection. */
 382         /* Write enable. */
 383         qla2x00_nv_write(ha, NVR_DATA_OUT);
 384         qla2x00_nv_write(ha, 0);
 385         qla2x00_nv_write(ha, 0);
 386         for (word = 0; word < 8; word++)
 387                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 388
 389         qla2x00_nv_deselect(ha);
 390
 391         /* Enable protection register. */
 392         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 393         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 394         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 395         for (word = 0; word < 8; word++)
 396                 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 397
 398         qla2x00_nv_deselect(ha);
 399
 400         /* Enable protection register. */
 401         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 402         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 403         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 404         for (word = 0; word < 8; word++)
 405                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 406
 407         qla2x00_nv_deselect(ha);
 408
 409         /* Wait for NVRAM to become ready. */
 410         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 411         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 412         wait_cnt = NVR_WAIT_CNT;
 413         do {
 414                 if (!--wait_cnt) {
 415                         DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
 416                             __func__, ha->host_no));
 417                         break;
 418                 }
 419                 NVRAM_DELAY();
 420                 word = RD_REG_WORD(&reg->nvram);
 421         } while ((word & NVR_DATA_IN) == 0);
 422 }
 423
 424
 425 /*****************************************************************************/
 426 /* Flash Manipulation Routines                                               */
 427 /*****************************************************************************/
 428
 429 #define OPTROM_BURST_SIZE       0x1000
 430 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
 431
 432 static inline uint32_t
 433 flash_conf_to_access_addr(uint32_t faddr)
 434 {
 435         return FARX_ACCESS_FLASH_CONF | faddr;
 436 }
 437
 438 static inline uint32_t
 439 flash_data_to_access_addr(uint32_t faddr)
 440 {
 441         return FARX_ACCESS_FLASH_DATA | faddr;
 442 }
 443
 444 static inline uint32_t
 445 nvram_conf_to_access_addr(uint32_t naddr)
 446 {
 447         return FARX_ACCESS_NVRAM_CONF | naddr;
 448 }
 449
 450 static inline uint32_t
 451 nvram_data_to_access_addr(uint32_t naddr)
 452 {
 453         return FARX_ACCESS_NVRAM_DATA | naddr;
 454 }
 455
 456 static uint32_t
 457 qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
 458 {
 459         int rval;
 460         uint32_t cnt, data;
 461         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 462
 463         WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
 464         /* Wait for READ cycle to complete. */
 465         rval = QLA_SUCCESS;
 466         for (cnt = 3000;
 467             (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
 468             rval == QLA_SUCCESS; cnt--) {
 469                 if (cnt)
 470                         udelay(10);
 471                 else
 472                         rval = QLA_FUNCTION_TIMEOUT;
 473                 cond_resched();
 474         }
 475
 476         /* TODO: What happens if we time out? */
 477         data = 0xDEADDEAD;
 478         if (rval == QLA_SUCCESS)
 479                 data = RD_REG_DWORD(&reg->flash_data);
 480
 481         return data;
 482 }
 483
 484 uint32_t *
 485 qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
 486     uint32_t dwords)
 487 {
 488         uint32_t i;
 489
 490         /* Dword reads to flash. */
 491         for (i = 0; i < dwords; i++, faddr++)
 492                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 493                     flash_data_to_access_addr(faddr)));
 494
 495         return dwptr;
 496 }
 497
 498 static int
 499 qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
 500 {
 501         int rval;
 502         uint32_t cnt;
 503         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 504
 505         WRT_REG_DWORD(&reg->flash_data, data);
 506         RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
 507         WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
 508         /* Wait for Write cycle to complete. */
 509         rval = QLA_SUCCESS;
 510         for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
 511             rval == QLA_SUCCESS; cnt--) {
 512                 if (cnt)
 513                         udelay(10);
 514                 else
 515                         rval = QLA_FUNCTION_TIMEOUT;
 516                 cond_resched();
 517         }
 518         return rval;
 519 }
 520
 521 static void
 522 qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
 523     uint8_t *flash_id)
 524 {
 525         uint32_t ids;
 526
 527         ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
 528         *man_id = LSB(ids);
 529         *flash_id = MSB(ids);
 530
 531         /* Check if man_id and flash_id are valid. */
 532         if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
 533                 /* Read information using 0x9f opcode
 534                  * Device ID, Mfg ID would be read in the format:
 535                  *   <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
 536                  * Example: ATMEL 0x00 01 45 1F
 537                  * Extract MFG and Dev ID from last two bytes.
 538                  */
 539                 ids = qla24xx_read_flash_dword(ha,
 540                     flash_data_to_access_addr(0xd009f));
 541                 *man_id = LSB(ids);
 542                 *flash_id = MSB(ids);
 543         }
 544 }
 545
 546 static int
 547 qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
 548     uint32_t dwords)
 549 {
 550         int ret;
 551         uint32_t liter, miter;
 552         uint32_t sec_mask, rest_addr, conf_addr;
 553         uint32_t fdata, findex, cnt;
 554         uint8_t man_id, flash_id;
 555         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 556         dma_addr_t optrom_dma;
 557         void *optrom = NULL;
 558         uint32_t *s, *d;
 559
 560         ret = QLA_SUCCESS;
 561
 562         /* Prepare burst-capable write on supported ISPs. */
 563         if (IS_QLA25XX(ha) && !(faddr & 0xfff) &&
 564             dwords > OPTROM_BURST_DWORDS) {
 565                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
 566                     &optrom_dma, GFP_KERNEL);
 567                 if (!optrom) {
 568                         qla_printk(KERN_DEBUG, ha,
 569                             "Unable to allocate memory for optrom burst write "
 570                             "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
 571                 }
 572         }
 573
 574         qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
 575         DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
 576             ha->host_no, man_id, flash_id));
 577
 578         conf_addr = flash_conf_to_access_addr(0x03d8);
 579         switch (man_id) {
 580         case 0xbf: /* STT flash. */
 581                 if (flash_id == 0x8e) {
 582                         rest_addr = 0x3fff;
 583                         sec_mask = 0x7c000;
 584                 } else {
 585                         rest_addr = 0x1fff;
 586                         sec_mask = 0x7e000;
 587                 }
 588                 if (flash_id == 0x80)
 589                         conf_addr = flash_conf_to_access_addr(0x0352);
 590                 break;
 591         case 0x13: /* ST M25P80. */
 592                 rest_addr = 0x3fff;
 593                 sec_mask = 0x7c000;
 594                 break;
 595         case 0x1f: // Atmel 26DF081A
 596                 rest_addr = 0x3fff;
 597                 sec_mask = 0x7c000;
 598                 conf_addr = flash_conf_to_access_addr(0x0320);
 599                 break;
 600         default:
 601                 /* Default to 64 kb sector size. */
 602                 rest_addr = 0x3fff;
 603                 sec_mask = 0x7c000;
 604                 break;
 605         }
 606
 607         /* Enable flash write. */
 608         WRT_REG_DWORD(&reg->ctrl_status,
 609             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
 610         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 611
 612         /* Disable flash write-protection. */
 613         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
 614         /* Some flash parts need an additional zero-write to clear bits.*/
 615         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
 616
 617         for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
 618                 if (man_id == 0x1f) {
 619                         findex = faddr << 2;
 620                         fdata = findex & sec_mask;
 621                 } else {
 622                         findex = faddr;
 623                         fdata = (findex & sec_mask) << 2;
 624                 }
 625
 626                 /* Are we at the beginning of a sector? */
 627                 if ((findex & rest_addr) == 0) {
 628                         /* Do sector unprotect at 4K boundry for Atmel part. */
 629                         if (man_id == 0x1f)
 630                                 qla24xx_write_flash_dword(ha,
 631                                     flash_conf_to_access_addr(0x0339),
 632                                     (fdata & 0xff00) | ((fdata << 16) &
 633                                     0xff0000) | ((fdata >> 16) & 0xff));
 634                         ret = qla24xx_write_flash_dword(ha, conf_addr,
 635                             (fdata & 0xff00) |((fdata << 16) &
 636                             0xff0000) | ((fdata >> 16) & 0xff));
 637                         if (ret != QLA_SUCCESS) {
 638                                 DEBUG9(printk("%s(%ld) Unable to flash "
 639                                     "sector: address=%x.\n", __func__,
 640                                     ha->host_no, faddr));
 641                                 break;
 642                         }
 643                 }
 644
 645                 /* Go with burst-write. */
 646                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
 647                         /* Copy data to DMA'ble buffer. */
 648                         for (miter = 0, s = optrom, d = dwptr;
 649                             miter < OPTROM_BURST_DWORDS; miter++, s++, d++)
 650                                 *s = cpu_to_le32(*d);
 651
 652                         ret = qla2x00_load_ram(ha, optrom_dma,
 653                             flash_data_to_access_addr(faddr),
 654                             OPTROM_BURST_DWORDS);
 655                         if (ret != QLA_SUCCESS) {
 656                                 qla_printk(KERN_WARNING, ha,
 657                                     "Unable to burst-write optrom segment "
 658                                     "(%x/%x/%llx).\n", ret,
 659                                     flash_data_to_access_addr(faddr),
 660                                     (unsigned long long)optrom_dma);
 661                                 qla_printk(KERN_WARNING, ha,
 662                                     "Reverting to slow-write.\n");
 663
 664                                 dma_free_coherent(&ha->pdev->dev,
 665                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
 666                                 optrom = NULL;
 667                         } else {
 668                                 liter += OPTROM_BURST_DWORDS - 1;
 669                                 faddr += OPTROM_BURST_DWORDS - 1;
 670                                 dwptr += OPTROM_BURST_DWORDS - 1;
 671                                 continue;
 672                         }
 673                 }
 674
 675                 ret = qla24xx_write_flash_dword(ha,
 676                     flash_data_to_access_addr(faddr), cpu_to_le32(*dwptr));
 677                 if (ret != QLA_SUCCESS) {
 678                         DEBUG9(printk("%s(%ld) Unable to program flash "
 679                             "address=%x data=%x.\n", __func__,
 680                             ha->host_no, faddr, *dwptr));
 681                         break;
 682                 }
 683
 684                 /* Do sector protect at 4K boundry for Atmel part. */
 685                 if (man_id == 0x1f &&
 686                     ((faddr & rest_addr) == rest_addr))
 687                         qla24xx_write_flash_dword(ha,
 688                             flash_conf_to_access_addr(0x0336),
 689                             (fdata & 0xff00) | ((fdata << 16) &
 690                             0xff0000) | ((fdata >> 16) & 0xff));
 691         }
 692
 693         /* Enable flash write-protection and wait for completion. */
 694         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0x9c);
 695         for (cnt = 300; cnt &&
 696             qla24xx_read_flash_dword(ha,
 697                     flash_conf_to_access_addr(0x005)) & BIT_0;
 698             cnt--) {
 699                 udelay(10);
 700         }
 701
 702         /* Disable flash write. */
 703         WRT_REG_DWORD(&reg->ctrl_status,
 704             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
 705         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 706
 707         if (optrom)
 708                 dma_free_coherent(&ha->pdev->dev,
 709                     OPTROM_BURST_SIZE, optrom, optrom_dma);
 710
 711         return ret;
 712 }
 713
 714 uint8_t *
 715 qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 716     uint32_t bytes)
 717 {
 718         uint32_t i;
 719         uint16_t *wptr;
 720
 721         /* Word reads to NVRAM via registers. */
 722         wptr = (uint16_t *)buf;
 723         qla2x00_lock_nvram_access(ha);
 724         for (i = 0; i < bytes >> 1; i++, naddr++)
 725                 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
 726                     naddr));
 727         qla2x00_unlock_nvram_access(ha);
 728
 729         return buf;
 730 }
 731
 732 uint8_t *
 733 qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 734     uint32_t bytes)
 735 {
 736         uint32_t i;
 737         uint32_t *dwptr;
 738
 739         /* Dword reads to flash. */
 740         dwptr = (uint32_t *)buf;
 741         for (i = 0; i < bytes >> 2; i++, naddr++)
 742                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 743                     nvram_data_to_access_addr(naddr)));
 744
 745         return buf;
 746 }
 747
 748 int
 749 qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 750     uint32_t bytes)
 751 {
 752         int ret, stat;
 753         uint32_t i;
 754         uint16_t *wptr;
 755         unsigned long flags;
 756
 757         ret = QLA_SUCCESS;
 758
 759         spin_lock_irqsave(&ha->hardware_lock, flags);
 760         qla2x00_lock_nvram_access(ha);
 761
 762         /* Disable NVRAM write-protection. */
 763         stat = qla2x00_clear_nvram_protection(ha);
 764
 765         wptr = (uint16_t *)buf;
 766         for (i = 0; i < bytes >> 1; i++, naddr++) {
 767                 qla2x00_write_nvram_word(ha, naddr,
 768                     cpu_to_le16(*wptr));
 769                 wptr++;
 770         }
 771
 772         /* Enable NVRAM write-protection. */
 773         qla2x00_set_nvram_protection(ha, stat);
 774
 775         qla2x00_unlock_nvram_access(ha);
 776         spin_unlock_irqrestore(&ha->hardware_lock, flags);
 777
 778         return ret;
 779 }
 780
 781 int
 782 qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 783     uint32_t bytes)
 784 {
 785         int ret;
 786         uint32_t i;
 787         uint32_t *dwptr;
 788         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 789         unsigned long flags;
 790
 791         ret = QLA_SUCCESS;
 792
 793         spin_lock_irqsave(&ha->hardware_lock, flags);
 794         /* Enable flash write. */
 795         WRT_REG_DWORD(&reg->ctrl_status,
 796             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
 797         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 798
 799         /* Disable NVRAM write-protection. */
 800         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
 801             0);
 802         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
 803             0);
 804
 805         /* Dword writes to flash. */
 806         dwptr = (uint32_t *)buf;
 807         for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
 808                 ret = qla24xx_write_flash_dword(ha,
 809                     nvram_data_to_access_addr(naddr),
 810                     cpu_to_le32(*dwptr));
 811                 if (ret != QLA_SUCCESS) {
 812                         DEBUG9(printk("%s(%ld) Unable to program "
 813                             "nvram address=%x data=%x.\n", __func__,
 814                             ha->host_no, naddr, *dwptr));
 815                         break;
 816                 }
 817         }
 818
 819         /* Enable NVRAM write-protection. */
 820         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
 821             0x8c);
 822
 823         /* Disable flash write. */
 824         WRT_REG_DWORD(&reg->ctrl_status,
 825             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
 826         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 827         spin_unlock_irqrestore(&ha->hardware_lock, flags);
 828
 829         return ret;
 830 }
 831
 832 uint8_t *
 833 qla25xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 834     uint32_t bytes)
 835 {
 836         uint32_t i;
 837         uint32_t *dwptr;
 838
 839         /* Dword reads to flash. */
 840         dwptr = (uint32_t *)buf;
 841         for (i = 0; i < bytes >> 2; i++, naddr++)
 842                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 843                     flash_data_to_access_addr(FA_VPD_NVRAM_ADDR | naddr)));
 844
 845         return buf;
 846 }
 847
 848 int
 849 qla25xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 850     uint32_t bytes)
 851 {
 852 #define RMW_BUFFER_SIZE (64 * 1024)
 853         uint8_t *dbuf;
 854
 855         dbuf = vmalloc(RMW_BUFFER_SIZE);
 856         if (!dbuf)
 857                 return QLA_MEMORY_ALLOC_FAILED;
 858         ha->isp_ops->read_optrom(ha, dbuf, FA_VPD_NVRAM_ADDR << 2,
 859             RMW_BUFFER_SIZE);
 860         memcpy(dbuf + (naddr << 2), buf, bytes);
 861         ha->isp_ops->write_optrom(ha, dbuf, FA_VPD_NVRAM_ADDR << 2,
 862             RMW_BUFFER_SIZE);
 863         vfree(dbuf);
 864
 865         return QLA_SUCCESS;
 866 }
 867
 868 static inline void
 869 qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
 870 {
 871         if (IS_QLA2322(ha)) {
 872                 /* Flip all colors. */
 873                 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
 874                         /* Turn off. */
 875                         ha->beacon_color_state = 0;
 876                         *pflags = GPIO_LED_ALL_OFF;
 877                 } else {
 878                         /* Turn on. */
 879                         ha->beacon_color_state = QLA_LED_ALL_ON;
 880                         *pflags = GPIO_LED_RGA_ON;
 881                 }
 882         } else {
 883                 /* Flip green led only. */
 884                 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
 885                         /* Turn off. */
 886                         ha->beacon_color_state = 0;
 887                         *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
 888                 } else {
 889                         /* Turn on. */
 890                         ha->beacon_color_state = QLA_LED_GRN_ON;
 891                         *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
 892                 }
 893         }
 894 }
 895
 896 void
 897 qla2x00_beacon_blink(struct scsi_qla_host *ha)
 898 {
 899         uint16_t gpio_enable;
 900         uint16_t gpio_data;
 901         uint16_t led_color = 0;
 902         unsigned long flags;
 903         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 904
 905         if (ha->pio_address)
 906                 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
 907
 908         spin_lock_irqsave(&ha->hardware_lock, flags);
 909
 910         /* Save the Original GPIOE. */
 911         if (ha->pio_address) {
 912                 gpio_enable = RD_REG_WORD_PIO(&reg->gpioe);
 913                 gpio_data = RD_REG_WORD_PIO(&reg->gpiod);
 914         } else {
 915                 gpio_enable = RD_REG_WORD(&reg->gpioe);
 916                 gpio_data = RD_REG_WORD(&reg->gpiod);
 917         }
 918
 919         /* Set the modified gpio_enable values */
 920         gpio_enable |= GPIO_LED_MASK;
 921
 922         if (ha->pio_address) {
 923                 WRT_REG_WORD_PIO(&reg->gpioe, gpio_enable);
 924         } else {
 925                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
 926                 RD_REG_WORD(&reg->gpioe);
 927         }
 928
 929         qla2x00_flip_colors(ha, &led_color);
 930
 931         /* Clear out any previously set LED color. */
 932         gpio_data &= ~GPIO_LED_MASK;
 933
 934         /* Set the new input LED color to GPIOD. */
 935         gpio_data |= led_color;
 936
 937         /* Set the modified gpio_data values */
 938         if (ha->pio_address) {
 939                 WRT_REG_WORD_PIO(&reg->gpiod, gpio_data);
 940         } else {
 941                 WRT_REG_WORD(&reg->gpiod, gpio_data);
 942                 RD_REG_WORD(&reg->gpiod);
 943         }
 944
 945         spin_unlock_irqrestore(&ha->hardware_lock, flags);
 946 }
 947
 948 int
 949 qla2x00_beacon_on(struct scsi_qla_host *ha)
 950 {
 951         uint16_t gpio_enable;
 952         uint16_t gpio_data;
 953         unsigned long flags;
 954         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 955
 956         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
 957         ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
 958
 959         if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
 960                 qla_printk(KERN_WARNING, ha,
 961                     "Unable to update fw options (beacon on).\n");
 962                 return QLA_FUNCTION_FAILED;
 963         }
 964
 965         if (ha->pio_address)
 966                 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
 967
 968         /* Turn off LEDs. */
 969         spin_lock_irqsave(&ha->hardware_lock, flags);
 970         if (ha->pio_address) {
 971                 gpio_enable = RD_REG_WORD_PIO(&reg->gpioe);
 972                 gpio_data = RD_REG_WORD_PIO(&reg->gpiod);
 973         } else {
 974                 gpio_enable = RD_REG_WORD(&reg->gpioe);
 975                 gpio_data = RD_REG_WORD(&reg->gpiod);
 976         }
 977         gpio_enable |= GPIO_LED_MASK;
 978
 979         /* Set the modified gpio_enable values. */
 980         if (ha->pio_address) {
 981                 WRT_REG_WORD_PIO(&reg->gpioe, gpio_enable);
 982         } else {
 983                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
 984                 RD_REG_WORD(&reg->gpioe);
 985         }
 986
 987         /* Clear out previously set LED colour. */
 988         gpio_data &= ~GPIO_LED_MASK;
 989         if (ha->pio_address) {
 990                 WRT_REG_WORD_PIO(&reg->gpiod, gpio_data);
 991         } else {
 992                 WRT_REG_WORD(&reg->gpiod, gpio_data);
 993                 RD_REG_WORD(&reg->gpiod);
 994         }
 995         spin_unlock_irqrestore(&ha->hardware_lock, flags);
 996
 997         /*
 998          * Let the per HBA timer kick off the blinking process based on
 999          * the following flags. No need to do anything else now.
1000          */
1001         ha->beacon_blink_led = 1;
1002         ha->beacon_color_state = 0;
1003
1004         return QLA_SUCCESS;
1005 }
1006
1007 int
1008 qla2x00_beacon_off(struct scsi_qla_host *ha)
1009 {
1010         int rval = QLA_SUCCESS;
1011
1012         ha->beacon_blink_led = 0;
1013
1014         /* Set the on flag so when it gets flipped it will be off. */
1015         if (IS_QLA2322(ha))
1016                 ha->beacon_color_state = QLA_LED_ALL_ON;
1017         else
1018                 ha->beacon_color_state = QLA_LED_GRN_ON;
1019
1020         ha->isp_ops->beacon_blink(ha);  /* This turns green LED off */
1021
1022         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1023         ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1024
1025         rval = qla2x00_set_fw_options(ha, ha->fw_options);
1026         if (rval != QLA_SUCCESS)
1027                 qla_printk(KERN_WARNING, ha,
1028                     "Unable to update fw options (beacon off).\n");
1029         return rval;
1030 }
1031
1032
1033 static inline void
1034 qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
1035 {
1036         /* Flip all colors. */
1037         if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1038                 /* Turn off. */
1039                 ha->beacon_color_state = 0;
1040                 *pflags = 0;
1041         } else {
1042                 /* Turn on. */
1043                 ha->beacon_color_state = QLA_LED_ALL_ON;
1044                 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1045         }
1046 }
1047
1048 void
1049 qla24xx_beacon_blink(struct scsi_qla_host *ha)
1050 {
1051         uint16_t led_color = 0;
1052         uint32_t gpio_data;
1053         unsigned long flags;
1054         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1055
1056         /* Save the Original GPIOD. */
1057         spin_lock_irqsave(&ha->hardware_lock, flags);
1058         gpio_data = RD_REG_DWORD(&reg->gpiod);
1059
1060         /* Enable the gpio_data reg for update. */
1061         gpio_data |= GPDX_LED_UPDATE_MASK;
1062
1063         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1064         gpio_data = RD_REG_DWORD(&reg->gpiod);
1065
1066         /* Set the color bits. */
1067         qla24xx_flip_colors(ha, &led_color);
1068
1069         /* Clear out any previously set LED color. */
1070         gpio_data &= ~GPDX_LED_COLOR_MASK;
1071
1072         /* Set the new input LED color to GPIOD. */
1073         gpio_data |= led_color;
1074
1075         /* Set the modified gpio_data values. */
1076         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1077         gpio_data = RD_REG_DWORD(&reg->gpiod);
1078         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1079 }
1080
1081 int
1082 qla24xx_beacon_on(struct scsi_qla_host *ha)
1083 {
1084         uint32_t gpio_data;
1085         unsigned long flags;
1086         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1087
1088         if (ha->beacon_blink_led == 0) {
1089                 /* Enable firmware for update */
1090                 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1091
1092                 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS)
1093                         return QLA_FUNCTION_FAILED;
1094
1095                 if (qla2x00_get_fw_options(ha, ha->fw_options) !=
1096                     QLA_SUCCESS) {
1097                         qla_printk(KERN_WARNING, ha,
1098                             "Unable to update fw options (beacon on).\n");
1099                         return QLA_FUNCTION_FAILED;
1100                 }
1101
1102                 spin_lock_irqsave(&ha->hardware_lock, flags);
1103                 gpio_data = RD_REG_DWORD(&reg->gpiod);
1104
1105                 /* Enable the gpio_data reg for update. */
1106                 gpio_data |= GPDX_LED_UPDATE_MASK;
1107                 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1108                 RD_REG_DWORD(&reg->gpiod);
1109
1110                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1111         }
1112
1113         /* So all colors blink together. */
1114         ha->beacon_color_state = 0;
1115
1116         /* Let the per HBA timer kick off the blinking process. */
1117         ha->beacon_blink_led = 1;
1118
1119         return QLA_SUCCESS;
1120 }
1121
1122 int
1123 qla24xx_beacon_off(struct scsi_qla_host *ha)
1124 {
1125         uint32_t gpio_data;
1126         unsigned long flags;
1127         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1128
1129         ha->beacon_blink_led = 0;
1130         ha->beacon_color_state = QLA_LED_ALL_ON;
1131
1132         ha->isp_ops->beacon_blink(ha);  /* Will flip to all off. */
1133
1134         /* Give control back to firmware. */
1135         spin_lock_irqsave(&ha->hardware_lock, flags);
1136         gpio_data = RD_REG_DWORD(&reg->gpiod);
1137
1138         /* Disable the gpio_data reg for update. */
1139         gpio_data &= ~GPDX_LED_UPDATE_MASK;
1140         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1141         RD_REG_DWORD(&reg->gpiod);
1142         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1143
1144         ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1145
1146         if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1147                 qla_printk(KERN_WARNING, ha,
1148                     "Unable to update fw options (beacon off).\n");
1149                 return QLA_FUNCTION_FAILED;
1150         }
1151
1152         if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1153                 qla_printk(KERN_WARNING, ha,
1154                     "Unable to get fw options (beacon off).\n");
1155                 return QLA_FUNCTION_FAILED;
1156         }
1157
1158         return QLA_SUCCESS;
1159 }
1160
1161
1162 /*
1163  * Flash support routines
1164  */
1165
1166 /**
1167  * qla2x00_flash_enable() - Setup flash for reading and writing.
1168  * @ha: HA context
1169  */
1170 static void
1171 qla2x00_flash_enable(scsi_qla_host_t *ha)
1172 {
1173         uint16_t data;
1174         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1175
1176         data = RD_REG_WORD(&reg->ctrl_status);
1177         data |= CSR_FLASH_ENABLE;
1178         WRT_REG_WORD(&reg->ctrl_status, data);
1179         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1180 }
1181
1182 /**
1183  * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1184  * @ha: HA context
1185  */
1186 static void
1187 qla2x00_flash_disable(scsi_qla_host_t *ha)
1188 {
1189         uint16_t data;
1190         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1191
1192         data = RD_REG_WORD(&reg->ctrl_status);
1193         data &= ~(CSR_FLASH_ENABLE);
1194         WRT_REG_WORD(&reg->ctrl_status, data);
1195         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1196 }
1197
1198 /**
1199  * qla2x00_read_flash_byte() - Reads a byte from flash
1200  * @ha: HA context
1201  * @addr: Address in flash to read
1202  *
1203  * A word is read from the chip, but, only the lower byte is valid.
1204  *
1205  * Returns the byte read from flash @addr.
1206  */
1207 static uint8_t
1208 qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr)
1209 {
1210         uint16_t data;
1211         uint16_t bank_select;
1212         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1213
1214         bank_select = RD_REG_WORD(&reg->ctrl_status);
1215
1216         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1217                 /* Specify 64K address range: */
1218                 /*  clear out Module Select and Flash Address bits [19:16]. */
1219                 bank_select &= ~0xf8;
1220                 bank_select |= addr >> 12 & 0xf0;
1221                 bank_select |= CSR_FLASH_64K_BANK;
1222                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1223                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1224
1225                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1226                 data = RD_REG_WORD(&reg->flash_data);
1227
1228                 return (uint8_t)data;
1229         }
1230
1231         /* Setup bit 16 of flash address. */
1232         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1233                 bank_select |= CSR_FLASH_64K_BANK;
1234                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1235                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1236         } else if (((addr & BIT_16) == 0) &&
1237             (bank_select & CSR_FLASH_64K_BANK)) {
1238                 bank_select &= ~(CSR_FLASH_64K_BANK);
1239                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1240                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1241         }
1242
1243         /* Always perform IO mapped accesses to the FLASH registers. */
1244         if (ha->pio_address) {
1245                 uint16_t data2;
1246
1247                 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
1248                 WRT_REG_WORD_PIO(&reg->flash_address, (uint16_t)addr);
1249                 do {
1250                         data = RD_REG_WORD_PIO(&reg->flash_data);
1251                         barrier();
1252                         cpu_relax();
1253                         data2 = RD_REG_WORD_PIO(&reg->flash_data);
1254                 } while (data != data2);
1255         } else {
1256                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1257                 data = qla2x00_debounce_register(&reg->flash_data);
1258         }
1259
1260         return (uint8_t)data;
1261 }
1262
1263 /**
1264  * qla2x00_write_flash_byte() - Write a byte to flash
1265  * @ha: HA context
1266  * @addr: Address in flash to write
1267  * @data: Data to write
1268  */
1269 static void
1270 qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data)
1271 {
1272         uint16_t bank_select;
1273         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1274
1275         bank_select = RD_REG_WORD(&reg->ctrl_status);
1276         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1277                 /* Specify 64K address range: */
1278                 /*  clear out Module Select and Flash Address bits [19:16]. */
1279                 bank_select &= ~0xf8;
1280                 bank_select |= addr >> 12 & 0xf0;
1281                 bank_select |= CSR_FLASH_64K_BANK;
1282                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1283                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1284
1285                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1286                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1287                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1288                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1289
1290                 return;
1291         }
1292
1293         /* Setup bit 16 of flash address. */
1294         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1295                 bank_select |= CSR_FLASH_64K_BANK;
1296                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1297                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1298         } else if (((addr & BIT_16) == 0) &&
1299             (bank_select & CSR_FLASH_64K_BANK)) {
1300                 bank_select &= ~(CSR_FLASH_64K_BANK);
1301                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1302                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1303         }
1304
1305         /* Always perform IO mapped accesses to the FLASH registers. */
1306         if (ha->pio_address) {
1307                 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
1308                 WRT_REG_WORD_PIO(&reg->flash_address, (uint16_t)addr);
1309                 WRT_REG_WORD_PIO(&reg->flash_data, (uint16_t)data);
1310         } else {
1311                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1312                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1313                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1314                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1315         }
1316 }
1317
1318 /**
1319  * qla2x00_poll_flash() - Polls flash for completion.
1320  * @ha: HA context
1321  * @addr: Address in flash to poll
1322  * @poll_data: Data to be polled
1323  * @man_id: Flash manufacturer ID
1324  * @flash_id: Flash ID
1325  *
1326  * This function polls the device until bit 7 of what is read matches data
1327  * bit 7 or until data bit 5 becomes a 1.  If that hapens, the flash ROM timed
1328  * out (a fatal error).  The flash book recommeds reading bit 7 again after
1329  * reading bit 5 as a 1.
1330  *
1331  * Returns 0 on success, else non-zero.
1332  */
1333 static int
1334 qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data,
1335     uint8_t man_id, uint8_t flash_id)
1336 {
1337         int status;
1338         uint8_t flash_data;
1339         uint32_t cnt;
1340
1341         status = 1;
1342
1343         /* Wait for 30 seconds for command to finish. */
1344         poll_data &= BIT_7;
1345         for (cnt = 3000000; cnt; cnt--) {
1346                 flash_data = qla2x00_read_flash_byte(ha, addr);
1347                 if ((flash_data & BIT_7) == poll_data) {
1348                         status = 0;
1349                         break;
1350                 }
1351
1352                 if (man_id != 0x40 && man_id != 0xda) {
1353                         if ((flash_data & BIT_5) && cnt > 2)
1354                                 cnt = 2;
1355                 }
1356                 udelay(10);
1357                 barrier();
1358                 cond_resched();
1359         }
1360         return status;
1361 }
1362
1363 /**
1364  * qla2x00_program_flash_address() - Programs a flash address
1365  * @ha: HA context
1366  * @addr: Address in flash to program
1367  * @data: Data to be written in flash
1368  * @man_id: Flash manufacturer ID
1369  * @flash_id: Flash ID
1370  *
1371  * Returns 0 on success, else non-zero.
1372  */
1373 static int
1374 qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data,
1375     uint8_t man_id, uint8_t flash_id)
1376 {
1377         /* Write Program Command Sequence. */
1378         if (IS_OEM_001(ha)) {
1379                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1380                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1381                 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1382                 qla2x00_write_flash_byte(ha, addr, data);
1383         } else {
1384                 if (man_id == 0xda && flash_id == 0xc1) {
1385                         qla2x00_write_flash_byte(ha, addr, data);
1386                         if (addr & 0x7e)
1387                                 return 0;
1388                 } else {
1389                         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1390                         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1391                         qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1392                         qla2x00_write_flash_byte(ha, addr, data);
1393                 }
1394         }
1395
1396         udelay(150);
1397
1398         /* Wait for write to complete. */
1399         return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1400 }
1401
1402 /**
1403  * qla2x00_erase_flash() - Erase the flash.
1404  * @ha: HA context
1405  * @man_id: Flash manufacturer ID
1406  * @flash_id: Flash ID
1407  *
1408  * Returns 0 on success, else non-zero.
1409  */
1410 static int
1411 qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id)
1412 {
1413         /* Individual Sector Erase Command Sequence */
1414         if (IS_OEM_001(ha)) {
1415                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1416                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1417                 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1418                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1419                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1420                 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1421         } else {
1422                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1423                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1424                 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1425                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1426                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1427                 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1428         }
1429
1430         udelay(150);
1431
1432         /* Wait for erase to complete. */
1433         return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1434 }
1435
1436 /**
1437  * qla2x00_erase_flash_sector() - Erase a flash sector.
1438  * @ha: HA context
1439  * @addr: Flash sector to erase
1440  * @sec_mask: Sector address mask
1441  * @man_id: Flash manufacturer ID
1442  * @flash_id: Flash ID
1443  *
1444  * Returns 0 on success, else non-zero.
1445  */
1446 static int
1447 qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr,
1448     uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1449 {
1450         /* Individual Sector Erase Command Sequence */
1451         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1452         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1453         qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1454         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1455         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1456         if (man_id == 0x1f && flash_id == 0x13)
1457                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1458         else
1459                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1460
1461         udelay(150);
1462
1463         /* Wait for erase to complete. */
1464         return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1465 }
1466
1467 /**
1468  * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1469  * @man_id: Flash manufacturer ID
1470  * @flash_id: Flash ID
1471  */
1472 static void
1473 qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
1474     uint8_t *flash_id)
1475 {
1476         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1477         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1478         qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1479         *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1480         *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1481         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1482         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1483         qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1484 }
1485
1486 static void
1487 qla2x00_read_flash_data(scsi_qla_host_t *ha, uint8_t *tmp_buf, uint32_t saddr,
1488         uint32_t length)
1489 {
1490         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1491         uint32_t midpoint, ilength;
1492         uint8_t data;
1493
1494         midpoint = length / 2;
1495
1496         WRT_REG_WORD(&reg->nvram, 0);
1497         RD_REG_WORD(&reg->nvram);
1498         for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1499                 if (ilength == midpoint) {
1500                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1501                         RD_REG_WORD(&reg->nvram);
1502                 }
1503                 data = qla2x00_read_flash_byte(ha, saddr);
1504                 if (saddr % 100)
1505                         udelay(10);
1506                 *tmp_buf = data;
1507                 cond_resched();
1508         }
1509 }
1510
1511 static inline void
1512 qla2x00_suspend_hba(struct scsi_qla_host *ha)
1513 {
1514         int cnt;
1515         unsigned long flags;
1516         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1517
1518         /* Suspend HBA. */
1519         scsi_block_requests(ha->host);
1520         ha->isp_ops->disable_intrs(ha);
1521         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1522
1523         /* Pause RISC. */
1524         spin_lock_irqsave(&ha->hardware_lock, flags);
1525         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1526         RD_REG_WORD(&reg->hccr);
1527         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1528                 for (cnt = 0; cnt < 30000; cnt++) {
1529                         if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1530                                 break;
1531                         udelay(100);
1532                 }
1533         } else {
1534                 udelay(10);
1535         }
1536         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1537 }
1538
1539 static inline void
1540 qla2x00_resume_hba(struct scsi_qla_host *ha)
1541 {
1542         /* Resume HBA. */
1543         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1544         set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
1545         qla2xxx_wake_dpc(ha);
1546         qla2x00_wait_for_hba_online(ha);
1547         scsi_unblock_requests(ha->host);
1548 }
1549
1550 uint8_t *
1551 qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1552     uint32_t offset, uint32_t length)
1553 {
1554         uint32_t addr, midpoint;
1555         uint8_t *data;
1556         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1557
1558         /* Suspend HBA. */
1559         qla2x00_suspend_hba(ha);
1560
1561         /* Go with read. */
1562         midpoint = ha->optrom_size / 2;
1563
1564         qla2x00_flash_enable(ha);
1565         WRT_REG_WORD(&reg->nvram, 0);
1566         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
1567         for (addr = offset, data = buf; addr < length; addr++, data++) {
1568                 if (addr == midpoint) {
1569                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1570                         RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
1571                 }
1572
1573                 *data = qla2x00_read_flash_byte(ha, addr);
1574         }
1575         qla2x00_flash_disable(ha);
1576
1577         /* Resume HBA. */
1578         qla2x00_resume_hba(ha);
1579
1580         return buf;
1581 }
1582
1583 int
1584 qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1585     uint32_t offset, uint32_t length)
1586 {
1587
1588         int rval;
1589         uint8_t man_id, flash_id, sec_number, data;
1590         uint16_t wd;
1591         uint32_t addr, liter, sec_mask, rest_addr;
1592         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1593
1594         /* Suspend HBA. */
1595         qla2x00_suspend_hba(ha);
1596
1597         rval = QLA_SUCCESS;
1598         sec_number = 0;
1599
1600         /* Reset ISP chip. */
1601         WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1602         pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1603
1604         /* Go with write. */
1605         qla2x00_flash_enable(ha);
1606         do {    /* Loop once to provide quick error exit */
1607                 /* Structure of flash memory based on manufacturer */
1608                 if (IS_OEM_001(ha)) {
1609                         /* OEM variant with special flash part. */
1610                         man_id = flash_id = 0;
1611                         rest_addr = 0xffff;
1612                         sec_mask   = 0x10000;
1613                         goto update_flash;
1614                 }
1615                 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1616                 switch (man_id) {
1617                 case 0x20: /* ST flash. */
1618                         if (flash_id == 0xd2 || flash_id == 0xe3) {
1619                                 /*
1620                                  * ST m29w008at part - 64kb sector size with
1621                                  * 32kb,8kb,8kb,16kb sectors at memory address
1622                                  * 0xf0000.
1623                                  */
1624                                 rest_addr = 0xffff;
1625                                 sec_mask = 0x10000;
1626                                 break;
1627                         }
1628                         /*
1629                          * ST m29w010b part - 16kb sector size
1630                          * Default to 16kb sectors
1631                          */
1632                         rest_addr = 0x3fff;
1633                         sec_mask = 0x1c000;
1634                         break;
1635                 case 0x40: /* Mostel flash. */
1636                         /* Mostel v29c51001 part - 512 byte sector size. */
1637                         rest_addr = 0x1ff;
1638                         sec_mask = 0x1fe00;
1639                         break;
1640                 case 0xbf: /* SST flash. */
1641                         /* SST39sf10 part - 4kb sector size. */
1642                         rest_addr = 0xfff;
1643                         sec_mask = 0x1f000;
1644                         break;
1645                 case 0xda: /* Winbond flash. */
1646                         /* Winbond W29EE011 part - 256 byte sector size. */
1647                         rest_addr = 0x7f;
1648                         sec_mask = 0x1ff80;
1649                         break;
1650                 case 0xc2: /* Macronix flash. */
1651                         /* 64k sector size. */
1652                         if (flash_id == 0x38 || flash_id == 0x4f) {
1653                                 rest_addr = 0xffff;
1654                                 sec_mask = 0x10000;
1655                                 break;
1656                         }
1657                         /* Fall through... */
1658
1659                 case 0x1f: /* Atmel flash. */
1660                         /* 512k sector size. */
1661                         if (flash_id == 0x13) {
1662                                 rest_addr = 0x7fffffff;
1663                                 sec_mask =   0x80000000;
1664                                 break;
1665                         }
1666                         /* Fall through... */
1667
1668                 case 0x01: /* AMD flash. */
1669                         if (flash_id == 0x38 || flash_id == 0x40 ||
1670                             flash_id == 0x4f) {
1671                                 /* Am29LV081 part - 64kb sector size. */
1672                                 /* Am29LV002BT part - 64kb sector size. */
1673                                 rest_addr = 0xffff;
1674                                 sec_mask = 0x10000;
1675                                 break;
1676                         } else if (flash_id == 0x3e) {
1677                                 /*
1678                                  * Am29LV008b part - 64kb sector size with
1679                                  * 32kb,8kb,8kb,16kb sector at memory address
1680                                  * h0xf0000.
1681                                  */
1682                                 rest_addr = 0xffff;
1683                                 sec_mask = 0x10000;
1684                                 break;
1685                         } else if (flash_id == 0x20 || flash_id == 0x6e) {
1686                                 /*
1687                                  * Am29LV010 part or AM29f010 - 16kb sector
1688                                  * size.
1689                                  */
1690                                 rest_addr = 0x3fff;
1691                                 sec_mask = 0x1c000;
1692                                 break;
1693                         } else if (flash_id == 0x6d) {
1694                                 /* Am29LV001 part - 8kb sector size. */
1695                                 rest_addr = 0x1fff;
1696                                 sec_mask = 0x1e000;
1697                                 break;
1698                         }
1699                 default:
1700                         /* Default to 16 kb sector size. */
1701                         rest_addr = 0x3fff;
1702                         sec_mask = 0x1c000;
1703                         break;
1704                 }
1705
1706 update_flash:
1707                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1708                         if (qla2x00_erase_flash(ha, man_id, flash_id)) {
1709                                 rval = QLA_FUNCTION_FAILED;
1710                                 break;
1711                         }
1712                 }
1713
1714                 for (addr = offset, liter = 0; liter < length; liter++,
1715                     addr++) {
1716                         data = buf[liter];
1717                         /* Are we at the beginning of a sector? */
1718                         if ((addr & rest_addr) == 0) {
1719                                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1720                                         if (addr >= 0x10000UL) {
1721                                                 if (((addr >> 12) & 0xf0) &&
1722                                                     ((man_id == 0x01 &&
1723                                                         flash_id == 0x3e) ||
1724                                                      (man_id == 0x20 &&
1725                                                          flash_id == 0xd2))) {
1726                                                         sec_number++;
1727                                                         if (sec_number == 1) {
1728                                                                 rest_addr =
1729                                                                     0x7fff;
1730                                                                 sec_mask =
1731                                                                     0x18000;
1732                                                         } else if (
1733                                                             sec_number == 2 ||
1734                                                             sec_number == 3) {
1735                                                                 rest_addr =
1736                                                                     0x1fff;
1737                                                                 sec_mask =
1738                                                                     0x1e000;
1739                                                         } else if (
1740                                                             sec_number == 4) {
1741                                                                 rest_addr =
1742                                                                     0x3fff;
1743                                                                 sec_mask =
1744                                                                     0x1c000;
1745                                                         }
1746                                                 }
1747                                         }
1748                                 } else if (addr == ha->optrom_size / 2) {
1749                                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1750                                         RD_REG_WORD(&reg->nvram);
1751                                 }
1752
1753                                 if (flash_id == 0xda && man_id == 0xc1) {
1754                                         qla2x00_write_flash_byte(ha, 0x5555,
1755                                             0xaa);
1756                                         qla2x00_write_flash_byte(ha, 0x2aaa,
1757                                             0x55);
1758                                         qla2x00_write_flash_byte(ha, 0x5555,
1759                                             0xa0);
1760                                 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
1761                                         /* Then erase it */
1762                                         if (qla2x00_erase_flash_sector(ha,
1763                                             addr, sec_mask, man_id,
1764                                             flash_id)) {
1765                                                 rval = QLA_FUNCTION_FAILED;
1766                                                 break;
1767                                         }
1768                                         if (man_id == 0x01 && flash_id == 0x6d)
1769                                                 sec_number++;
1770                                 }
1771                         }
1772
1773                         if (man_id == 0x01 && flash_id == 0x6d) {
1774                                 if (sec_number == 1 &&
1775                                     addr == (rest_addr - 1)) {
1776                                         rest_addr = 0x0fff;
1777                                         sec_mask   = 0x1f000;
1778                                 } else if (sec_number == 3 && (addr & 0x7ffe)) {
1779                                         rest_addr = 0x3fff;
1780                                         sec_mask   = 0x1c000;
1781                                 }
1782                         }
1783
1784                         if (qla2x00_program_flash_address(ha, addr, data,
1785                             man_id, flash_id)) {
1786                                 rval = QLA_FUNCTION_FAILED;
1787                                 break;
1788                         }
1789                         cond_resched();
1790                 }
1791         } while (0);
1792         qla2x00_flash_disable(ha);
1793
1794         /* Resume HBA. */
1795         qla2x00_resume_hba(ha);
1796
1797         return rval;
1798 }
1799
1800 uint8_t *
1801 qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1802     uint32_t offset, uint32_t length)
1803 {
1804         /* Suspend HBA. */
1805         scsi_block_requests(ha->host);
1806         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1807
1808         /* Go with read. */
1809         qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2);
1810
1811         /* Resume HBA. */
1812         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1813         scsi_unblock_requests(ha->host);
1814
1815         return buf;
1816 }
1817
1818 int
1819 qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1820     uint32_t offset, uint32_t length)
1821 {
1822         int rval;
1823
1824         /* Suspend HBA. */
1825         scsi_block_requests(ha->host);
1826         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1827
1828         /* Go with write. */
1829         rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2,
1830             length >> 2);
1831
1832         /* Resume HBA -- RISC reset needed. */
1833         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1834         set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
1835         qla2xxx_wake_dpc(ha);
1836         qla2x00_wait_for_hba_online(ha);
1837         scsi_unblock_requests(ha->host);
1838
1839         return rval;
1840 }
1841
1842 uint8_t *
1843 qla25xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1844     uint32_t offset, uint32_t length)
1845 {
1846         int rval;
1847         dma_addr_t optrom_dma;
1848         void *optrom;
1849         uint8_t *pbuf;
1850         uint32_t faddr, left, burst;
1851
1852         if (offset & 0xfff)
1853                 goto slow_read;
1854         if (length < OPTROM_BURST_SIZE)
1855                 goto slow_read;
1856
1857         optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1858             &optrom_dma, GFP_KERNEL);
1859         if (!optrom) {
1860                 qla_printk(KERN_DEBUG, ha,
1861                     "Unable to allocate memory for optrom burst read "
1862                     "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1863
1864                 goto slow_read;
1865         }
1866
1867         pbuf = buf;
1868         faddr = offset >> 2;
1869         left = length >> 2;
1870         burst = OPTROM_BURST_DWORDS;
1871         while (left != 0) {
1872                 if (burst > left)
1873                         burst = left;
1874
1875                 rval = qla2x00_dump_ram(ha, optrom_dma,
1876                     flash_data_to_access_addr(faddr), burst);
1877                 if (rval) {
1878                         qla_printk(KERN_WARNING, ha,
1879                             "Unable to burst-read optrom segment "
1880                             "(%x/%x/%llx).\n", rval,
1881                             flash_data_to_access_addr(faddr),
1882                             (unsigned long long)optrom_dma);
1883                         qla_printk(KERN_WARNING, ha,
1884                             "Reverting to slow-read.\n");
1885
1886                         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1887                             optrom, optrom_dma);
1888                         goto slow_read;
1889                 }
1890
1891                 memcpy(pbuf, optrom, burst * 4);
1892
1893                 left -= burst;
1894                 faddr += burst;
1895                 pbuf += burst * 4;
1896         }
1897
1898         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
1899             optrom_dma);
1900
1901         return buf;
1902
1903 slow_read:
1904     return qla24xx_read_optrom_data(ha, buf, offset, length);
1905 }
1906
1907 /**
1908  * qla2x00_get_fcode_version() - Determine an FCODE image's version.
1909  * @ha: HA context
1910  * @pcids: Pointer to the FCODE PCI data structure
1911  *
1912  * The process of retrieving the FCODE version information is at best
1913  * described as interesting.
1914  *
1915  * Within the first 100h bytes of the image an ASCII string is present
1916  * which contains several pieces of information including the FCODE
1917  * version.  Unfortunately it seems the only reliable way to retrieve
1918  * the version is by scanning for another sentinel within the string,
1919  * the FCODE build date:
1920  *
1921  *      ... 2.00.02 10/17/02 ...
1922  *
1923  * Returns QLA_SUCCESS on successful retrieval of version.
1924  */
1925 static void
1926 qla2x00_get_fcode_version(scsi_qla_host_t *ha, uint32_t pcids)
1927 {
1928         int ret = QLA_FUNCTION_FAILED;
1929         uint32_t istart, iend, iter, vend;
1930         uint8_t do_next, rbyte, *vbyte;
1931
1932         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
1933
1934         /* Skip the PCI data structure. */
1935         istart = pcids +
1936             ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
1937                 qla2x00_read_flash_byte(ha, pcids + 0x0A));
1938         iend = istart + 0x100;
1939         do {
1940                 /* Scan for the sentinel date string...eeewww. */
1941                 do_next = 0;
1942                 iter = istart;
1943                 while ((iter < iend) && !do_next) {
1944                         iter++;
1945                         if (qla2x00_read_flash_byte(ha, iter) == '/') {
1946                                 if (qla2x00_read_flash_byte(ha, iter + 2) ==
1947                                     '/')
1948                                         do_next++;
1949                                 else if (qla2x00_read_flash_byte(ha,
1950                                     iter + 3) == '/')
1951                                         do_next++;
1952                         }
1953                 }
1954                 if (!do_next)
1955                         break;
1956
1957                 /* Backtrack to previous ' ' (space). */
1958                 do_next = 0;
1959                 while ((iter > istart) && !do_next) {
1960                         iter--;
1961                         if (qla2x00_read_flash_byte(ha, iter) == ' ')
1962                                 do_next++;
1963                 }
1964                 if (!do_next)
1965                         break;
1966
1967                 /*
1968                  * Mark end of version tag, and find previous ' ' (space) or
1969                  * string length (recent FCODE images -- major hack ahead!!!).
1970                  */
1971                 vend = iter - 1;
1972                 do_next = 0;
1973                 while ((iter > istart) && !do_next) {
1974                         iter--;
1975                         rbyte = qla2x00_read_flash_byte(ha, iter);
1976                         if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
1977                                 do_next++;
1978                 }
1979                 if (!do_next)
1980                         break;
1981
1982                 /* Mark beginning of version tag, and copy data. */
1983                 iter++;
1984                 if ((vend - iter) &&
1985                     ((vend - iter) < sizeof(ha->fcode_revision))) {
1986                         vbyte = ha->fcode_revision;
1987                         while (iter <= vend) {
1988                                 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
1989                                 iter++;
1990                         }
1991                         ret = QLA_SUCCESS;
1992                 }
1993         } while (0);
1994
1995         if (ret != QLA_SUCCESS)
1996                 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
1997 }
1998
1999 int
2000 qla2x00_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
2001 {
2002         int ret = QLA_SUCCESS;
2003         uint8_t code_type, last_image;
2004         uint32_t pcihdr, pcids;
2005         uint8_t *dbyte;
2006         uint16_t *dcode;
2007
2008         if (!ha->pio_address || !mbuf)
2009                 return QLA_FUNCTION_FAILED;
2010
2011         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2012         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2013         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2014         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2015
2016         qla2x00_flash_enable(ha);
2017
2018         /* Begin with first PCI expansion ROM header. */
2019         pcihdr = 0;
2020         last_image = 1;
2021         do {
2022                 /* Verify PCI expansion ROM header. */
2023                 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2024                     qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2025                         /* No signature */
2026                         DEBUG2(printk("scsi(%ld): No matching ROM "
2027                             "signature.\n", ha->host_no));
2028                         ret = QLA_FUNCTION_FAILED;
2029                         break;
2030                 }
2031
2032                 /* Locate PCI data structure. */
2033                 pcids = pcihdr +
2034                     ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2035                         qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2036
2037                 /* Validate signature of PCI data structure. */
2038                 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2039                     qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2040                     qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2041                     qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2042                         /* Incorrect header. */
2043                         DEBUG2(printk("%s(): PCI data struct not found "
2044                             "pcir_adr=%x.\n", __func__, pcids));
2045                         ret = QLA_FUNCTION_FAILED;
2046                         break;
2047                 }
2048
2049                 /* Read version */
2050                 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2051                 switch (code_type) {
2052                 case ROM_CODE_TYPE_BIOS:
2053                         /* Intel x86, PC-AT compatible. */
2054                         ha->bios_revision[0] =
2055                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2056                         ha->bios_revision[1] =
2057                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2058                         DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
2059                             ha->bios_revision[1], ha->bios_revision[0]));
2060                         break;
2061                 case ROM_CODE_TYPE_FCODE:
2062                         /* Open Firmware standard for PCI (FCode). */
2063                         /* Eeeewww... */
2064                         qla2x00_get_fcode_version(ha, pcids);
2065                         break;
2066                 case ROM_CODE_TYPE_EFI:
2067                         /* Extensible Firmware Interface (EFI). */
2068                         ha->efi_revision[0] =
2069                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2070                         ha->efi_revision[1] =
2071                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2072                         DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
2073                             ha->efi_revision[1], ha->efi_revision[0]));
2074                         break;
2075                 default:
2076                         DEBUG2(printk("%s(): Unrecognized code type %x at "
2077                             "pcids %x.\n", __func__, code_type, pcids));
2078                         break;
2079                 }
2080
2081                 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2082
2083                 /* Locate next PCI expansion ROM. */
2084                 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2085                     qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2086         } while (!last_image);
2087
2088         if (IS_QLA2322(ha)) {
2089                 /* Read firmware image information. */
2090                 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2091                 dbyte = mbuf;
2092                 memset(dbyte, 0, 8);
2093                 dcode = (uint16_t *)dbyte;
2094
2095                 qla2x00_read_flash_data(ha, dbyte, FA_RISC_CODE_ADDR * 4 + 10,
2096                     8);
2097                 DEBUG3(printk("%s(%ld): dumping fw ver from flash:\n",
2098                     __func__, ha->host_no));
2099                 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2100
2101                 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2102                     dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2103                     (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2104                     dcode[3] == 0)) {
2105                         DEBUG2(printk("%s(): Unrecognized fw revision at "
2106                             "%x.\n", __func__, FA_RISC_CODE_ADDR * 4));
2107                 } else {
2108                         /* values are in big endian */
2109                         ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2110                         ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2111                         ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2112                 }
2113         }
2114
2115         qla2x00_flash_disable(ha);
2116
2117         return ret;
2118 }
2119
2120 int
2121 qla24xx_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
2122 {
2123         int ret = QLA_SUCCESS;
2124         uint32_t pcihdr, pcids;
2125         uint32_t *dcode;
2126         uint8_t *bcode;
2127         uint8_t code_type, last_image;
2128         int i;
2129
2130         if (!mbuf)
2131                 return QLA_FUNCTION_FAILED;
2132
2133         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2134         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2135         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2136         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2137
2138         dcode = mbuf;
2139
2140         /* Begin with first PCI expansion ROM header. */
2141         pcihdr = 0;
2142         last_image = 1;
2143         do {
2144                 /* Verify PCI expansion ROM header. */
2145                 qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20);
2146                 bcode = mbuf + (pcihdr % 4);
2147                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2148                         /* No signature */
2149                         DEBUG2(printk("scsi(%ld): No matching ROM "
2150                             "signature.\n", ha->host_no));
2151                         ret = QLA_FUNCTION_FAILED;
2152                         break;
2153                 }
2154
2155                 /* Locate PCI data structure. */
2156                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2157
2158                 qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20);
2159                 bcode = mbuf + (pcihdr % 4);
2160
2161                 /* Validate signature of PCI data structure. */
2162                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2163                     bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2164                         /* Incorrect header. */
2165                         DEBUG2(printk("%s(): PCI data struct not found "
2166                             "pcir_adr=%x.\n", __func__, pcids));
2167                         ret = QLA_FUNCTION_FAILED;
2168                         break;
2169                 }
2170
2171                 /* Read version */
2172                 code_type = bcode[0x14];
2173                 switch (code_type) {
2174                 case ROM_CODE_TYPE_BIOS:
2175                         /* Intel x86, PC-AT compatible. */
2176                         ha->bios_revision[0] = bcode[0x12];
2177                         ha->bios_revision[1] = bcode[0x13];
2178                         DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
2179                             ha->bios_revision[1], ha->bios_revision[0]));
2180                         break;
2181                 case ROM_CODE_TYPE_FCODE:
2182                         /* Open Firmware standard for PCI (FCode). */
2183                         ha->fcode_revision[0] = bcode[0x12];
2184                         ha->fcode_revision[1] = bcode[0x13];
2185                         DEBUG3(printk("%s(): read FCODE %d.%d.\n", __func__,
2186                             ha->fcode_revision[1], ha->fcode_revision[0]));
2187                         break;
2188                 case ROM_CODE_TYPE_EFI:
2189                         /* Extensible Firmware Interface (EFI). */
2190                         ha->efi_revision[0] = bcode[0x12];
2191                         ha->efi_revision[1] = bcode[0x13];
2192                         DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
2193                             ha->efi_revision[1], ha->efi_revision[0]));
2194                         break;
2195                 default:
2196                         DEBUG2(printk("%s(): Unrecognized code type %x at "
2197                             "pcids %x.\n", __func__, code_type, pcids));
2198                         break;
2199                 }
2200
2201                 last_image = bcode[0x15] & BIT_7;
2202
2203                 /* Locate next PCI expansion ROM. */
2204                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2205         } while (!last_image);
2206
2207         /* Read firmware image information. */
2208         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2209         dcode = mbuf;
2210
2211         qla24xx_read_flash_data(ha, dcode, FA_RISC_CODE_ADDR + 4, 4);
2212         for (i = 0; i < 4; i++)
2213                 dcode[i] = be32_to_cpu(dcode[i]);
2214
2215         if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2216             dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2217             (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2218             dcode[3] == 0)) {
2219                 DEBUG2(printk("%s(): Unrecognized fw version at %x.\n",
2220                     __func__, FA_RISC_CODE_ADDR));
2221         } else {
2222                 ha->fw_revision[0] = dcode[0];
2223                 ha->fw_revision[1] = dcode[1];
2224                 ha->fw_revision[2] = dcode[2];
2225                 ha->fw_revision[3] = dcode[3];
2226         }
2227
2228         return ret;
2229 }