git.oblomov.eu Git - linux-2.6/blob - drivers/ide/pci/hpt34x.c

   1 /*
   2  * Copyright (C) 1998-2000      Andre Hedrick <andre@linux-ide.org>
   3  *
   4  * May be copied or modified under the terms of the GNU General Public License
   5  *
   6  *
   7  * 00:12.0 Unknown mass storage controller:
   8  * Triones Technologies, Inc.
   9  * Unknown device 0003 (rev 01)
  10  *
  11  * hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
  12  * hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
  13  * hde: DMA 2  (0x0000 0x0002) (0x0000 0x0010)
  14  * hdf: DMA 2  (0x0002 0x0012) (0x0010 0x0030)
  15  * hdg: DMA 1  (0x0012 0x0052) (0x0030 0x0070)
  16  * hdh: DMA 1  (0x0052 0x0252) (0x0070 0x00f0)
  17  *
  18  * ide-pci.c reference
  19  *
  20  * Since there are two cards that report almost identically,
  21  * the only discernable difference is the values reported in pcicmd.
  22  * Booting-BIOS card or HPT363 :: pcicmd == 0x07
  23  * Non-bootable card or HPT343 :: pcicmd == 0x05
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/types.h>
  28 #include <linux/kernel.h>
  29 #include <linux/ioport.h>
  30 #include <linux/hdreg.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/pci.h>
  33 #include <linux/init.h>
  34 #include <linux/ide.h>
  35
  36 #define HPT343_DEBUG_DRIVE_INFO         0
  37
  38 static void hpt34x_set_mode(ide_drive_t *drive, const u8 speed)
  39 {
  40         struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  41         u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
  42         u8                      hi_speed, lo_speed;
  43
  44         hi_speed = speed >> 4;
  45         lo_speed = speed & 0x0f;
  46
  47         if (hi_speed & 7) {
  48                 hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
  49         } else {
  50                 lo_speed <<= 5;
  51                 lo_speed >>= 5;
  52         }
  53
  54         pci_read_config_dword(dev, 0x44, &reg1);
  55         pci_read_config_dword(dev, 0x48, &reg2);
  56         tmp1 = ((lo_speed << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
  57         tmp2 = ((hi_speed << drive->dn) | (reg2 & ~(0x11 << drive->dn)));
  58         pci_write_config_dword(dev, 0x44, tmp1);
  59         pci_write_config_dword(dev, 0x48, tmp2);
  60
  61 #if HPT343_DEBUG_DRIVE_INFO
  62         printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \
  63                 " (0x%02x 0x%02x)\n",
  64                 drive->name, ide_xfer_verbose(speed),
  65                 drive->dn, reg1, tmp1, reg2, tmp2,
  66                 hi_speed, lo_speed);
  67 #endif /* HPT343_DEBUG_DRIVE_INFO */
  68 }
  69
  70 static void hpt34x_set_pio_mode(ide_drive_t *drive, const u8 pio)
  71 {
  72         hpt34x_set_mode(drive, XFER_PIO_0 + pio);
  73 }
  74
  75 /*
  76  * If the BIOS does not set the IO base addaress to XX00, 343 will fail.
  77  */
  78 #define HPT34X_PCI_INIT_REG             0x80
  79
  80 static unsigned int __devinit init_chipset_hpt34x(struct pci_dev *dev, const char *name)
  81 {
  82         int i = 0;
  83         unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
  84         unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c };
  85         unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 };
  86         u16 cmd;
  87         unsigned long flags;
  88
  89         local_irq_save(flags);
  90
  91         pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
  92         pci_read_config_word(dev, PCI_COMMAND, &cmd);
  93
  94         if (cmd & PCI_COMMAND_MEMORY)
  95                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
  96         else
  97                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
  98
  99         /*
 100          * Since 20-23 can be assigned and are R/W, we correct them.
 101          */
 102         pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
 103         for(i=0; i<4; i++) {
 104                 dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]);
 105                 dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i];
 106                 dev->resource[i].flags = IORESOURCE_IO;
 107                 pci_write_config_dword(dev,
 108                                 (PCI_BASE_ADDRESS_0 + (i * 4)),
 109                                 dev->resource[i].start);
 110         }
 111         pci_write_config_word(dev, PCI_COMMAND, cmd);
 112
 113         local_irq_restore(flags);
 114
 115         return dev->irq;
 116 }
 117
 118 static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif)
 119 {
 120         hwif->set_pio_mode = &hpt34x_set_pio_mode;
 121         hwif->set_dma_mode = &hpt34x_set_mode;
 122 }
 123
 124 #define IDE_HFLAGS_HPT34X \
 125         (IDE_HFLAG_NO_ATAPI_DMA | \
 126          IDE_HFLAG_NO_DSC | \
 127          IDE_HFLAG_ABUSE_SET_DMA_MODE | \
 128          IDE_HFLAG_NO_AUTODMA)
 129
 130 static const struct ide_port_info hpt34x_chipsets[] __devinitdata = {
 131         { /* 0 */
 132                 .name           = "HPT343",
 133                 .init_chipset   = init_chipset_hpt34x,
 134                 .init_hwif      = init_hwif_hpt34x,
 135                 .extra          = 16,
 136                 .host_flags     = IDE_HFLAGS_HPT34X,
 137                 .pio_mask       = ATA_PIO5,
 138         },
 139         { /* 1 */
 140                 .name           = "HPT345",
 141                 .init_chipset   = init_chipset_hpt34x,
 142                 .init_hwif      = init_hwif_hpt34x,
 143                 .extra          = 16,
 144                 .host_flags     = IDE_HFLAGS_HPT34X | IDE_HFLAG_OFF_BOARD,
 145                 .pio_mask       = ATA_PIO5,
 146 #ifdef CONFIG_HPT34X_AUTODMA
 147                 .swdma_mask     = ATA_SWDMA2,
 148                 .mwdma_mask     = ATA_MWDMA2,
 149                 .udma_mask      = ATA_UDMA2,
 150 #endif
 151         }
 152 };
 153
 154 static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 155 {
 156         const struct ide_port_info *d;
 157         u16 pcicmd = 0;
 158
 159         pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
 160
 161         d = &hpt34x_chipsets[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];
 162
 163         return ide_setup_pci_device(dev, d);
 164 }
 165
 166 static const struct pci_device_id hpt34x_pci_tbl[] = {
 167         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), 0 },
 168         { 0, },
 169 };
 170 MODULE_DEVICE_TABLE(pci, hpt34x_pci_tbl);
 171
 172 static struct pci_driver driver = {
 173         .name           = "HPT34x_IDE",
 174         .id_table       = hpt34x_pci_tbl,
 175         .probe          = hpt34x_init_one,
 176 };
 177
 178 static int __init hpt34x_ide_init(void)
 179 {
 180         return ide_pci_register_driver(&driver);
 181 }
 182
 183 module_init(hpt34x_ide_init);
 184
 185 MODULE_AUTHOR("Andre Hedrick");
 186 MODULE_DESCRIPTION("PCI driver module for Highpoint 34x IDE");
 187 MODULE_LICENSE("GPL");