4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
6 * 2006 (c) MontaVista Software, Inc.
7 * Vitaly Bordug <vbordug@ru.mvista.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
15 #include <linux/stddef.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/errno.h>
19 #include <linux/major.h>
20 #include <linux/delay.h>
21 #include <linux/irq.h>
22 #include <linux/module.h>
23 #include <linux/device.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_platform.h>
26 #include <linux/phy.h>
27 #include <linux/phy_fixed.h>
28 #include <linux/spi/spi.h>
29 #include <linux/fsl_devices.h>
30 #include <linux/fs_enet_pd.h>
31 #include <linux/fs_uart_pd.h>
33 #include <asm/system.h>
34 #include <asm/atomic.h>
39 #include <sysdev/fsl_soc.h>
40 #include <mm/mmu_decl.h>
43 extern void init_fcc_ioports(struct fs_platform_info*);
44 extern void init_fec_ioports(struct fs_platform_info*);
45 extern void init_smc_ioports(struct fs_uart_platform_info*);
46 static phys_addr_t immrbase = -1;
48 phys_addr_t get_immrbase(void)
50 struct device_node *soc;
55 soc = of_find_node_by_type(NULL, "soc");
59 const u32 *prop = of_get_property(soc, "#address-cells", &size);
61 if (prop && size == 4)
66 prop = of_get_property(soc, "ranges", &size);
68 immrbase = of_translate_address(soc, prop + naddr);
76 EXPORT_SYMBOL(get_immrbase);
78 static u32 sysfreq = -1;
80 u32 fsl_get_sys_freq(void)
82 struct device_node *soc;
89 soc = of_find_node_by_type(NULL, "soc");
93 prop = of_get_property(soc, "clock-frequency", &size);
94 if (!prop || size != sizeof(*prop) || *prop == 0)
95 prop = of_get_property(soc, "bus-frequency", &size);
97 if (prop && size == sizeof(*prop))
103 EXPORT_SYMBOL(fsl_get_sys_freq);
105 #if defined(CONFIG_CPM2) || defined(CONFIG_QUICC_ENGINE) || defined(CONFIG_8xx)
107 static u32 brgfreq = -1;
109 u32 get_brgfreq(void)
111 struct device_node *node;
112 const unsigned int *prop;
118 node = of_find_compatible_node(NULL, NULL, "fsl,cpm-brg");
120 prop = of_get_property(node, "clock-frequency", &size);
121 if (prop && size == 4)
128 /* Legacy device binding -- will go away when no users are left. */
129 node = of_find_node_by_type(NULL, "cpm");
131 node = of_find_compatible_node(NULL, NULL, "fsl,qe");
133 node = of_find_node_by_type(NULL, "qe");
136 prop = of_get_property(node, "brg-frequency", &size);
137 if (prop && size == 4)
140 if (brgfreq == -1 || brgfreq == 0) {
141 prop = of_get_property(node, "bus-frequency", &size);
142 if (prop && size == 4)
151 EXPORT_SYMBOL(get_brgfreq);
153 static u32 fs_baudrate = -1;
155 u32 get_baudrate(void)
157 struct device_node *node;
159 if (fs_baudrate != -1)
162 node = of_find_node_by_type(NULL, "serial");
165 const unsigned int *prop = of_get_property(node,
166 "current-speed", &size);
176 EXPORT_SYMBOL(get_baudrate);
177 #endif /* CONFIG_CPM2 */
179 #ifdef CONFIG_FIXED_PHY
180 static int __init of_add_fixed_phys(void)
183 struct device_node *np;
185 struct fixed_phy_status status = {};
187 for_each_node_by_name(np, "ethernet") {
188 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
193 status.duplex = fixed_link[1];
194 status.speed = fixed_link[2];
195 status.pause = fixed_link[3];
196 status.asym_pause = fixed_link[4];
198 ret = fixed_phy_add(PHY_POLL, fixed_link[0], &status);
207 arch_initcall(of_add_fixed_phys);
208 #endif /* CONFIG_FIXED_PHY */
210 static int gfar_mdio_of_init_one(struct device_node *np)
213 struct device_node *child = NULL;
214 struct gianfar_mdio_data mdio_data;
215 struct platform_device *mdio_dev;
219 memset(&res, 0, sizeof(res));
220 memset(&mdio_data, 0, sizeof(mdio_data));
222 ret = of_address_to_resource(np, 0, &res);
226 mdio_dev = platform_device_register_simple("fsl-gianfar_mdio",
227 res.start&0xfffff, &res, 1);
228 if (IS_ERR(mdio_dev))
229 return PTR_ERR(mdio_dev);
231 for (k = 0; k < 32; k++)
232 mdio_data.irq[k] = PHY_POLL;
234 while ((child = of_get_next_child(np, child)) != NULL) {
235 int irq = irq_of_parse_and_map(child, 0);
237 const u32 *id = of_get_property(child, "reg", NULL);
238 mdio_data.irq[*id] = irq;
242 ret = platform_device_add_data(mdio_dev, &mdio_data,
243 sizeof(struct gianfar_mdio_data));
245 platform_device_unregister(mdio_dev);
250 static int __init gfar_mdio_of_init(void)
252 struct device_node *np = NULL;
254 for_each_compatible_node(np, NULL, "fsl,gianfar-mdio")
255 gfar_mdio_of_init_one(np);
257 /* try the deprecated version */
258 for_each_compatible_node(np, "mdio", "gianfar");
259 gfar_mdio_of_init_one(np);
264 arch_initcall(gfar_mdio_of_init);
266 static const char *gfar_tx_intr = "tx";
267 static const char *gfar_rx_intr = "rx";
268 static const char *gfar_err_intr = "error";
270 static int __init gfar_of_init(void)
272 struct device_node *np;
274 struct platform_device *gfar_dev;
278 for (np = NULL, i = 0;
279 (np = of_find_compatible_node(np, "network", "gianfar")) != NULL;
281 struct resource r[4];
282 struct device_node *phy, *mdio;
283 struct gianfar_platform_data gfar_data;
284 const unsigned int *id;
287 const void *mac_addr;
291 if (!of_device_is_available(np))
294 memset(r, 0, sizeof(r));
295 memset(&gfar_data, 0, sizeof(gfar_data));
297 ret = of_address_to_resource(np, 0, &r[0]);
301 of_irq_to_resource(np, 0, &r[1]);
303 model = of_get_property(np, "model", NULL);
305 /* If we aren't the FEC we have multiple interrupts */
306 if (model && strcasecmp(model, "FEC")) {
307 r[1].name = gfar_tx_intr;
309 r[2].name = gfar_rx_intr;
310 of_irq_to_resource(np, 1, &r[2]);
312 r[3].name = gfar_err_intr;
313 of_irq_to_resource(np, 2, &r[3]);
319 platform_device_register_simple("fsl-gianfar", i, &r[0],
322 if (IS_ERR(gfar_dev)) {
323 ret = PTR_ERR(gfar_dev);
327 mac_addr = of_get_mac_address(np);
329 memcpy(gfar_data.mac_addr, mac_addr, 6);
331 if (model && !strcasecmp(model, "TSEC"))
332 gfar_data.device_flags =
333 FSL_GIANFAR_DEV_HAS_GIGABIT |
334 FSL_GIANFAR_DEV_HAS_COALESCE |
335 FSL_GIANFAR_DEV_HAS_RMON |
336 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
337 if (model && !strcasecmp(model, "eTSEC"))
338 gfar_data.device_flags =
339 FSL_GIANFAR_DEV_HAS_GIGABIT |
340 FSL_GIANFAR_DEV_HAS_COALESCE |
341 FSL_GIANFAR_DEV_HAS_RMON |
342 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
343 FSL_GIANFAR_DEV_HAS_CSUM |
344 FSL_GIANFAR_DEV_HAS_VLAN |
345 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
347 ctype = of_get_property(np, "phy-connection-type", NULL);
349 /* We only care about rgmii-id. The rest are autodetected */
350 if (ctype && !strcmp(ctype, "rgmii-id"))
351 gfar_data.interface = PHY_INTERFACE_MODE_RGMII_ID;
353 gfar_data.interface = PHY_INTERFACE_MODE_MII;
355 if (of_get_property(np, "fsl,magic-packet", NULL))
356 gfar_data.device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
358 ph = of_get_property(np, "phy-handle", NULL);
362 fixed_link = (u32 *)of_get_property(np, "fixed-link",
369 snprintf(gfar_data.bus_id, MII_BUS_ID_SIZE, "0");
370 gfar_data.phy_id = fixed_link[0];
372 phy = of_find_node_by_phandle(*ph);
379 mdio = of_get_parent(phy);
381 id = of_get_property(phy, "reg", NULL);
382 ret = of_address_to_resource(mdio, 0, &res);
389 gfar_data.phy_id = *id;
390 snprintf(gfar_data.bus_id, MII_BUS_ID_SIZE, "%llx",
391 (unsigned long long)res.start&0xfffff);
398 platform_device_add_data(gfar_dev, &gfar_data,
400 gianfar_platform_data));
408 platform_device_unregister(gfar_dev);
413 arch_initcall(gfar_of_init);
416 #ifdef CONFIG_PPC_83xx
417 static int __init mpc83xx_wdt_init(void)
420 struct device_node *np;
421 struct platform_device *dev;
422 u32 freq = fsl_get_sys_freq();
425 np = of_find_compatible_node(NULL, "watchdog", "mpc83xx_wdt");
432 memset(&r, 0, sizeof(r));
434 ret = of_address_to_resource(np, 0, &r);
438 dev = platform_device_register_simple("mpc83xx_wdt", 0, &r, 1);
444 ret = platform_device_add_data(dev, &freq, sizeof(freq));
452 platform_device_unregister(dev);
459 arch_initcall(mpc83xx_wdt_init);
462 static enum fsl_usb2_phy_modes determine_usb_phy(const char *phy_type)
465 return FSL_USB2_PHY_NONE;
466 if (!strcasecmp(phy_type, "ulpi"))
467 return FSL_USB2_PHY_ULPI;
468 if (!strcasecmp(phy_type, "utmi"))
469 return FSL_USB2_PHY_UTMI;
470 if (!strcasecmp(phy_type, "utmi_wide"))
471 return FSL_USB2_PHY_UTMI_WIDE;
472 if (!strcasecmp(phy_type, "serial"))
473 return FSL_USB2_PHY_SERIAL;
475 return FSL_USB2_PHY_NONE;
478 static int __init fsl_usb_of_init(void)
480 struct device_node *np;
482 struct platform_device *usb_dev_mph = NULL, *usb_dev_dr_host = NULL,
483 *usb_dev_dr_client = NULL;
486 for_each_compatible_node(np, NULL, "fsl-usb2-mph") {
487 struct resource r[2];
488 struct fsl_usb2_platform_data usb_data;
489 const unsigned char *prop = NULL;
491 memset(&r, 0, sizeof(r));
492 memset(&usb_data, 0, sizeof(usb_data));
494 ret = of_address_to_resource(np, 0, &r[0]);
498 of_irq_to_resource(np, 0, &r[1]);
501 platform_device_register_simple("fsl-ehci", i, r, 2);
502 if (IS_ERR(usb_dev_mph)) {
503 ret = PTR_ERR(usb_dev_mph);
507 usb_dev_mph->dev.coherent_dma_mask = 0xffffffffUL;
508 usb_dev_mph->dev.dma_mask = &usb_dev_mph->dev.coherent_dma_mask;
510 usb_data.operating_mode = FSL_USB2_MPH_HOST;
512 prop = of_get_property(np, "port0", NULL);
514 usb_data.port_enables |= FSL_USB2_PORT0_ENABLED;
516 prop = of_get_property(np, "port1", NULL);
518 usb_data.port_enables |= FSL_USB2_PORT1_ENABLED;
520 prop = of_get_property(np, "phy_type", NULL);
521 usb_data.phy_mode = determine_usb_phy(prop);
524 platform_device_add_data(usb_dev_mph, &usb_data,
526 fsl_usb2_platform_data));
532 for_each_compatible_node(np, NULL, "fsl-usb2-dr") {
533 struct resource r[2];
534 struct fsl_usb2_platform_data usb_data;
535 const unsigned char *prop = NULL;
537 memset(&r, 0, sizeof(r));
538 memset(&usb_data, 0, sizeof(usb_data));
540 ret = of_address_to_resource(np, 0, &r[0]);
544 of_irq_to_resource(np, 0, &r[1]);
546 prop = of_get_property(np, "dr_mode", NULL);
548 if (!prop || !strcmp(prop, "host")) {
549 usb_data.operating_mode = FSL_USB2_DR_HOST;
550 usb_dev_dr_host = platform_device_register_simple(
551 "fsl-ehci", i, r, 2);
552 if (IS_ERR(usb_dev_dr_host)) {
553 ret = PTR_ERR(usb_dev_dr_host);
556 } else if (prop && !strcmp(prop, "peripheral")) {
557 usb_data.operating_mode = FSL_USB2_DR_DEVICE;
558 usb_dev_dr_client = platform_device_register_simple(
559 "fsl-usb2-udc", i, r, 2);
560 if (IS_ERR(usb_dev_dr_client)) {
561 ret = PTR_ERR(usb_dev_dr_client);
564 } else if (prop && !strcmp(prop, "otg")) {
565 usb_data.operating_mode = FSL_USB2_DR_OTG;
566 usb_dev_dr_host = platform_device_register_simple(
567 "fsl-ehci", i, r, 2);
568 if (IS_ERR(usb_dev_dr_host)) {
569 ret = PTR_ERR(usb_dev_dr_host);
572 usb_dev_dr_client = platform_device_register_simple(
573 "fsl-usb2-udc", i, r, 2);
574 if (IS_ERR(usb_dev_dr_client)) {
575 ret = PTR_ERR(usb_dev_dr_client);
583 prop = of_get_property(np, "phy_type", NULL);
584 usb_data.phy_mode = determine_usb_phy(prop);
586 if (usb_dev_dr_host) {
587 usb_dev_dr_host->dev.coherent_dma_mask = 0xffffffffUL;
588 usb_dev_dr_host->dev.dma_mask = &usb_dev_dr_host->
589 dev.coherent_dma_mask;
590 if ((ret = platform_device_add_data(usb_dev_dr_host,
591 &usb_data, sizeof(struct
592 fsl_usb2_platform_data))))
595 if (usb_dev_dr_client) {
596 usb_dev_dr_client->dev.coherent_dma_mask = 0xffffffffUL;
597 usb_dev_dr_client->dev.dma_mask = &usb_dev_dr_client->
598 dev.coherent_dma_mask;
599 if ((ret = platform_device_add_data(usb_dev_dr_client,
600 &usb_data, sizeof(struct
601 fsl_usb2_platform_data))))
610 platform_device_unregister(usb_dev_dr_host);
611 if (usb_dev_dr_client)
612 platform_device_unregister(usb_dev_dr_client);
615 platform_device_unregister(usb_dev_mph);
620 arch_initcall(fsl_usb_of_init);
622 static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk,
623 struct spi_board_info *board_infos,
624 unsigned int num_board_infos,
625 void (*activate_cs)(u8 cs, u8 polarity),
626 void (*deactivate_cs)(u8 cs, u8 polarity))
628 struct device_node *np;
631 for_each_compatible_node(np, type, compatible) {
635 struct resource res[2];
636 struct platform_device *pdev;
637 struct fsl_spi_platform_data pdata = {
638 .activate_cs = activate_cs,
639 .deactivate_cs = deactivate_cs,
642 memset(res, 0, sizeof(res));
644 pdata.sysclk = sysclk;
646 prop = of_get_property(np, "reg", NULL);
649 pdata.bus_num = *(u32 *)prop;
651 prop = of_get_property(np, "cell-index", NULL);
655 prop = of_get_property(np, "mode", NULL);
656 if (prop && !strcmp(prop, "cpu-qe"))
659 for (j = 0; j < num_board_infos; j++) {
660 if (board_infos[j].bus_num == pdata.bus_num)
661 pdata.max_chipselect++;
664 if (!pdata.max_chipselect)
667 ret = of_address_to_resource(np, 0, &res[0]);
671 ret = of_irq_to_resource(np, 0, &res[1]);
675 pdev = platform_device_alloc("mpc83xx_spi", i);
679 ret = platform_device_add_data(pdev, &pdata, sizeof(pdata));
683 ret = platform_device_add_resources(pdev, res,
688 ret = platform_device_add(pdev);
694 platform_device_del(pdev);
696 pr_err("%s: registration failed\n", np->full_name);
704 int __init fsl_spi_init(struct spi_board_info *board_infos,
705 unsigned int num_board_infos,
706 void (*activate_cs)(u8 cs, u8 polarity),
707 void (*deactivate_cs)(u8 cs, u8 polarity))
712 #ifdef CONFIG_QUICC_ENGINE
713 /* SPI controller is either clocked from QE or SoC clock */
714 sysclk = get_brgfreq();
717 sysclk = fsl_get_sys_freq();
722 ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos,
723 num_board_infos, activate_cs, deactivate_cs);
725 of_fsl_spi_probe("spi", "fsl_spi", sysclk, board_infos,
726 num_board_infos, activate_cs, deactivate_cs);
728 return spi_register_board_info(board_infos, num_board_infos);
731 #if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
732 static __be32 __iomem *rstcr;
734 static int __init setup_rstcr(void)
736 struct device_node *np;
737 np = of_find_node_by_name(NULL, "global-utilities");
738 if ((np && of_get_property(np, "fsl,has-rstcr", NULL))) {
739 const u32 *prop = of_get_property(np, "reg", NULL);
741 /* map reset control register
742 * 0xE00B0 is offset of reset control register
744 rstcr = ioremap(get_immrbase() + *prop + 0xB0, 0xff);
746 printk (KERN_EMERG "Error: reset control "
747 "register not mapped!\n");
750 printk (KERN_INFO "rstcr compatible register does not exist!\n");
756 arch_initcall(setup_rstcr);
758 void fsl_rstcr_restart(char *cmd)
762 /* set reset control register */
763 out_be32(rstcr, 0x2); /* HRESET_REQ */
769 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
770 struct platform_diu_data_ops diu_ops = {
771 .diu_size = 1280 * 1024 * 4, /* default one 1280x1024 buffer */
773 EXPORT_SYMBOL(diu_ops);
775 int __init preallocate_diu_videomemory(void)
777 pr_debug("diu_size=%lu\n", diu_ops.diu_size);
779 diu_ops.diu_mem = __alloc_bootmem(diu_ops.diu_size, 8, 0);
780 if (!diu_ops.diu_mem) {
781 printk(KERN_ERR "fsl-diu: cannot allocate %lu bytes\n",
786 pr_debug("diu_mem=%p\n", diu_ops.diu_mem);
788 rh_init(&diu_ops.diu_rh_info, 4096, ARRAY_SIZE(diu_ops.diu_rh_block),
789 diu_ops.diu_rh_block);
790 return rh_attach_region(&diu_ops.diu_rh_info,
791 (unsigned long) diu_ops.diu_mem,
795 static int __init early_parse_diufb(char *p)
800 diu_ops.diu_size = _ALIGN_UP(memparse(p, &p), 8);
802 pr_debug("diu_size=%lu\n", diu_ops.diu_size);
806 early_param("diufb", early_parse_diufb);