2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
4 #ifndef _ASM_POWERPC_SYSTEM_H
5 #define _ASM_POWERPC_SYSTEM_H
7 #include <linux/kernel.h>
8 #include <linux/irqflags.h>
10 #include <asm/hw_irq.h>
14 * The sync instruction guarantees that all memory accesses initiated
15 * by this processor have been performed (with respect to all other
16 * mechanisms that access memory). The eieio instruction is a barrier
17 * providing an ordering (separately) for (a) cacheable stores and (b)
18 * loads and stores to non-cacheable memory (e.g. I/O devices).
20 * mb() prevents loads and stores being reordered across this point.
21 * rmb() prevents loads being reordered across this point.
22 * wmb() prevents stores being reordered across this point.
23 * read_barrier_depends() prevents data-dependent loads being reordered
24 * across this point (nop on PPC).
26 * We have to use the sync instructions for mb(), since lwsync doesn't
27 * order loads with respect to previous stores. Lwsync is fine for
28 * rmb(), though. Note that rmb() actually uses a sync on 32-bit
31 * For wmb(), we use sync since wmb is used in drivers to order
32 * stores to system memory with respect to writes to the device.
33 * However, smp_wmb() can be a lighter-weight eieio barrier on
34 * SMP since it is only used to order updates to system memory.
36 #define mb() __asm__ __volatile__ ("sync" : : : "memory")
37 #define rmb() __asm__ __volatile__ (__stringify(LWSYNC) : : : "memory")
38 #define wmb() __asm__ __volatile__ ("sync" : : : "memory")
39 #define read_barrier_depends() do { } while(0)
41 #define set_mb(var, value) do { var = value; mb(); } while (0)
44 #define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
47 #define smp_rmb() rmb()
48 #define smp_wmb() eieio()
49 #define smp_read_barrier_depends() read_barrier_depends()
51 #define smp_mb() barrier()
52 #define smp_rmb() barrier()
53 #define smp_wmb() barrier()
54 #define smp_read_barrier_depends() do { } while(0)
55 #endif /* CONFIG_SMP */
58 * This is a barrier which prevents following instructions from being
59 * started until the value of the argument x is known. For example, if
60 * x is a variable loaded from memory, this prevents following
61 * instructions from being executed until the load has been performed.
63 #define data_barrier(x) \
64 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
69 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
71 extern int (*__debugger)(struct pt_regs *regs);
72 extern int (*__debugger_ipi)(struct pt_regs *regs);
73 extern int (*__debugger_bpt)(struct pt_regs *regs);
74 extern int (*__debugger_sstep)(struct pt_regs *regs);
75 extern int (*__debugger_iabr_match)(struct pt_regs *regs);
76 extern int (*__debugger_dabr_match)(struct pt_regs *regs);
77 extern int (*__debugger_fault_handler)(struct pt_regs *regs);
79 #define DEBUGGER_BOILERPLATE(__NAME) \
80 static inline int __NAME(struct pt_regs *regs) \
82 if (unlikely(__ ## __NAME)) \
83 return __ ## __NAME(regs); \
87 DEBUGGER_BOILERPLATE(debugger)
88 DEBUGGER_BOILERPLATE(debugger_ipi)
89 DEBUGGER_BOILERPLATE(debugger_bpt)
90 DEBUGGER_BOILERPLATE(debugger_sstep)
91 DEBUGGER_BOILERPLATE(debugger_iabr_match)
92 DEBUGGER_BOILERPLATE(debugger_dabr_match)
93 DEBUGGER_BOILERPLATE(debugger_fault_handler)
96 static inline int debugger(struct pt_regs *regs) { return 0; }
97 static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
98 static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
99 static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
100 static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
101 static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
102 static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
105 extern int set_dabr(unsigned long dabr);
106 extern void print_backtrace(unsigned long *);
107 extern void show_regs(struct pt_regs * regs);
108 extern void flush_instruction_cache(void);
109 extern void hard_reset_now(void);
110 extern void poweroff_now(void);
113 extern long _get_L2CR(void);
114 extern long _get_L3CR(void);
115 extern void _set_L2CR(unsigned long);
116 extern void _set_L3CR(unsigned long);
118 #define _get_L2CR() 0L
119 #define _get_L3CR() 0L
120 #define _set_L2CR(val) do { } while(0)
121 #define _set_L3CR(val) do { } while(0)
124 extern void via_cuda_init(void);
125 extern void read_rtc_time(void);
126 extern void pmac_find_display(void);
127 extern void giveup_fpu(struct task_struct *);
128 extern void disable_kernel_fp(void);
129 extern void enable_kernel_fp(void);
130 extern void flush_fp_to_thread(struct task_struct *);
131 extern void enable_kernel_altivec(void);
132 extern void giveup_altivec(struct task_struct *);
133 extern void load_up_altivec(struct task_struct *);
134 extern int emulate_altivec(struct pt_regs *);
135 extern void enable_kernel_spe(void);
136 extern void giveup_spe(struct task_struct *);
137 extern void load_up_spe(struct task_struct *);
138 extern int fix_alignment(struct pt_regs *);
139 extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
140 extern void cvt_df(double *from, float *to, struct thread_struct *thread);
143 extern void discard_lazy_cpu_state(void);
145 static inline void discard_lazy_cpu_state(void)
150 #ifdef CONFIG_ALTIVEC
151 extern void flush_altivec_to_thread(struct task_struct *);
153 static inline void flush_altivec_to_thread(struct task_struct *t)
159 extern void flush_spe_to_thread(struct task_struct *);
161 static inline void flush_spe_to_thread(struct task_struct *t)
166 extern int call_rtas(const char *, int, int, unsigned long *, ...);
167 extern void cacheable_memzero(void *p, unsigned int nb);
168 extern void *cacheable_memcpy(void *, const void *, unsigned int);
169 extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
170 extern void bad_page_fault(struct pt_regs *, unsigned long, int);
171 extern int die(const char *, struct pt_regs *, long);
172 extern void _exception(int, struct pt_regs *, int, unsigned long);
173 extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
175 #ifdef CONFIG_BOOKE_WDT
176 extern u32 booke_wdt_enabled;
177 extern u32 booke_wdt_period;
178 #endif /* CONFIG_BOOKE_WDT */
181 extern void note_scsi_host(struct device_node *, void *);
183 extern struct task_struct *__switch_to(struct task_struct *,
184 struct task_struct *);
185 #define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
187 struct thread_struct;
188 extern struct task_struct *_switch(struct thread_struct *prev,
189 struct thread_struct *next);
191 extern unsigned int rtas_data;
192 extern int mem_init_done; /* set on boot once kmalloc can be called */
193 extern int init_bootmem_done; /* set on !NUMA once bootmem is available */
194 extern unsigned long memory_limit;
195 extern unsigned long klimit;
197 extern void *alloc_maybe_bootmem(size_t size, gfp_t mask);
198 extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
200 extern int powersave_nap; /* set if nap mode can be used in idle loop */
205 * Changes the memory location '*ptr' to be val and returns
206 * the previous value stored there.
208 static __always_inline unsigned long
209 __xchg_u32(volatile void *p, unsigned long val)
213 __asm__ __volatile__(
215 "1: lwarx %0,0,%2 \n"
220 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
230 * Changes the memory location '*ptr' to be val and returns
231 * the previous value stored there.
233 static __always_inline unsigned long
234 __xchg_u32_local(volatile void *p, unsigned long val)
238 __asm__ __volatile__(
239 "1: lwarx %0,0,%2 \n"
243 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
251 static __always_inline unsigned long
252 __xchg_u64(volatile void *p, unsigned long val)
256 __asm__ __volatile__(
258 "1: ldarx %0,0,%2 \n"
263 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
270 static __always_inline unsigned long
271 __xchg_u64_local(volatile void *p, unsigned long val)
275 __asm__ __volatile__(
276 "1: ldarx %0,0,%2 \n"
280 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
289 * This function doesn't exist, so you'll get a linker error
290 * if something tries to do an invalid xchg().
292 extern void __xchg_called_with_bad_pointer(void);
294 static __always_inline unsigned long
295 __xchg(volatile void *ptr, unsigned long x, unsigned int size)
299 return __xchg_u32(ptr, x);
302 return __xchg_u64(ptr, x);
305 __xchg_called_with_bad_pointer();
309 static __always_inline unsigned long
310 __xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
314 return __xchg_u32_local(ptr, x);
317 return __xchg_u64_local(ptr, x);
320 __xchg_called_with_bad_pointer();
323 #define xchg(ptr,x) \
325 __typeof__(*(ptr)) _x_ = (x); \
326 (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
329 #define xchg_local(ptr,x) \
331 __typeof__(*(ptr)) _x_ = (x); \
332 (__typeof__(*(ptr))) __xchg_local((ptr), \
333 (unsigned long)_x_, sizeof(*(ptr))); \
337 * Compare and exchange - if *p == old, set it to new,
338 * and return the old value of *p.
340 #define __HAVE_ARCH_CMPXCHG 1
342 static __always_inline unsigned long
343 __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
347 __asm__ __volatile__ (
349 "1: lwarx %0,0,%2 # __cmpxchg_u32\n\
358 : "=&r" (prev), "+m" (*p)
359 : "r" (p), "r" (old), "r" (new)
365 static __always_inline unsigned long
366 __cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
371 __asm__ __volatile__ (
372 "1: lwarx %0,0,%2 # __cmpxchg_u32\n\
380 : "=&r" (prev), "+m" (*p)
381 : "r" (p), "r" (old), "r" (new)
388 static __always_inline unsigned long
389 __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
393 __asm__ __volatile__ (
395 "1: ldarx %0,0,%2 # __cmpxchg_u64\n\
403 : "=&r" (prev), "+m" (*p)
404 : "r" (p), "r" (old), "r" (new)
410 static __always_inline unsigned long
411 __cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
416 __asm__ __volatile__ (
417 "1: ldarx %0,0,%2 # __cmpxchg_u64\n\
424 : "=&r" (prev), "+m" (*p)
425 : "r" (p), "r" (old), "r" (new)
432 /* This function doesn't exist, so you'll get a linker error
433 if something tries to do an invalid cmpxchg(). */
434 extern void __cmpxchg_called_with_bad_pointer(void);
436 static __always_inline unsigned long
437 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
442 return __cmpxchg_u32(ptr, old, new);
445 return __cmpxchg_u64(ptr, old, new);
448 __cmpxchg_called_with_bad_pointer();
452 static __always_inline unsigned long
453 __cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
458 return __cmpxchg_u32_local(ptr, old, new);
461 return __cmpxchg_u64_local(ptr, old, new);
464 __cmpxchg_called_with_bad_pointer();
468 #define cmpxchg(ptr, o, n) \
470 __typeof__(*(ptr)) _o_ = (o); \
471 __typeof__(*(ptr)) _n_ = (n); \
472 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
473 (unsigned long)_n_, sizeof(*(ptr))); \
477 #define cmpxchg_local(ptr, o, n) \
479 __typeof__(*(ptr)) _o_ = (o); \
480 __typeof__(*(ptr)) _n_ = (n); \
481 (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
482 (unsigned long)_n_, sizeof(*(ptr))); \
487 * We handle most unaligned accesses in hardware. On the other hand
488 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
489 * powers of 2 writes until it reaches sufficient alignment).
491 * Based on this we disable the IP header alignment in network drivers.
492 * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
493 * cacheline alignment of buffers.
495 #define NET_IP_ALIGN 0
496 #define NET_SKB_PAD L1_CACHE_BYTES
498 #define cmpxchg64(ptr, o, n) \
500 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
501 cmpxchg((ptr), (o), (n)); \
503 #define cmpxchg64_local(ptr, o, n) \
505 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
506 cmpxchg_local((ptr), (o), (n)); \
509 #include <asm-generic/cmpxchg-local.h>
510 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
513 #define arch_align_stack(x) (x)
515 /* Used in very early kernel initialization. */
516 extern unsigned long reloc_offset(void);
517 extern unsigned long add_reloc_offset(unsigned long);
518 extern void reloc_got2(unsigned long);
520 #define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
522 static inline void create_instruction(unsigned long addr, unsigned int instr)
525 p = (unsigned int *)addr;
527 asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p));
530 /* Flags for create_branch:
531 * "b" == create_branch(addr, target, 0);
532 * "ba" == create_branch(addr, target, BRANCH_ABSOLUTE);
533 * "bl" == create_branch(addr, target, BRANCH_SET_LINK);
534 * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
536 #define BRANCH_SET_LINK 0x1
537 #define BRANCH_ABSOLUTE 0x2
539 static inline void create_branch(unsigned long addr,
540 unsigned long target, int flags)
542 unsigned int instruction;
544 if (! (flags & BRANCH_ABSOLUTE))
545 target = target - addr;
547 /* Mask out the flags and target, so they don't step on each other. */
548 instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC);
550 create_instruction(addr, instruction);
553 static inline void create_function_call(unsigned long addr, void * func)
555 unsigned long func_addr;
559 * On PPC64 the function pointer actually points to the function's
560 * descriptor. The first entry in the descriptor is the address
561 * of the function text.
563 func_addr = *(unsigned long *)func;
565 func_addr = (unsigned long)func;
567 create_branch(addr, func_addr, BRANCH_SET_LINK);
570 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
571 extern void account_system_vtime(struct task_struct *);
574 extern struct dentry *powerpc_debugfs_root;
576 #endif /* __KERNEL__ */
577 #endif /* _ASM_POWERPC_SYSTEM_H */