git.oblomov.eu Git - linux-2.6/blob - arch/sparc64/kernel/pci_sun4v.c

   1 /* pci_sun4v.c: SUN4V specific PCI controller support.
   2  *
   3  * Copyright (C) 2006, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/types.h>
   8 #include <linux/pci.h>
   9 #include <linux/init.h>
  10 #include <linux/slab.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/percpu.h>
  13 #include <linux/irq.h>
  14 #include <linux/msi.h>
  15 #include <linux/log2.h>
  16 #include <linux/of_device.h>
  17
  18 #include <asm/iommu.h>
  19 #include <asm/irq.h>
  20 #include <asm/hypervisor.h>
  21 #include <asm/prom.h>
  22
  23 #include "pci_impl.h"
  24 #include "iommu_common.h"
  25
  26 #include "pci_sun4v.h"
  27
  28 #define DRIVER_NAME     "pci_sun4v"
  29 #define PFX             DRIVER_NAME ": "
  30
  31 static unsigned long vpci_major = 1;
  32 static unsigned long vpci_minor = 1;
  33
  34 #define PGLIST_NENTS    (PAGE_SIZE / sizeof(u64))
  35
  36 struct iommu_batch {
  37         struct device   *dev;           /* Device mapping is for.       */
  38         unsigned long   prot;           /* IOMMU page protections       */
  39         unsigned long   entry;          /* Index into IOTSB.            */
  40         u64             *pglist;        /* List of physical pages       */
  41         unsigned long   npages;         /* Number of pages in list.     */
  42 };
  43
  44 static DEFINE_PER_CPU(struct iommu_batch, iommu_batch);
  45
  46 /* Interrupts must be disabled.  */
  47 static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry)
  48 {
  49         struct iommu_batch *p = &__get_cpu_var(iommu_batch);
  50
  51         p->dev          = dev;
  52         p->prot         = prot;
  53         p->entry        = entry;
  54         p->npages       = 0;
  55 }
  56
  57 /* Interrupts must be disabled.  */
  58 static long iommu_batch_flush(struct iommu_batch *p)
  59 {
  60         struct pci_pbm_info *pbm = p->dev->archdata.host_controller;
  61         unsigned long devhandle = pbm->devhandle;
  62         unsigned long prot = p->prot;
  63         unsigned long entry = p->entry;
  64         u64 *pglist = p->pglist;
  65         unsigned long npages = p->npages;
  66
  67         while (npages != 0) {
  68                 long num;
  69
  70                 num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
  71                                           npages, prot, __pa(pglist));
  72                 if (unlikely(num < 0)) {
  73                         if (printk_ratelimit())
  74                                 printk("iommu_batch_flush: IOMMU map of "
  75                                        "[%08lx:%08lx:%lx:%lx:%lx] failed with "
  76                                        "status %ld\n",
  77                                        devhandle, HV_PCI_TSBID(0, entry),
  78                                        npages, prot, __pa(pglist), num);
  79                         return -1;
  80                 }
  81
  82                 entry += num;
  83                 npages -= num;
  84                 pglist += num;
  85         }
  86
  87         p->entry = entry;
  88         p->npages = 0;
  89
  90         return 0;
  91 }
  92
  93 static inline void iommu_batch_new_entry(unsigned long entry)
  94 {
  95         struct iommu_batch *p = &__get_cpu_var(iommu_batch);
  96
  97         if (p->entry + p->npages == entry)
  98                 return;
  99         if (p->entry != ~0UL)
 100                 iommu_batch_flush(p);
 101         p->entry = entry;
 102 }
 103
 104 /* Interrupts must be disabled.  */
 105 static inline long iommu_batch_add(u64 phys_page)
 106 {
 107         struct iommu_batch *p = &__get_cpu_var(iommu_batch);
 108
 109         BUG_ON(p->npages >= PGLIST_NENTS);
 110
 111         p->pglist[p->npages++] = phys_page;
 112         if (p->npages == PGLIST_NENTS)
 113                 return iommu_batch_flush(p);
 114
 115         return 0;
 116 }
 117
 118 /* Interrupts must be disabled.  */
 119 static inline long iommu_batch_end(void)
 120 {
 121         struct iommu_batch *p = &__get_cpu_var(iommu_batch);
 122
 123         BUG_ON(p->npages >= PGLIST_NENTS);
 124
 125         return iommu_batch_flush(p);
 126 }
 127
 128 static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
 129                                    dma_addr_t *dma_addrp, gfp_t gfp)
 130 {
 131         unsigned long flags, order, first_page, npages, n;
 132         struct iommu *iommu;
 133         struct page *page;
 134         void *ret;
 135         long entry;
 136         int nid;
 137
 138         size = IO_PAGE_ALIGN(size);
 139         order = get_order(size);
 140         if (unlikely(order >= MAX_ORDER))
 141                 return NULL;
 142
 143         npages = size >> IO_PAGE_SHIFT;
 144
 145         nid = dev->archdata.numa_node;
 146         page = alloc_pages_node(nid, gfp, order);
 147         if (unlikely(!page))
 148                 return NULL;
 149
 150         first_page = (unsigned long) page_address(page);
 151         memset((char *)first_page, 0, PAGE_SIZE << order);
 152
 153         iommu = dev->archdata.iommu;
 154
 155         spin_lock_irqsave(&iommu->lock, flags);
 156         entry = iommu_range_alloc(dev, iommu, npages, NULL);
 157         spin_unlock_irqrestore(&iommu->lock, flags);
 158
 159         if (unlikely(entry == DMA_ERROR_CODE))
 160                 goto range_alloc_fail;
 161
 162         *dma_addrp = (iommu->page_table_map_base +
 163                       (entry << IO_PAGE_SHIFT));
 164         ret = (void *) first_page;
 165         first_page = __pa(first_page);
 166
 167         local_irq_save(flags);
 168
 169         iommu_batch_start(dev,
 170                           (HV_PCI_MAP_ATTR_READ |
 171                            HV_PCI_MAP_ATTR_WRITE),
 172                           entry);
 173
 174         for (n = 0; n < npages; n++) {
 175                 long err = iommu_batch_add(first_page + (n * PAGE_SIZE));
 176                 if (unlikely(err < 0L))
 177                         goto iommu_map_fail;
 178         }
 179
 180         if (unlikely(iommu_batch_end() < 0L))
 181                 goto iommu_map_fail;
 182
 183         local_irq_restore(flags);
 184
 185         return ret;
 186
 187 iommu_map_fail:
 188         /* Interrupts are disabled.  */
 189         spin_lock(&iommu->lock);
 190         iommu_range_free(iommu, *dma_addrp, npages);
 191         spin_unlock_irqrestore(&iommu->lock, flags);
 192
 193 range_alloc_fail:
 194         free_pages(first_page, order);
 195         return NULL;
 196 }
 197
 198 static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
 199                                  dma_addr_t dvma)
 200 {
 201         struct pci_pbm_info *pbm;
 202         struct iommu *iommu;
 203         unsigned long flags, order, npages, entry;
 204         u32 devhandle;
 205
 206         npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
 207         iommu = dev->archdata.iommu;
 208         pbm = dev->archdata.host_controller;
 209         devhandle = pbm->devhandle;
 210         entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 211
 212         spin_lock_irqsave(&iommu->lock, flags);
 213
 214         iommu_range_free(iommu, dvma, npages);
 215
 216         do {
 217                 unsigned long num;
 218
 219                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
 220                                             npages);
 221                 entry += num;
 222                 npages -= num;
 223         } while (npages != 0);
 224
 225         spin_unlock_irqrestore(&iommu->lock, flags);
 226
 227         order = get_order(size);
 228         if (order < 10)
 229                 free_pages((unsigned long)cpu, order);
 230 }
 231
 232 static dma_addr_t dma_4v_map_single(struct device *dev, void *ptr, size_t sz,
 233                                     enum dma_data_direction direction)
 234 {
 235         struct iommu *iommu;
 236         unsigned long flags, npages, oaddr;
 237         unsigned long i, base_paddr;
 238         u32 bus_addr, ret;
 239         unsigned long prot;
 240         long entry;
 241
 242         iommu = dev->archdata.iommu;
 243
 244         if (unlikely(direction == DMA_NONE))
 245                 goto bad;
 246
 247         oaddr = (unsigned long)ptr;
 248         npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
 249         npages >>= IO_PAGE_SHIFT;
 250
 251         spin_lock_irqsave(&iommu->lock, flags);
 252         entry = iommu_range_alloc(dev, iommu, npages, NULL);
 253         spin_unlock_irqrestore(&iommu->lock, flags);
 254
 255         if (unlikely(entry == DMA_ERROR_CODE))
 256                 goto bad;
 257
 258         bus_addr = (iommu->page_table_map_base +
 259                     (entry << IO_PAGE_SHIFT));
 260         ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
 261         base_paddr = __pa(oaddr & IO_PAGE_MASK);
 262         prot = HV_PCI_MAP_ATTR_READ;
 263         if (direction != DMA_TO_DEVICE)
 264                 prot |= HV_PCI_MAP_ATTR_WRITE;
 265
 266         local_irq_save(flags);
 267
 268         iommu_batch_start(dev, prot, entry);
 269
 270         for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
 271                 long err = iommu_batch_add(base_paddr);
 272                 if (unlikely(err < 0L))
 273                         goto iommu_map_fail;
 274         }
 275         if (unlikely(iommu_batch_end() < 0L))
 276                 goto iommu_map_fail;
 277
 278         local_irq_restore(flags);
 279
 280         return ret;
 281
 282 bad:
 283         if (printk_ratelimit())
 284                 WARN_ON(1);
 285         return DMA_ERROR_CODE;
 286
 287 iommu_map_fail:
 288         /* Interrupts are disabled.  */
 289         spin_lock(&iommu->lock);
 290         iommu_range_free(iommu, bus_addr, npages);
 291         spin_unlock_irqrestore(&iommu->lock, flags);
 292
 293         return DMA_ERROR_CODE;
 294 }
 295
 296 static void dma_4v_unmap_single(struct device *dev, dma_addr_t bus_addr,
 297                                 size_t sz, enum dma_data_direction direction)
 298 {
 299         struct pci_pbm_info *pbm;
 300         struct iommu *iommu;
 301         unsigned long flags, npages;
 302         long entry;
 303         u32 devhandle;
 304
 305         if (unlikely(direction == DMA_NONE)) {
 306                 if (printk_ratelimit())
 307                         WARN_ON(1);
 308                 return;
 309         }
 310
 311         iommu = dev->archdata.iommu;
 312         pbm = dev->archdata.host_controller;
 313         devhandle = pbm->devhandle;
 314
 315         npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
 316         npages >>= IO_PAGE_SHIFT;
 317         bus_addr &= IO_PAGE_MASK;
 318
 319         spin_lock_irqsave(&iommu->lock, flags);
 320
 321         iommu_range_free(iommu, bus_addr, npages);
 322
 323         entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
 324         do {
 325                 unsigned long num;
 326
 327                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
 328                                             npages);
 329                 entry += num;
 330                 npages -= num;
 331         } while (npages != 0);
 332
 333         spin_unlock_irqrestore(&iommu->lock, flags);
 334 }
 335
 336 static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
 337                          int nelems, enum dma_data_direction direction)
 338 {
 339         struct scatterlist *s, *outs, *segstart;
 340         unsigned long flags, handle, prot;
 341         dma_addr_t dma_next = 0, dma_addr;
 342         unsigned int max_seg_size;
 343         unsigned long seg_boundary_size;
 344         int outcount, incount, i;
 345         struct iommu *iommu;
 346         unsigned long base_shift;
 347         long err;
 348
 349         BUG_ON(direction == DMA_NONE);
 350
 351         iommu = dev->archdata.iommu;
 352         if (nelems == 0 || !iommu)
 353                 return 0;
 354
 355         prot = HV_PCI_MAP_ATTR_READ;
 356         if (direction != DMA_TO_DEVICE)
 357                 prot |= HV_PCI_MAP_ATTR_WRITE;
 358
 359         outs = s = segstart = &sglist[0];
 360         outcount = 1;
 361         incount = nelems;
 362         handle = 0;
 363
 364         /* Init first segment length for backout at failure */
 365         outs->dma_length = 0;
 366
 367         spin_lock_irqsave(&iommu->lock, flags);
 368
 369         iommu_batch_start(dev, prot, ~0UL);
 370
 371         max_seg_size = dma_get_max_seg_size(dev);
 372         seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
 373                                   IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
 374         base_shift = iommu->page_table_map_base >> IO_PAGE_SHIFT;
 375         for_each_sg(sglist, s, nelems, i) {
 376                 unsigned long paddr, npages, entry, out_entry = 0, slen;
 377
 378                 slen = s->length;
 379                 /* Sanity check */
 380                 if (slen == 0) {
 381                         dma_next = 0;
 382                         continue;
 383                 }
 384                 /* Allocate iommu entries for that segment */
 385                 paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
 386                 npages = iommu_num_pages(paddr, slen);
 387                 entry = iommu_range_alloc(dev, iommu, npages, &handle);
 388
 389                 /* Handle failure */
 390                 if (unlikely(entry == DMA_ERROR_CODE)) {
 391                         if (printk_ratelimit())
 392                                 printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx"
 393                                        " npages %lx\n", iommu, paddr, npages);
 394                         goto iommu_map_failed;
 395                 }
 396
 397                 iommu_batch_new_entry(entry);
 398
 399                 /* Convert entry to a dma_addr_t */
 400                 dma_addr = iommu->page_table_map_base +
 401                         (entry << IO_PAGE_SHIFT);
 402                 dma_addr |= (s->offset & ~IO_PAGE_MASK);
 403
 404                 /* Insert into HW table */
 405                 paddr &= IO_PAGE_MASK;
 406                 while (npages--) {
 407                         err = iommu_batch_add(paddr);
 408                         if (unlikely(err < 0L))
 409                                 goto iommu_map_failed;
 410                         paddr += IO_PAGE_SIZE;
 411                 }
 412
 413                 /* If we are in an open segment, try merging */
 414                 if (segstart != s) {
 415                         /* We cannot merge if:
 416                          * - allocated dma_addr isn't contiguous to previous allocation
 417                          */
 418                         if ((dma_addr != dma_next) ||
 419                             (outs->dma_length + s->length > max_seg_size) ||
 420                             (is_span_boundary(out_entry, base_shift,
 421                                               seg_boundary_size, outs, s))) {
 422                                 /* Can't merge: create a new segment */
 423                                 segstart = s;
 424                                 outcount++;
 425                                 outs = sg_next(outs);
 426                         } else {
 427                                 outs->dma_length += s->length;
 428                         }
 429                 }
 430
 431                 if (segstart == s) {
 432                         /* This is a new segment, fill entries */
 433                         outs->dma_address = dma_addr;
 434                         outs->dma_length = slen;
 435                         out_entry = entry;
 436                 }
 437
 438                 /* Calculate next page pointer for contiguous check */
 439                 dma_next = dma_addr + slen;
 440         }
 441
 442         err = iommu_batch_end();
 443
 444         if (unlikely(err < 0L))
 445                 goto iommu_map_failed;
 446
 447         spin_unlock_irqrestore(&iommu->lock, flags);
 448
 449         if (outcount < incount) {
 450                 outs = sg_next(outs);
 451                 outs->dma_address = DMA_ERROR_CODE;
 452                 outs->dma_length = 0;
 453         }
 454
 455         return outcount;
 456
 457 iommu_map_failed:
 458         for_each_sg(sglist, s, nelems, i) {
 459                 if (s->dma_length != 0) {
 460                         unsigned long vaddr, npages;
 461
 462                         vaddr = s->dma_address & IO_PAGE_MASK;
 463                         npages = iommu_num_pages(s->dma_address, s->dma_length);
 464                         iommu_range_free(iommu, vaddr, npages);
 465                         /* XXX demap? XXX */
 466                         s->dma_address = DMA_ERROR_CODE;
 467                         s->dma_length = 0;
 468                 }
 469                 if (s == outs)
 470                         break;
 471         }
 472         spin_unlock_irqrestore(&iommu->lock, flags);
 473
 474         return 0;
 475 }
 476
 477 static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
 478                             int nelems, enum dma_data_direction direction)
 479 {
 480         struct pci_pbm_info *pbm;
 481         struct scatterlist *sg;
 482         struct iommu *iommu;
 483         unsigned long flags;
 484         u32 devhandle;
 485
 486         BUG_ON(direction == DMA_NONE);
 487
 488         iommu = dev->archdata.iommu;
 489         pbm = dev->archdata.host_controller;
 490         devhandle = pbm->devhandle;
 491
 492         spin_lock_irqsave(&iommu->lock, flags);
 493
 494         sg = sglist;
 495         while (nelems--) {
 496                 dma_addr_t dma_handle = sg->dma_address;
 497                 unsigned int len = sg->dma_length;
 498                 unsigned long npages, entry;
 499
 500                 if (!len)
 501                         break;
 502                 npages = iommu_num_pages(dma_handle, len);
 503                 iommu_range_free(iommu, dma_handle, npages);
 504
 505                 entry = ((dma_handle - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 506                 while (npages) {
 507                         unsigned long num;
 508
 509                         num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
 510                                                     npages);
 511                         entry += num;
 512                         npages -= num;
 513                 }
 514
 515                 sg = sg_next(sg);
 516         }
 517
 518         spin_unlock_irqrestore(&iommu->lock, flags);
 519 }
 520
 521 static void dma_4v_sync_single_for_cpu(struct device *dev,
 522                                        dma_addr_t bus_addr, size_t sz,
 523                                        enum dma_data_direction direction)
 524 {
 525         /* Nothing to do... */
 526 }
 527
 528 static void dma_4v_sync_sg_for_cpu(struct device *dev,
 529                                    struct scatterlist *sglist, int nelems,
 530                                    enum dma_data_direction direction)
 531 {
 532         /* Nothing to do... */
 533 }
 534
 535 static const struct dma_ops sun4v_dma_ops = {
 536         .alloc_coherent                 = dma_4v_alloc_coherent,
 537         .free_coherent                  = dma_4v_free_coherent,
 538         .map_single                     = dma_4v_map_single,
 539         .unmap_single                   = dma_4v_unmap_single,
 540         .map_sg                         = dma_4v_map_sg,
 541         .unmap_sg                       = dma_4v_unmap_sg,
 542         .sync_single_for_cpu            = dma_4v_sync_single_for_cpu,
 543         .sync_sg_for_cpu                = dma_4v_sync_sg_for_cpu,
 544 };
 545
 546 static void __init pci_sun4v_scan_bus(struct pci_pbm_info *pbm)
 547 {
 548         struct property *prop;
 549         struct device_node *dp;
 550
 551         dp = pbm->prom_node;
 552         prop = of_find_property(dp, "66mhz-capable", NULL);
 553         pbm->is_66mhz_capable = (prop != NULL);
 554         pbm->pci_bus = pci_scan_one_pbm(pbm);
 555
 556         /* XXX register error interrupt handlers XXX */
 557 }
 558
 559 static unsigned long __init probe_existing_entries(struct pci_pbm_info *pbm,
 560                                                    struct iommu *iommu)
 561 {
 562         struct iommu_arena *arena = &iommu->arena;
 563         unsigned long i, cnt = 0;
 564         u32 devhandle;
 565
 566         devhandle = pbm->devhandle;
 567         for (i = 0; i < arena->limit; i++) {
 568                 unsigned long ret, io_attrs, ra;
 569
 570                 ret = pci_sun4v_iommu_getmap(devhandle,
 571                                              HV_PCI_TSBID(0, i),
 572                                              &io_attrs, &ra);
 573                 if (ret == HV_EOK) {
 574                         if (page_in_phys_avail(ra)) {
 575                                 pci_sun4v_iommu_demap(devhandle,
 576                                                       HV_PCI_TSBID(0, i), 1);
 577                         } else {
 578                                 cnt++;
 579                                 __set_bit(i, arena->map);
 580                         }
 581                 }
 582         }
 583
 584         return cnt;
 585 }
 586
 587 static int __init pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
 588 {
 589         struct iommu *iommu = pbm->iommu;
 590         struct property *prop;
 591         unsigned long num_tsb_entries, sz, tsbsize;
 592         u32 vdma[2], dma_mask, dma_offset;
 593
 594         prop = of_find_property(pbm->prom_node, "virtual-dma", NULL);
 595         if (prop) {
 596                 u32 *val = prop->value;
 597
 598                 vdma[0] = val[0];
 599                 vdma[1] = val[1];
 600         } else {
 601                 /* No property, use default values. */
 602                 vdma[0] = 0x80000000;
 603                 vdma[1] = 0x80000000;
 604         }
 605
 606         if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
 607                 printk(KERN_ERR PFX "Strange virtual-dma[%08x:%08x].\n",
 608                        vdma[0], vdma[1]);
 609                 return -EINVAL;
 610         };
 611
 612         dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
 613         num_tsb_entries = vdma[1] / IO_PAGE_SIZE;
 614         tsbsize = num_tsb_entries * sizeof(iopte_t);
 615
 616         dma_offset = vdma[0];
 617
 618         /* Setup initial software IOMMU state. */
 619         spin_lock_init(&iommu->lock);
 620         iommu->ctx_lowest_free = 1;
 621         iommu->page_table_map_base = dma_offset;
 622         iommu->dma_addr_mask = dma_mask;
 623
 624         /* Allocate and initialize the free area map.  */
 625         sz = (num_tsb_entries + 7) / 8;
 626         sz = (sz + 7UL) & ~7UL;
 627         iommu->arena.map = kzalloc(sz, GFP_KERNEL);
 628         if (!iommu->arena.map) {
 629                 printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n");
 630                 return -ENOMEM;
 631         }
 632         iommu->arena.limit = num_tsb_entries;
 633
 634         sz = probe_existing_entries(pbm, iommu);
 635         if (sz)
 636                 printk("%s: Imported %lu TSB entries from OBP\n",
 637                        pbm->name, sz);
 638
 639         return 0;
 640 }
 641
 642 #ifdef CONFIG_PCI_MSI
 643 struct pci_sun4v_msiq_entry {
 644         u64             version_type;
 645 #define MSIQ_VERSION_MASK               0xffffffff00000000UL
 646 #define MSIQ_VERSION_SHIFT              32
 647 #define MSIQ_TYPE_MASK                  0x00000000000000ffUL
 648 #define MSIQ_TYPE_SHIFT                 0
 649 #define MSIQ_TYPE_NONE                  0x00
 650 #define MSIQ_TYPE_MSG                   0x01
 651 #define MSIQ_TYPE_MSI32                 0x02
 652 #define MSIQ_TYPE_MSI64                 0x03
 653 #define MSIQ_TYPE_INTX                  0x08
 654 #define MSIQ_TYPE_NONE2                 0xff
 655
 656         u64             intx_sysino;
 657         u64             reserved1;
 658         u64             stick;
 659         u64             req_id;  /* bus/device/func */
 660 #define MSIQ_REQID_BUS_MASK             0xff00UL
 661 #define MSIQ_REQID_BUS_SHIFT            8
 662 #define MSIQ_REQID_DEVICE_MASK          0x00f8UL
 663 #define MSIQ_REQID_DEVICE_SHIFT         3
 664 #define MSIQ_REQID_FUNC_MASK            0x0007UL
 665 #define MSIQ_REQID_FUNC_SHIFT           0
 666
 667         u64             msi_address;
 668
 669         /* The format of this value is message type dependent.
 670          * For MSI bits 15:0 are the data from the MSI packet.
 671          * For MSI-X bits 31:0 are the data from the MSI packet.
 672          * For MSG, the message code and message routing code where:
 673          *      bits 39:32 is the bus/device/fn of the msg target-id
 674          *      bits 18:16 is the message routing code
 675          *      bits 7:0 is the message code
 676          * For INTx the low order 2-bits are:
 677          *      00 - INTA
 678          *      01 - INTB
 679          *      10 - INTC
 680          *      11 - INTD
 681          */
 682         u64             msi_data;
 683
 684         u64             reserved2;
 685 };
 686
 687 static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
 688                               unsigned long *head)
 689 {
 690         unsigned long err, limit;
 691
 692         err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head);
 693         if (unlikely(err))
 694                 return -ENXIO;
 695
 696         limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
 697         if (unlikely(*head >= limit))
 698                 return -EFBIG;
 699
 700         return 0;
 701 }
 702
 703 static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm,
 704                                  unsigned long msiqid, unsigned long *head,
 705                                  unsigned long *msi)
 706 {
 707         struct pci_sun4v_msiq_entry *ep;
 708         unsigned long err, type;
 709
 710         /* Note: void pointer arithmetic, 'head' is a byte offset  */
 711         ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
 712                                  (pbm->msiq_ent_count *
 713                                   sizeof(struct pci_sun4v_msiq_entry))) +
 714               *head);
 715
 716         if ((ep->version_type & MSIQ_TYPE_MASK) == 0)
 717                 return 0;
 718
 719         type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
 720         if (unlikely(type != MSIQ_TYPE_MSI32 &&
 721                      type != MSIQ_TYPE_MSI64))
 722                 return -EINVAL;
 723
 724         *msi = ep->msi_data;
 725
 726         err = pci_sun4v_msi_setstate(pbm->devhandle,
 727                                      ep->msi_data /* msi_num */,
 728                                      HV_MSISTATE_IDLE);
 729         if (unlikely(err))
 730                 return -ENXIO;
 731
 732         /* Clear the entry.  */
 733         ep->version_type &= ~MSIQ_TYPE_MASK;
 734
 735         (*head) += sizeof(struct pci_sun4v_msiq_entry);
 736         if (*head >=
 737             (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry)))
 738                 *head = 0;
 739
 740         return 1;
 741 }
 742
 743 static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
 744                               unsigned long head)
 745 {
 746         unsigned long err;
 747
 748         err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
 749         if (unlikely(err))
 750                 return -EINVAL;
 751
 752         return 0;
 753 }
 754
 755 static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
 756                                unsigned long msi, int is_msi64)
 757 {
 758         if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid,
 759                                   (is_msi64 ?
 760                                    HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
 761                 return -ENXIO;
 762         if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE))
 763                 return -ENXIO;
 764         if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID))
 765                 return -ENXIO;
 766         return 0;
 767 }
 768
 769 static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
 770 {
 771         unsigned long err, msiqid;
 772
 773         err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid);
 774         if (err)
 775                 return -ENXIO;
 776
 777         pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID);
 778
 779         return 0;
 780 }
 781
 782 static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm)
 783 {
 784         unsigned long q_size, alloc_size, pages, order;
 785         int i;
 786
 787         q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
 788         alloc_size = (pbm->msiq_num * q_size);
 789         order = get_order(alloc_size);
 790         pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
 791         if (pages == 0UL) {
 792                 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
 793                        order);
 794                 return -ENOMEM;
 795         }
 796         memset((char *)pages, 0, PAGE_SIZE << order);
 797         pbm->msi_queues = (void *) pages;
 798
 799         for (i = 0; i < pbm->msiq_num; i++) {
 800                 unsigned long err, base = __pa(pages + (i * q_size));
 801                 unsigned long ret1, ret2;
 802
 803                 err = pci_sun4v_msiq_conf(pbm->devhandle,
 804                                           pbm->msiq_first + i,
 805                                           base, pbm->msiq_ent_count);
 806                 if (err) {
 807                         printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
 808                                err);
 809                         goto h_error;
 810                 }
 811
 812                 err = pci_sun4v_msiq_info(pbm->devhandle,
 813                                           pbm->msiq_first + i,
 814                                           &ret1, &ret2);
 815                 if (err) {
 816                         printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
 817                                err);
 818                         goto h_error;
 819                 }
 820                 if (ret1 != base || ret2 != pbm->msiq_ent_count) {
 821                         printk(KERN_ERR "MSI: Bogus qconf "
 822                                "expected[%lx:%x] got[%lx:%lx]\n",
 823                                base, pbm->msiq_ent_count,
 824                                ret1, ret2);
 825                         goto h_error;
 826                 }
 827         }
 828
 829         return 0;
 830
 831 h_error:
 832         free_pages(pages, order);
 833         return -EINVAL;
 834 }
 835
 836 static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm)
 837 {
 838         unsigned long q_size, alloc_size, pages, order;
 839         int i;
 840
 841         for (i = 0; i < pbm->msiq_num; i++) {
 842                 unsigned long msiqid = pbm->msiq_first + i;
 843
 844                 (void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0);
 845         }
 846
 847         q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
 848         alloc_size = (pbm->msiq_num * q_size);
 849         order = get_order(alloc_size);
 850
 851         pages = (unsigned long) pbm->msi_queues;
 852
 853         free_pages(pages, order);
 854
 855         pbm->msi_queues = NULL;
 856 }
 857
 858 static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm,
 859                                     unsigned long msiqid,
 860                                     unsigned long devino)
 861 {
 862         unsigned int virt_irq = sun4v_build_irq(pbm->devhandle, devino);
 863
 864         if (!virt_irq)
 865                 return -ENOMEM;
 866
 867         if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
 868                 return -EINVAL;
 869         if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
 870                 return -EINVAL;
 871
 872         return virt_irq;
 873 }
 874
 875 static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = {
 876         .get_head       =       pci_sun4v_get_head,
 877         .dequeue_msi    =       pci_sun4v_dequeue_msi,
 878         .set_head       =       pci_sun4v_set_head,
 879         .msi_setup      =       pci_sun4v_msi_setup,
 880         .msi_teardown   =       pci_sun4v_msi_teardown,
 881         .msiq_alloc     =       pci_sun4v_msiq_alloc,
 882         .msiq_free      =       pci_sun4v_msiq_free,
 883         .msiq_build_irq =       pci_sun4v_msiq_build_irq,
 884 };
 885
 886 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
 887 {
 888         sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops);
 889 }
 890 #else /* CONFIG_PCI_MSI */
 891 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
 892 {
 893 }
 894 #endif /* !(CONFIG_PCI_MSI) */
 895
 896 static int __init pci_sun4v_pbm_init(struct pci_controller_info *p,
 897                                      struct device_node *dp, u32 devhandle)
 898 {
 899         struct pci_pbm_info *pbm;
 900         int err;
 901
 902         if (devhandle & 0x40)
 903                 pbm = &p->pbm_B;
 904         else
 905                 pbm = &p->pbm_A;
 906
 907         pbm->next = pci_pbm_root;
 908         pci_pbm_root = pbm;
 909
 910         pbm->numa_node = of_node_to_nid(dp);
 911
 912         pbm->pci_ops = &sun4v_pci_ops;
 913         pbm->config_space_reg_bits = 12;
 914
 915         pbm->index = pci_num_pbms++;
 916
 917         pbm->parent = p;
 918         pbm->prom_node = dp;
 919
 920         pbm->devhandle = devhandle;
 921
 922         pbm->name = dp->full_name;
 923
 924         printk("%s: SUN4V PCI Bus Module\n", pbm->name);
 925         printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node);
 926
 927         pci_determine_mem_io_space(pbm);
 928
 929         pci_get_pbm_props(pbm);
 930
 931         err = pci_sun4v_iommu_init(pbm);
 932         if (err)
 933                 return err;
 934
 935         pci_sun4v_msi_init(pbm);
 936
 937         pci_sun4v_scan_bus(pbm);
 938
 939         return 0;
 940 }
 941
 942 static int __devinit pci_sun4v_probe(struct of_device *op,
 943                                      const struct of_device_id *match)
 944 {
 945         const struct linux_prom64_registers *regs;
 946         static int hvapi_negotiated = 0;
 947         struct pci_controller_info *p;
 948         struct pci_pbm_info *pbm;
 949         struct device_node *dp;
 950         struct iommu *iommu;
 951         u32 devhandle;
 952         int i;
 953
 954         dp = op->node;
 955
 956         if (!hvapi_negotiated++) {
 957                 int err = sun4v_hvapi_register(HV_GRP_PCI,
 958                                                vpci_major,
 959                                                &vpci_minor);
 960
 961                 if (err) {
 962                         printk(KERN_ERR PFX "Could not register hvapi, "
 963                                "err=%d\n", err);
 964                         return err;
 965                 }
 966                 printk(KERN_INFO PFX "Registered hvapi major[%lu] minor[%lu]\n",
 967                        vpci_major, vpci_minor);
 968
 969                 dma_ops = &sun4v_dma_ops;
 970         }
 971
 972         regs = of_get_property(dp, "reg", NULL);
 973         if (!regs) {
 974                 printk(KERN_ERR PFX "Could not find config registers\n");
 975                 return -ENODEV;
 976         }
 977         devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
 978
 979         for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
 980                 if (pbm->devhandle == (devhandle ^ 0x40)) {
 981                         return pci_sun4v_pbm_init(pbm->parent, dp, devhandle);
 982                 }
 983         }
 984
 985         for_each_possible_cpu(i) {
 986                 unsigned long page = get_zeroed_page(GFP_ATOMIC);
 987
 988                 if (!page)
 989                         return -ENOMEM;
 990
 991                 per_cpu(iommu_batch, i).pglist = (u64 *) page;
 992         }
 993
 994         p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
 995         if (!p) {
 996                 printk(KERN_ERR PFX "Could not allocate pci_controller_info\n");
 997                 goto out_free;
 998         }
 999
1000         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1001         if (!iommu) {
1002                 printk(KERN_ERR PFX "Could not allocate pbm A iommu\n");
1003                 goto out_free;
1004         }
1005
1006         p->pbm_A.iommu = iommu;
1007
1008         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1009         if (!iommu) {
1010                 printk(KERN_ERR PFX "Could not allocate pbm B iommu\n");
1011                 goto out_free;
1012         }
1013
1014         p->pbm_B.iommu = iommu;
1015
1016         return pci_sun4v_pbm_init(p, dp, devhandle);
1017
1018 out_free:
1019         if (p) {
1020                 if (p->pbm_A.iommu)
1021                         kfree(p->pbm_A.iommu);
1022                 if (p->pbm_B.iommu)
1023                         kfree(p->pbm_B.iommu);
1024                 kfree(p);
1025         }
1026         return -ENOMEM;
1027 }
1028
1029 static struct of_device_id __initdata pci_sun4v_match[] = {
1030         {
1031                 .name = "pci",
1032                 .compatible = "SUNW,sun4v-pci",
1033         },
1034         {},
1035 };
1036
1037 static struct of_platform_driver pci_sun4v_driver = {
1038         .name           = DRIVER_NAME,
1039         .match_table    = pci_sun4v_match,
1040         .probe          = pci_sun4v_probe,
1041 };
1042
1043 static int __init pci_sun4v_init(void)
1044 {
1045         return of_register_driver(&pci_sun4v_driver, &of_bus_type);
1046 }
1047
1048 subsys_initcall(pci_sun4v_init);