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[linux-2.6] / arch / powerpc / boot / dts / sbc8548.dts
1 /*
2  * SBC8548 Device Tree Source
3  *
4  * Copyright 2007 Wind River Systems Inc.
5  *
6  * Paul Gortmaker (see MAINTAINERS for contact information)
7  *
8  * This program is free software; you can redistribute  it and/or modify it
9  * under  the terms of  the GNU General  Public License as published by the
10  * Free Software Foundation;  either version 2 of the  License, or (at your
11  * option) any later version.
12  */
13
14
15 /dts-v1/;
16
17 / {
18         model = "SBC8548";
19         compatible = "SBC8548";
20         #address-cells = <1>;
21         #size-cells = <1>;
22
23         aliases {
24                 ethernet0 = &enet0;
25                 ethernet1 = &enet1;
26                 serial0 = &serial0;
27                 serial1 = &serial1;
28                 pci0 = &pci0;
29                 /* pci1 doesn't have a corresponding physical connector */
30                 pci2 = &pci2;
31         };
32
33         cpus {
34                 #address-cells = <1>;
35                 #size-cells = <0>;
36
37                 PowerPC,8548@0 {
38                         device_type = "cpu";
39                         reg = <0>;
40                         d-cache-line-size = <0x20>;     // 32 bytes
41                         i-cache-line-size = <0x20>;     // 32 bytes
42                         d-cache-size = <0x8000>;        // L1, 32K
43                         i-cache-size = <0x8000>;        // L1, 32K
44                         timebase-frequency = <0>;       // From uboot
45                         bus-frequency = <0>;
46                         clock-frequency = <0>;
47                         next-level-cache = <&L2>;
48                 };
49         };
50
51         memory {
52                 device_type = "memory";
53                 reg = <0x00000000 0x10000000>;
54         };
55
56         localbus@e0000000 {
57                 #address-cells = <2>;
58                 #size-cells = <1>;
59                 compatible = "simple-bus";
60                 reg = <0xe0000000 0x5000>;
61                 interrupt-parent = <&mpic>;
62
63                 ranges = <0x0 0x0 0xff800000 0x00800000         /*8MB Flash*/
64                           0x3 0x0 0xf0000000 0x04000000         /*64MB SDRAM*/
65                           0x4 0x0 0xf4000000 0x04000000         /*64MB SDRAM*/
66                           0x5 0x0 0xf8000000 0x00b10000         /* EPLD */
67                           0x6 0x0 0xfb800000 0x04000000>;       /*64MB Flash*/
68
69
70                 flash@0,0 {
71                         #address-cells = <1>;
72                         #size-cells = <1>;
73                         compatible = "cfi-flash";
74                         reg = <0x0 0x0 0x800000>;
75                         bank-width = <1>;
76                         device-width = <1>;
77                         partition@0x0 {
78                                 label = "space";
79                                 reg = <0x00000000 0x00100000>;
80                         };
81                         partition@0x100000 {
82                                 label = "bootloader";
83                                 reg = <0x00100000 0x00700000>;
84                                 read-only;
85                         };
86                 };
87
88                 epld@5,0 {
89                         compatible = "wrs,epld-localbus";
90                         #address-cells = <2>;
91                         #size-cells = <1>;
92                         reg = <0x5 0x0 0x00b10000>;
93                         ranges = <
94                                 0x0 0x0 0x5 0x000000 0x1fff     /* LED */
95                                 0x1 0x0 0x5 0x100000 0x1fff     /* Switches */
96                                 0x3 0x0 0x5 0x300000 0x1fff     /* HW Rev. */
97                                 0xb 0x0 0x5 0xb00000 0x1fff     /* EEPROM */
98                         >;
99
100                         led@0,0 {
101                                 compatible = "led";
102                                 reg = <0x0 0x0 0x1fff>;
103                         };
104
105                         switches@1,0 {
106                                 compatible = "switches";
107                                 reg = <0x1 0x0 0x1fff>;
108                         };
109
110                         hw-rev@3,0 {
111                                 compatible = "hw-rev";
112                                 reg = <0x3 0x0 0x1fff>;
113                         };
114
115                         eeprom@b,0 {
116                                 compatible = "eeprom";
117                                 reg = <0xb 0 0x1fff>;
118                         };
119
120                 };
121
122                 alt-flash@6,0 {
123                         #address-cells = <1>;
124                         #size-cells = <1>;
125                         reg = <0x6 0x0 0x04000000>;
126                         compatible = "cfi-flash";
127                         bank-width = <4>;
128                         device-width = <1>;
129                         partition@0x0 {
130                                 label = "bootloader";
131                                 reg = <0x00000000 0x00100000>;
132                                 read-only;
133                         };
134                         partition@0x00100000 {
135                                 label = "file-system";
136                                 reg = <0x00100000 0x01f00000>;
137                         };
138                         partition@0x02000000 {
139                                 label = "boot-config";
140                                 reg = <0x02000000 0x00100000>;
141                         };
142                         partition@0x02100000 {
143                                 label = "space";
144                                 reg = <0x02100000 0x01f00000>;
145                         };
146                 };
147         };
148
149         soc8548@e0000000 {
150                 #address-cells = <1>;
151                 #size-cells = <1>;
152                 device_type = "soc";
153                 ranges = <0x00000000 0xe0000000 0x00100000>;
154                 reg = <0xe0000000 0x00001000>;  // CCSRBAR
155                 bus-frequency = <0>;
156                 compatible = "simple-bus";
157
158                 memory-controller@2000 {
159                         compatible = "fsl,8548-memory-controller";
160                         reg = <0x2000 0x1000>;
161                         interrupt-parent = <&mpic>;
162                         interrupts = <0x12 0x2>;
163                 };
164
165                 L2: l2-cache-controller@20000 {
166                         compatible = "fsl,8548-l2-cache-controller";
167                         reg = <0x20000 0x1000>;
168                         cache-line-size = <0x20>;       // 32 bytes
169                         cache-size = <0x80000>; // L2, 512K
170                         interrupt-parent = <&mpic>;
171                         interrupts = <0x10 0x2>;
172                 };
173
174                 i2c@3000 {
175                         #address-cells = <1>;
176                         #size-cells = <0>;
177                         cell-index = <0>;
178                         compatible = "fsl-i2c";
179                         reg = <0x3000 0x100>;
180                         interrupts = <0x2b 0x2>;
181                         interrupt-parent = <&mpic>;
182                         dfsrr;
183                 };
184
185                 i2c@3100 {
186                         #address-cells = <1>;
187                         #size-cells = <0>;
188                         cell-index = <1>;
189                         compatible = "fsl-i2c";
190                         reg = <0x3100 0x100>;
191                         interrupts = <0x2b 0x2>;
192                         interrupt-parent = <&mpic>;
193                         dfsrr;
194                 };
195
196                 dma@21300 {
197                         #address-cells = <1>;
198                         #size-cells = <1>;
199                         compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
200                         reg = <0x21300 0x4>;
201                         ranges = <0x0 0x21100 0x200>;
202                         cell-index = <0>;
203                         dma-channel@0 {
204                                 compatible = "fsl,mpc8548-dma-channel",
205                                                 "fsl,eloplus-dma-channel";
206                                 reg = <0x0 0x80>;
207                                 cell-index = <0>;
208                                 interrupt-parent = <&mpic>;
209                                 interrupts = <20 2>;
210                         };
211                         dma-channel@80 {
212                                 compatible = "fsl,mpc8548-dma-channel",
213                                                 "fsl,eloplus-dma-channel";
214                                 reg = <0x80 0x80>;
215                                 cell-index = <1>;
216                                 interrupt-parent = <&mpic>;
217                                 interrupts = <21 2>;
218                         };
219                         dma-channel@100 {
220                                 compatible = "fsl,mpc8548-dma-channel",
221                                                 "fsl,eloplus-dma-channel";
222                                 reg = <0x100 0x80>;
223                                 cell-index = <2>;
224                                 interrupt-parent = <&mpic>;
225                                 interrupts = <22 2>;
226                         };
227                         dma-channel@180 {
228                                 compatible = "fsl,mpc8548-dma-channel",
229                                                 "fsl,eloplus-dma-channel";
230                                 reg = <0x180 0x80>;
231                                 cell-index = <3>;
232                                 interrupt-parent = <&mpic>;
233                                 interrupts = <23 2>;
234                         };
235                 };
236
237                 mdio@24520 {
238                         #address-cells = <1>;
239                         #size-cells = <0>;
240                         compatible = "fsl,gianfar-mdio";
241                         reg = <0x24520 0x20>;
242
243                         phy0: ethernet-phy@19 {
244                                 interrupt-parent = <&mpic>;
245                                 interrupts = <0x6 0x1>;
246                                 reg = <0x19>;
247                                 device_type = "ethernet-phy";
248                         };
249                         phy1: ethernet-phy@1a {
250                                 interrupt-parent = <&mpic>;
251                                 interrupts = <0x7 0x1>;
252                                 reg = <0x1a>;
253                                 device_type = "ethernet-phy";
254                         };
255                         tbi0: tbi-phy@11 {
256                                 reg = <0x11>;
257                                 device_type = "tbi-phy";
258                         };
259                 };
260
261                 mdio@25520 {
262                         #address-cells = <1>;
263                         #size-cells = <0>;
264                         compatible = "fsl,gianfar-tbi";
265                         reg = <0x25520 0x20>;
266
267                         tbi1: tbi-phy@11 {
268                                 reg = <0x11>;
269                                 device_type = "tbi-phy";
270                         };
271                 };
272
273                 enet0: ethernet@24000 {
274                         cell-index = <0>;
275                         device_type = "network";
276                         model = "eTSEC";
277                         compatible = "gianfar";
278                         reg = <0x24000 0x1000>;
279                         local-mac-address = [ 00 00 00 00 00 00 ];
280                         interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
281                         interrupt-parent = <&mpic>;
282                         tbi-handle = <&tbi0>;
283                         phy-handle = <&phy0>;
284                 };
285
286                 enet1: ethernet@25000 {
287                         cell-index = <1>;
288                         device_type = "network";
289                         model = "eTSEC";
290                         compatible = "gianfar";
291                         reg = <0x25000 0x1000>;
292                         local-mac-address = [ 00 00 00 00 00 00 ];
293                         interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
294                         interrupt-parent = <&mpic>;
295                         tbi-handle = <&tbi1>;
296                         phy-handle = <&phy1>;
297                 };
298
299                 serial0: serial@4500 {
300                         cell-index = <0>;
301                         device_type = "serial";
302                         compatible = "ns16550";
303                         reg = <0x4500 0x100>;   // reg base, size
304                         clock-frequency = <0>;  // should we fill in in uboot?
305                         interrupts = <0x2a 0x2>;
306                         interrupt-parent = <&mpic>;
307                 };
308
309                 serial1: serial@4600 {
310                         cell-index = <1>;
311                         device_type = "serial";
312                         compatible = "ns16550";
313                         reg = <0x4600 0x100>;   // reg base, size
314                         clock-frequency = <0>;  // should we fill in in uboot?
315                         interrupts = <0x2a 0x2>;
316                         interrupt-parent = <&mpic>;
317                 };
318
319                 global-utilities@e0000 {        //global utilities reg
320                         compatible = "fsl,mpc8548-guts";
321                         reg = <0xe0000 0x1000>;
322                         fsl,has-rstcr;
323                 };
324
325                 crypto@30000 {
326                         compatible = "fsl,sec2.1", "fsl,sec2.0";
327                         reg = <0x30000 0x10000>;
328                         interrupts = <45 2>;
329                         interrupt-parent = <&mpic>;
330                         fsl,num-channels = <4>;
331                         fsl,channel-fifo-len = <24>;
332                         fsl,exec-units-mask = <0xfe>;
333                         fsl,descriptor-types-mask = <0x12b0ebf>;
334                 };
335
336                 mpic: pic@40000 {
337                         interrupt-controller;
338                         #address-cells = <0>;
339                         #interrupt-cells = <2>;
340                         reg = <0x40000 0x40000>;
341                         compatible = "chrp,open-pic";
342                         device_type = "open-pic";
343                 };
344         };
345
346         pci0: pci@e0008000 {
347                 cell-index = <0>;
348                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
349                 interrupt-map = <
350                         /* IDSEL 0x01 (PCI-X slot) @66MHz */
351                         0x0800 0x0 0x0 0x1 &mpic 0x2 0x1
352                         0x0800 0x0 0x0 0x2 &mpic 0x3 0x1
353                         0x0800 0x0 0x0 0x3 &mpic 0x4 0x1
354                         0x0800 0x0 0x0 0x4 &mpic 0x1 0x1
355
356                         /* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */
357                         0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
358                         0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
359                         0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
360                         0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>;
361
362                 interrupt-parent = <&mpic>;
363                 interrupts = <0x18 0x2>;
364                 bus-range = <0 0>;
365                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
366                           0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
367                 clock-frequency = <66666666>;
368                 #interrupt-cells = <1>;
369                 #size-cells = <2>;
370                 #address-cells = <3>;
371                 reg = <0xe0008000 0x1000>;
372                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
373                 device_type = "pci";
374         };
375
376         pci2: pcie@e000a000 {
377                 cell-index = <2>;
378                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
379                 interrupt-map = <
380
381                         /* IDSEL 0x0 (PEX) */
382                         0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
383                         0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
384                         0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
385                         0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;
386
387                 interrupt-parent = <&mpic>;
388                 interrupts = <0x1a 0x2>;
389                 bus-range = <0x0 0xff>;
390                 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
391                           0x01000000 0x0 0x00000000 0xe3000000 0x0 0x08000000>;
392                 clock-frequency = <33333333>;
393                 #interrupt-cells = <1>;
394                 #size-cells = <2>;
395                 #address-cells = <3>;
396                 reg = <0xe000a000 0x1000>;
397                 compatible = "fsl,mpc8548-pcie";
398                 device_type = "pci";
399                 pcie@0 {
400                         reg = <0x0 0x0 0x0 0x0 0x0>;
401                         #size-cells = <2>;
402                         #address-cells = <3>;
403                         device_type = "pci";
404                         ranges = <0x02000000 0x0 0xa0000000
405                                   0x02000000 0x0 0xa0000000
406                                   0x0 0x20000000
407
408                                   0x01000000 0x0 0x00000000
409                                   0x01000000 0x0 0x00000000
410                                   0x0 0x08000000>;
411                 };
412         };
413 };