Merge with /pub/scm/linux/kernel/git/torvalds/linux-2.6.git
[linux-2.6] / arch / arm / mach-ixp4xx / common.c
1 /*
2  * arch/arm/mach-ixp4xx/common.c
3  *
4  * Generic code shared across all IXP4XX platforms
5  *
6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
7  *
8  * Copyright 2002 (c) Intel Corporation
9  * Copyright 2003-2004 (c) MontaVista, Software, Inc. 
10  * 
11  * This file is licensed under  the terms of the GNU General Public 
12  * License version 2. This program is licensed "as is" without any 
13  * warranty of any kind, whether express or implied.
14  */
15
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/mm.h>
19 #include <linux/init.h>
20 #include <linux/serial.h>
21 #include <linux/sched.h>
22 #include <linux/tty.h>
23 #include <linux/platform_device.h>
24 #include <linux/serial_core.h>
25 #include <linux/bootmem.h>
26 #include <linux/interrupt.h>
27 #include <linux/bitops.h>
28 #include <linux/time.h>
29 #include <linux/timex.h>
30
31 #include <asm/hardware.h>
32 #include <asm/uaccess.h>
33 #include <asm/io.h>
34 #include <asm/pgtable.h>
35 #include <asm/page.h>
36 #include <asm/irq.h>
37
38 #include <asm/mach/map.h>
39 #include <asm/mach/irq.h>
40 #include <asm/mach/time.h>
41
42 /*************************************************************************
43  * IXP4xx chipset I/O mapping
44  *************************************************************************/
45 static struct map_desc ixp4xx_io_desc[] __initdata = {
46         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
47                 .virtual        = IXP4XX_PERIPHERAL_BASE_VIRT,
48                 .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
49                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
50                 .type           = MT_DEVICE
51         }, {    /* Expansion Bus Config Registers */
52                 .virtual        = IXP4XX_EXP_CFG_BASE_VIRT,
53                 .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
54                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
55                 .type           = MT_DEVICE
56         }, {    /* PCI Registers */
57                 .virtual        = IXP4XX_PCI_CFG_BASE_VIRT,
58                 .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
59                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
60                 .type           = MT_DEVICE
61         },
62 #ifdef CONFIG_DEBUG_LL
63         {       /* Debug UART mapping */
64                 .virtual        = IXP4XX_DEBUG_UART_BASE_VIRT,
65                 .pfn            = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
66                 .length         = IXP4XX_DEBUG_UART_REGION_SIZE,
67                 .type           = MT_DEVICE
68         }
69 #endif
70 };
71
72 void __init ixp4xx_map_io(void)
73 {
74         iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
75 }
76
77
78 /*************************************************************************
79  * IXP4xx chipset IRQ handling
80  *
81  * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
82  *       (be it PCI or something else) configures that GPIO line
83  *       as an IRQ.
84  **************************************************************************/
85 enum ixp4xx_irq_type {
86         IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
87 };
88
89 static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type);
90
91 /*
92  * IRQ -> GPIO mapping table
93  */
94 static int irq2gpio[32] = {
95         -1, -1, -1, -1, -1, -1,  0,  1,
96         -1, -1, -1, -1, -1, -1, -1, -1,
97         -1, -1, -1,  2,  3,  4,  5,  6,
98          7,  8,  9, 10, 11, 12, -1, -1,
99 };
100
101 static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
102 {
103         int line = irq2gpio[irq];
104         u32 int_style;
105         enum ixp4xx_irq_type irq_type;
106         volatile u32 *int_reg;
107
108         /*
109          * Only for GPIO IRQs
110          */
111         if (line < 0)
112                 return -EINVAL;
113
114         switch (type){
115         case IRQT_BOTHEDGE:
116                 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
117                 irq_type = IXP4XX_IRQ_EDGE;
118                 break;
119         case IRQT_RISING:
120                 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
121                 irq_type = IXP4XX_IRQ_EDGE;
122                 break;
123         case IRQT_FALLING:
124                 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
125                 irq_type = IXP4XX_IRQ_EDGE;
126                 break;
127         case IRQT_HIGH:
128                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
129                 irq_type = IXP4XX_IRQ_LEVEL;
130                 break;
131         case IRQT_LOW:
132                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
133                 irq_type = IXP4XX_IRQ_LEVEL;
134                 break;
135         default:
136                 return -EINVAL;
137         }
138         ixp4xx_config_irq(irq, irq_type);
139
140         if (line >= 8) {        /* pins 8-15 */
141                 line -= 8;
142                 int_reg = IXP4XX_GPIO_GPIT2R;
143         } else {                /* pins 0-7 */
144                 int_reg = IXP4XX_GPIO_GPIT1R;
145         }
146
147         /* Clear the style for the appropriate pin */
148         *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
149                         (line * IXP4XX_GPIO_STYLE_SIZE));
150
151         *IXP4XX_GPIO_GPISR = (1 << line);
152
153         /* Set the new style */
154         *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
155
156         return 0;
157 }
158
159 static void ixp4xx_irq_mask(unsigned int irq)
160 {
161         if (cpu_is_ixp46x() && irq >= 32)
162                 *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
163         else
164                 *IXP4XX_ICMR &= ~(1 << irq);
165 }
166
167 static void ixp4xx_irq_unmask(unsigned int irq)
168 {
169         if (cpu_is_ixp46x() && irq >= 32)
170                 *IXP4XX_ICMR2 |= (1 << (irq - 32));
171         else
172                 *IXP4XX_ICMR |= (1 << irq);
173 }
174
175 static void ixp4xx_irq_ack(unsigned int irq)
176 {
177         int line = (irq < 32) ? irq2gpio[irq] : -1;
178
179         if (line >= 0)
180                 *IXP4XX_GPIO_GPISR = (1 << line);
181 }
182
183 /*
184  * Level triggered interrupts on GPIO lines can only be cleared when the
185  * interrupt condition disappears.
186  */
187 static void ixp4xx_irq_level_unmask(unsigned int irq)
188 {
189         ixp4xx_irq_ack(irq);
190         ixp4xx_irq_unmask(irq);
191 }
192
193 static struct irqchip ixp4xx_irq_level_chip = {
194         .ack            = ixp4xx_irq_mask,
195         .mask           = ixp4xx_irq_mask,
196         .unmask         = ixp4xx_irq_level_unmask,
197         .set_type       = ixp4xx_set_irq_type,
198 };
199
200 static struct irqchip ixp4xx_irq_edge_chip = {
201         .ack            = ixp4xx_irq_ack,
202         .mask           = ixp4xx_irq_mask,
203         .unmask         = ixp4xx_irq_unmask,
204         .set_type       = ixp4xx_set_irq_type,
205 };
206
207 static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type)
208 {
209         switch (type) {
210         case IXP4XX_IRQ_LEVEL:
211                 set_irq_chip(irq, &ixp4xx_irq_level_chip);
212                 set_irq_handler(irq, do_level_IRQ);
213                 break;
214         case IXP4XX_IRQ_EDGE:
215                 set_irq_chip(irq, &ixp4xx_irq_edge_chip);
216                 set_irq_handler(irq, do_edge_IRQ);
217                 break;
218         }
219         set_irq_flags(irq, IRQF_VALID);
220 }
221
222 void __init ixp4xx_init_irq(void)
223 {
224         int i = 0;
225
226         /* Route all sources to IRQ instead of FIQ */
227         *IXP4XX_ICLR = 0x0;
228
229         /* Disable all interrupt */
230         *IXP4XX_ICMR = 0x0; 
231
232         if (cpu_is_ixp46x()) {
233                 /* Route upper 32 sources to IRQ instead of FIQ */
234                 *IXP4XX_ICLR2 = 0x00;
235
236                 /* Disable upper 32 interrupts */
237                 *IXP4XX_ICMR2 = 0x00;
238         }
239
240         /* Default to all level triggered */
241         for(i = 0; i < NR_IRQS; i++)
242                 ixp4xx_config_irq(i, IXP4XX_IRQ_LEVEL);
243 }
244
245
246 /*************************************************************************
247  * IXP4xx timer tick
248  * We use OS timer1 on the CPU for the timer tick and the timestamp 
249  * counter as a source of real clock ticks to account for missed jiffies.
250  *************************************************************************/
251
252 static unsigned volatile last_jiffy_time;
253
254 #define CLOCK_TICKS_PER_USEC    ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
255
256 /* IRQs are disabled before entering here from do_gettimeofday() */
257 static unsigned long ixp4xx_gettimeoffset(void)
258 {
259         u32 elapsed;
260
261         elapsed = *IXP4XX_OSTS - last_jiffy_time;
262
263         return elapsed / CLOCK_TICKS_PER_USEC;
264 }
265
266 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
267 {
268         write_seqlock(&xtime_lock);
269
270         /* Clear Pending Interrupt by writing '1' to it */
271         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
272
273         /*
274          * Catch up with the real idea of time
275          */
276         while ((*IXP4XX_OSTS - last_jiffy_time) > LATCH) {
277                 timer_tick(regs);
278                 last_jiffy_time += LATCH;
279         }
280
281         write_sequnlock(&xtime_lock);
282
283         return IRQ_HANDLED;
284 }
285
286 static struct irqaction ixp4xx_timer_irq = {
287         .name           = "IXP4xx Timer Tick",
288         .flags          = SA_INTERRUPT | SA_TIMER,
289         .handler        = ixp4xx_timer_interrupt,
290 };
291
292 static void __init ixp4xx_timer_init(void)
293 {
294         /* Clear Pending Interrupt by writing '1' to it */
295         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
296
297         /* Setup the Timer counter value */
298         *IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE;
299
300         /* Reset time-stamp counter */
301         *IXP4XX_OSTS = 0;
302         last_jiffy_time = 0;
303
304         /* Connect the interrupt handler and enable the interrupt */
305         setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
306 }
307
308 struct sys_timer ixp4xx_timer = {
309         .init           = ixp4xx_timer_init,
310         .offset         = ixp4xx_gettimeoffset,
311 };
312
313 static struct resource ixp46x_i2c_resources[] = {
314         [0] = {
315                 .start  = 0xc8011000,
316                 .end    = 0xc801101c,
317                 .flags  = IORESOURCE_MEM,
318         },
319         [1] = {
320                 .start  = IRQ_IXP4XX_I2C,
321                 .end    = IRQ_IXP4XX_I2C,
322                 .flags  = IORESOURCE_IRQ
323         }
324 };
325
326 /*
327  * I2C controller. The IXP46x uses the same block as the IOP3xx, so
328  * we just use the same device name.
329  */
330 static struct platform_device ixp46x_i2c_controller = {
331         .name           = "IOP3xx-I2C",
332         .id             = 0,
333         .num_resources  = 2,
334         .resource       = ixp46x_i2c_resources
335 };
336
337 static struct platform_device *ixp46x_devices[] __initdata = {
338         &ixp46x_i2c_controller
339 };
340
341 unsigned long ixp4xx_exp_bus_size;
342 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
343
344 void __init ixp4xx_sys_init(void)
345 {
346         ixp4xx_exp_bus_size = SZ_16M;
347
348         if (cpu_is_ixp46x()) {
349                 int region;
350
351                 platform_add_devices(ixp46x_devices,
352                                 ARRAY_SIZE(ixp46x_devices));
353
354                 for (region = 0; region < 7; region++) {
355                         if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
356                                 ixp4xx_exp_bus_size = SZ_32M;
357                                 break;
358                         }
359                 }
360         }
361
362         printk("IXP4xx: Using %luMiB expansion bus window size\n",
363                         ixp4xx_exp_bus_size >> 20);
364 }
365