4 * Copyright (C) 2008 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/uio_driver.h>
16 #include <linux/sh_timer.h>
17 #include <asm/clock.h>
18 #include <asm/mmzone.h>
20 static struct uio_info vpu_platform_data = {
26 static struct resource vpu_resources[] = {
31 .flags = IORESOURCE_MEM,
34 /* place holder for contiguous memory */
38 static struct platform_device vpu_device = {
39 .name = "uio_pdrv_genirq",
42 .platform_data = &vpu_platform_data,
44 .resource = vpu_resources,
45 .num_resources = ARRAY_SIZE(vpu_resources),
48 static struct uio_info veu0_platform_data = {
54 static struct resource veu0_resources[] = {
59 .flags = IORESOURCE_MEM,
62 /* place holder for contiguous memory */
66 static struct platform_device veu0_device = {
67 .name = "uio_pdrv_genirq",
70 .platform_data = &veu0_platform_data,
72 .resource = veu0_resources,
73 .num_resources = ARRAY_SIZE(veu0_resources),
76 static struct uio_info veu1_platform_data = {
82 static struct resource veu1_resources[] = {
87 .flags = IORESOURCE_MEM,
90 /* place holder for contiguous memory */
94 static struct platform_device veu1_device = {
95 .name = "uio_pdrv_genirq",
98 .platform_data = &veu1_platform_data,
100 .resource = veu1_resources,
101 .num_resources = ARRAY_SIZE(veu1_resources),
104 static struct sh_timer_config cmt_platform_data = {
106 .channel_offset = 0x60,
109 .clockevent_rating = 125,
110 .clocksource_rating = 125,
113 static struct resource cmt_resources[] = {
118 .flags = IORESOURCE_MEM,
122 .flags = IORESOURCE_IRQ,
126 static struct platform_device cmt_device = {
130 .platform_data = &cmt_platform_data,
132 .resource = cmt_resources,
133 .num_resources = ARRAY_SIZE(cmt_resources),
136 static struct sh_timer_config tmu0_platform_data = {
138 .channel_offset = 0x04,
141 .clockevent_rating = 200,
144 static struct resource tmu0_resources[] = {
149 .flags = IORESOURCE_MEM,
153 .flags = IORESOURCE_IRQ,
157 static struct platform_device tmu0_device = {
161 .platform_data = &tmu0_platform_data,
163 .resource = tmu0_resources,
164 .num_resources = ARRAY_SIZE(tmu0_resources),
167 static struct sh_timer_config tmu1_platform_data = {
169 .channel_offset = 0x10,
172 .clocksource_rating = 200,
175 static struct resource tmu1_resources[] = {
180 .flags = IORESOURCE_MEM,
184 .flags = IORESOURCE_IRQ,
188 static struct platform_device tmu1_device = {
192 .platform_data = &tmu1_platform_data,
194 .resource = tmu1_resources,
195 .num_resources = ARRAY_SIZE(tmu1_resources),
198 static struct sh_timer_config tmu2_platform_data = {
200 .channel_offset = 0x1c,
205 static struct resource tmu2_resources[] = {
210 .flags = IORESOURCE_MEM,
214 .flags = IORESOURCE_IRQ,
218 static struct platform_device tmu2_device = {
222 .platform_data = &tmu2_platform_data,
224 .resource = tmu2_resources,
225 .num_resources = ARRAY_SIZE(tmu2_resources),
228 static struct sh_timer_config tmu3_platform_data = {
230 .channel_offset = 0x04,
235 static struct resource tmu3_resources[] = {
240 .flags = IORESOURCE_MEM,
244 .flags = IORESOURCE_IRQ,
248 static struct platform_device tmu3_device = {
252 .platform_data = &tmu3_platform_data,
254 .resource = tmu3_resources,
255 .num_resources = ARRAY_SIZE(tmu3_resources),
258 static struct sh_timer_config tmu4_platform_data = {
260 .channel_offset = 0x10,
265 static struct resource tmu4_resources[] = {
270 .flags = IORESOURCE_MEM,
274 .flags = IORESOURCE_IRQ,
278 static struct platform_device tmu4_device = {
282 .platform_data = &tmu4_platform_data,
284 .resource = tmu4_resources,
285 .num_resources = ARRAY_SIZE(tmu4_resources),
288 static struct sh_timer_config tmu5_platform_data = {
290 .channel_offset = 0x1c,
295 static struct resource tmu5_resources[] = {
300 .flags = IORESOURCE_MEM,
304 .flags = IORESOURCE_IRQ,
308 static struct platform_device tmu5_device = {
312 .platform_data = &tmu5_platform_data,
314 .resource = tmu5_resources,
315 .num_resources = ARRAY_SIZE(tmu5_resources),
318 static struct plat_sci_port sci_platform_data[] = {
320 .mapbase = 0xffe00000,
321 .flags = UPF_BOOT_AUTOCONF,
323 .irqs = { 80, 80, 80, 80 },
326 .mapbase = 0xffe10000,
327 .flags = UPF_BOOT_AUTOCONF,
329 .irqs = { 81, 81, 81, 81 },
332 .mapbase = 0xffe20000,
333 .flags = UPF_BOOT_AUTOCONF,
335 .irqs = { 82, 82, 82, 82 },
338 .mapbase = 0xa4e30000,
339 .flags = UPF_BOOT_AUTOCONF,
341 .irqs = { 56, 56, 56, 56 },
344 .mapbase = 0xa4e40000,
345 .flags = UPF_BOOT_AUTOCONF,
347 .irqs = { 88, 88, 88, 88 },
350 .mapbase = 0xa4e50000,
351 .flags = UPF_BOOT_AUTOCONF,
353 .irqs = { 109, 109, 109, 109 },
360 static struct platform_device sci_device = {
364 .platform_data = sci_platform_data,
368 static struct resource rtc_resources[] = {
371 .end = 0xa465fec0 + 0x58 - 1,
372 .flags = IORESOURCE_IO,
377 .flags = IORESOURCE_IRQ,
382 .flags = IORESOURCE_IRQ,
387 .flags = IORESOURCE_IRQ,
391 static struct platform_device rtc_device = {
394 .num_resources = ARRAY_SIZE(rtc_resources),
395 .resource = rtc_resources,
398 static struct resource sh7723_usb_host_resources[] = {
400 .name = "r8a66597_hcd",
403 .flags = IORESOURCE_MEM,
408 .flags = IORESOURCE_IRQ,
412 static struct platform_device sh7723_usb_host_device = {
413 .name = "r8a66597_hcd",
416 .dma_mask = NULL, /* not use dma */
417 .coherent_dma_mask = 0xffffffff,
419 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources),
420 .resource = sh7723_usb_host_resources,
423 static struct resource iic_resources[] = {
428 .flags = IORESOURCE_MEM,
433 .flags = IORESOURCE_IRQ,
437 static struct platform_device iic_device = {
438 .name = "i2c-sh_mobile",
439 .id = 0, /* "i2c0" clock */
440 .num_resources = ARRAY_SIZE(iic_resources),
441 .resource = iic_resources,
444 static struct platform_device *sh7723_devices[] __initdata = {
455 &sh7723_usb_host_device,
461 static int __init sh7723_devices_setup(void)
463 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
464 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
465 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
467 return platform_add_devices(sh7723_devices,
468 ARRAY_SIZE(sh7723_devices));
470 __initcall(sh7723_devices_setup);
472 static struct platform_device *sh7723_early_devices[] __initdata = {
482 void __init plat_early_device_setup(void)
484 early_platform_add_devices(sh7723_early_devices,
485 ARRAY_SIZE(sh7723_early_devices));
491 /* interrupt sources */
492 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
494 DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
495 _2DG_TRI,_2DG_INI,_2DG_CEI,
496 DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
497 VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
503 RTC_ATI,RTC_PRI,RTC_CUI,
504 DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
505 DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
507 SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
508 MSIOF_MSIOFI0,MSIOF_MSIOFI1,
510 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
511 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
512 SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
517 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
520 SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
523 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
525 /* interrupt groups */
526 DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
527 SDHI1, RTC, DMAC1B, SDHI0,
530 static struct intc_vect vectors[] __initdata = {
531 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
532 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
533 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
534 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
536 INTC_VECT(DMAC1A_DEI0,0x700),
537 INTC_VECT(DMAC1A_DEI1,0x720),
538 INTC_VECT(DMAC1A_DEI2,0x740),
539 INTC_VECT(DMAC1A_DEI3,0x760),
541 INTC_VECT(_2DG_TRI, 0x780),
542 INTC_VECT(_2DG_INI, 0x7A0),
543 INTC_VECT(_2DG_CEI, 0x7C0),
545 INTC_VECT(DMAC0A_DEI0,0x800),
546 INTC_VECT(DMAC0A_DEI1,0x820),
547 INTC_VECT(DMAC0A_DEI2,0x840),
548 INTC_VECT(DMAC0A_DEI3,0x860),
550 INTC_VECT(VIO_CEUI,0x880),
551 INTC_VECT(VIO_BEUI,0x8A0),
552 INTC_VECT(VIO_VEU2HI,0x8C0),
553 INTC_VECT(VIO_VOUI,0x8E0),
555 INTC_VECT(SCIFA_SCIFA0,0x900),
556 INTC_VECT(VPU_VPUI,0x980),
557 INTC_VECT(TPU_TPUI,0x9A0),
558 INTC_VECT(ADC_ADI,0x9E0),
559 INTC_VECT(USB_USI0,0xA20),
561 INTC_VECT(RTC_ATI,0xA80),
562 INTC_VECT(RTC_PRI,0xAA0),
563 INTC_VECT(RTC_CUI,0xAC0),
565 INTC_VECT(DMAC1B_DEI4,0xB00),
566 INTC_VECT(DMAC1B_DEI5,0xB20),
567 INTC_VECT(DMAC1B_DADERR,0xB40),
569 INTC_VECT(DMAC0B_DEI4,0xB80),
570 INTC_VECT(DMAC0B_DEI5,0xBA0),
571 INTC_VECT(DMAC0B_DADERR,0xBC0),
573 INTC_VECT(KEYSC_KEYI,0xBE0),
574 INTC_VECT(SCIF_SCIF0,0xC00),
575 INTC_VECT(SCIF_SCIF1,0xC20),
576 INTC_VECT(SCIF_SCIF2,0xC40),
577 INTC_VECT(MSIOF_MSIOFI0,0xC80),
578 INTC_VECT(MSIOF_MSIOFI1,0xCA0),
579 INTC_VECT(SCIFA_SCIFA1,0xD00),
581 INTC_VECT(FLCTL_FLSTEI,0xD80),
582 INTC_VECT(FLCTL_FLTENDI,0xDA0),
583 INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
584 INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
586 INTC_VECT(I2C_ALI,0xE00),
587 INTC_VECT(I2C_TACKI,0xE20),
588 INTC_VECT(I2C_WAITI,0xE40),
589 INTC_VECT(I2C_DTEI,0xE60),
591 INTC_VECT(SDHI0_SDHII0,0xE80),
592 INTC_VECT(SDHI0_SDHII1,0xEA0),
593 INTC_VECT(SDHI0_SDHII2,0xEC0),
595 INTC_VECT(CMT_CMTI,0xF00),
596 INTC_VECT(TSIF_TSIFI,0xF20),
597 INTC_VECT(SIU_SIUI,0xF80),
598 INTC_VECT(SCIFA_SCIFA2,0xFA0),
600 INTC_VECT(TMU0_TUNI0,0x400),
601 INTC_VECT(TMU0_TUNI1,0x420),
602 INTC_VECT(TMU0_TUNI2,0x440),
604 INTC_VECT(IRDA_IRDAI,0x480),
605 INTC_VECT(ATAPI_ATAPII,0x4A0),
607 INTC_VECT(SDHI1_SDHII0,0x4E0),
608 INTC_VECT(SDHI1_SDHII1,0x500),
609 INTC_VECT(SDHI1_SDHII2,0x520),
611 INTC_VECT(VEU2H1_VEU2HI,0x560),
612 INTC_VECT(LCDC_LCDCI,0x580),
614 INTC_VECT(TMU1_TUNI0,0x920),
615 INTC_VECT(TMU1_TUNI1,0x940),
616 INTC_VECT(TMU1_TUNI2,0x960),
620 static struct intc_group groups[] __initdata = {
621 INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
622 INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
623 INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
624 INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
625 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
626 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
627 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
628 INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
629 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
630 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
631 INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
634 static struct intc_mask_reg mask_registers[] __initdata = {
635 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
636 { 0, TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
637 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
638 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
639 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
640 { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
641 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
642 { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
643 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
644 { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
645 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
646 { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
647 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
648 { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
649 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
650 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
651 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
652 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
653 { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
654 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
655 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
656 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
657 { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
658 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
659 { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
660 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
661 { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
662 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
663 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
666 static struct intc_prio_reg prio_registers[] __initdata = {
667 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
668 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
669 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
670 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
671 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
672 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
673 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
674 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
675 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
676 { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
677 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
678 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
679 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
680 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
683 static struct intc_sense_reg sense_registers[] __initdata = {
684 { 0xa414001c, 16, 2, /* ICR1 */
685 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
688 static struct intc_mask_reg ack_registers[] __initdata = {
689 { 0xa4140024, 0, 8, /* INTREQ00 */
690 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
693 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups,
694 mask_registers, prio_registers, sense_registers,
697 void __init plat_irq_setup(void)
699 register_intc_controller(&intc_desc);