1 #include <linux/serial_core.h>
5 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6 #include <asm/regs306x.h>
8 #if defined(CONFIG_H8S2678)
9 #include <asm/regs267x.h>
12 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7709)
16 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
19 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
20 # define SCIF0 0xA4400000
21 # define SCIF2 0xA4410000
22 # define SCSMR_Ir 0xA44A0000
23 # define IRDA_SCIF SCIF0
24 # define SCPCR 0xA4000116
25 # define SCPDR 0xA4000136
27 /* Set the clock source,
28 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
29 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
31 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
32 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7721)
34 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
35 # define PORT_PTCR 0xA405011EUL
36 # define PORT_PVCR 0xA4050122UL
37 # define SCIF_ORER 0x0200 /* overrun error bit */
38 #elif defined(CONFIG_SH_RTS7751R2D)
39 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
40 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
41 # define SCIF_ORER 0x0001 /* overrun error bit */
42 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
43 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
44 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
45 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
46 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
47 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
48 defined(CONFIG_CPU_SUBTYPE_SH7751R)
49 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
50 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
51 # define SCIF_ORER 0x0001 /* overrun error bit */
52 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
53 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
54 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
55 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
56 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
57 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
58 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
59 # define SCIF_ORER 0x0001 /* overrun error bit */
60 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
61 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
62 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */
63 # define SCIF_ORER 0x0001 /* overrun error bit */
64 # define PACR 0xa4050100
65 # define PBCR 0xa4050102
66 # define SCSCR_INIT(port) 0x3B
67 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
68 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */
69 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */
70 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */
71 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */
72 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
73 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
74 # define PADR 0xA4050120
75 # define PSDR 0xA405013e
76 # define PWDR 0xA4050166
77 # define PSCR 0xA405011E
78 # define SCIF_ORER 0x0001 /* overrun error bit */
79 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
80 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
81 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
82 # define SCSPTR0 SCPDR0
83 # define SCIF_ORER 0x0001 /* overrun error bit */
84 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
85 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
86 # define SCSPTR0 0xa4050160
87 # define SCSPTR1 0xa405013e
88 # define SCSPTR2 0xa4050160
89 # define SCSPTR3 0xa405013e
90 # define SCSPTR4 0xa4050128
91 # define SCSPTR5 0xa4050128
92 # define SCIF_ORER 0x0001 /* overrun error bit */
93 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
94 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
95 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
96 # define SCIF_ORER 0x0001 /* overrun error bit */
97 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
98 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
99 # define SCIF_BASE_ADDR 0x01030000
100 # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
101 # define SCIF_PTR2_OFFS 0x0000020
102 # define SCIF_LSR2_OFFS 0x0000024
103 # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
104 # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
105 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
106 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
107 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
108 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
109 #elif defined(CONFIG_H8S2678)
110 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
111 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
112 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
113 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
114 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
115 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
116 # define SCIF_ORER 0x0001 /* overrun error bit */
117 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
118 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
119 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
120 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
121 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
122 # define SCIF_ORER 0x0001 /* overrun error bit */
123 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
124 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
125 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
126 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */
127 # define SCIF_ORER 0x0001 /* Overrun error bit */
128 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
129 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
130 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */
131 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
132 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */
133 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */
134 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */
135 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */
136 # define SCIF_OPER 0x0001 /* Overrun error bit */
137 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
138 #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
139 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
140 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
141 defined(CONFIG_CPU_SUBTYPE_SH7263)
142 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
143 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
144 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
145 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
146 # if defined(CONFIG_CPU_SUBTYPE_SH7201)
147 # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
148 # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
149 # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
150 # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
152 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
153 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
154 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
155 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
156 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
157 # define SCIF_ORER 0x0001 /* overrun error bit */
158 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
159 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
160 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */
161 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */
162 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */
163 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */
164 # define SCIF_ORER 0x0001 /* Overrun error bit */
165 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
167 # error CPU subtype not defined
171 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
172 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
173 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
174 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
175 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
176 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
177 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
178 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
179 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
180 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
181 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
182 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
183 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
184 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
185 defined(CONFIG_CPU_SUBTYPE_SHX3)
186 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
188 #define SCI_CTRL_FLAGS_REIE 0
190 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
191 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
192 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
193 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
196 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
197 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
198 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
199 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
200 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
201 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
202 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
203 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
205 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
208 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
209 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
210 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
211 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
212 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
213 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
214 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
215 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
217 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
218 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
219 defined(CONFIG_CPU_SUBTYPE_SH7721)
220 # define SCIF_ORER 0x0200
221 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
222 # define SCIF_RFDC_MASK 0x007f
223 # define SCIF_TXROOM_MAX 64
224 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
225 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
226 # define SCIF_RFDC_MASK 0x007f
227 # define SCIF_TXROOM_MAX 64
228 /* SH7763 SCIF2 support */
229 # define SCIF2_RFDC_MASK 0x001f
230 # define SCIF2_TXROOM_MAX 16
232 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
233 # define SCIF_RFDC_MASK 0x001f
234 # define SCIF_TXROOM_MAX 16
238 #define SCIF_ORER 0x0000
241 #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
242 #define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
243 #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
244 #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
245 #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
246 #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
247 #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
248 #define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
250 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
251 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
252 defined(CONFIG_CPU_SUBTYPE_SH7721)
253 # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
254 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
255 # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
256 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
258 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
259 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
260 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
261 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
265 #define SCFCR_RFRST 0x0002
266 #define SCFCR_TFRST 0x0004
267 #define SCFCR_TCRST 0x4000
268 #define SCFCR_MCE 0x0008
270 #define SCI_MAJOR 204
271 #define SCI_MINOR_START 8
273 /* Generic serial flags */
274 #define SCI_RX_THROTTLE 0x0000001
276 #define SCI_MAGIC 0xbabeface
279 * Events are used to schedule things to happen at timer-interrupt
280 * time, instead of at rs interrupt time.
282 #define SCI_EVENT_WRITE_WAKEUP 0
284 #define SCI_IN(size, offset) \
286 return ioread8(port->membase + (offset)); \
288 return ioread16(port->membase + (offset)); \
290 #define SCI_OUT(size, offset, value) \
292 iowrite8(value, port->membase + (offset)); \
293 } else if ((size) == 16) { \
294 iowrite16(value, port->membase + (offset)); \
297 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
298 static inline unsigned int sci_##name##_in(struct uart_port *port) \
300 if (port->type == PORT_SCIF) { \
301 SCI_IN(scif_size, scif_offset) \
302 } else { /* PORT_SCI or PORT_SCIFA */ \
303 SCI_IN(sci_size, sci_offset); \
306 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
308 if (port->type == PORT_SCIF) { \
309 SCI_OUT(scif_size, scif_offset, value) \
310 } else { /* PORT_SCI or PORT_SCIFA */ \
311 SCI_OUT(sci_size, sci_offset, value); \
315 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
316 static inline unsigned int sci_##name##_in(struct uart_port *port) \
318 SCI_IN(scif_size, scif_offset); \
320 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
322 SCI_OUT(scif_size, scif_offset, value); \
325 #define CPU_SCI_FNS(name, sci_offset, sci_size) \
326 static inline unsigned int sci_##name##_in(struct uart_port* port) \
328 SCI_IN(sci_size, sci_offset); \
330 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
332 SCI_OUT(sci_size, sci_offset, value); \
335 #ifdef CONFIG_CPU_SH3
336 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
337 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
338 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
339 h8_sci_offset, h8_sci_size) \
340 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
341 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
342 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
343 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
344 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
345 defined(CONFIG_CPU_SUBTYPE_SH7721)
346 #define SCIF_FNS(name, scif_offset, scif_size) \
347 CPU_SCIF_FNS(name, scif_offset, scif_size)
349 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
350 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
351 h8_sci_offset, h8_sci_size) \
352 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
353 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
354 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
356 #elif defined(__H8300H__) || defined(__H8300S__)
357 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
358 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
359 h8_sci_offset, h8_sci_size) \
360 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
361 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
362 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
363 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
364 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
365 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
366 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
368 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
369 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
370 h8_sci_offset, h8_sci_size) \
371 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
372 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
373 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
376 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
377 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
378 defined(CONFIG_CPU_SUBTYPE_SH7721)
380 SCIF_FNS(SCSMR, 0x00, 16)
381 SCIF_FNS(SCBRR, 0x04, 8)
382 SCIF_FNS(SCSCR, 0x08, 16)
383 SCIF_FNS(SCTDSR, 0x0c, 8)
384 SCIF_FNS(SCFER, 0x10, 16)
385 SCIF_FNS(SCxSR, 0x14, 16)
386 SCIF_FNS(SCFCR, 0x18, 16)
387 SCIF_FNS(SCFDR, 0x1c, 16)
388 SCIF_FNS(SCxTDR, 0x20, 8)
389 SCIF_FNS(SCxRDR, 0x24, 8)
390 SCIF_FNS(SCLSR, 0x24, 16)
391 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
392 SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
393 SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
394 SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
395 SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
396 SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
397 SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
398 SCIF_FNS(SCTDSR, 0x0c, 8)
399 SCIF_FNS(SCFER, 0x10, 16)
400 SCIF_FNS(SCFCR, 0x18, 16)
401 SCIF_FNS(SCFDR, 0x1c, 16)
402 SCIF_FNS(SCLSR, 0x24, 16)
404 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
405 /* name off sz off sz off sz off sz off sz*/
406 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
407 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
408 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
409 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
410 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
411 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
412 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
413 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
414 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
415 defined(CONFIG_CPU_SUBTYPE_SH7785)
416 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
417 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
418 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
419 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
420 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
421 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
422 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
423 SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
424 SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
425 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
426 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
427 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
428 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
430 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
431 #if defined(CONFIG_CPU_SUBTYPE_SH7722)
432 SCIF_FNS(SCSPTR, 0, 0, 0, 0)
434 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
436 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
439 #define sci_in(port, reg) sci_##reg##_in(port)
440 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
442 /* H8/300 series SCI pins assignment */
443 #if defined(__H8300H__) || defined(__H8300S__)
444 static const struct __attribute__((packed)) {
445 int port; /* GPIO port no */
446 unsigned short rx,tx; /* GPIO bit no */
447 } h8300_sci_pins[] = {
448 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
450 .port = H8300_GPIO_P9,
455 .port = H8300_GPIO_P9,
460 .port = H8300_GPIO_PB,
464 #elif defined(CONFIG_H8S2678)
466 .port = H8300_GPIO_P3,
471 .port = H8300_GPIO_P3,
476 .port = H8300_GPIO_P5,
484 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
485 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
486 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
487 defined(CONFIG_CPU_SUBTYPE_SH7709)
488 static inline int sci_rxd_in(struct uart_port *port)
490 if (port->mapbase == 0xfffffe80)
491 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
492 if (port->mapbase == 0xa4000150)
493 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
494 if (port->mapbase == 0xa4000140)
495 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
498 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
499 static inline int sci_rxd_in(struct uart_port *port)
501 if (port->mapbase == SCIF0)
502 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
503 if (port->mapbase == SCIF2)
504 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
507 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
508 static inline int sci_rxd_in(struct uart_port *port)
510 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
512 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
513 defined(CONFIG_CPU_SUBTYPE_SH7721)
514 static inline int sci_rxd_in(struct uart_port *port)
516 if (port->mapbase == 0xa4430000)
517 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
518 else if (port->mapbase == 0xa4438000)
519 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
522 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
523 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
524 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
525 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
526 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
527 defined(CONFIG_CPU_SUBTYPE_SH7091)
528 static inline int sci_rxd_in(struct uart_port *port)
530 if (port->mapbase == 0xffe00000)
531 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
532 if (port->mapbase == 0xffe80000)
533 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
536 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
537 static inline int sci_rxd_in(struct uart_port *port)
539 if (port->mapbase == 0xffe80000)
540 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
543 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
544 static inline int sci_rxd_in(struct uart_port *port)
546 if (port->mapbase == 0xfe600000)
547 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
548 if (port->mapbase == 0xfe610000)
549 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
550 if (port->mapbase == 0xfe620000)
551 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
554 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
555 static inline int sci_rxd_in(struct uart_port *port)
557 if (port->mapbase == 0xffe00000)
558 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
559 if (port->mapbase == 0xffe10000)
560 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
561 if (port->mapbase == 0xffe20000)
562 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
563 if (port->mapbase == 0xffe30000)
564 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
567 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
568 static inline int sci_rxd_in(struct uart_port *port)
570 if (port->mapbase == 0xffe00000)
571 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
574 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
575 static inline int sci_rxd_in(struct uart_port *port)
577 if (port->mapbase == 0xffe00000)
578 return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
579 if (port->mapbase == 0xffe10000)
580 return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
581 if (port->mapbase == 0xffe20000)
582 return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
586 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
587 static inline int sci_rxd_in(struct uart_port *port)
589 if (port->mapbase == 0xffe00000)
590 return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
591 if (port->mapbase == 0xffe10000)
592 return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
593 if (port->mapbase == 0xffe20000)
594 return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
595 if (port->mapbase == 0xa4e30000)
596 return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
597 if (port->mapbase == 0xa4e40000)
598 return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
599 if (port->mapbase == 0xa4e50000)
600 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
603 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
604 static inline int sci_rxd_in(struct uart_port *port)
606 return sci_in(port, SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
608 #elif defined(__H8300H__) || defined(__H8300S__)
609 static inline int sci_rxd_in(struct uart_port *port)
611 int ch = (port->mapbase - SMR0) >> 3;
612 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
614 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
615 static inline int sci_rxd_in(struct uart_port *port)
617 if (port->mapbase == 0xffe00000)
618 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
619 if (port->mapbase == 0xffe08000)
620 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
621 if (port->mapbase == 0xffe10000)
622 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */
626 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
627 static inline int sci_rxd_in(struct uart_port *port)
629 if (port->mapbase == 0xff923000)
630 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
631 if (port->mapbase == 0xff924000)
632 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
633 if (port->mapbase == 0xff925000)
634 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
637 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
638 static inline int sci_rxd_in(struct uart_port *port)
640 if (port->mapbase == 0xffe00000)
641 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
642 if (port->mapbase == 0xffe10000)
643 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
646 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
647 static inline int sci_rxd_in(struct uart_port *port)
649 if (port->mapbase == 0xffea0000)
650 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
651 if (port->mapbase == 0xffeb0000)
652 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
653 if (port->mapbase == 0xffec0000)
654 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
655 if (port->mapbase == 0xffed0000)
656 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
657 if (port->mapbase == 0xffee0000)
658 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
659 if (port->mapbase == 0xffef0000)
660 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
663 #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
664 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
665 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
666 defined(CONFIG_CPU_SUBTYPE_SH7263)
667 static inline int sci_rxd_in(struct uart_port *port)
669 if (port->mapbase == 0xfffe8000)
670 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
671 if (port->mapbase == 0xfffe8800)
672 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
673 if (port->mapbase == 0xfffe9000)
674 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
675 if (port->mapbase == 0xfffe9800)
676 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
677 #if defined(CONFIG_CPU_SUBTYPE_SH7201)
678 if (port->mapbase == 0xfffeA000)
679 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
680 if (port->mapbase == 0xfffeA800)
681 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
682 if (port->mapbase == 0xfffeB000)
683 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
684 if (port->mapbase == 0xfffeB800)
685 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
689 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
690 static inline int sci_rxd_in(struct uart_port *port)
692 if (port->mapbase == 0xf8400000)
693 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
694 if (port->mapbase == 0xf8410000)
695 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
696 if (port->mapbase == 0xf8420000)
697 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
700 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
701 static inline int sci_rxd_in(struct uart_port *port)
703 if (port->mapbase == 0xffc30000)
704 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
705 if (port->mapbase == 0xffc40000)
706 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
707 if (port->mapbase == 0xffc50000)
708 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
709 if (port->mapbase == 0xffc60000)
710 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
716 * Values for the BitRate Register (SCBRR)
718 * The values are actually divisors for a frequency which can
719 * be internal to the SH3 (14.7456MHz) or derived from an external
720 * clock source. This driver assumes the internal clock is used;
721 * to support using an external clock source, config options or
722 * possibly command-line options would need to be added.
724 * Also, to support speeds below 2400 (why?) the lower 2 bits of
725 * the SCSMR register would also need to be set to non-zero values.
727 * -- Greg Banks 27Feb2000
729 * Answer: The SCBRR register is only eight bits, and the value in
730 * it gets larger with lower baud rates. At around 2400 (depending on
731 * the peripherial module clock) you run out of bits. However the
732 * lower two bits of SCSMR allow the module clock to be divided down,
733 * scaling the value which is needed in SCBRR.
735 * -- Stuart Menefy - 23 May 2000
737 * I meant, why would anyone bother with bitrates below 2400.
739 * -- Greg Banks - 7Jul2000
741 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
742 * tape reader as a console!
744 * -- Mitch Davis - 15 Jul 2000
747 #if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
748 defined(CONFIG_CPU_SUBTYPE_SH7785)
749 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
750 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
751 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
752 defined(CONFIG_CPU_SUBTYPE_SH7721)
753 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
754 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
755 static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
757 if (port->type == PORT_SCIF)
758 return (clk+16*bps)/(32*bps)-1;
760 return ((clk*2)+16*bps)/(16*bps)-1;
762 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
763 #elif defined(__H8300H__) || defined(__H8300S__)
764 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
765 #else /* Generic SH */
766 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)