Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
[linux-2.6] / drivers / mtd / nand / atmel_nand.c
1 /*
2  *  Copyright (C) 2003 Rick Bronson
3  *
4  *  Derived from drivers/mtd/nand/autcpu12.c
5  *       Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
6  *
7  *  Derived from drivers/mtd/spia.c
8  *       Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
9  *
10  *
11  *  Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12  *     Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
13  *
14  *     Derived from Das U-Boot source code
15  *              (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16  *     (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
17  *
18  *
19  * This program is free software; you can redistribute it and/or modify
20  * it under the terms of the GNU General Public License version 2 as
21  * published by the Free Software Foundation.
22  *
23  */
24
25 #include <linux/slab.h>
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/nand.h>
30 #include <linux/mtd/partitions.h>
31
32 #include <linux/gpio.h>
33 #include <linux/io.h>
34
35 #include <mach/board.h>
36 #include <mach/cpu.h>
37
38 #ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
39 #define hard_ecc        1
40 #else
41 #define hard_ecc        0
42 #endif
43
44 #ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE
45 #define no_ecc          1
46 #else
47 #define no_ecc          0
48 #endif
49
50 /* Register access macros */
51 #define ecc_readl(add, reg)                             \
52         __raw_readl(add + ATMEL_ECC_##reg)
53 #define ecc_writel(add, reg, value)                     \
54         __raw_writel((value), add + ATMEL_ECC_##reg)
55
56 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
57
58 /* oob layout for large page size
59  * bad block info is on bytes 0 and 1
60  * the bytes have to be consecutives to avoid
61  * several NAND_CMD_RNDOUT during read
62  */
63 static struct nand_ecclayout atmel_oobinfo_large = {
64         .eccbytes = 4,
65         .eccpos = {60, 61, 62, 63},
66         .oobfree = {
67                 {2, 58}
68         },
69 };
70
71 /* oob layout for small page size
72  * bad block info is on bytes 4 and 5
73  * the bytes have to be consecutives to avoid
74  * several NAND_CMD_RNDOUT during read
75  */
76 static struct nand_ecclayout atmel_oobinfo_small = {
77         .eccbytes = 4,
78         .eccpos = {0, 1, 2, 3},
79         .oobfree = {
80                 {6, 10}
81         },
82 };
83
84 struct atmel_nand_host {
85         struct nand_chip        nand_chip;
86         struct mtd_info         mtd;
87         void __iomem            *io_base;
88         struct atmel_nand_data  *board;
89         struct device           *dev;
90         void __iomem            *ecc;
91 };
92
93 /*
94  * Enable NAND.
95  */
96 static void atmel_nand_enable(struct atmel_nand_host *host)
97 {
98         if (host->board->enable_pin)
99                 gpio_set_value(host->board->enable_pin, 0);
100 }
101
102 /*
103  * Disable NAND.
104  */
105 static void atmel_nand_disable(struct atmel_nand_host *host)
106 {
107         if (host->board->enable_pin)
108                 gpio_set_value(host->board->enable_pin, 1);
109 }
110
111 /*
112  * Hardware specific access to control-lines
113  */
114 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
115 {
116         struct nand_chip *nand_chip = mtd->priv;
117         struct atmel_nand_host *host = nand_chip->priv;
118
119         if (ctrl & NAND_CTRL_CHANGE) {
120                 if (ctrl & NAND_NCE)
121                         atmel_nand_enable(host);
122                 else
123                         atmel_nand_disable(host);
124         }
125         if (cmd == NAND_CMD_NONE)
126                 return;
127
128         if (ctrl & NAND_CLE)
129                 writeb(cmd, host->io_base + (1 << host->board->cle));
130         else
131                 writeb(cmd, host->io_base + (1 << host->board->ale));
132 }
133
134 /*
135  * Read the Device Ready pin.
136  */
137 static int atmel_nand_device_ready(struct mtd_info *mtd)
138 {
139         struct nand_chip *nand_chip = mtd->priv;
140         struct atmel_nand_host *host = nand_chip->priv;
141
142         return gpio_get_value(host->board->rdy_pin);
143 }
144
145 /*
146  * Minimal-overhead PIO for data access.
147  */
148 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
149 {
150         struct nand_chip        *nand_chip = mtd->priv;
151
152         __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
153 }
154
155 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
156 {
157         struct nand_chip        *nand_chip = mtd->priv;
158
159         __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
160 }
161
162 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
163 {
164         struct nand_chip        *nand_chip = mtd->priv;
165
166         __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
167 }
168
169 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
170 {
171         struct nand_chip        *nand_chip = mtd->priv;
172
173         __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
174 }
175
176 /*
177  * Calculate HW ECC
178  *
179  * function called after a write
180  *
181  * mtd:        MTD block structure
182  * dat:        raw data (unused)
183  * ecc_code:   buffer for ECC
184  */
185 static int atmel_nand_calculate(struct mtd_info *mtd,
186                 const u_char *dat, unsigned char *ecc_code)
187 {
188         struct nand_chip *nand_chip = mtd->priv;
189         struct atmel_nand_host *host = nand_chip->priv;
190         uint32_t *eccpos = nand_chip->ecc.layout->eccpos;
191         unsigned int ecc_value;
192
193         /* get the first 2 ECC bytes */
194         ecc_value = ecc_readl(host->ecc, PR);
195
196         ecc_code[0] = ecc_value & 0xFF;
197         ecc_code[1] = (ecc_value >> 8) & 0xFF;
198
199         /* get the last 2 ECC bytes */
200         ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
201
202         ecc_code[2] = ecc_value & 0xFF;
203         ecc_code[3] = (ecc_value >> 8) & 0xFF;
204
205         return 0;
206 }
207
208 /*
209  * HW ECC read page function
210  *
211  * mtd:        mtd info structure
212  * chip:       nand chip info structure
213  * buf:        buffer to store read data
214  */
215 static int atmel_nand_read_page(struct mtd_info *mtd,
216                 struct nand_chip *chip, uint8_t *buf)
217 {
218         int eccsize = chip->ecc.size;
219         int eccbytes = chip->ecc.bytes;
220         uint32_t *eccpos = chip->ecc.layout->eccpos;
221         uint8_t *p = buf;
222         uint8_t *oob = chip->oob_poi;
223         uint8_t *ecc_pos;
224         int stat;
225
226         /*
227          * Errata: ALE is incorrectly wired up to the ECC controller
228          * on the AP7000, so it will include the address cycles in the
229          * ECC calculation.
230          *
231          * Workaround: Reset the parity registers before reading the
232          * actual data.
233          */
234         if (cpu_is_at32ap7000()) {
235                 struct atmel_nand_host *host = chip->priv;
236                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
237         }
238
239         /* read the page */
240         chip->read_buf(mtd, p, eccsize);
241
242         /* move to ECC position if needed */
243         if (eccpos[0] != 0) {
244                 /* This only works on large pages
245                  * because the ECC controller waits for
246                  * NAND_CMD_RNDOUTSTART after the
247                  * NAND_CMD_RNDOUT.
248                  * anyway, for small pages, the eccpos[0] == 0
249                  */
250                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
251                                 mtd->writesize + eccpos[0], -1);
252         }
253
254         /* the ECC controller needs to read the ECC just after the data */
255         ecc_pos = oob + eccpos[0];
256         chip->read_buf(mtd, ecc_pos, eccbytes);
257
258         /* check if there's an error */
259         stat = chip->ecc.correct(mtd, p, oob, NULL);
260
261         if (stat < 0)
262                 mtd->ecc_stats.failed++;
263         else
264                 mtd->ecc_stats.corrected += stat;
265
266         /* get back to oob start (end of page) */
267         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
268
269         /* read the oob */
270         chip->read_buf(mtd, oob, mtd->oobsize);
271
272         return 0;
273 }
274
275 /*
276  * HW ECC Correction
277  *
278  * function called after a read
279  *
280  * mtd:        MTD block structure
281  * dat:        raw data read from the chip
282  * read_ecc:   ECC from the chip (unused)
283  * isnull:     unused
284  *
285  * Detect and correct a 1 bit error for a page
286  */
287 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
288                 u_char *read_ecc, u_char *isnull)
289 {
290         struct nand_chip *nand_chip = mtd->priv;
291         struct atmel_nand_host *host = nand_chip->priv;
292         unsigned int ecc_status;
293         unsigned int ecc_word, ecc_bit;
294
295         /* get the status from the Status Register */
296         ecc_status = ecc_readl(host->ecc, SR);
297
298         /* if there's no error */
299         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
300                 return 0;
301
302         /* get error bit offset (4 bits) */
303         ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
304         /* get word address (12 bits) */
305         ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
306         ecc_word >>= 4;
307
308         /* if there are multiple errors */
309         if (ecc_status & ATMEL_ECC_MULERR) {
310                 /* check if it is a freshly erased block
311                  * (filled with 0xff) */
312                 if ((ecc_bit == ATMEL_ECC_BITADDR)
313                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
314                         /* the block has just been erased, return OK */
315                         return 0;
316                 }
317                 /* it doesn't seems to be a freshly
318                  * erased block.
319                  * We can't correct so many errors */
320                 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
321                                 " Unable to correct.\n");
322                 return -EIO;
323         }
324
325         /* if there's a single bit error : we can correct it */
326         if (ecc_status & ATMEL_ECC_ECCERR) {
327                 /* there's nothing much to do here.
328                  * the bit error is on the ECC itself.
329                  */
330                 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
331                                 " Nothing to correct\n");
332                 return 0;
333         }
334
335         dev_dbg(host->dev, "atmel_nand : one bit error on data."
336                         " (word offset in the page :"
337                         " 0x%x bit offset : 0x%x)\n",
338                         ecc_word, ecc_bit);
339         /* correct the error */
340         if (nand_chip->options & NAND_BUSWIDTH_16) {
341                 /* 16 bits words */
342                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
343         } else {
344                 /* 8 bits words */
345                 dat[ecc_word] ^= (1 << ecc_bit);
346         }
347         dev_dbg(host->dev, "atmel_nand : error corrected\n");
348         return 1;
349 }
350
351 /*
352  * Enable HW ECC : unused on most chips
353  */
354 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
355 {
356         if (cpu_is_at32ap7000()) {
357                 struct nand_chip *nand_chip = mtd->priv;
358                 struct atmel_nand_host *host = nand_chip->priv;
359                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
360         }
361 }
362
363 #ifdef CONFIG_MTD_PARTITIONS
364 static const char *part_probes[] = { "cmdlinepart", NULL };
365 #endif
366
367 /*
368  * Probe for the NAND device.
369  */
370 static int __init atmel_nand_probe(struct platform_device *pdev)
371 {
372         struct atmel_nand_host *host;
373         struct mtd_info *mtd;
374         struct nand_chip *nand_chip;
375         struct resource *regs;
376         struct resource *mem;
377         int res;
378
379 #ifdef CONFIG_MTD_PARTITIONS
380         struct mtd_partition *partitions = NULL;
381         int num_partitions = 0;
382 #endif
383
384         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
385         if (!mem) {
386                 printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
387                 return -ENXIO;
388         }
389
390         /* Allocate memory for the device structure (and zero it) */
391         host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
392         if (!host) {
393                 printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
394                 return -ENOMEM;
395         }
396
397         host->io_base = ioremap(mem->start, mem->end - mem->start + 1);
398         if (host->io_base == NULL) {
399                 printk(KERN_ERR "atmel_nand: ioremap failed\n");
400                 res = -EIO;
401                 goto err_nand_ioremap;
402         }
403
404         mtd = &host->mtd;
405         nand_chip = &host->nand_chip;
406         host->board = pdev->dev.platform_data;
407         host->dev = &pdev->dev;
408
409         nand_chip->priv = host;         /* link the private data structures */
410         mtd->priv = nand_chip;
411         mtd->owner = THIS_MODULE;
412
413         /* Set address of NAND IO lines */
414         nand_chip->IO_ADDR_R = host->io_base;
415         nand_chip->IO_ADDR_W = host->io_base;
416         nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
417
418         if (host->board->rdy_pin)
419                 nand_chip->dev_ready = atmel_nand_device_ready;
420
421         regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
422         if (!regs && hard_ecc) {
423                 printk(KERN_ERR "atmel_nand: can't get I/O resource "
424                                 "regs\nFalling back on software ECC\n");
425         }
426
427         nand_chip->ecc.mode = NAND_ECC_SOFT;    /* enable ECC */
428         if (no_ecc)
429                 nand_chip->ecc.mode = NAND_ECC_NONE;
430         if (hard_ecc && regs) {
431                 host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
432                 if (host->ecc == NULL) {
433                         printk(KERN_ERR "atmel_nand: ioremap failed\n");
434                         res = -EIO;
435                         goto err_ecc_ioremap;
436                 }
437                 nand_chip->ecc.mode = NAND_ECC_HW;
438                 nand_chip->ecc.calculate = atmel_nand_calculate;
439                 nand_chip->ecc.correct = atmel_nand_correct;
440                 nand_chip->ecc.hwctl = atmel_nand_hwctl;
441                 nand_chip->ecc.read_page = atmel_nand_read_page;
442                 nand_chip->ecc.bytes = 4;
443         }
444
445         nand_chip->chip_delay = 20;             /* 20us command delay time */
446
447         if (host->board->bus_width_16) {        /* 16-bit bus width */
448                 nand_chip->options |= NAND_BUSWIDTH_16;
449                 nand_chip->read_buf = atmel_read_buf16;
450                 nand_chip->write_buf = atmel_write_buf16;
451         } else {
452                 nand_chip->read_buf = atmel_read_buf;
453                 nand_chip->write_buf = atmel_write_buf;
454         }
455
456         platform_set_drvdata(pdev, host);
457         atmel_nand_enable(host);
458
459         if (host->board->det_pin) {
460                 if (gpio_get_value(host->board->det_pin)) {
461                         printk("No SmartMedia card inserted.\n");
462                         res = ENXIO;
463                         goto err_no_card;
464                 }
465         }
466
467         /* first scan to find the device and get the page size */
468         if (nand_scan_ident(mtd, 1)) {
469                 res = -ENXIO;
470                 goto err_scan_ident;
471         }
472
473         if (nand_chip->ecc.mode == NAND_ECC_HW) {
474                 /* ECC is calculated for the whole page (1 step) */
475                 nand_chip->ecc.size = mtd->writesize;
476
477                 /* set ECC page size and oob layout */
478                 switch (mtd->writesize) {
479                 case 512:
480                         nand_chip->ecc.layout = &atmel_oobinfo_small;
481                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
482                         break;
483                 case 1024:
484                         nand_chip->ecc.layout = &atmel_oobinfo_large;
485                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
486                         break;
487                 case 2048:
488                         nand_chip->ecc.layout = &atmel_oobinfo_large;
489                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
490                         break;
491                 case 4096:
492                         nand_chip->ecc.layout = &atmel_oobinfo_large;
493                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
494                         break;
495                 default:
496                         /* page size not handled by HW ECC */
497                         /* switching back to soft ECC */
498                         nand_chip->ecc.mode = NAND_ECC_SOFT;
499                         nand_chip->ecc.calculate = NULL;
500                         nand_chip->ecc.correct = NULL;
501                         nand_chip->ecc.hwctl = NULL;
502                         nand_chip->ecc.read_page = NULL;
503                         nand_chip->ecc.postpad = 0;
504                         nand_chip->ecc.prepad = 0;
505                         nand_chip->ecc.bytes = 0;
506                         break;
507                 }
508         }
509
510         /* second phase scan */
511         if (nand_scan_tail(mtd)) {
512                 res = -ENXIO;
513                 goto err_scan_tail;
514         }
515
516 #ifdef CONFIG_MTD_PARTITIONS
517 #ifdef CONFIG_MTD_CMDLINE_PARTS
518         mtd->name = "atmel_nand";
519         num_partitions = parse_mtd_partitions(mtd, part_probes,
520                                               &partitions, 0);
521 #endif
522         if (num_partitions <= 0 && host->board->partition_info)
523                 partitions = host->board->partition_info(mtd->size,
524                                                          &num_partitions);
525
526         if ((!partitions) || (num_partitions == 0)) {
527                 printk(KERN_ERR "atmel_nand: No parititions defined, or unsupported device.\n");
528                 res = ENXIO;
529                 goto err_no_partitions;
530         }
531
532         res = add_mtd_partitions(mtd, partitions, num_partitions);
533 #else
534         res = add_mtd_device(mtd);
535 #endif
536
537         if (!res)
538                 return res;
539
540 #ifdef CONFIG_MTD_PARTITIONS
541 err_no_partitions:
542 #endif
543         nand_release(mtd);
544 err_scan_tail:
545 err_scan_ident:
546 err_no_card:
547         atmel_nand_disable(host);
548         platform_set_drvdata(pdev, NULL);
549         if (host->ecc)
550                 iounmap(host->ecc);
551 err_ecc_ioremap:
552         iounmap(host->io_base);
553 err_nand_ioremap:
554         kfree(host);
555         return res;
556 }
557
558 /*
559  * Remove a NAND device.
560  */
561 static int __exit atmel_nand_remove(struct platform_device *pdev)
562 {
563         struct atmel_nand_host *host = platform_get_drvdata(pdev);
564         struct mtd_info *mtd = &host->mtd;
565
566         nand_release(mtd);
567
568         atmel_nand_disable(host);
569
570         if (host->ecc)
571                 iounmap(host->ecc);
572         iounmap(host->io_base);
573         kfree(host);
574
575         return 0;
576 }
577
578 static struct platform_driver atmel_nand_driver = {
579         .remove         = __exit_p(atmel_nand_remove),
580         .driver         = {
581                 .name   = "atmel_nand",
582                 .owner  = THIS_MODULE,
583         },
584 };
585
586 static int __init atmel_nand_init(void)
587 {
588         return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe);
589 }
590
591
592 static void __exit atmel_nand_exit(void)
593 {
594         platform_driver_unregister(&atmel_nand_driver);
595 }
596
597
598 module_init(atmel_nand_init);
599 module_exit(atmel_nand_exit);
600
601 MODULE_LICENSE("GPL");
602 MODULE_AUTHOR("Rick Bronson");
603 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
604 MODULE_ALIAS("platform:atmel_nand");