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   1 /* pci_fire.c: Sun4u platform PCI-E controller support.
   2  *
   3  * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
   4  */
   5 #include <linux/kernel.h>
   6 #include <linux/pci.h>
   7 #include <linux/slab.h>
   8 #include <linux/init.h>
   9
  10 #include <asm/oplib.h>
  11 #include <asm/prom.h>
  12
  13 #include "pci_impl.h"
  14
  15 #define fire_read(__reg) \
  16 ({      u64 __ret; \
  17         __asm__ __volatile__("ldxa [%1] %2, %0" \
  18                              : "=r" (__ret) \
  19                              : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
  20                              : "memory"); \
  21         __ret; \
  22 })
  23 #define fire_write(__reg, __val) \
  24         __asm__ __volatile__("stxa %0, [%1] %2" \
  25                              : /* no outputs */ \
  26                              : "r" (__val), "r" (__reg), \
  27                                "i" (ASI_PHYS_BYPASS_EC_E) \
  28                              : "memory")
  29
  30 static void pci_fire_scan_bus(struct pci_pbm_info *pbm)
  31 {
  32         pbm->pci_bus = pci_scan_one_pbm(pbm);
  33
  34         /* XXX register error interrupt handlers XXX */
  35 }
  36
  37 #define FIRE_IOMMU_CONTROL      0x40000UL
  38 #define FIRE_IOMMU_TSBBASE      0x40008UL
  39 #define FIRE_IOMMU_FLUSH        0x40100UL
  40 #define FIRE_IOMMU_FLUSHINV     0x40108UL
  41
  42 static void pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
  43 {
  44         struct iommu *iommu = pbm->iommu;
  45         u32 vdma[2], dma_mask;
  46         u64 control;
  47         int tsbsize;
  48
  49         /* No virtual-dma property on these guys, use largest size.  */
  50         vdma[0] = 0xc0000000; /* base */
  51         vdma[1] = 0x40000000; /* size */
  52         dma_mask = 0xffffffff;
  53         tsbsize = 128;
  54
  55         /* Register addresses. */
  56         iommu->iommu_control  = pbm->pbm_regs + FIRE_IOMMU_CONTROL;
  57         iommu->iommu_tsbbase  = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;
  58         iommu->iommu_flush    = pbm->pbm_regs + FIRE_IOMMU_FLUSH;
  59         iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;
  60
  61         /* We use the main control/status register of FIRE as the write
  62          * completion register.
  63          */
  64         iommu->write_complete_reg = pbm->controller_regs + 0x410000UL;
  65
  66         /*
  67          * Invalidate TLB Entries.
  68          */
  69         fire_write(iommu->iommu_flushinv, ~(u64)0);
  70
  71         pci_iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask);
  72
  73         fire_write(iommu->iommu_tsbbase, __pa(iommu->page_table) | 0x7UL);
  74
  75         control = fire_read(iommu->iommu_control);
  76         control |= (0x00000400 /* TSB cache snoop enable */     |
  77                     0x00000300 /* Cache mode */                 |
  78                     0x00000002 /* Bypass enable */              |
  79                     0x00000001 /* Translation enable */);
  80         fire_write(iommu->iommu_control, control);
  81 }
  82
  83 /* Based at pbm->controller_regs */
  84 #define FIRE_PARITY_CONTROL     0x470010UL
  85 #define  FIRE_PARITY_ENAB       0x8000000000000000UL
  86 #define FIRE_FATAL_RESET_CTL    0x471028UL
  87 #define  FIRE_FATAL_RESET_SPARE 0x0000000004000000UL
  88 #define  FIRE_FATAL_RESET_MB    0x0000000002000000UL
  89 #define  FIRE_FATAL_RESET_CPE   0x0000000000008000UL
  90 #define  FIRE_FATAL_RESET_APE   0x0000000000004000UL
  91 #define  FIRE_FATAL_RESET_PIO   0x0000000000000040UL
  92 #define  FIRE_FATAL_RESET_JW    0x0000000000000004UL
  93 #define  FIRE_FATAL_RESET_JI    0x0000000000000002UL
  94 #define  FIRE_FATAL_RESET_JR    0x0000000000000001UL
  95 #define FIRE_CORE_INTR_ENABLE   0x471800UL
  96
  97 /* Based at pbm->pbm_regs */
  98 #define FIRE_TLU_CTRL           0x80000UL
  99 #define  FIRE_TLU_CTRL_TIM      0x00000000da000000UL
 100 #define  FIRE_TLU_CTRL_QDET     0x0000000000000100UL
 101 #define  FIRE_TLU_CTRL_CFG      0x0000000000000001UL
 102 #define FIRE_TLU_DEV_CTRL       0x90008UL
 103 #define FIRE_TLU_LINK_CTRL      0x90020UL
 104 #define FIRE_TLU_LINK_CTRL_CLK  0x0000000000000040UL
 105 #define FIRE_LPU_RESET          0xe2008UL
 106 #define FIRE_LPU_LLCFG          0xe2200UL
 107 #define  FIRE_LPU_LLCFG_VC0     0x0000000000000100UL
 108 #define FIRE_LPU_FCTRL_UCTRL    0xe2240UL
 109 #define  FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL
 110 #define  FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL
 111 #define FIRE_LPU_TXL_FIFOP      0xe2430UL
 112 #define FIRE_LPU_LTSSM_CFG2     0xe2788UL
 113 #define FIRE_LPU_LTSSM_CFG3     0xe2790UL
 114 #define FIRE_LPU_LTSSM_CFG4     0xe2798UL
 115 #define FIRE_LPU_LTSSM_CFG5     0xe27a0UL
 116 #define FIRE_DMC_IENAB          0x31800UL
 117 #define FIRE_DMC_DBG_SEL_A      0x53000UL
 118 #define FIRE_DMC_DBG_SEL_B      0x53008UL
 119 #define FIRE_PEC_IENAB          0x51800UL
 120
 121 static void pci_fire_hw_init(struct pci_pbm_info *pbm)
 122 {
 123         u64 val;
 124
 125         fire_write(pbm->controller_regs + FIRE_PARITY_CONTROL,
 126                    FIRE_PARITY_ENAB);
 127
 128         fire_write(pbm->controller_regs + FIRE_FATAL_RESET_CTL,
 129                    (FIRE_FATAL_RESET_SPARE |
 130                     FIRE_FATAL_RESET_MB |
 131                     FIRE_FATAL_RESET_CPE |
 132                     FIRE_FATAL_RESET_APE |
 133                     FIRE_FATAL_RESET_PIO |
 134                     FIRE_FATAL_RESET_JW |
 135                     FIRE_FATAL_RESET_JI |
 136                     FIRE_FATAL_RESET_JR));
 137
 138         fire_write(pbm->controller_regs + FIRE_CORE_INTR_ENABLE, ~(u64)0);
 139
 140         val = fire_read(pbm->pbm_regs + FIRE_TLU_CTRL);
 141         val |= (FIRE_TLU_CTRL_TIM |
 142                 FIRE_TLU_CTRL_QDET |
 143                 FIRE_TLU_CTRL_CFG);
 144         fire_write(pbm->pbm_regs + FIRE_TLU_CTRL, val);
 145         fire_write(pbm->pbm_regs + FIRE_TLU_DEV_CTRL, 0);
 146         fire_write(pbm->pbm_regs + FIRE_TLU_LINK_CTRL,
 147                    FIRE_TLU_LINK_CTRL_CLK);
 148
 149         fire_write(pbm->pbm_regs + FIRE_LPU_RESET, 0);
 150         fire_write(pbm->pbm_regs + FIRE_LPU_LLCFG,
 151                    FIRE_LPU_LLCFG_VC0);
 152         fire_write(pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL,
 153                    (FIRE_LPU_FCTRL_UCTRL_N |
 154                     FIRE_LPU_FCTRL_UCTRL_P));
 155         fire_write(pbm->pbm_regs + FIRE_LPU_TXL_FIFOP,
 156                    ((0xffff << 16) | (0x0000 << 0)));
 157         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2, 3000000);
 158         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3, 500000);
 159         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4,
 160                    (2 << 16) | (140 << 8));
 161         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5, 0);
 162
 163         fire_write(pbm->pbm_regs + FIRE_DMC_IENAB, ~(u64)0);
 164         fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_A, 0);
 165         fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_B, 0);
 166
 167         fire_write(pbm->pbm_regs + FIRE_PEC_IENAB, ~(u64)0);
 168 }
 169
 170 static void pci_fire_pbm_init(struct pci_controller_info *p,
 171                               struct device_node *dp, u32 portid)
 172 {
 173         const struct linux_prom64_registers *regs;
 174         struct pci_pbm_info *pbm;
 175
 176         if ((portid & 1) == 0)
 177                 pbm = &p->pbm_A;
 178         else
 179                 pbm = &p->pbm_B;
 180
 181         pbm->next = pci_pbm_root;
 182         pci_pbm_root = pbm;
 183
 184         pbm->scan_bus = pci_fire_scan_bus;
 185         pbm->pci_ops = &sun4u_pci_ops;
 186         pbm->config_space_reg_bits = 12;
 187
 188         pbm->index = pci_num_pbms++;
 189
 190         pbm->portid = portid;
 191         pbm->parent = p;
 192         pbm->prom_node = dp;
 193         pbm->name = dp->full_name;
 194
 195         regs = of_get_property(dp, "reg", NULL);
 196         pbm->pbm_regs = regs[0].phys_addr;
 197         pbm->controller_regs = regs[1].phys_addr - 0x410000UL;
 198
 199         printk("%s: SUN4U PCIE Bus Module\n", pbm->name);
 200
 201         pci_determine_mem_io_space(pbm);
 202
 203         pci_get_pbm_props(pbm);
 204
 205         pci_fire_hw_init(pbm);
 206         pci_fire_pbm_iommu_init(pbm);
 207 }
 208
 209 static inline int portid_compare(u32 x, u32 y)
 210 {
 211         if (x == (y ^ 1))
 212                 return 1;
 213         return 0;
 214 }
 215
 216 void fire_pci_init(struct device_node *dp, const char *model_name)
 217 {
 218         struct pci_controller_info *p;
 219         u32 portid = of_getintprop_default(dp, "portid", 0xff);
 220         struct iommu *iommu;
 221         struct pci_pbm_info *pbm;
 222
 223         for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
 224                 if (portid_compare(pbm->portid, portid)) {
 225                         pci_fire_pbm_init(pbm->parent, dp, portid);
 226                         return;
 227                 }
 228         }
 229
 230         p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
 231         if (!p)
 232                 goto fatal_memory_error;
 233
 234         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
 235         if (!iommu)
 236                 goto fatal_memory_error;
 237
 238         p->pbm_A.iommu = iommu;
 239
 240         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
 241         if (!iommu)
 242                 goto fatal_memory_error;
 243
 244         p->pbm_B.iommu = iommu;
 245
 246         /* XXX MSI support XXX */
 247
 248         /* Like PSYCHO and SCHIZO we have a 2GB aligned area
 249          * for memory space.
 250          */
 251         pci_memspace_mask = 0x7fffffffUL;
 252
 253         pci_fire_pbm_init(p, dp, portid);
 254         return;
 255
 256 fatal_memory_error:
 257         prom_printf("PCI_FIRE: Fatal memory allocation error.\n");
 258         prom_halt();
 259 }