2 * Contains the definition of registers common to all PowerPC variants.
3 * If a register definition has been changed in a different PowerPC
4 * variant, we will case it in #ifndef XXX ... #endif, and have the
5 * number used in the Programming Environments Manual For 32-Bit
6 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
9 #ifndef _ASM_POWERPC_REG_H
10 #define _ASM_POWERPC_REG_H
13 #include <linux/stringify.h>
14 #include <asm/cputable.h>
16 /* Pickup Book E specific registers. */
17 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
18 #include <asm/reg_booke.h>
19 #endif /* CONFIG_BOOKE || CONFIG_40x */
22 #include <asm/reg_8xx.h>
23 #endif /* CONFIG_8xx */
25 #define MSR_SF_LG 63 /* Enable 64 bit mode */
26 #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
27 #define MSR_HV_LG 60 /* Hypervisor state */
28 #define MSR_VEC_LG 25 /* Enable AltiVec */
29 #define MSR_POW_LG 18 /* Enable Power Management */
30 #define MSR_WE_LG 18 /* Wait State Enable */
31 #define MSR_TGPR_LG 17 /* TLB Update registers in use */
32 #define MSR_CE_LG 17 /* Critical Interrupt Enable */
33 #define MSR_ILE_LG 16 /* Interrupt Little Endian */
34 #define MSR_EE_LG 15 /* External Interrupt Enable */
35 #define MSR_PR_LG 14 /* Problem State / Privilege Level */
36 #define MSR_FP_LG 13 /* Floating Point enable */
37 #define MSR_ME_LG 12 /* Machine Check Enable */
38 #define MSR_FE0_LG 11 /* Floating Exception mode 0 */
39 #define MSR_SE_LG 10 /* Single Step */
40 #define MSR_BE_LG 9 /* Branch Trace */
41 #define MSR_DE_LG 9 /* Debug Exception Enable */
42 #define MSR_FE1_LG 8 /* Floating Exception mode 1 */
43 #define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */
44 #define MSR_IR_LG 5 /* Instruction Relocate */
45 #define MSR_DR_LG 4 /* Data Relocate */
46 #define MSR_PE_LG 3 /* Protection Enable */
47 #define MSR_PX_LG 2 /* Protection Exclusive Mode */
48 #define MSR_PMM_LG 2 /* Performance monitor */
49 #define MSR_RI_LG 1 /* Recoverable Exception */
50 #define MSR_LE_LG 0 /* Little Endian */
53 #define __MASK(X) (1<<(X))
55 #define __MASK(X) (1UL<<(X))
59 #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
60 #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
61 #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
63 /* so tests for these bits fail on 32-bit */
69 #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */
70 #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */
71 #define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */
72 #define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */
73 #define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */
74 #define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */
75 #define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */
76 #define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */
77 #define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */
78 #define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */
79 #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
80 #define MSR_SE __MASK(MSR_SE_LG) /* Single Step */
81 #define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */
82 #define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */
83 #define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */
84 #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
85 #define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */
86 #define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */
87 #define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */
88 #define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */
90 #define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */
92 #define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */
93 #define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
96 #define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV
97 #define MSR_KERNEL MSR_ | MSR_SF
99 #define MSR_USER32 MSR_ | MSR_PR | MSR_EE
100 #define MSR_USER64 MSR_USER32 | MSR_SF
103 /* Default MSR for kernel mode. */
104 #ifndef MSR_KERNEL /* reg_booke.h also defines this */
105 #ifdef CONFIG_APUS_FAST_EXCEPT
106 #define MSR_KERNEL (MSR_ME|MSR_IP|MSR_RI|MSR_IR|MSR_DR)
108 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
112 #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
115 /* Floating Point Status and Control Register (FPSCR) Fields */
116 #define FPSCR_FX 0x80000000 /* FPU exception summary */
117 #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
118 #define FPSCR_VX 0x20000000 /* Invalid operation summary */
119 #define FPSCR_OX 0x10000000 /* Overflow exception summary */
120 #define FPSCR_UX 0x08000000 /* Underflow exception summary */
121 #define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */
122 #define FPSCR_XX 0x02000000 /* Inexact exception summary */
123 #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
124 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
125 #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
126 #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
127 #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
128 #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
129 #define FPSCR_FR 0x00040000 /* Fraction rounded */
130 #define FPSCR_FI 0x00020000 /* Fraction inexact */
131 #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
132 #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
133 #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
134 #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
135 #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
136 #define FPSCR_VE 0x00000080 /* Invalid op exception enable */
137 #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
138 #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
139 #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
140 #define FPSCR_XE 0x00000008 /* FP inexact exception enable */
141 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
142 #define FPSCR_RN 0x00000003 /* FPU rounding control */
144 /* Special Purpose Registers (SPRNs)*/
145 #define SPRN_CTR 0x009 /* Count Register */
146 #define SPRN_DSCR 0x11
147 #define SPRN_CTRLF 0x088
148 #define SPRN_CTRLT 0x098
149 #define CTRL_CT 0xc0000000 /* current thread */
150 #define CTRL_CT0 0x80000000 /* thread 0 */
151 #define CTRL_CT1 0x40000000 /* thread 1 */
152 #define CTRL_TE 0x00c00000 /* thread enable */
153 #define CTRL_RUNLATCH 0x1
154 #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
155 #define DABR_TRANSLATION (1UL << 2)
156 #define SPRN_DAR 0x013 /* Data Address Register */
157 #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
158 #define DSISR_NOHPTE 0x40000000 /* no translation found */
159 #define DSISR_PROTFAULT 0x08000000 /* protection fault */
160 #define DSISR_ISSTORE 0x02000000 /* access was a store */
161 #define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */
162 #define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */
163 #define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */
164 #define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */
165 #define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */
166 #define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */
167 #define SPRN_SPURR 0x134 /* Scaled PURR */
168 #define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
169 #define SPRN_LPCR 0x13E /* LPAR Control Register */
170 #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
171 #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
172 #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
173 #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
174 #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
175 #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
176 #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
177 #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
178 #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
179 #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
180 #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
181 #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
182 #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
183 #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
184 #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
185 #define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */
187 #define SPRN_DEC 0x016 /* Decrement Register */
188 #define SPRN_DER 0x095 /* Debug Enable Regsiter */
189 #define DER_RSTE 0x40000000 /* Reset Interrupt */
190 #define DER_CHSTPE 0x20000000 /* Check Stop */
191 #define DER_MCIE 0x10000000 /* Machine Check Interrupt */
192 #define DER_EXTIE 0x02000000 /* External Interrupt */
193 #define DER_ALIE 0x01000000 /* Alignment Interrupt */
194 #define DER_PRIE 0x00800000 /* Program Interrupt */
195 #define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */
196 #define DER_DECIE 0x00200000 /* Decrementer Interrupt */
197 #define DER_SYSIE 0x00040000 /* System Call Interrupt */
198 #define DER_TRE 0x00020000 /* Trace Interrupt */
199 #define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */
200 #define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */
201 #define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */
202 #define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */
203 #define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */
204 #define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */
205 #define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */
206 #define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */
207 #define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */
208 #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
209 #define SPRN_EAR 0x11A /* External Address Register */
210 #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
211 #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
212 #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
213 #define HID0_EMCP (1<<31) /* Enable Machine Check pin */
214 #define HID0_EBA (1<<29) /* Enable Bus Address Parity */
215 #define HID0_EBD (1<<28) /* Enable Bus Data Parity */
216 #define HID0_SBCLK (1<<27)
217 #define HID0_EICE (1<<26)
218 #define HID0_TBEN (1<<26) /* Timebase enable - 745x */
219 #define HID0_ECLK (1<<25)
220 #define HID0_PAR (1<<24)
221 #define HID0_STEN (1<<24) /* Software table search enable - 745x */
222 #define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */
223 #define HID0_DOZE (1<<23)
224 #define HID0_NAP (1<<22)
225 #define HID0_SLEEP (1<<21)
226 #define HID0_DPM (1<<20)
227 #define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */
228 #define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */
229 #define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/
230 #define HID0_ICE (1<<15) /* Instruction Cache Enable */
231 #define HID0_DCE (1<<14) /* Data Cache Enable */
232 #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
233 #define HID0_DLOCK (1<<12) /* Data Cache Lock */
234 #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
235 #define HID0_DCI (1<<10) /* Data Cache Invalidate */
236 #define HID0_SPD (1<<9) /* Speculative disable */
237 #define HID0_DAPUEN (1<<8) /* Debug APU enable */
238 #define HID0_SGE (1<<7) /* Store Gathering Enable */
239 #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
240 #define HID0_DFCA (1<<6) /* Data Cache Flush Assist */
241 #define HID0_LRSTK (1<<4) /* Link register stack - 745x */
242 #define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */
243 #define HID0_ABE (1<<3) /* Address Broadcast Enable */
244 #define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */
245 #define HID0_BHTE (1<<2) /* Branch History Table Enable */
246 #define HID0_BTCD (1<<1) /* Branch target cache disable */
247 #define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */
248 #define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */
250 #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
251 #define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */
252 #define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */
253 #define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */
254 #define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */
255 #define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */
256 #define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */
257 #define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */
258 #define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */
259 #define HID1_PS (1<<16) /* 750FX PLL selection */
260 #define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */
261 #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
262 #define SPRN_HID4 0x3F4 /* 970 HID4 */
263 #define SPRN_HID5 0x3F6 /* 970 HID5 */
264 #define SPRN_HID6 0x3F9 /* BE HID 6 */
265 #define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */
266 #define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */
267 #define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */
268 #define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */
269 #define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */
270 #define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */
271 #define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */
272 #define SPRN_TSC 0x3FD /* Thread switch control on others */
273 #define SPRN_TST 0x3FC /* Thread switch timeout on others */
274 #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
275 #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
276 #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
278 #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
279 #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
280 #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
281 #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
282 #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
283 #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
284 #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
285 #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
286 #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
287 #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
288 #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
289 #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
290 #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
291 #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
292 #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
293 #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
294 #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
295 #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
296 #define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */
297 #define ICTRL_EICE 0x08000000 /* enable icache parity errs */
298 #define ICTRL_EDC 0x04000000 /* enable dcache parity errs */
299 #define ICTRL_EICP 0x00000100 /* enable icache par. check */
300 #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
301 #define SPRN_IMMR 0x27E /* Internal Memory Map Register */
302 #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
303 #define SPRN_L2CR2 0x3f8
304 #define L2CR_L2E 0x80000000 /* L2 enable */
305 #define L2CR_L2PE 0x40000000 /* L2 parity enable */
306 #define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */
307 #define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */
308 #define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */
309 #define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */
310 #define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */
311 #define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */
312 #define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */
313 #define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */
314 #define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */
315 #define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */
316 #define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */
317 #define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */
318 #define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */
319 #define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */
320 #define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */
321 #define L2CR_L2DO 0x00400000 /* L2 data only */
322 #define L2CR_L2I 0x00200000 /* L2 global invalidate */
323 #define L2CR_L2CTL 0x00100000 /* L2 RAM control */
324 #define L2CR_L2WT 0x00080000 /* L2 write-through */
325 #define L2CR_L2TS 0x00040000 /* L2 test support */
326 #define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */
327 #define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */
328 #define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */
329 #define L2CR_L2SL 0x00008000 /* L2 DLL slow */
330 #define L2CR_L2DF 0x00004000 /* L2 differential clock */
331 #define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */
332 #define L2CR_L2IP 0x00000001 /* L2 GI in progress */
333 #define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */
334 #define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */
335 #define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */
336 #define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */
337 #define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter */
338 #define L3CR_L3E 0x80000000 /* L3 enable */
339 #define L3CR_L3PE 0x40000000 /* L3 data parity enable */
340 #define L3CR_L3APE 0x20000000 /* L3 addr parity enable */
341 #define L3CR_L3SIZ 0x10000000 /* L3 size */
342 #define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */
343 #define L3CR_L3RES 0x04000000 /* L3 special reserved bit */
344 #define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */
345 #define L3CR_L3IO 0x00400000 /* L3 instruction only */
346 #define L3CR_L3SPO 0x00040000 /* L3 sample point override */
347 #define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */
348 #define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */
349 #define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */
350 #define L3CR_L3HWF 0x00000800 /* L3 hardware flush */
351 #define L3CR_L3I 0x00000400 /* L3 global invalidate */
352 #define L3CR_L3RT 0x00000300 /* L3 SRAM type */
353 #define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */
354 #define L3CR_L3DO 0x00000040 /* L3 data only mode */
355 #define L3CR_PMEN 0x00000004 /* L3 private memory enable */
356 #define L3CR_PMSIZ 0x00000001 /* L3 private memory size */
358 #define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */
359 #define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */
360 #define SPRN_LDSTCR 0x3f8 /* Load/Store control register */
361 #define SPRN_LDSTDB 0x3f4 /* */
362 #define SPRN_LR 0x008 /* Link Register */
364 #define SPRN_PIR 0x3FF /* Processor Identification Register */
366 #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
367 #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
368 #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */
369 #define SPRN_PVR 0x11F /* Processor Version Register */
370 #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
371 #define SPRN_SDA 0x3BF /* Sampled Data Address Register */
372 #define SPRN_SDR1 0x019 /* MMU Hash Base Register */
373 #define SPRN_ASR 0x118 /* Address Space Register */
374 #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
375 #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
376 #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
377 #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
378 #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
379 #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
380 #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
381 #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
382 #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
383 #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
384 #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
385 #define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */
386 #define SRR1_WAKERESET 0x00380000 /* System reset */
387 #define SRR1_WAKESYSERR 0x00300000 /* System error */
388 #define SRR1_WAKEEE 0x00200000 /* External interrupt */
389 #define SRR1_WAKEMT 0x00280000 /* mtctrl */
390 #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
391 #define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */
392 #define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */
393 #define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */
395 #define SPRN_TBCTL 0x35f /* PA6T Timebase control register */
396 #define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */
397 #define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */
398 #define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */
399 #define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */
402 #define SPRN_SVR 0x11E /* System Version Register */
404 #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
405 /* these bits were defined in inverted endian sense originally, ugh, confusing */
406 #define THRM1_TIN (1 << 31)
407 #define THRM1_TIV (1 << 30)
408 #define THRM1_THRES(x) ((x&0x7f)<<23)
409 #define THRM3_SITV(x) ((x&0x3fff)<<1)
410 #define THRM1_TID (1<<2)
411 #define THRM1_TIE (1<<1)
412 #define THRM1_V (1<<0)
413 #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
414 #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
415 #define THRM3_E (1<<0)
416 #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
417 #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
418 #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
419 #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
420 #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
421 #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
422 #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
423 #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
424 #define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
425 #define SPRN_XER 0x001 /* Fixed Point Exception Register */
427 #define SPRN_SCOMC 0x114 /* SCOM Access Control */
428 #define SPRN_SCOMD 0x115 /* SCOM Access DATA */
430 /* Performance monitor SPRs */
432 #define SPRN_MMCR0 795
433 #define MMCR0_FC 0x80000000UL /* freeze counters */
434 #define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
435 #define MMCR0_KERNEL_DISABLE MMCR0_FCS
436 #define MMCR0_FCP 0x20000000UL /* freeze in problem state */
437 #define MMCR0_PROBLEM_DISABLE MMCR0_FCP
438 #define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
439 #define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
440 #define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
441 #define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
442 #define MMCR0_TBEE 0x00400000UL /* time base exception enable */
443 #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
444 #define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/
445 #define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
446 #define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
447 #define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */
448 #define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */
449 #define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */
450 #define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
451 #define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */
452 #define SPRN_MMCR1 798
453 #define SPRN_MMCRA 0x312
454 #define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
455 #define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
456 #define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
457 #define POWER6_MMCRA_SIHV 0x0000040000000000ULL
458 #define POWER6_MMCRA_SIPR 0x0000020000000000ULL
459 #define POWER6_MMCRA_THRM 0x00000020UL
460 #define POWER6_MMCRA_OTHER 0x0000000EUL
461 #define SPRN_PMC1 787
462 #define SPRN_PMC2 788
463 #define SPRN_PMC3 789
464 #define SPRN_PMC4 790
465 #define SPRN_PMC5 791
466 #define SPRN_PMC6 792
467 #define SPRN_PMC7 793
468 #define SPRN_PMC8 794
469 #define SPRN_SIAR 780
470 #define SPRN_SDAR 781
472 #define PA6T_SPRN_PMC0 787
473 #define PA6T_SPRN_PMC1 788
474 #define PA6T_SPRN_PMC2 789
475 #define PA6T_SPRN_PMC3 790
476 #define PA6T_SPRN_PMC4 791
477 #define PA6T_SPRN_PMC5 792
480 #define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */
481 #define MMCR0_FC 0x80000000UL /* freeze counters */
482 #define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
483 #define MMCR0_FCP 0x20000000UL /* freeze in problem state */
484 #define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
485 #define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
486 #define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
487 #define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
488 #define MMCR0_TBEE 0x00400000UL /* time base exception enable */
489 #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
490 #define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/
491 #define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
492 #define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
493 #define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
495 #define SPRN_MMCR1 956
496 #define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
497 #define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
498 #define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
499 #define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
500 #define SPRN_MMCR2 944
501 #define SPRN_PMC1 953 /* Performance Counter Register 1 */
502 #define SPRN_PMC2 954 /* Performance Counter Register 2 */
503 #define SPRN_PMC3 957 /* Performance Counter Register 3 */
504 #define SPRN_PMC4 958 /* Performance Counter Register 4 */
505 #define SPRN_PMC5 945 /* Performance Counter Register 5 */
506 #define SPRN_PMC6 946 /* Performance Counter Register 6 */
508 #define SPRN_SIAR 955 /* Sampled Instruction Address Register */
510 /* Bit definitions for MMCR0 and PMC1 / PMC2. */
511 #define MMCR0_PMC1_CYCLES (1 << 7)
512 #define MMCR0_PMC1_ICACHEMISS (5 << 7)
513 #define MMCR0_PMC1_DTLB (6 << 7)
514 #define MMCR0_PMC2_DCACHEMISS 0x6
515 #define MMCR0_PMC2_CYCLES 0x1
516 #define MMCR0_PMC2_ITLB 0x7
517 #define MMCR0_PMC2_LOADMISSTIME 0x5
521 * An mtfsf instruction with the L bit set. On CPUs that support this a
522 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
524 * Until binutils gets the new form of mtfsf, hardwire the instruction.
527 #define MTFSF_L(REG) \
528 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
530 #define MTFSF_L(REG) mtfsf 0xff, (REG)
533 /* Processor Version Register (PVR) field extraction */
535 #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
536 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
538 #define __is_processor(pv) (PVR_VER(mfspr(SPRN_PVR)) == (pv))
541 * IBM has further subdivided the standard PowerPC 16-bit version and
542 * revision subfields of the PVR for the PowerPC 403s into the following:
545 #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
546 #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
547 #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
548 #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
549 #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
550 #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
552 /* Processor Version Numbers */
554 #define PVR_403GA 0x00200000
555 #define PVR_403GB 0x00200100
556 #define PVR_403GC 0x00200200
557 #define PVR_403GCX 0x00201400
558 #define PVR_405GP 0x40110000
559 #define PVR_STB03XXX 0x40310000
560 #define PVR_NP405H 0x41410000
561 #define PVR_NP405L 0x41610000
562 #define PVR_601 0x00010000
563 #define PVR_602 0x00050000
564 #define PVR_603 0x00030000
565 #define PVR_603e 0x00060000
566 #define PVR_603ev 0x00070000
567 #define PVR_603r 0x00071000
568 #define PVR_604 0x00040000
569 #define PVR_604e 0x00090000
570 #define PVR_604r 0x000A0000
571 #define PVR_620 0x00140000
572 #define PVR_740 0x00080000
573 #define PVR_750 PVR_740
574 #define PVR_740P 0x10080000
575 #define PVR_750P PVR_740P
576 #define PVR_7400 0x000C0000
577 #define PVR_7410 0x800C0000
578 #define PVR_7450 0x80000000
579 #define PVR_8540 0x80200000
580 #define PVR_8560 0x80200000
582 * For the 8xx processors, all of them report the same PVR family for
583 * the PowerPC core. The various versions of these processors must be
584 * differentiated by the version number in the Communication Processor
587 #define PVR_821 0x00500000
588 #define PVR_823 PVR_821
589 #define PVR_850 PVR_821
590 #define PVR_860 PVR_821
591 #define PVR_8240 0x00810100
592 #define PVR_8245 0x80811014
593 #define PVR_8260 PVR_8240
595 /* 64-bit processors */
596 /* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */
597 #define PV_NORTHSTAR 0x0033
598 #define PV_PULSAR 0x0034
599 #define PV_POWER4 0x0035
600 #define PV_ICESTAR 0x0036
601 #define PV_SSTAR 0x0037
602 #define PV_POWER4p 0x0038
603 #define PV_970 0x0039
604 #define PV_POWER5 0x003A
605 #define PV_POWER5p 0x003B
606 #define PV_970FX 0x003C
607 #define PV_630 0x0040
608 #define PV_630p 0x0041
609 #define PV_970MP 0x0044
610 #define PV_970GX 0x0045
612 #define PV_PA6T 0x0090
615 * Number of entries in the SLB. If this ever changes we should handle
616 * it with a use a cpu feature fixup.
618 #define SLB_NUM_ENTRIES 64
620 /* Macros for setting and retrieving special purpose registers */
622 #define mfmsr() ({unsigned long rval; \
623 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
625 #define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
627 #define mtmsrd(v) __mtmsrd((v), 0)
628 #define mtmsr(v) mtmsrd(v)
630 #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
633 #define mfspr(rn) ({unsigned long rval; \
634 asm volatile("mfspr %0," __stringify(rn) \
635 : "=r" (rval)); rval;})
636 #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
639 #ifdef CONFIG_PPC_CELL
640 #define mftb() ({unsigned long rval; \
643 "97: cmpwi %0,0;\n" \
646 ".section __ftr_fixup,\"a\"\n" \
651 " .llong 97b-98b\n" \
652 " .llong 99b-98b\n" \
654 : "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;})
656 #define mftb() ({unsigned long rval; \
657 asm volatile("mftb %0" : "=r" (rval)); rval;})
658 #endif /* !CONFIG_PPC_CELL */
660 #else /* __powerpc64__ */
662 #define mftbl() ({unsigned long rval; \
663 asm volatile("mftbl %0" : "=r" (rval)); rval;})
664 #define mftbu() ({unsigned long rval; \
665 asm volatile("mftbu %0" : "=r" (rval)); rval;})
666 #endif /* !__powerpc64__ */
668 #define mttbl(v) asm volatile("mttbl %0":: "r"(v))
669 #define mttbu(v) asm volatile("mttbu %0":: "r"(v))
672 #define mfsrin(v) ({unsigned int rval; \
673 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
677 #define proc_trap() asm volatile("trap")
681 extern void ppc64_runlatch_on(void);
682 extern void ppc64_runlatch_off(void);
684 extern unsigned long scom970_read(unsigned int address);
685 extern void scom970_write(unsigned int address, unsigned long value);
688 #define ppc64_runlatch_on()
689 #define ppc64_runlatch_off()
691 #endif /* CONFIG_PPC64 */
693 #define __get_SP() ({unsigned long sp; \
694 asm volatile("mr %0,1": "=r" (sp)); sp;})
696 #endif /* __ASSEMBLY__ */
697 #endif /* __KERNEL__ */
698 #endif /* _ASM_POWERPC_REG_H */
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