git.oblomov.eu Git - linux-2.6/blob - arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33
  34 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  35
  36 MODULE_AUTHOR("Qumranet");
  37 MODULE_LICENSE("GPL");
  38
  39 #define IOPM_ALLOC_ORDER 2
  40 #define MSRPM_ALLOC_ORDER 1
  41
  42 #define SEG_TYPE_LDT 2
  43 #define SEG_TYPE_BUSY_TSS16 3
  44
  45 #define SVM_FEATURE_NPT  (1 << 0)
  46 #define SVM_FEATURE_LBRV (1 << 1)
  47 #define SVM_FEATURE_SVML (1 << 2)
  48
  49 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  50
  51 /* Turn on to get debugging output*/
  52 /* #define NESTED_DEBUG */
  53
  54 #ifdef NESTED_DEBUG
  55 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  56 #else
  57 #define nsvm_printk(fmt, args...) do {} while(0)
  58 #endif
  59
  60 /* enable NPT for AMD64 and X86 with PAE */
  61 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  62 static bool npt_enabled = true;
  63 #else
  64 static bool npt_enabled = false;
  65 #endif
  66 static int npt = 1;
  67
  68 module_param(npt, int, S_IRUGO);
  69
  70 static int nested = 0;
  71 module_param(nested, int, S_IRUGO);
  72
  73 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  74
  75 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
  76 static int nested_svm_vmexit(struct vcpu_svm *svm);
  77 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
  78                              void *arg2, void *opaque);
  79 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
  80                                       bool has_error_code, u32 error_code);
  81
  82 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  83 {
  84         return container_of(vcpu, struct vcpu_svm, vcpu);
  85 }
  86
  87 static inline bool is_nested(struct vcpu_svm *svm)
  88 {
  89         return svm->nested_vmcb;
  90 }
  91
  92 static unsigned long iopm_base;
  93
  94 struct kvm_ldttss_desc {
  95         u16 limit0;
  96         u16 base0;
  97         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  98         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  99         u32 base3;
 100         u32 zero1;
 101 } __attribute__((packed));
 102
 103 struct svm_cpu_data {
 104         int cpu;
 105
 106         u64 asid_generation;
 107         u32 max_asid;
 108         u32 next_asid;
 109         struct kvm_ldttss_desc *tss_desc;
 110
 111         struct page *save_area;
 112 };
 113
 114 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 115 static uint32_t svm_features;
 116
 117 struct svm_init_data {
 118         int cpu;
 119         int r;
 120 };
 121
 122 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 123
 124 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 125 #define MSRS_RANGE_SIZE 2048
 126 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 127
 128 #define MAX_INST_SIZE 15
 129
 130 static inline u32 svm_has(u32 feat)
 131 {
 132         return svm_features & feat;
 133 }
 134
 135 static inline void clgi(void)
 136 {
 137         asm volatile (__ex(SVM_CLGI));
 138 }
 139
 140 static inline void stgi(void)
 141 {
 142         asm volatile (__ex(SVM_STGI));
 143 }
 144
 145 static inline void invlpga(unsigned long addr, u32 asid)
 146 {
 147         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 148 }
 149
 150 static inline unsigned long kvm_read_cr2(void)
 151 {
 152         unsigned long cr2;
 153
 154         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 155         return cr2;
 156 }
 157
 158 static inline void kvm_write_cr2(unsigned long val)
 159 {
 160         asm volatile ("mov %0, %%cr2" :: "r" (val));
 161 }
 162
 163 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 164 {
 165         to_svm(vcpu)->asid_generation--;
 166 }
 167
 168 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 169 {
 170         force_new_asid(vcpu);
 171 }
 172
 173 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 174 {
 175         if (!npt_enabled && !(efer & EFER_LMA))
 176                 efer &= ~EFER_LME;
 177
 178         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 179         vcpu->arch.shadow_efer = efer;
 180 }
 181
 182 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 183                                 bool has_error_code, u32 error_code)
 184 {
 185         struct vcpu_svm *svm = to_svm(vcpu);
 186
 187         /* If we are within a nested VM we'd better #VMEXIT and let the
 188            guest handle the exception */
 189         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 190                 return;
 191
 192         svm->vmcb->control.event_inj = nr
 193                 | SVM_EVTINJ_VALID
 194                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 195                 | SVM_EVTINJ_TYPE_EXEPT;
 196         svm->vmcb->control.event_inj_err = error_code;
 197 }
 198
 199 static int is_external_interrupt(u32 info)
 200 {
 201         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 202         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 203 }
 204
 205 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 206 {
 207         struct vcpu_svm *svm = to_svm(vcpu);
 208
 209         if (!svm->next_rip) {
 210                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 211                 return;
 212         }
 213         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 214                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 215                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 216
 217         kvm_rip_write(vcpu, svm->next_rip);
 218         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 219 }
 220
 221 static int has_svm(void)
 222 {
 223         const char *msg;
 224
 225         if (!cpu_has_svm(&msg)) {
 226                 printk(KERN_INFO "has_svm: %s\n", msg);
 227                 return 0;
 228         }
 229
 230         return 1;
 231 }
 232
 233 static void svm_hardware_disable(void *garbage)
 234 {
 235         cpu_svm_disable();
 236 }
 237
 238 static void svm_hardware_enable(void *garbage)
 239 {
 240
 241         struct svm_cpu_data *svm_data;
 242         uint64_t efer;
 243         struct desc_ptr gdt_descr;
 244         struct desc_struct *gdt;
 245         int me = raw_smp_processor_id();
 246
 247         if (!has_svm()) {
 248                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 249                 return;
 250         }
 251         svm_data = per_cpu(svm_data, me);
 252
 253         if (!svm_data) {
 254                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 255                        me);
 256                 return;
 257         }
 258
 259         svm_data->asid_generation = 1;
 260         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 261         svm_data->next_asid = svm_data->max_asid + 1;
 262
 263         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 264         gdt = (struct desc_struct *)gdt_descr.address;
 265         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 266
 267         rdmsrl(MSR_EFER, efer);
 268         wrmsrl(MSR_EFER, efer | EFER_SVME);
 269
 270         wrmsrl(MSR_VM_HSAVE_PA,
 271                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 272 }
 273
 274 static void svm_cpu_uninit(int cpu)
 275 {
 276         struct svm_cpu_data *svm_data
 277                 = per_cpu(svm_data, raw_smp_processor_id());
 278
 279         if (!svm_data)
 280                 return;
 281
 282         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 283         __free_page(svm_data->save_area);
 284         kfree(svm_data);
 285 }
 286
 287 static int svm_cpu_init(int cpu)
 288 {
 289         struct svm_cpu_data *svm_data;
 290         int r;
 291
 292         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 293         if (!svm_data)
 294                 return -ENOMEM;
 295         svm_data->cpu = cpu;
 296         svm_data->save_area = alloc_page(GFP_KERNEL);
 297         r = -ENOMEM;
 298         if (!svm_data->save_area)
 299                 goto err_1;
 300
 301         per_cpu(svm_data, cpu) = svm_data;
 302
 303         return 0;
 304
 305 err_1:
 306         kfree(svm_data);
 307         return r;
 308
 309 }
 310
 311 static void set_msr_interception(u32 *msrpm, unsigned msr,
 312                                  int read, int write)
 313 {
 314         int i;
 315
 316         for (i = 0; i < NUM_MSR_MAPS; i++) {
 317                 if (msr >= msrpm_ranges[i] &&
 318                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 319                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 320                                           msrpm_ranges[i]) * 2;
 321
 322                         u32 *base = msrpm + (msr_offset / 32);
 323                         u32 msr_shift = msr_offset % 32;
 324                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 325                         *base = (*base & ~(0x3 << msr_shift)) |
 326                                 (mask << msr_shift);
 327                         return;
 328                 }
 329         }
 330         BUG();
 331 }
 332
 333 static void svm_vcpu_init_msrpm(u32 *msrpm)
 334 {
 335         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 336
 337 #ifdef CONFIG_X86_64
 338         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 339         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 340         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 341         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 342         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 343         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 344 #endif
 345         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 346         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 347         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 348         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 349 }
 350
 351 static void svm_enable_lbrv(struct vcpu_svm *svm)
 352 {
 353         u32 *msrpm = svm->msrpm;
 354
 355         svm->vmcb->control.lbr_ctl = 1;
 356         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 357         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 358         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 359         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 360 }
 361
 362 static void svm_disable_lbrv(struct vcpu_svm *svm)
 363 {
 364         u32 *msrpm = svm->msrpm;
 365
 366         svm->vmcb->control.lbr_ctl = 0;
 367         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 368         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 369         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 370         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 371 }
 372
 373 static __init int svm_hardware_setup(void)
 374 {
 375         int cpu;
 376         struct page *iopm_pages;
 377         void *iopm_va;
 378         int r;
 379
 380         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 381
 382         if (!iopm_pages)
 383                 return -ENOMEM;
 384
 385         iopm_va = page_address(iopm_pages);
 386         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 387         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 388
 389         if (boot_cpu_has(X86_FEATURE_NX))
 390                 kvm_enable_efer_bits(EFER_NX);
 391
 392         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 393                 kvm_enable_efer_bits(EFER_FFXSR);
 394
 395         if (nested) {
 396                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 397                 kvm_enable_efer_bits(EFER_SVME);
 398         }
 399
 400         for_each_online_cpu(cpu) {
 401                 r = svm_cpu_init(cpu);
 402                 if (r)
 403                         goto err;
 404         }
 405
 406         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 407
 408         if (!svm_has(SVM_FEATURE_NPT))
 409                 npt_enabled = false;
 410
 411         if (npt_enabled && !npt) {
 412                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 413                 npt_enabled = false;
 414         }
 415
 416         if (npt_enabled) {
 417                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 418                 kvm_enable_tdp();
 419         } else
 420                 kvm_disable_tdp();
 421
 422         return 0;
 423
 424 err:
 425         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 426         iopm_base = 0;
 427         return r;
 428 }
 429
 430 static __exit void svm_hardware_unsetup(void)
 431 {
 432         int cpu;
 433
 434         for_each_online_cpu(cpu)
 435                 svm_cpu_uninit(cpu);
 436
 437         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 438         iopm_base = 0;
 439 }
 440
 441 static void init_seg(struct vmcb_seg *seg)
 442 {
 443         seg->selector = 0;
 444         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 445                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 446         seg->limit = 0xffff;
 447         seg->base = 0;
 448 }
 449
 450 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 451 {
 452         seg->selector = 0;
 453         seg->attrib = SVM_SELECTOR_P_MASK | type;
 454         seg->limit = 0xffff;
 455         seg->base = 0;
 456 }
 457
 458 static void init_vmcb(struct vcpu_svm *svm)
 459 {
 460         struct vmcb_control_area *control = &svm->vmcb->control;
 461         struct vmcb_save_area *save = &svm->vmcb->save;
 462
 463         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 464                                         INTERCEPT_CR3_MASK |
 465                                         INTERCEPT_CR4_MASK;
 466
 467         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 468                                         INTERCEPT_CR3_MASK |
 469                                         INTERCEPT_CR4_MASK |
 470                                         INTERCEPT_CR8_MASK;
 471
 472         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 473                                         INTERCEPT_DR1_MASK |
 474                                         INTERCEPT_DR2_MASK |
 475                                         INTERCEPT_DR3_MASK;
 476
 477         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 478                                         INTERCEPT_DR1_MASK |
 479                                         INTERCEPT_DR2_MASK |
 480                                         INTERCEPT_DR3_MASK |
 481                                         INTERCEPT_DR5_MASK |
 482                                         INTERCEPT_DR7_MASK;
 483
 484         control->intercept_exceptions = (1 << PF_VECTOR) |
 485                                         (1 << UD_VECTOR) |
 486                                         (1 << MC_VECTOR);
 487
 488
 489         control->intercept =    (1ULL << INTERCEPT_INTR) |
 490                                 (1ULL << INTERCEPT_NMI) |
 491                                 (1ULL << INTERCEPT_SMI) |
 492                                 (1ULL << INTERCEPT_CPUID) |
 493                                 (1ULL << INTERCEPT_INVD) |
 494                                 (1ULL << INTERCEPT_HLT) |
 495                                 (1ULL << INTERCEPT_INVLPG) |
 496                                 (1ULL << INTERCEPT_INVLPGA) |
 497                                 (1ULL << INTERCEPT_IOIO_PROT) |
 498                                 (1ULL << INTERCEPT_MSR_PROT) |
 499                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 500                                 (1ULL << INTERCEPT_SHUTDOWN) |
 501                                 (1ULL << INTERCEPT_VMRUN) |
 502                                 (1ULL << INTERCEPT_VMMCALL) |
 503                                 (1ULL << INTERCEPT_VMLOAD) |
 504                                 (1ULL << INTERCEPT_VMSAVE) |
 505                                 (1ULL << INTERCEPT_STGI) |
 506                                 (1ULL << INTERCEPT_CLGI) |
 507                                 (1ULL << INTERCEPT_SKINIT) |
 508                                 (1ULL << INTERCEPT_WBINVD) |
 509                                 (1ULL << INTERCEPT_MONITOR) |
 510                                 (1ULL << INTERCEPT_MWAIT);
 511
 512         control->iopm_base_pa = iopm_base;
 513         control->msrpm_base_pa = __pa(svm->msrpm);
 514         control->tsc_offset = 0;
 515         control->int_ctl = V_INTR_MASKING_MASK;
 516
 517         init_seg(&save->es);
 518         init_seg(&save->ss);
 519         init_seg(&save->ds);
 520         init_seg(&save->fs);
 521         init_seg(&save->gs);
 522
 523         save->cs.selector = 0xf000;
 524         /* Executable/Readable Code Segment */
 525         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 526                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 527         save->cs.limit = 0xffff;
 528         /*
 529          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 530          * be consistent with it.
 531          *
 532          * Replace when we have real mode working for vmx.
 533          */
 534         save->cs.base = 0xf0000;
 535
 536         save->gdtr.limit = 0xffff;
 537         save->idtr.limit = 0xffff;
 538
 539         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 540         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 541
 542         save->efer = EFER_SVME;
 543         save->dr6 = 0xffff0ff0;
 544         save->dr7 = 0x400;
 545         save->rflags = 2;
 546         save->rip = 0x0000fff0;
 547         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 548
 549         /*
 550          * cr0 val on cpu init should be 0x60000010, we enable cpu
 551          * cache by default. the orderly way is to enable cache in bios.
 552          */
 553         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 554         save->cr4 = X86_CR4_PAE;
 555         /* rdx = ?? */
 556
 557         if (npt_enabled) {
 558                 /* Setup VMCB for Nested Paging */
 559                 control->nested_ctl = 1;
 560                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 561                                         (1ULL << INTERCEPT_INVLPG));
 562                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 563                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 564                                                 INTERCEPT_CR3_MASK);
 565                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 566                                                  INTERCEPT_CR3_MASK);
 567                 save->g_pat = 0x0007040600070406ULL;
 568                 /* enable caching because the QEMU Bios doesn't enable it */
 569                 save->cr0 = X86_CR0_ET;
 570                 save->cr3 = 0;
 571                 save->cr4 = 0;
 572         }
 573         force_new_asid(&svm->vcpu);
 574
 575         svm->nested_vmcb = 0;
 576         svm->vcpu.arch.hflags = HF_GIF_MASK;
 577 }
 578
 579 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 580 {
 581         struct vcpu_svm *svm = to_svm(vcpu);
 582
 583         init_vmcb(svm);
 584
 585         if (vcpu->vcpu_id != 0) {
 586                 kvm_rip_write(vcpu, 0);
 587                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 588                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 589         }
 590         vcpu->arch.regs_avail = ~0;
 591         vcpu->arch.regs_dirty = ~0;
 592
 593         return 0;
 594 }
 595
 596 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 597 {
 598         struct vcpu_svm *svm;
 599         struct page *page;
 600         struct page *msrpm_pages;
 601         struct page *hsave_page;
 602         struct page *nested_msrpm_pages;
 603         int err;
 604
 605         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 606         if (!svm) {
 607                 err = -ENOMEM;
 608                 goto out;
 609         }
 610
 611         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 612         if (err)
 613                 goto free_svm;
 614
 615         page = alloc_page(GFP_KERNEL);
 616         if (!page) {
 617                 err = -ENOMEM;
 618                 goto uninit;
 619         }
 620
 621         err = -ENOMEM;
 622         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 623         if (!msrpm_pages)
 624                 goto uninit;
 625
 626         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 627         if (!nested_msrpm_pages)
 628                 goto uninit;
 629
 630         svm->msrpm = page_address(msrpm_pages);
 631         svm_vcpu_init_msrpm(svm->msrpm);
 632
 633         hsave_page = alloc_page(GFP_KERNEL);
 634         if (!hsave_page)
 635                 goto uninit;
 636         svm->hsave = page_address(hsave_page);
 637
 638         svm->nested_msrpm = page_address(nested_msrpm_pages);
 639
 640         svm->vmcb = page_address(page);
 641         clear_page(svm->vmcb);
 642         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 643         svm->asid_generation = 0;
 644         init_vmcb(svm);
 645
 646         fx_init(&svm->vcpu);
 647         svm->vcpu.fpu_active = 1;
 648         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 649         if (svm->vcpu.vcpu_id == 0)
 650                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 651
 652         return &svm->vcpu;
 653
 654 uninit:
 655         kvm_vcpu_uninit(&svm->vcpu);
 656 free_svm:
 657         kmem_cache_free(kvm_vcpu_cache, svm);
 658 out:
 659         return ERR_PTR(err);
 660 }
 661
 662 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 663 {
 664         struct vcpu_svm *svm = to_svm(vcpu);
 665
 666         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 667         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 668         __free_page(virt_to_page(svm->hsave));
 669         __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
 670         kvm_vcpu_uninit(vcpu);
 671         kmem_cache_free(kvm_vcpu_cache, svm);
 672 }
 673
 674 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 675 {
 676         struct vcpu_svm *svm = to_svm(vcpu);
 677         int i;
 678
 679         if (unlikely(cpu != vcpu->cpu)) {
 680                 u64 tsc_this, delta;
 681
 682                 /*
 683                  * Make sure that the guest sees a monotonically
 684                  * increasing TSC.
 685                  */
 686                 rdtscll(tsc_this);
 687                 delta = vcpu->arch.host_tsc - tsc_this;
 688                 svm->vmcb->control.tsc_offset += delta;
 689                 vcpu->cpu = cpu;
 690                 kvm_migrate_timers(vcpu);
 691         }
 692
 693         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 694                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 695 }
 696
 697 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 698 {
 699         struct vcpu_svm *svm = to_svm(vcpu);
 700         int i;
 701
 702         ++vcpu->stat.host_state_reload;
 703         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 704                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 705
 706         rdtscll(vcpu->arch.host_tsc);
 707 }
 708
 709 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 710 {
 711         return to_svm(vcpu)->vmcb->save.rflags;
 712 }
 713
 714 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 715 {
 716         to_svm(vcpu)->vmcb->save.rflags = rflags;
 717 }
 718
 719 static void svm_set_vintr(struct vcpu_svm *svm)
 720 {
 721         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 722 }
 723
 724 static void svm_clear_vintr(struct vcpu_svm *svm)
 725 {
 726         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 727 }
 728
 729 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 730 {
 731         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 732
 733         switch (seg) {
 734         case VCPU_SREG_CS: return &save->cs;
 735         case VCPU_SREG_DS: return &save->ds;
 736         case VCPU_SREG_ES: return &save->es;
 737         case VCPU_SREG_FS: return &save->fs;
 738         case VCPU_SREG_GS: return &save->gs;
 739         case VCPU_SREG_SS: return &save->ss;
 740         case VCPU_SREG_TR: return &save->tr;
 741         case VCPU_SREG_LDTR: return &save->ldtr;
 742         }
 743         BUG();
 744         return NULL;
 745 }
 746
 747 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 748 {
 749         struct vmcb_seg *s = svm_seg(vcpu, seg);
 750
 751         return s->base;
 752 }
 753
 754 static void svm_get_segment(struct kvm_vcpu *vcpu,
 755                             struct kvm_segment *var, int seg)
 756 {
 757         struct vmcb_seg *s = svm_seg(vcpu, seg);
 758
 759         var->base = s->base;
 760         var->limit = s->limit;
 761         var->selector = s->selector;
 762         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 763         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 764         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 765         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 766         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 767         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 768         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 769         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 770
 771         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 772          * for cross vendor migration purposes by "not present"
 773          */
 774         var->unusable = !var->present || (var->type == 0);
 775
 776         switch (seg) {
 777         case VCPU_SREG_CS:
 778                 /*
 779                  * SVM always stores 0 for the 'G' bit in the CS selector in
 780                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 781                  * Intel's VMENTRY has a check on the 'G' bit.
 782                  */
 783                 var->g = s->limit > 0xfffff;
 784                 break;
 785         case VCPU_SREG_TR:
 786                 /*
 787                  * Work around a bug where the busy flag in the tr selector
 788                  * isn't exposed
 789                  */
 790                 var->type |= 0x2;
 791                 break;
 792         case VCPU_SREG_DS:
 793         case VCPU_SREG_ES:
 794         case VCPU_SREG_FS:
 795         case VCPU_SREG_GS:
 796                 /*
 797                  * The accessed bit must always be set in the segment
 798                  * descriptor cache, although it can be cleared in the
 799                  * descriptor, the cached bit always remains at 1. Since
 800                  * Intel has a check on this, set it here to support
 801                  * cross-vendor migration.
 802                  */
 803                 if (!var->unusable)
 804                         var->type |= 0x1;
 805                 break;
 806         case VCPU_SREG_SS:
 807                 /* On AMD CPUs sometimes the DB bit in the segment
 808                  * descriptor is left as 1, although the whole segment has
 809                  * been made unusable. Clear it here to pass an Intel VMX
 810                  * entry check when cross vendor migrating.
 811                  */
 812                 if (var->unusable)
 813                         var->db = 0;
 814                 break;
 815         }
 816 }
 817
 818 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 819 {
 820         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 821
 822         return save->cpl;
 823 }
 824
 825 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 826 {
 827         struct vcpu_svm *svm = to_svm(vcpu);
 828
 829         dt->limit = svm->vmcb->save.idtr.limit;
 830         dt->base = svm->vmcb->save.idtr.base;
 831 }
 832
 833 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 834 {
 835         struct vcpu_svm *svm = to_svm(vcpu);
 836
 837         svm->vmcb->save.idtr.limit = dt->limit;
 838         svm->vmcb->save.idtr.base = dt->base ;
 839 }
 840
 841 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 842 {
 843         struct vcpu_svm *svm = to_svm(vcpu);
 844
 845         dt->limit = svm->vmcb->save.gdtr.limit;
 846         dt->base = svm->vmcb->save.gdtr.base;
 847 }
 848
 849 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 850 {
 851         struct vcpu_svm *svm = to_svm(vcpu);
 852
 853         svm->vmcb->save.gdtr.limit = dt->limit;
 854         svm->vmcb->save.gdtr.base = dt->base ;
 855 }
 856
 857 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 858 {
 859 }
 860
 861 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 862 {
 863         struct vcpu_svm *svm = to_svm(vcpu);
 864
 865 #ifdef CONFIG_X86_64
 866         if (vcpu->arch.shadow_efer & EFER_LME) {
 867                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 868                         vcpu->arch.shadow_efer |= EFER_LMA;
 869                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 870                 }
 871
 872                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 873                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 874                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 875                 }
 876         }
 877 #endif
 878         if (npt_enabled)
 879                 goto set;
 880
 881         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 882                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 883                 vcpu->fpu_active = 1;
 884         }
 885
 886         vcpu->arch.cr0 = cr0;
 887         cr0 |= X86_CR0_PG | X86_CR0_WP;
 888         if (!vcpu->fpu_active) {
 889                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 890                 cr0 |= X86_CR0_TS;
 891         }
 892 set:
 893         /*
 894          * re-enable caching here because the QEMU bios
 895          * does not do it - this results in some delay at
 896          * reboot
 897          */
 898         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 899         svm->vmcb->save.cr0 = cr0;
 900 }
 901
 902 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 903 {
 904         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 905         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 906
 907         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 908                 force_new_asid(vcpu);
 909
 910         vcpu->arch.cr4 = cr4;
 911         if (!npt_enabled)
 912                 cr4 |= X86_CR4_PAE;
 913         cr4 |= host_cr4_mce;
 914         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 915 }
 916
 917 static void svm_set_segment(struct kvm_vcpu *vcpu,
 918                             struct kvm_segment *var, int seg)
 919 {
 920         struct vcpu_svm *svm = to_svm(vcpu);
 921         struct vmcb_seg *s = svm_seg(vcpu, seg);
 922
 923         s->base = var->base;
 924         s->limit = var->limit;
 925         s->selector = var->selector;
 926         if (var->unusable)
 927                 s->attrib = 0;
 928         else {
 929                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 930                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 931                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 932                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 933                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 934                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 935                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 936                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 937         }
 938         if (seg == VCPU_SREG_CS)
 939                 svm->vmcb->save.cpl
 940                         = (svm->vmcb->save.cs.attrib
 941                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 942
 943 }
 944
 945 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
 946 {
 947         int old_debug = vcpu->guest_debug;
 948         struct vcpu_svm *svm = to_svm(vcpu);
 949
 950         vcpu->guest_debug = dbg->control;
 951
 952         svm->vmcb->control.intercept_exceptions &=
 953                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
 954         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 955                 if (vcpu->guest_debug &
 956                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
 957                         svm->vmcb->control.intercept_exceptions |=
 958                                 1 << DB_VECTOR;
 959                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 960                         svm->vmcb->control.intercept_exceptions |=
 961                                 1 << BP_VECTOR;
 962         } else
 963                 vcpu->guest_debug = 0;
 964
 965         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
 966                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
 967         else
 968                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
 969
 970         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
 971                 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
 972         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
 973                 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 974
 975         return 0;
 976 }
 977
 978 static void load_host_msrs(struct kvm_vcpu *vcpu)
 979 {
 980 #ifdef CONFIG_X86_64
 981         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 982 #endif
 983 }
 984
 985 static void save_host_msrs(struct kvm_vcpu *vcpu)
 986 {
 987 #ifdef CONFIG_X86_64
 988         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 989 #endif
 990 }
 991
 992 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 993 {
 994         if (svm_data->next_asid > svm_data->max_asid) {
 995                 ++svm_data->asid_generation;
 996                 svm_data->next_asid = 1;
 997                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 998         }
 999
1000         svm->vcpu.cpu = svm_data->cpu;
1001         svm->asid_generation = svm_data->asid_generation;
1002         svm->vmcb->control.asid = svm_data->next_asid++;
1003 }
1004
1005 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1006 {
1007         struct vcpu_svm *svm = to_svm(vcpu);
1008         unsigned long val;
1009
1010         switch (dr) {
1011         case 0 ... 3:
1012                 val = vcpu->arch.db[dr];
1013                 break;
1014         case 6:
1015                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1016                         val = vcpu->arch.dr6;
1017                 else
1018                         val = svm->vmcb->save.dr6;
1019                 break;
1020         case 7:
1021                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1022                         val = vcpu->arch.dr7;
1023                 else
1024                         val = svm->vmcb->save.dr7;
1025                 break;
1026         default:
1027                 val = 0;
1028         }
1029
1030         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1031         return val;
1032 }
1033
1034 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1035                        int *exception)
1036 {
1037         struct vcpu_svm *svm = to_svm(vcpu);
1038
1039         KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
1040
1041         *exception = 0;
1042
1043         switch (dr) {
1044         case 0 ... 3:
1045                 vcpu->arch.db[dr] = value;
1046                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1047                         vcpu->arch.eff_db[dr] = value;
1048                 return;
1049         case 4 ... 5:
1050                 if (vcpu->arch.cr4 & X86_CR4_DE)
1051                         *exception = UD_VECTOR;
1052                 return;
1053         case 6:
1054                 if (value & 0xffffffff00000000ULL) {
1055                         *exception = GP_VECTOR;
1056                         return;
1057                 }
1058                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1059                 return;
1060         case 7:
1061                 if (value & 0xffffffff00000000ULL) {
1062                         *exception = GP_VECTOR;
1063                         return;
1064                 }
1065                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1066                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1067                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1068                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1069                 }
1070                 return;
1071         default:
1072                 /* FIXME: Possible case? */
1073                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1074                        __func__, dr);
1075                 *exception = UD_VECTOR;
1076                 return;
1077         }
1078 }
1079
1080 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1081 {
1082         u64 fault_address;
1083         u32 error_code;
1084
1085         fault_address  = svm->vmcb->control.exit_info_2;
1086         error_code = svm->vmcb->control.exit_info_1;
1087
1088         if (!npt_enabled)
1089                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1090                             (u32)fault_address, (u32)(fault_address >> 32),
1091                             handler);
1092         else
1093                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1094                             (u32)fault_address, (u32)(fault_address >> 32),
1095                             handler);
1096         /*
1097          * FIXME: Tis shouldn't be necessary here, but there is a flush
1098          * missing in the MMU code. Until we find this bug, flush the
1099          * complete TLB here on an NPF
1100          */
1101         if (npt_enabled)
1102                 svm_flush_tlb(&svm->vcpu);
1103         else {
1104                 if (svm->vcpu.arch.interrupt.pending ||
1105                                 svm->vcpu.arch.exception.pending)
1106                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1107         }
1108         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1109 }
1110
1111 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1112 {
1113         if (!(svm->vcpu.guest_debug &
1114               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1115                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1116                 return 1;
1117         }
1118         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1119         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1120         kvm_run->debug.arch.exception = DB_VECTOR;
1121         return 0;
1122 }
1123
1124 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1125 {
1126         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1127         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1128         kvm_run->debug.arch.exception = BP_VECTOR;
1129         return 0;
1130 }
1131
1132 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1133 {
1134         int er;
1135
1136         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1137         if (er != EMULATE_DONE)
1138                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1139         return 1;
1140 }
1141
1142 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1143 {
1144         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1145         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1146                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1147         svm->vcpu.fpu_active = 1;
1148
1149         return 1;
1150 }
1151
1152 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1153 {
1154         /*
1155          * On an #MC intercept the MCE handler is not called automatically in
1156          * the host. So do it by hand here.
1157          */
1158         asm volatile (
1159                 "int $0x12\n");
1160         /* not sure if we ever come back to this point */
1161
1162         return 1;
1163 }
1164
1165 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1166 {
1167         /*
1168          * VMCB is undefined after a SHUTDOWN intercept
1169          * so reinitialize it.
1170          */
1171         clear_page(svm->vmcb);
1172         init_vmcb(svm);
1173
1174         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1175         return 0;
1176 }
1177
1178 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1179 {
1180         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1181         int size, in, string;
1182         unsigned port;
1183
1184         ++svm->vcpu.stat.io_exits;
1185
1186         svm->next_rip = svm->vmcb->control.exit_info_2;
1187
1188         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1189
1190         if (string) {
1191                 if (emulate_instruction(&svm->vcpu,
1192                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1193                         return 0;
1194                 return 1;
1195         }
1196
1197         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1198         port = io_info >> 16;
1199         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1200
1201         skip_emulated_instruction(&svm->vcpu);
1202         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1203 }
1204
1205 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1206 {
1207         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1208         return 1;
1209 }
1210
1211 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1212 {
1213         ++svm->vcpu.stat.irq_exits;
1214         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1215         return 1;
1216 }
1217
1218 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1219 {
1220         return 1;
1221 }
1222
1223 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1224 {
1225         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1226         skip_emulated_instruction(&svm->vcpu);
1227         return kvm_emulate_halt(&svm->vcpu);
1228 }
1229
1230 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1231 {
1232         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1233         skip_emulated_instruction(&svm->vcpu);
1234         kvm_emulate_hypercall(&svm->vcpu);
1235         return 1;
1236 }
1237
1238 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1239 {
1240         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1241             || !is_paging(&svm->vcpu)) {
1242                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1243                 return 1;
1244         }
1245
1246         if (svm->vmcb->save.cpl) {
1247                 kvm_inject_gp(&svm->vcpu, 0);
1248                 return 1;
1249         }
1250
1251        return 0;
1252 }
1253
1254 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1255                                       bool has_error_code, u32 error_code)
1256 {
1257         if (is_nested(svm)) {
1258                 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1259                 svm->vmcb->control.exit_code_hi = 0;
1260                 svm->vmcb->control.exit_info_1 = error_code;
1261                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1262                 if (nested_svm_exit_handled(svm, false)) {
1263                         nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1264
1265                         nested_svm_vmexit(svm);
1266                         return 1;
1267                 }
1268         }
1269
1270         return 0;
1271 }
1272
1273 static inline int nested_svm_intr(struct vcpu_svm *svm)
1274 {
1275         if (is_nested(svm)) {
1276                 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1277                         return 0;
1278
1279                 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1280                         return 0;
1281
1282                 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1283
1284                 if (nested_svm_exit_handled(svm, false)) {
1285                         nsvm_printk("VMexit -> INTR\n");
1286                         nested_svm_vmexit(svm);
1287                         return 1;
1288                 }
1289         }
1290
1291         return 0;
1292 }
1293
1294 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1295 {
1296         struct page *page;
1297
1298         down_read(&current->mm->mmap_sem);
1299         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1300         up_read(&current->mm->mmap_sem);
1301
1302         if (is_error_page(page)) {
1303                 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1304                        __func__, gpa);
1305                 kvm_release_page_clean(page);
1306                 kvm_inject_gp(&svm->vcpu, 0);
1307                 return NULL;
1308         }
1309         return page;
1310 }
1311
1312 static int nested_svm_do(struct vcpu_svm *svm,
1313                          u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1314                          int (*handler)(struct vcpu_svm *svm,
1315                                         void *arg1,
1316                                         void *arg2,
1317                                         void *opaque))
1318 {
1319         struct page *arg1_page;
1320         struct page *arg2_page = NULL;
1321         void *arg1;
1322         void *arg2 = NULL;
1323         int retval;
1324
1325         arg1_page = nested_svm_get_page(svm, arg1_gpa);
1326         if(arg1_page == NULL)
1327                 return 1;
1328
1329         if (arg2_gpa) {
1330                 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1331                 if(arg2_page == NULL) {
1332                         kvm_release_page_clean(arg1_page);
1333                         return 1;
1334                 }
1335         }
1336
1337         arg1 = kmap_atomic(arg1_page, KM_USER0);
1338         if (arg2_gpa)
1339                 arg2 = kmap_atomic(arg2_page, KM_USER1);
1340
1341         retval = handler(svm, arg1, arg2, opaque);
1342
1343         kunmap_atomic(arg1, KM_USER0);
1344         if (arg2_gpa)
1345                 kunmap_atomic(arg2, KM_USER1);
1346
1347         kvm_release_page_dirty(arg1_page);
1348         if (arg2_gpa)
1349                 kvm_release_page_dirty(arg2_page);
1350
1351         return retval;
1352 }
1353
1354 static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1355                                         void *arg1,
1356                                         void *arg2,
1357                                         void *opaque)
1358 {
1359         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1360         bool kvm_overrides = *(bool *)opaque;
1361         u32 exit_code = svm->vmcb->control.exit_code;
1362
1363         if (kvm_overrides) {
1364                 switch (exit_code) {
1365                 case SVM_EXIT_INTR:
1366                 case SVM_EXIT_NMI:
1367                         return 0;
1368                 /* For now we are always handling NPFs when using them */
1369                 case SVM_EXIT_NPF:
1370                         if (npt_enabled)
1371                                 return 0;
1372                         break;
1373                 /* When we're shadowing, trap PFs */
1374                 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1375                         if (!npt_enabled)
1376                                 return 0;
1377                         break;
1378                 default:
1379                         break;
1380                 }
1381         }
1382
1383         switch (exit_code) {
1384         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1385                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1386                 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1387                         return 1;
1388                 break;
1389         }
1390         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1391                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1392                 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1393                         return 1;
1394                 break;
1395         }
1396         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1397                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1398                 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1399                         return 1;
1400                 break;
1401         }
1402         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1403                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1404                 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1405                         return 1;
1406                 break;
1407         }
1408         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1409                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1410                 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1411                         return 1;
1412                 break;
1413         }
1414         default: {
1415                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1416                 nsvm_printk("exit code: 0x%x\n", exit_code);
1417                 if (nested_vmcb->control.intercept & exit_bits)
1418                         return 1;
1419         }
1420         }
1421
1422         return 0;
1423 }
1424
1425 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1426                                        void *arg1, void *arg2,
1427                                        void *opaque)
1428 {
1429         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1430         u8 *msrpm = (u8 *)arg2;
1431         u32 t0, t1;
1432         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1433         u32 param = svm->vmcb->control.exit_info_1 & 1;
1434
1435         if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1436                 return 0;
1437
1438         switch(msr) {
1439         case 0 ... 0x1fff:
1440                 t0 = (msr * 2) % 8;
1441                 t1 = msr / 8;
1442                 break;
1443         case 0xc0000000 ... 0xc0001fff:
1444                 t0 = (8192 + msr - 0xc0000000) * 2;
1445                 t1 = (t0 / 8);
1446                 t0 %= 8;
1447                 break;
1448         case 0xc0010000 ... 0xc0011fff:
1449                 t0 = (16384 + msr - 0xc0010000) * 2;
1450                 t1 = (t0 / 8);
1451                 t0 %= 8;
1452                 break;
1453         default:
1454                 return 1;
1455                 break;
1456         }
1457         if (msrpm[t1] & ((1 << param) << t0))
1458                 return 1;
1459
1460         return 0;
1461 }
1462
1463 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1464 {
1465         bool k = kvm_override;
1466
1467         switch (svm->vmcb->control.exit_code) {
1468         case SVM_EXIT_MSR:
1469                 return nested_svm_do(svm, svm->nested_vmcb,
1470                                      svm->nested_vmcb_msrpm, NULL,
1471                                      nested_svm_exit_handled_msr);
1472         default: break;
1473         }
1474
1475         return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1476                              nested_svm_exit_handled_real);
1477 }
1478
1479 static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1480                                   void *arg2, void *opaque)
1481 {
1482         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1483         struct vmcb *hsave = svm->hsave;
1484         u64 nested_save[] = { nested_vmcb->save.cr0,
1485                               nested_vmcb->save.cr3,
1486                               nested_vmcb->save.cr4,
1487                               nested_vmcb->save.efer,
1488                               nested_vmcb->control.intercept_cr_read,
1489                               nested_vmcb->control.intercept_cr_write,
1490                               nested_vmcb->control.intercept_dr_read,
1491                               nested_vmcb->control.intercept_dr_write,
1492                               nested_vmcb->control.intercept_exceptions,
1493                               nested_vmcb->control.intercept,
1494                               nested_vmcb->control.msrpm_base_pa,
1495                               nested_vmcb->control.iopm_base_pa,
1496                               nested_vmcb->control.tsc_offset };
1497
1498         /* Give the current vmcb to the guest */
1499         memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1500         nested_vmcb->save.cr0 = nested_save[0];
1501         if (!npt_enabled)
1502                 nested_vmcb->save.cr3 = nested_save[1];
1503         nested_vmcb->save.cr4 = nested_save[2];
1504         nested_vmcb->save.efer = nested_save[3];
1505         nested_vmcb->control.intercept_cr_read = nested_save[4];
1506         nested_vmcb->control.intercept_cr_write = nested_save[5];
1507         nested_vmcb->control.intercept_dr_read = nested_save[6];
1508         nested_vmcb->control.intercept_dr_write = nested_save[7];
1509         nested_vmcb->control.intercept_exceptions = nested_save[8];
1510         nested_vmcb->control.intercept = nested_save[9];
1511         nested_vmcb->control.msrpm_base_pa = nested_save[10];
1512         nested_vmcb->control.iopm_base_pa = nested_save[11];
1513         nested_vmcb->control.tsc_offset = nested_save[12];
1514
1515         /* We always set V_INTR_MASKING and remember the old value in hflags */
1516         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1517                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1518
1519         if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1520             (nested_vmcb->control.int_vector)) {
1521                 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1522                                 nested_vmcb->control.int_vector);
1523         }
1524
1525         /* Restore the original control entries */
1526         svm->vmcb->control = hsave->control;
1527
1528         /* Kill any pending exceptions */
1529         if (svm->vcpu.arch.exception.pending == true)
1530                 nsvm_printk("WARNING: Pending Exception\n");
1531         svm->vcpu.arch.exception.pending = false;
1532
1533         /* Restore selected save entries */
1534         svm->vmcb->save.es = hsave->save.es;
1535         svm->vmcb->save.cs = hsave->save.cs;
1536         svm->vmcb->save.ss = hsave->save.ss;
1537         svm->vmcb->save.ds = hsave->save.ds;
1538         svm->vmcb->save.gdtr = hsave->save.gdtr;
1539         svm->vmcb->save.idtr = hsave->save.idtr;
1540         svm->vmcb->save.rflags = hsave->save.rflags;
1541         svm_set_efer(&svm->vcpu, hsave->save.efer);
1542         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1543         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1544         if (npt_enabled) {
1545                 svm->vmcb->save.cr3 = hsave->save.cr3;
1546                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1547         } else {
1548                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1549         }
1550         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1551         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1552         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1553         svm->vmcb->save.dr7 = 0;
1554         svm->vmcb->save.cpl = 0;
1555         svm->vmcb->control.exit_int_info = 0;
1556
1557         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1558         /* Exit nested SVM mode */
1559         svm->nested_vmcb = 0;
1560
1561         return 0;
1562 }
1563
1564 static int nested_svm_vmexit(struct vcpu_svm *svm)
1565 {
1566         nsvm_printk("VMexit\n");
1567         if (nested_svm_do(svm, svm->nested_vmcb, 0,
1568                           NULL, nested_svm_vmexit_real))
1569                 return 1;
1570
1571         kvm_mmu_reset_context(&svm->vcpu);
1572         kvm_mmu_load(&svm->vcpu);
1573
1574         return 0;
1575 }
1576
1577 static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1578                                   void *arg2, void *opaque)
1579 {
1580         int i;
1581         u32 *nested_msrpm = (u32*)arg1;
1582         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1583                 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1584         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1585
1586         return 0;
1587 }
1588
1589 static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1590                             void *arg2, void *opaque)
1591 {
1592         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1593         struct vmcb *hsave = svm->hsave;
1594
1595         /* nested_vmcb is our indicator if nested SVM is activated */
1596         svm->nested_vmcb = svm->vmcb->save.rax;
1597
1598         /* Clear internal status */
1599         svm->vcpu.arch.exception.pending = false;
1600
1601         /* Save the old vmcb, so we don't need to pick what we save, but
1602            can restore everything when a VMEXIT occurs */
1603         memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1604         /* We need to remember the original CR3 in the SPT case */
1605         if (!npt_enabled)
1606                 hsave->save.cr3 = svm->vcpu.arch.cr3;
1607         hsave->save.cr4 = svm->vcpu.arch.cr4;
1608         hsave->save.rip = svm->next_rip;
1609
1610         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1611                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1612         else
1613                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1614
1615         /* Load the nested guest state */
1616         svm->vmcb->save.es = nested_vmcb->save.es;
1617         svm->vmcb->save.cs = nested_vmcb->save.cs;
1618         svm->vmcb->save.ss = nested_vmcb->save.ss;
1619         svm->vmcb->save.ds = nested_vmcb->save.ds;
1620         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1621         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1622         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1623         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1624         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1625         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1626         if (npt_enabled) {
1627                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1628                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1629         } else {
1630                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1631                 kvm_mmu_reset_context(&svm->vcpu);
1632         }
1633         svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1634         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1635         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1636         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1637         /* In case we don't even reach vcpu_run, the fields are not updated */
1638         svm->vmcb->save.rax = nested_vmcb->save.rax;
1639         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1640         svm->vmcb->save.rip = nested_vmcb->save.rip;
1641         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1642         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1643         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1644
1645         /* We don't want a nested guest to be more powerful than the guest,
1646            so all intercepts are ORed */
1647         svm->vmcb->control.intercept_cr_read |=
1648                 nested_vmcb->control.intercept_cr_read;
1649         svm->vmcb->control.intercept_cr_write |=
1650                 nested_vmcb->control.intercept_cr_write;
1651         svm->vmcb->control.intercept_dr_read |=
1652                 nested_vmcb->control.intercept_dr_read;
1653         svm->vmcb->control.intercept_dr_write |=
1654                 nested_vmcb->control.intercept_dr_write;
1655         svm->vmcb->control.intercept_exceptions |=
1656                 nested_vmcb->control.intercept_exceptions;
1657
1658         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1659
1660         svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1661
1662         force_new_asid(&svm->vcpu);
1663         svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1664         svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1665         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1666         if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1667                 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1668                                 nested_vmcb->control.int_ctl);
1669         }
1670         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1671                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1672         else
1673                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1674
1675         nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1676                         nested_vmcb->control.exit_int_info,
1677                         nested_vmcb->control.int_state);
1678
1679         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1680         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1681         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1682         if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1683                 nsvm_printk("Injecting Event: 0x%x\n",
1684                                 nested_vmcb->control.event_inj);
1685         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1686         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1687
1688         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1689
1690         return 0;
1691 }
1692
1693 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1694 {
1695         to_vmcb->save.fs = from_vmcb->save.fs;
1696         to_vmcb->save.gs = from_vmcb->save.gs;
1697         to_vmcb->save.tr = from_vmcb->save.tr;
1698         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1699         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1700         to_vmcb->save.star = from_vmcb->save.star;
1701         to_vmcb->save.lstar = from_vmcb->save.lstar;
1702         to_vmcb->save.cstar = from_vmcb->save.cstar;
1703         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1704         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1705         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1706         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1707
1708         return 1;
1709 }
1710
1711 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1712                              void *arg2, void *opaque)
1713 {
1714         return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1715 }
1716
1717 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1718                              void *arg2, void *opaque)
1719 {
1720         return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1721 }
1722
1723 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1724 {
1725         if (nested_svm_check_permissions(svm))
1726                 return 1;
1727
1728         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1729         skip_emulated_instruction(&svm->vcpu);
1730
1731         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1732
1733         return 1;
1734 }
1735
1736 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1737 {
1738         if (nested_svm_check_permissions(svm))
1739                 return 1;
1740
1741         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1742         skip_emulated_instruction(&svm->vcpu);
1743
1744         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1745
1746         return 1;
1747 }
1748
1749 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1750 {
1751         nsvm_printk("VMrun\n");
1752         if (nested_svm_check_permissions(svm))
1753                 return 1;
1754
1755         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1756         skip_emulated_instruction(&svm->vcpu);
1757
1758         if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1759                           NULL, nested_svm_vmrun))
1760                 return 1;
1761
1762         if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1763                       NULL, nested_svm_vmrun_msrpm))
1764                 return 1;
1765
1766         return 1;
1767 }
1768
1769 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1770 {
1771         if (nested_svm_check_permissions(svm))
1772                 return 1;
1773
1774         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1775         skip_emulated_instruction(&svm->vcpu);
1776
1777         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1778
1779         return 1;
1780 }
1781
1782 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1783 {
1784         if (nested_svm_check_permissions(svm))
1785                 return 1;
1786
1787         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1788         skip_emulated_instruction(&svm->vcpu);
1789
1790         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1791
1792         /* After a CLGI no interrupts should come */
1793         svm_clear_vintr(svm);
1794         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1795
1796         return 1;
1797 }
1798
1799 static int invalid_op_interception(struct vcpu_svm *svm,
1800                                    struct kvm_run *kvm_run)
1801 {
1802         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1803         return 1;
1804 }
1805
1806 static int task_switch_interception(struct vcpu_svm *svm,
1807                                     struct kvm_run *kvm_run)
1808 {
1809         u16 tss_selector;
1810         int reason;
1811         int int_type = svm->vmcb->control.exit_int_info &
1812                 SVM_EXITINTINFO_TYPE_MASK;
1813         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1814         uint32_t type =
1815                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1816         uint32_t idt_v =
1817                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1818
1819         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1820
1821         if (svm->vmcb->control.exit_info_2 &
1822             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1823                 reason = TASK_SWITCH_IRET;
1824         else if (svm->vmcb->control.exit_info_2 &
1825                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1826                 reason = TASK_SWITCH_JMP;
1827         else if (idt_v)
1828                 reason = TASK_SWITCH_GATE;
1829         else
1830                 reason = TASK_SWITCH_CALL;
1831
1832         if (reason == TASK_SWITCH_GATE) {
1833                 switch (type) {
1834                 case SVM_EXITINTINFO_TYPE_NMI:
1835                         svm->vcpu.arch.nmi_injected = false;
1836                         break;
1837                 case SVM_EXITINTINFO_TYPE_EXEPT:
1838                         kvm_clear_exception_queue(&svm->vcpu);
1839                         break;
1840                 case SVM_EXITINTINFO_TYPE_INTR:
1841                         kvm_clear_interrupt_queue(&svm->vcpu);
1842                         break;
1843                 default:
1844                         break;
1845                 }
1846         }
1847
1848         if (reason != TASK_SWITCH_GATE ||
1849             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
1850             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
1851              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
1852                 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0,
1853                                         EMULTYPE_SKIP) != EMULATE_DONE)
1854                         return 0;
1855         }
1856
1857         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
1858 }
1859
1860 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1861 {
1862         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1863         kvm_emulate_cpuid(&svm->vcpu);
1864         return 1;
1865 }
1866
1867 static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1868 {
1869         ++svm->vcpu.stat.nmi_window_exits;
1870         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
1871         svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
1872         return 1;
1873 }
1874
1875 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1876 {
1877         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1878                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1879         return 1;
1880 }
1881
1882 static int emulate_on_interception(struct vcpu_svm *svm,
1883                                    struct kvm_run *kvm_run)
1884 {
1885         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1886                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1887         return 1;
1888 }
1889
1890 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1891 {
1892         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
1893         /* instruction emulation calls kvm_set_cr8() */
1894         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1895         if (irqchip_in_kernel(svm->vcpu.kvm)) {
1896                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1897                 return 1;
1898         }
1899         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
1900                 return 1;
1901         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1902         return 0;
1903 }
1904
1905 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1906 {
1907         struct vcpu_svm *svm = to_svm(vcpu);
1908
1909         switch (ecx) {
1910         case MSR_IA32_TIME_STAMP_COUNTER: {
1911                 u64 tsc;
1912
1913                 rdtscll(tsc);
1914                 *data = svm->vmcb->control.tsc_offset + tsc;
1915                 break;
1916         }
1917         case MSR_K6_STAR:
1918                 *data = svm->vmcb->save.star;
1919                 break;
1920 #ifdef CONFIG_X86_64
1921         case MSR_LSTAR:
1922                 *data = svm->vmcb->save.lstar;
1923                 break;
1924         case MSR_CSTAR:
1925                 *data = svm->vmcb->save.cstar;
1926                 break;
1927         case MSR_KERNEL_GS_BASE:
1928                 *data = svm->vmcb->save.kernel_gs_base;
1929                 break;
1930         case MSR_SYSCALL_MASK:
1931                 *data = svm->vmcb->save.sfmask;
1932                 break;
1933 #endif
1934         case MSR_IA32_SYSENTER_CS:
1935                 *data = svm->vmcb->save.sysenter_cs;
1936                 break;
1937         case MSR_IA32_SYSENTER_EIP:
1938                 *data = svm->vmcb->save.sysenter_eip;
1939                 break;
1940         case MSR_IA32_SYSENTER_ESP:
1941                 *data = svm->vmcb->save.sysenter_esp;
1942                 break;
1943         /* Nobody will change the following 5 values in the VMCB so
1944            we can safely return them on rdmsr. They will always be 0
1945            until LBRV is implemented. */
1946         case MSR_IA32_DEBUGCTLMSR:
1947                 *data = svm->vmcb->save.dbgctl;
1948                 break;
1949         case MSR_IA32_LASTBRANCHFROMIP:
1950                 *data = svm->vmcb->save.br_from;
1951                 break;
1952         case MSR_IA32_LASTBRANCHTOIP:
1953                 *data = svm->vmcb->save.br_to;
1954                 break;
1955         case MSR_IA32_LASTINTFROMIP:
1956                 *data = svm->vmcb->save.last_excp_from;
1957                 break;
1958         case MSR_IA32_LASTINTTOIP:
1959                 *data = svm->vmcb->save.last_excp_to;
1960                 break;
1961         case MSR_VM_HSAVE_PA:
1962                 *data = svm->hsave_msr;
1963                 break;
1964         case MSR_VM_CR:
1965                 *data = 0;
1966                 break;
1967         case MSR_IA32_UCODE_REV:
1968                 *data = 0x01000065;
1969                 break;
1970         default:
1971                 return kvm_get_msr_common(vcpu, ecx, data);
1972         }
1973         return 0;
1974 }
1975
1976 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1977 {
1978         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1979         u64 data;
1980
1981         if (svm_get_msr(&svm->vcpu, ecx, &data))
1982                 kvm_inject_gp(&svm->vcpu, 0);
1983         else {
1984                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1985                             (u32)(data >> 32), handler);
1986
1987                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
1988                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1989                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1990                 skip_emulated_instruction(&svm->vcpu);
1991         }
1992         return 1;
1993 }
1994
1995 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1996 {
1997         struct vcpu_svm *svm = to_svm(vcpu);
1998
1999         switch (ecx) {
2000         case MSR_IA32_TIME_STAMP_COUNTER: {
2001                 u64 tsc;
2002
2003                 rdtscll(tsc);
2004                 svm->vmcb->control.tsc_offset = data - tsc;
2005                 break;
2006         }
2007         case MSR_K6_STAR:
2008                 svm->vmcb->save.star = data;
2009                 break;
2010 #ifdef CONFIG_X86_64
2011         case MSR_LSTAR:
2012                 svm->vmcb->save.lstar = data;
2013                 break;
2014         case MSR_CSTAR:
2015                 svm->vmcb->save.cstar = data;
2016                 break;
2017         case MSR_KERNEL_GS_BASE:
2018                 svm->vmcb->save.kernel_gs_base = data;
2019                 break;
2020         case MSR_SYSCALL_MASK:
2021                 svm->vmcb->save.sfmask = data;
2022                 break;
2023 #endif
2024         case MSR_IA32_SYSENTER_CS:
2025                 svm->vmcb->save.sysenter_cs = data;
2026                 break;
2027         case MSR_IA32_SYSENTER_EIP:
2028                 svm->vmcb->save.sysenter_eip = data;
2029                 break;
2030         case MSR_IA32_SYSENTER_ESP:
2031                 svm->vmcb->save.sysenter_esp = data;
2032                 break;
2033         case MSR_IA32_DEBUGCTLMSR:
2034                 if (!svm_has(SVM_FEATURE_LBRV)) {
2035                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2036                                         __func__, data);
2037                         break;
2038                 }
2039                 if (data & DEBUGCTL_RESERVED_BITS)
2040                         return 1;
2041
2042                 svm->vmcb->save.dbgctl = data;
2043                 if (data & (1ULL<<0))
2044                         svm_enable_lbrv(svm);
2045                 else
2046                         svm_disable_lbrv(svm);
2047                 break;
2048         case MSR_K7_EVNTSEL0:
2049         case MSR_K7_EVNTSEL1:
2050         case MSR_K7_EVNTSEL2:
2051         case MSR_K7_EVNTSEL3:
2052         case MSR_K7_PERFCTR0:
2053         case MSR_K7_PERFCTR1:
2054         case MSR_K7_PERFCTR2:
2055         case MSR_K7_PERFCTR3:
2056                 /*
2057                  * Just discard all writes to the performance counters; this
2058                  * should keep both older linux and windows 64-bit guests
2059                  * happy
2060                  */
2061                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2062
2063                 break;
2064         case MSR_VM_HSAVE_PA:
2065                 svm->hsave_msr = data;
2066                 break;
2067         default:
2068                 return kvm_set_msr_common(vcpu, ecx, data);
2069         }
2070         return 0;
2071 }
2072
2073 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2074 {
2075         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2076         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2077                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2078
2079         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2080                     handler);
2081
2082         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2083         if (svm_set_msr(&svm->vcpu, ecx, data))
2084                 kvm_inject_gp(&svm->vcpu, 0);
2085         else
2086                 skip_emulated_instruction(&svm->vcpu);
2087         return 1;
2088 }
2089
2090 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2091 {
2092         if (svm->vmcb->control.exit_info_1)
2093                 return wrmsr_interception(svm, kvm_run);
2094         else
2095                 return rdmsr_interception(svm, kvm_run);
2096 }
2097
2098 static int interrupt_window_interception(struct vcpu_svm *svm,
2099                                    struct kvm_run *kvm_run)
2100 {
2101         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2102
2103         svm_clear_vintr(svm);
2104         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2105         /*
2106          * If the user space waits to inject interrupts, exit as soon as
2107          * possible
2108          */
2109         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2110             kvm_run->request_interrupt_window &&
2111             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2112                 ++svm->vcpu.stat.irq_window_exits;
2113                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2114                 return 0;
2115         }
2116
2117         return 1;
2118 }
2119
2120 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2121                                       struct kvm_run *kvm_run) = {
2122         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2123         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2124         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2125         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2126         /* for now: */
2127         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2128         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2129         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2130         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2131         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2132         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2133         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2134         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2135         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2136         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2137         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2138         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2139         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2140         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2141         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2142         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2143         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2144         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2145         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2146         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2147         [SVM_EXIT_INTR]                         = intr_interception,
2148         [SVM_EXIT_NMI]                          = nmi_interception,
2149         [SVM_EXIT_SMI]                          = nop_on_interception,
2150         [SVM_EXIT_INIT]                         = nop_on_interception,
2151         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2152         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2153         [SVM_EXIT_CPUID]                        = cpuid_interception,
2154         [SVM_EXIT_IRET]                         = iret_interception,
2155         [SVM_EXIT_INVD]                         = emulate_on_interception,
2156         [SVM_EXIT_HLT]                          = halt_interception,
2157         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2158         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
2159         [SVM_EXIT_IOIO]                         = io_interception,
2160         [SVM_EXIT_MSR]                          = msr_interception,
2161         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2162         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2163         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2164         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2165         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2166         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2167         [SVM_EXIT_STGI]                         = stgi_interception,
2168         [SVM_EXIT_CLGI]                         = clgi_interception,
2169         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
2170         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2171         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2172         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2173         [SVM_EXIT_NPF]                          = pf_interception,
2174 };
2175
2176 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2177 {
2178         struct vcpu_svm *svm = to_svm(vcpu);
2179         u32 exit_code = svm->vmcb->control.exit_code;
2180
2181         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2182                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2183
2184         if (is_nested(svm)) {
2185                 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2186                             exit_code, svm->vmcb->control.exit_info_1,
2187                             svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2188                 if (nested_svm_exit_handled(svm, true)) {
2189                         nested_svm_vmexit(svm);
2190                         nsvm_printk("-> #VMEXIT\n");
2191                         return 1;
2192                 }
2193         }
2194
2195         if (npt_enabled) {
2196                 int mmu_reload = 0;
2197                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2198                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2199                         mmu_reload = 1;
2200                 }
2201                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2202                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2203                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2204                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2205                                 kvm_inject_gp(vcpu, 0);
2206                                 return 1;
2207                         }
2208                 }
2209                 if (mmu_reload) {
2210                         kvm_mmu_reset_context(vcpu);
2211                         kvm_mmu_load(vcpu);
2212                 }
2213         }
2214
2215
2216         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2217                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2218                 kvm_run->fail_entry.hardware_entry_failure_reason
2219                         = svm->vmcb->control.exit_code;
2220                 return 0;
2221         }
2222
2223         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2224             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2225             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2226                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2227                        "exit_code 0x%x\n",
2228                        __func__, svm->vmcb->control.exit_int_info,
2229                        exit_code);
2230
2231         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2232             || !svm_exit_handlers[exit_code]) {
2233                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2234                 kvm_run->hw.hardware_exit_reason = exit_code;
2235                 return 0;
2236         }
2237
2238         return svm_exit_handlers[exit_code](svm, kvm_run);
2239 }
2240
2241 static void reload_tss(struct kvm_vcpu *vcpu)
2242 {
2243         int cpu = raw_smp_processor_id();
2244
2245         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2246         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2247         load_TR_desc();
2248 }
2249
2250 static void pre_svm_run(struct vcpu_svm *svm)
2251 {
2252         int cpu = raw_smp_processor_id();
2253
2254         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2255
2256         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2257         if (svm->vcpu.cpu != cpu ||
2258             svm->asid_generation != svm_data->asid_generation)
2259                 new_asid(svm, svm_data);
2260 }
2261
2262 static void svm_drop_interrupt_shadow(struct kvm_vcpu *vcpu)
2263 {
2264         struct vcpu_svm *svm = to_svm(vcpu);
2265         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
2266 }
2267
2268 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2269 {
2270         struct vcpu_svm *svm = to_svm(vcpu);
2271
2272         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2273         vcpu->arch.hflags |= HF_NMI_MASK;
2274         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2275         ++vcpu->stat.nmi_injections;
2276 }
2277
2278 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2279 {
2280         struct vmcb_control_area *control;
2281
2282         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2283
2284         ++svm->vcpu.stat.irq_injections;
2285         control = &svm->vmcb->control;
2286         control->int_vector = irq;
2287         control->int_ctl &= ~V_INTR_PRIO_MASK;
2288         control->int_ctl |= V_IRQ_MASK |
2289                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2290 }
2291
2292 static void svm_queue_irq(struct kvm_vcpu *vcpu, unsigned nr)
2293 {
2294         struct vcpu_svm *svm = to_svm(vcpu);
2295
2296         svm->vmcb->control.event_inj = nr |
2297                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2298 }
2299
2300 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
2301 {
2302         struct vcpu_svm *svm = to_svm(vcpu);
2303
2304         nested_svm_intr(svm);
2305
2306         svm_queue_irq(vcpu, irq);
2307 }
2308
2309 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2310 {
2311         struct vcpu_svm *svm = to_svm(vcpu);
2312
2313         if (irr == -1)
2314                 return;
2315
2316         if (tpr >= irr)
2317                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2318 }
2319
2320 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2321 {
2322         struct vcpu_svm *svm = to_svm(vcpu);
2323         struct vmcb *vmcb = svm->vmcb;
2324         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2325                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2326 }
2327
2328 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2329 {
2330         struct vcpu_svm *svm = to_svm(vcpu);
2331         struct vmcb *vmcb = svm->vmcb;
2332         return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2333                 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2334                 (svm->vcpu.arch.hflags & HF_GIF_MASK);
2335 }
2336
2337 static void enable_irq_window(struct kvm_vcpu *vcpu)
2338 {
2339         svm_set_vintr(to_svm(vcpu));
2340         svm_inject_irq(to_svm(vcpu), 0x0);
2341 }
2342
2343 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2344 {
2345         struct vcpu_svm *svm = to_svm(vcpu);
2346
2347         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
2348                 enable_irq_window(vcpu);
2349 }
2350
2351 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2352 {
2353         return 0;
2354 }
2355
2356 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2357 {
2358         force_new_asid(vcpu);
2359 }
2360
2361 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2362 {
2363 }
2364
2365 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2366 {
2367         struct vcpu_svm *svm = to_svm(vcpu);
2368
2369         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2370                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2371                 kvm_set_cr8(vcpu, cr8);
2372         }
2373 }
2374
2375 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2376 {
2377         struct vcpu_svm *svm = to_svm(vcpu);
2378         u64 cr8;
2379
2380         cr8 = kvm_get_cr8(vcpu);
2381         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2382         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2383 }
2384
2385 static void svm_complete_interrupts(struct vcpu_svm *svm)
2386 {
2387         u8 vector;
2388         int type;
2389         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2390
2391         svm->vcpu.arch.nmi_injected = false;
2392         kvm_clear_exception_queue(&svm->vcpu);
2393         kvm_clear_interrupt_queue(&svm->vcpu);
2394
2395         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2396                 return;
2397
2398         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2399         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2400
2401         switch (type) {
2402         case SVM_EXITINTINFO_TYPE_NMI:
2403                 svm->vcpu.arch.nmi_injected = true;
2404                 break;
2405         case SVM_EXITINTINFO_TYPE_EXEPT:
2406                 /* In case of software exception do not reinject an exception
2407                    vector, but re-execute and instruction instead */
2408                 if (vector == BP_VECTOR || vector == OF_VECTOR)
2409                         break;
2410                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2411                         u32 err = svm->vmcb->control.exit_int_info_err;
2412                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2413
2414                 } else
2415                         kvm_queue_exception(&svm->vcpu, vector);
2416                 break;
2417         case SVM_EXITINTINFO_TYPE_INTR:
2418                 kvm_queue_interrupt(&svm->vcpu, vector);
2419                 break;
2420         default:
2421                 break;
2422         }
2423 }
2424
2425 #ifdef CONFIG_X86_64
2426 #define R "r"
2427 #else
2428 #define R "e"
2429 #endif
2430
2431 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2432 {
2433         struct vcpu_svm *svm = to_svm(vcpu);
2434         u16 fs_selector;
2435         u16 gs_selector;
2436         u16 ldt_selector;
2437
2438         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2439         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2440         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2441
2442         pre_svm_run(svm);
2443
2444         sync_lapic_to_cr8(vcpu);
2445
2446         save_host_msrs(vcpu);
2447         fs_selector = kvm_read_fs();
2448         gs_selector = kvm_read_gs();
2449         ldt_selector = kvm_read_ldt();
2450         svm->host_cr2 = kvm_read_cr2();
2451         if (!is_nested(svm))
2452                 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2453         /* required for live migration with NPT */
2454         if (npt_enabled)
2455                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2456
2457         clgi();
2458
2459         local_irq_enable();
2460
2461         asm volatile (
2462                 "push %%"R"bp; \n\t"
2463                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2464                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2465                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2466                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2467                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2468                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2469 #ifdef CONFIG_X86_64
2470                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2471                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2472                 "mov %c[r10](%[svm]), %%r10 \n\t"
2473                 "mov %c[r11](%[svm]), %%r11 \n\t"
2474                 "mov %c[r12](%[svm]), %%r12 \n\t"
2475                 "mov %c[r13](%[svm]), %%r13 \n\t"
2476                 "mov %c[r14](%[svm]), %%r14 \n\t"
2477                 "mov %c[r15](%[svm]), %%r15 \n\t"
2478 #endif
2479
2480                 /* Enter guest mode */
2481                 "push %%"R"ax \n\t"
2482                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2483                 __ex(SVM_VMLOAD) "\n\t"
2484                 __ex(SVM_VMRUN) "\n\t"
2485                 __ex(SVM_VMSAVE) "\n\t"
2486                 "pop %%"R"ax \n\t"
2487
2488                 /* Save guest registers, load host registers */
2489                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2490                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2491                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2492                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2493                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2494                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2495 #ifdef CONFIG_X86_64
2496                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2497                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2498                 "mov %%r10, %c[r10](%[svm]) \n\t"
2499                 "mov %%r11, %c[r11](%[svm]) \n\t"
2500                 "mov %%r12, %c[r12](%[svm]) \n\t"
2501                 "mov %%r13, %c[r13](%[svm]) \n\t"
2502                 "mov %%r14, %c[r14](%[svm]) \n\t"
2503                 "mov %%r15, %c[r15](%[svm]) \n\t"
2504 #endif
2505                 "pop %%"R"bp"
2506                 :
2507                 : [svm]"a"(svm),
2508                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2509                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2510                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2511                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2512                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2513                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2514                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2515 #ifdef CONFIG_X86_64
2516                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2517                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2518                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2519                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2520                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2521                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2522                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2523                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2524 #endif
2525                 : "cc", "memory"
2526                 , R"bx", R"cx", R"dx", R"si", R"di"
2527 #ifdef CONFIG_X86_64
2528                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2529 #endif
2530                 );
2531
2532         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2533         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2534         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2535         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2536
2537         kvm_write_cr2(svm->host_cr2);
2538
2539         kvm_load_fs(fs_selector);
2540         kvm_load_gs(gs_selector);
2541         kvm_load_ldt(ldt_selector);
2542         load_host_msrs(vcpu);
2543
2544         reload_tss(vcpu);
2545
2546         local_irq_disable();
2547
2548         stgi();
2549
2550         sync_cr8_to_lapic(vcpu);
2551
2552         svm->next_rip = 0;
2553
2554         svm_complete_interrupts(svm);
2555 }
2556
2557 #undef R
2558
2559 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2560 {
2561         struct vcpu_svm *svm = to_svm(vcpu);
2562
2563         if (npt_enabled) {
2564                 svm->vmcb->control.nested_cr3 = root;
2565                 force_new_asid(vcpu);
2566                 return;
2567         }
2568
2569         svm->vmcb->save.cr3 = root;
2570         force_new_asid(vcpu);
2571
2572         if (vcpu->fpu_active) {
2573                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2574                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2575                 vcpu->fpu_active = 0;
2576         }
2577 }
2578
2579 static int is_disabled(void)
2580 {
2581         u64 vm_cr;
2582
2583         rdmsrl(MSR_VM_CR, vm_cr);
2584         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2585                 return 1;
2586
2587         return 0;
2588 }
2589
2590 static void
2591 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2592 {
2593         /*
2594          * Patch in the VMMCALL instruction:
2595          */
2596         hypercall[0] = 0x0f;
2597         hypercall[1] = 0x01;
2598         hypercall[2] = 0xd9;
2599 }
2600
2601 static void svm_check_processor_compat(void *rtn)
2602 {
2603         *(int *)rtn = 0;
2604 }
2605
2606 static bool svm_cpu_has_accelerated_tpr(void)
2607 {
2608         return false;
2609 }
2610
2611 static int get_npt_level(void)
2612 {
2613 #ifdef CONFIG_X86_64
2614         return PT64_ROOT_LEVEL;
2615 #else
2616         return PT32E_ROOT_LEVEL;
2617 #endif
2618 }
2619
2620 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2621 {
2622         return 0;
2623 }
2624
2625 static struct kvm_x86_ops svm_x86_ops = {
2626         .cpu_has_kvm_support = has_svm,
2627         .disabled_by_bios = is_disabled,
2628         .hardware_setup = svm_hardware_setup,
2629         .hardware_unsetup = svm_hardware_unsetup,
2630         .check_processor_compatibility = svm_check_processor_compat,
2631         .hardware_enable = svm_hardware_enable,
2632         .hardware_disable = svm_hardware_disable,
2633         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2634
2635         .vcpu_create = svm_create_vcpu,
2636         .vcpu_free = svm_free_vcpu,
2637         .vcpu_reset = svm_vcpu_reset,
2638
2639         .prepare_guest_switch = svm_prepare_guest_switch,
2640         .vcpu_load = svm_vcpu_load,
2641         .vcpu_put = svm_vcpu_put,
2642
2643         .set_guest_debug = svm_guest_debug,
2644         .get_msr = svm_get_msr,
2645         .set_msr = svm_set_msr,
2646         .get_segment_base = svm_get_segment_base,
2647         .get_segment = svm_get_segment,
2648         .set_segment = svm_set_segment,
2649         .get_cpl = svm_get_cpl,
2650         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2651         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2652         .set_cr0 = svm_set_cr0,
2653         .set_cr3 = svm_set_cr3,
2654         .set_cr4 = svm_set_cr4,
2655         .set_efer = svm_set_efer,
2656         .get_idt = svm_get_idt,
2657         .set_idt = svm_set_idt,
2658         .get_gdt = svm_get_gdt,
2659         .set_gdt = svm_set_gdt,
2660         .get_dr = svm_get_dr,
2661         .set_dr = svm_set_dr,
2662         .get_rflags = svm_get_rflags,
2663         .set_rflags = svm_set_rflags,
2664
2665         .tlb_flush = svm_flush_tlb,
2666
2667         .run = svm_vcpu_run,
2668         .handle_exit = handle_exit,
2669         .skip_emulated_instruction = skip_emulated_instruction,
2670         .patch_hypercall = svm_patch_hypercall,
2671         .set_irq = svm_set_irq,
2672         .set_nmi = svm_inject_nmi,
2673         .queue_exception = svm_queue_exception,
2674         .interrupt_allowed = svm_interrupt_allowed,
2675         .nmi_allowed = svm_nmi_allowed,
2676         .enable_nmi_window = enable_nmi_window,
2677         .enable_irq_window = enable_irq_window,
2678         .update_cr8_intercept = update_cr8_intercept,
2679         .drop_interrupt_shadow = svm_drop_interrupt_shadow,
2680
2681         .set_tss_addr = svm_set_tss_addr,
2682         .get_tdp_level = get_npt_level,
2683         .get_mt_mask = svm_get_mt_mask,
2684 };
2685
2686 static int __init svm_init(void)
2687 {
2688         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2689                               THIS_MODULE);
2690 }
2691
2692 static void __exit svm_exit(void)
2693 {
2694         kvm_exit();
2695 }
2696
2697 module_init(svm_init)
2698 module_exit(svm_exit)