1 /* $Id: pci.c,v 1.39 2002/01/05 01:13:43 davem Exp $
2 * pci.c: UltraSparc PCI controller support.
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
9 #include <linux/config.h>
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/string.h>
13 #include <linux/sched.h>
14 #include <linux/capability.h>
15 #include <linux/errno.h>
16 #include <linux/smp_lock.h>
17 #include <linux/init.h>
19 #include <asm/uaccess.h>
21 #include <asm/pgtable.h>
26 unsigned long pci_memspace_mask = 0xffffffffUL;
29 /* A "nop" PCI implementation. */
30 asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
31 unsigned long off, unsigned long len,
36 asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
37 unsigned long off, unsigned long len,
44 /* List of all PCI controllers found in the system. */
45 struct pci_controller_info *pci_controller_root = NULL;
47 /* Each PCI controller found gets a unique index. */
48 int pci_num_controllers = 0;
50 /* At boot time the user can give the kernel a command
51 * line option which controls if and how PCI devices
52 * are reordered at PCI bus probing time.
54 int pci_device_reorder = 0;
56 volatile int pci_poke_in_progress;
57 volatile int pci_poke_cpu = -1;
58 volatile int pci_poke_faulted;
60 static DEFINE_SPINLOCK(pci_poke_lock);
62 void pci_config_read8(u8 *addr, u8 *ret)
67 spin_lock_irqsave(&pci_poke_lock, flags);
68 pci_poke_cpu = smp_processor_id();
69 pci_poke_in_progress = 1;
71 __asm__ __volatile__("membar #Sync\n\t"
72 "lduba [%1] %2, %0\n\t"
75 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
77 pci_poke_in_progress = 0;
79 if (!pci_poke_faulted)
81 spin_unlock_irqrestore(&pci_poke_lock, flags);
84 void pci_config_read16(u16 *addr, u16 *ret)
89 spin_lock_irqsave(&pci_poke_lock, flags);
90 pci_poke_cpu = smp_processor_id();
91 pci_poke_in_progress = 1;
93 __asm__ __volatile__("membar #Sync\n\t"
94 "lduha [%1] %2, %0\n\t"
97 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
99 pci_poke_in_progress = 0;
101 if (!pci_poke_faulted)
103 spin_unlock_irqrestore(&pci_poke_lock, flags);
106 void pci_config_read32(u32 *addr, u32 *ret)
111 spin_lock_irqsave(&pci_poke_lock, flags);
112 pci_poke_cpu = smp_processor_id();
113 pci_poke_in_progress = 1;
114 pci_poke_faulted = 0;
115 __asm__ __volatile__("membar #Sync\n\t"
116 "lduwa [%1] %2, %0\n\t"
119 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
121 pci_poke_in_progress = 0;
123 if (!pci_poke_faulted)
125 spin_unlock_irqrestore(&pci_poke_lock, flags);
128 void pci_config_write8(u8 *addr, u8 val)
132 spin_lock_irqsave(&pci_poke_lock, flags);
133 pci_poke_cpu = smp_processor_id();
134 pci_poke_in_progress = 1;
135 pci_poke_faulted = 0;
136 __asm__ __volatile__("membar #Sync\n\t"
137 "stba %0, [%1] %2\n\t"
140 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
142 pci_poke_in_progress = 0;
144 spin_unlock_irqrestore(&pci_poke_lock, flags);
147 void pci_config_write16(u16 *addr, u16 val)
151 spin_lock_irqsave(&pci_poke_lock, flags);
152 pci_poke_cpu = smp_processor_id();
153 pci_poke_in_progress = 1;
154 pci_poke_faulted = 0;
155 __asm__ __volatile__("membar #Sync\n\t"
156 "stha %0, [%1] %2\n\t"
159 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
161 pci_poke_in_progress = 0;
163 spin_unlock_irqrestore(&pci_poke_lock, flags);
166 void pci_config_write32(u32 *addr, u32 val)
170 spin_lock_irqsave(&pci_poke_lock, flags);
171 pci_poke_cpu = smp_processor_id();
172 pci_poke_in_progress = 1;
173 pci_poke_faulted = 0;
174 __asm__ __volatile__("membar #Sync\n\t"
175 "stwa %0, [%1] %2\n\t"
178 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
180 pci_poke_in_progress = 0;
182 spin_unlock_irqrestore(&pci_poke_lock, flags);
185 /* Probe for all PCI controllers in the system. */
186 extern void sabre_init(int, char *);
187 extern void psycho_init(int, char *);
188 extern void schizo_init(int, char *);
189 extern void schizo_plus_init(int, char *);
190 extern void tomatillo_init(int, char *);
194 void (*init)(int, char *);
195 } pci_controller_table[] __initdata = {
196 { "SUNW,sabre", sabre_init },
197 { "pci108e,a000", sabre_init },
198 { "pci108e,a001", sabre_init },
199 { "SUNW,psycho", psycho_init },
200 { "pci108e,8000", psycho_init },
201 { "SUNW,schizo", schizo_init },
202 { "pci108e,8001", schizo_init },
203 { "SUNW,schizo+", schizo_plus_init },
204 { "pci108e,8002", schizo_plus_init },
205 { "SUNW,tomatillo", tomatillo_init },
206 { "pci108e,a801", tomatillo_init },
208 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
209 sizeof(pci_controller_table[0]))
211 static int __init pci_controller_init(char *model_name, int namelen, int node)
215 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
216 if (!strncmp(model_name,
217 pci_controller_table[i].model_name,
219 pci_controller_table[i].init(node, model_name);
223 printk("PCI: Warning unknown controller, model name [%s]\n",
225 printk("PCI: Ignoring controller...\n");
230 static int __init pci_is_controller(char *model_name, int namelen, int node)
234 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
235 if (!strncmp(model_name,
236 pci_controller_table[i].model_name,
244 static int __init pci_controller_scan(int (*handler)(char *, int, int))
250 node = prom_getchild(prom_root_node);
251 while ((node = prom_searchsiblings(node, "pci")) != 0) {
254 if ((len = prom_getproperty(node, "model", namebuf, sizeof(namebuf))) > 0 ||
255 (len = prom_getproperty(node, "compatible", namebuf, sizeof(namebuf))) > 0) {
258 /* Our value may be a multi-valued string in the
259 * case of some compatible properties. For sanity,
260 * only try the first one. */
262 while (namebuf[item_len] && len) {
267 if (handler(namebuf, item_len, node))
271 node = prom_getsibling(node);
280 /* Is there some PCI controller in the system? */
281 int __init pcic_present(void)
283 return pci_controller_scan(pci_is_controller);
286 /* Find each controller in the system, attach and initialize
287 * software state structure for each and link into the
288 * pci_controller_root. Setup the controller enough such
289 * that bus scanning can be done.
291 static void __init pci_controller_probe(void)
293 printk("PCI: Probing for controllers.\n");
295 pci_controller_scan(pci_controller_init);
298 static void __init pci_scan_each_controller_bus(void)
300 struct pci_controller_info *p;
302 for (p = pci_controller_root; p; p = p->next)
306 /* Reorder the pci_dev chain, so that onboard devices come first
307 * and then come the pluggable cards.
309 static void __init pci_reorder_devs(void)
311 struct list_head *pci_onboard = &pci_devices;
312 struct list_head *walk = pci_onboard->next;
314 while (walk != pci_onboard) {
315 struct pci_dev *pdev = pci_dev_g(walk);
316 struct list_head *walk_next = walk->next;
318 if (pdev->irq && (__irq_ino(pdev->irq) & 0x20)) {
320 list_add(walk, pci_onboard);
327 extern void clock_probe(void);
328 extern void power_init(void);
330 static int __init pcibios_init(void)
332 pci_controller_probe();
333 if (pci_controller_root == NULL)
336 pci_scan_each_controller_bus();
338 if (pci_device_reorder)
349 subsys_initcall(pcibios_init);
351 void pcibios_fixup_bus(struct pci_bus *pbus)
353 struct pci_pbm_info *pbm = pbus->sysdata;
355 /* Generic PCI bus probing sets these to point at
356 * &io{port,mem}_resouce which is wrong for us.
358 pbus->resource[0] = &pbm->io_space;
359 pbus->resource[1] = &pbm->mem_space;
362 int pci_claim_resource(struct pci_dev *pdev, int resource)
364 struct pci_pbm_info *pbm = pdev->bus->sysdata;
365 struct resource *res = &pdev->resource[resource];
366 struct resource *root;
371 if (res->flags & IORESOURCE_IO)
372 root = &pbm->io_space;
374 root = &pbm->mem_space;
376 pbm->parent->resource_adjust(pdev, res, root);
378 return request_resource(root, res);
382 * Given the PCI bus a device resides on, try to
383 * find an acceptable resource allocation for a
384 * specific device resource..
386 static int pci_assign_bus_resource(const struct pci_bus *bus,
388 struct resource *res,
393 unsigned int type_mask;
396 type_mask = IORESOURCE_IO | IORESOURCE_MEM;
397 for (i = 0 ; i < 4; i++) {
398 struct resource *r = bus->resource[i];
402 /* type_mask must match */
403 if ((res->flags ^ r->flags) & type_mask)
406 /* Ok, try it out.. */
407 if (allocate_resource(r, res, size, min, -1, size, NULL, NULL) < 0)
410 /* PCI config space updated by caller. */
416 void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno)
418 /* Not implemented for sparc64... */
422 int pci_assign_resource(struct pci_dev *pdev, int resource)
424 struct pcidev_cookie *pcp = pdev->sysdata;
425 struct pci_pbm_info *pbm = pcp->pbm;
426 struct resource *res = &pdev->resource[resource];
427 unsigned long min, size;
430 if (res->flags & IORESOURCE_IO)
431 min = pbm->io_space.start + 0x400UL;
433 min = pbm->mem_space.start;
435 size = res->end - res->start + 1;
437 err = pci_assign_bus_resource(pdev->bus, pdev, res, size, min, resource);
440 printk("PCI: Failed to allocate resource %d for %s\n",
441 resource, pci_name(pdev));
443 /* Update PCI config space. */
444 pbm->parent->base_address_update(pdev, resource);
450 /* Sort resources by alignment */
451 void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
455 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
457 struct resource_list *list, *tmp;
458 unsigned long r_align;
460 r = &dev->resource[i];
461 r_align = r->end - r->start;
463 if (!(r->flags) || r->parent)
466 printk(KERN_WARNING "PCI: Ignore bogus resource %d "
468 i, r->start, r->end, pci_name(dev));
471 r_align = (i < PCI_BRIDGE_RESOURCES) ? r_align + 1 : r->start;
472 for (list = head; ; list = list->next) {
473 unsigned long align = 0;
474 struct resource_list *ln = list->next;
478 idx = ln->res - &ln->dev->resource[0];
479 align = (idx < PCI_BRIDGE_RESOURCES) ?
480 ln->res->end - ln->res->start + 1 :
483 if (r_align > align) {
484 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
486 panic("pdev_sort_resources(): "
487 "kmalloc() failed!\n");
498 void pcibios_update_irq(struct pci_dev *pdev, int irq)
502 void pcibios_align_resource(void *data, struct resource *res,
503 unsigned long size, unsigned long align)
507 int pcibios_enable_device(struct pci_dev *pdev, int mask)
512 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
513 struct resource *res)
515 struct pci_pbm_info *pbm = pdev->bus->sysdata;
516 struct resource zero_res, *root;
520 zero_res.flags = res->flags;
522 if (res->flags & IORESOURCE_IO)
523 root = &pbm->io_space;
525 root = &pbm->mem_space;
527 pbm->parent->resource_adjust(pdev, &zero_res, root);
529 region->start = res->start - zero_res.start;
530 region->end = res->end - zero_res.start;
533 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
534 struct pci_bus_region *region)
536 struct pci_pbm_info *pbm = pdev->bus->sysdata;
537 struct resource *root;
539 res->start = region->start;
540 res->end = region->end;
542 if (res->flags & IORESOURCE_IO)
543 root = &pbm->io_space;
545 root = &pbm->mem_space;
547 pbm->parent->resource_adjust(pdev, res, root);
550 char * __init pcibios_setup(char *str)
552 if (!strcmp(str, "onboardfirst")) {
553 pci_device_reorder = 1;
556 if (!strcmp(str, "noreorder")) {
557 pci_device_reorder = 0;
563 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
565 /* If the user uses a host-bridge as the PCI device, he may use
566 * this to perform a raw mmap() of the I/O or MEM space behind
569 * This can be useful for execution of x86 PCI bios initialization code
570 * on a PCI card, like the xfree86 int10 stuff does.
572 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
573 enum pci_mmap_state mmap_state)
575 struct pcidev_cookie *pcp = pdev->sysdata;
576 struct pci_pbm_info *pbm;
577 struct pci_controller_info *p;
578 unsigned long space_size, user_offset, user_size;
587 if (p->pbms_same_domain) {
588 unsigned long lowest, highest;
590 lowest = ~0UL; highest = 0UL;
591 if (mmap_state == pci_mmap_io) {
592 if (p->pbm_A.io_space.flags) {
593 lowest = p->pbm_A.io_space.start;
594 highest = p->pbm_A.io_space.end + 1;
596 if (p->pbm_B.io_space.flags) {
597 if (lowest > p->pbm_B.io_space.start)
598 lowest = p->pbm_B.io_space.start;
599 if (highest < p->pbm_B.io_space.end + 1)
600 highest = p->pbm_B.io_space.end + 1;
602 space_size = highest - lowest;
604 if (p->pbm_A.mem_space.flags) {
605 lowest = p->pbm_A.mem_space.start;
606 highest = p->pbm_A.mem_space.end + 1;
608 if (p->pbm_B.mem_space.flags) {
609 if (lowest > p->pbm_B.mem_space.start)
610 lowest = p->pbm_B.mem_space.start;
611 if (highest < p->pbm_B.mem_space.end + 1)
612 highest = p->pbm_B.mem_space.end + 1;
614 space_size = highest - lowest;
617 if (mmap_state == pci_mmap_io) {
618 space_size = (pbm->io_space.end -
619 pbm->io_space.start) + 1;
621 space_size = (pbm->mem_space.end -
622 pbm->mem_space.start) + 1;
626 /* Make sure the request is in range. */
627 user_offset = vma->vm_pgoff << PAGE_SHIFT;
628 user_size = vma->vm_end - vma->vm_start;
630 if (user_offset >= space_size ||
631 (user_offset + user_size) > space_size)
634 if (p->pbms_same_domain) {
635 unsigned long lowest = ~0UL;
637 if (mmap_state == pci_mmap_io) {
638 if (p->pbm_A.io_space.flags)
639 lowest = p->pbm_A.io_space.start;
640 if (p->pbm_B.io_space.flags &&
641 lowest > p->pbm_B.io_space.start)
642 lowest = p->pbm_B.io_space.start;
644 if (p->pbm_A.mem_space.flags)
645 lowest = p->pbm_A.mem_space.start;
646 if (p->pbm_B.mem_space.flags &&
647 lowest > p->pbm_B.mem_space.start)
648 lowest = p->pbm_B.mem_space.start;
650 vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT;
652 if (mmap_state == pci_mmap_io) {
653 vma->vm_pgoff = (pbm->io_space.start +
654 user_offset) >> PAGE_SHIFT;
656 vma->vm_pgoff = (pbm->mem_space.start +
657 user_offset) >> PAGE_SHIFT;
664 /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
665 * to the 32-bit pci bus offset for DEV requested by the user.
667 * Basically, the user finds the base address for his device which he wishes
668 * to mmap. They read the 32-bit value from the config space base register,
669 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
670 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
672 * Returns negative error code on failure, zero on success.
674 static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
675 enum pci_mmap_state mmap_state)
677 unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
678 unsigned long user32 = user_offset & pci_memspace_mask;
679 unsigned long largest_base, this_base, addr32;
682 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
683 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
685 /* Figure out which base address this is for. */
687 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
688 struct resource *rp = &dev->resource[i];
695 if (i == PCI_ROM_RESOURCE) {
696 if (mmap_state != pci_mmap_mem)
699 if ((mmap_state == pci_mmap_io &&
700 (rp->flags & IORESOURCE_IO) == 0) ||
701 (mmap_state == pci_mmap_mem &&
702 (rp->flags & IORESOURCE_MEM) == 0))
706 this_base = rp->start;
708 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
710 if (mmap_state == pci_mmap_io)
713 if (addr32 <= user32 && this_base > largest_base)
714 largest_base = this_base;
717 if (largest_base == 0UL)
720 /* Now construct the final physical address. */
721 if (mmap_state == pci_mmap_io)
722 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
724 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
729 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
732 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
733 enum pci_mmap_state mmap_state)
735 vma->vm_flags |= (VM_IO | VM_RESERVED);
738 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
741 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
742 enum pci_mmap_state mmap_state)
744 /* Our io_remap_page_range/io_remap_pfn_range takes care of this,
748 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
749 * for this architecture. The region in the process to map is described by vm_start
750 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
751 * The pci device structure is provided so that architectures may make mapping
752 * decisions on a per-device or per-bus basis.
754 * Returns a negative error code on failure, zero on success.
756 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
757 enum pci_mmap_state mmap_state,
762 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
766 __pci_mmap_set_flags(dev, vma, mmap_state);
767 __pci_mmap_set_pgprot(dev, vma, mmap_state);
769 ret = io_remap_pfn_range(vma, vma->vm_start,
771 vma->vm_end - vma->vm_start,
776 vma->vm_flags |= VM_IO;
780 /* Return the domain nuber for this pci bus */
782 int pci_domain_nr(struct pci_bus *pbus)
784 struct pci_pbm_info *pbm = pbus->sysdata;
787 if (pbm == NULL || pbm->parent == NULL) {
790 struct pci_controller_info *p = pbm->parent;
793 if (p->pbms_same_domain == 0)
795 ((pbm == &pbm->parent->pbm_B) ? 1 : 0));
800 EXPORT_SYMBOL(pci_domain_nr);
802 int pcibios_prep_mwi(struct pci_dev *dev)
804 /* We set correct PCI_CACHE_LINE_SIZE register values for every
805 * device probed on this platform. So there is nothing to check
806 * and this always succeeds.
811 #endif /* !(CONFIG_PCI) */