2 * General Purpose functions for the global management of the
3 * 8260 Communication Processor Module.
4 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
5 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
8 * In addition to the individual control of the communication
9 * channels, there are a few functions that globally affect the
10 * communication processor.
12 * Buffer descriptors must be allocated from the dual ported memory
13 * space. The allocator for that is here. When the communication
14 * process is reset, we reclaim the memory available. There is
15 * currently no deallocator for this memory.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/param.h>
21 #include <linux/string.h>
23 #include <linux/interrupt.h>
24 #include <linux/bootmem.h>
25 #include <linux/module.h>
27 #include <asm/mpc8260.h>
29 #include <asm/pgtable.h>
30 #include <asm/immap_cpm2.h>
32 #include <asm/rheap.h>
34 static void cpm2_dpinit(void);
35 cpm_cpm2_t *cpmp; /* Pointer to comm processor space */
37 /* We allocate this here because it is used almost exclusively for
38 * the communication processor devices.
40 cpm2_map_t *cpm2_immr;
42 #define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount
43 of space for CPM as it is larger
49 cpm2_immr = (cpm2_map_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
51 /* Reclaim the DP memory for our use.
55 /* Tell everyone where the comm processor resides.
57 cpmp = &cpm2_immr->im_cpm;
60 /* Set a baud rate generator. This needs lots of work. There are
61 * eight BRGs, which can be connected to the CPM channels or output
62 * as clocks. The BRGs are in two different block of internal
63 * memory mapped space.
64 * The baud rate clock is the system clock divided by something.
65 * It was set up long ago during the initial boot phase and is
67 * Baud rate clocks are zero-based in the driver code (as that maps
68 * to port numbers). Documentation uses 1-based numbering.
70 #define BRG_INT_CLK (((bd_t *)__res)->bi_brgfreq)
71 #define BRG_UART_CLK (BRG_INT_CLK/16)
73 /* This function is used by UARTS, or anything else that uses a 16x
77 cpm_setbrg(uint brg, uint rate)
81 /* This is good enough to get SMCs running.....
84 bp = (uint *)&cpm2_immr->im_brgc1;
87 bp = (uint *)&cpm2_immr->im_brgc5;
91 *bp = ((BRG_UART_CLK / rate) << 1) | CPM_BRG_EN;
94 /* This function is used to set high speed synchronous baud rate
98 cpm2_fastbrg(uint brg, uint rate, int div16)
103 bp = (uint *)&cpm2_immr->im_brgc1;
106 bp = (uint *)&cpm2_immr->im_brgc5;
110 *bp = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN;
112 *bp |= CPM_BRG_DIV16;
116 * dpalloc / dpfree bits.
118 static spinlock_t cpm_dpmem_lock;
119 /* 16 blocks should be enough to satisfy all requests
120 * until the memory subsystem goes up... */
121 static rh_block_t cpm_boot_dpmem_rh_block[16];
122 static rh_info_t cpm_dpmem_info;
124 static void cpm2_dpinit(void)
126 spin_lock_init(&cpm_dpmem_lock);
128 /* initialize the info header */
129 rh_init(&cpm_dpmem_info, 1,
130 sizeof(cpm_boot_dpmem_rh_block) /
131 sizeof(cpm_boot_dpmem_rh_block[0]),
132 cpm_boot_dpmem_rh_block);
134 /* Attach the usable dpmem area */
135 /* XXX: This is actually crap. CPM_DATAONLY_BASE and
136 * CPM_DATAONLY_SIZE is only a subset of the available dpram. It
137 * varies with the processor and the microcode patches activated.
138 * But the following should be at least safe.
140 rh_attach_region(&cpm_dpmem_info, (void *)CPM_DATAONLY_BASE,
144 /* This function returns an index into the DPRAM area.
146 uint cpm_dpalloc(uint size, uint align)
151 spin_lock_irqsave(&cpm_dpmem_lock, flags);
152 cpm_dpmem_info.alignment = align;
153 start = rh_alloc(&cpm_dpmem_info, size, "commproc");
154 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
158 EXPORT_SYMBOL(cpm_dpalloc);
160 int cpm_dpfree(uint offset)
165 spin_lock_irqsave(&cpm_dpmem_lock, flags);
166 ret = rh_free(&cpm_dpmem_info, (void *)offset);
167 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
171 EXPORT_SYMBOL(cpm_dpfree);
173 /* not sure if this is ever needed */
174 uint cpm_dpalloc_fixed(uint offset, uint size, uint align)
179 spin_lock_irqsave(&cpm_dpmem_lock, flags);
180 cpm_dpmem_info.alignment = align;
181 start = rh_alloc_fixed(&cpm_dpmem_info, (void *)offset, size, "commproc");
182 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
186 EXPORT_SYMBOL(cpm_dpalloc_fixed);
188 void cpm_dpdump(void)
190 rh_dump(&cpm_dpmem_info);
192 EXPORT_SYMBOL(cpm_dpdump);
194 void *cpm_dpram_addr(uint offset)
196 return (void *)&cpm2_immr->im_dprambase[offset];
198 EXPORT_SYMBOL(cpm_dpram_addr);