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   1 /*
   2  *  arch/ppc64/kernel/cputable.c
   3  *
   4  *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
   5  *
   6  *  Modifications for ppc64:
   7  *      Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
   8  *
   9  *  This program is free software; you can redistribute it and/or
  10  *  modify it under the terms of the GNU General Public License
  11  *  as published by the Free Software Foundation; either version
  12  *  2 of the License, or (at your option) any later version.
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/string.h>
  17 #include <linux/sched.h>
  18 #include <linux/threads.h>
  19 #include <linux/init.h>
  20 #include <linux/module.h>
  21
  22 #include <asm/cputable.h>
  23
  24 struct cpu_spec* cur_cpu_spec = NULL;
  25 EXPORT_SYMBOL(cur_cpu_spec);
  26
  27 /* NOTE:
  28  * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  29  * the responsibility of the appropriate CPU save/restore functions to
  30  * eventually copy these settings over. Those save/restore aren't yet
  31  * part of the cputable though. That has to be fixed for both ppc32
  32  * and ppc64
  33  */
  34 extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec);
  35 extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
  36 extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  37 extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
  38
  39
  40 /* We only set the altivec features if the kernel was compiled with altivec
  41  * support
  42  */
  43 #ifdef CONFIG_ALTIVEC
  44 #define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
  45 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
  46 #else
  47 #define CPU_FTR_ALTIVEC_COMP    0
  48 #define PPC_FEATURE_HAS_ALTIVEC_COMP    0
  49 #endif
  50
  51 struct cpu_spec cpu_specs[] = {
  52     {   /* Power3 */
  53             0xffff0000, 0x00400000, "POWER3 (630)",
  54             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
  55                     CPU_FTR_IABR | CPU_FTR_PMC8,
  56             COMMON_USER_PPC64,
  57             128, 128,
  58             __setup_cpu_power3,
  59             COMMON_PPC64_FW
  60     },
  61     {   /* Power3+ */
  62             0xffff0000, 0x00410000, "POWER3 (630+)",
  63             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
  64                     CPU_FTR_IABR | CPU_FTR_PMC8,
  65             COMMON_USER_PPC64,
  66             128, 128,
  67             __setup_cpu_power3,
  68             COMMON_PPC64_FW
  69     },
  70     {   /* Northstar */
  71             0xffff0000, 0x00330000, "RS64-II (northstar)",
  72             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
  73                     CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
  74             COMMON_USER_PPC64,
  75             128, 128,
  76             __setup_cpu_power3,
  77             COMMON_PPC64_FW
  78     },
  79     {   /* Pulsar */
  80             0xffff0000, 0x00340000, "RS64-III (pulsar)",
  81             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
  82                     CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
  83             COMMON_USER_PPC64,
  84             128, 128,
  85             __setup_cpu_power3,
  86             COMMON_PPC64_FW
  87     },
  88     {   /* I-star */
  89             0xffff0000, 0x00360000, "RS64-III (icestar)",
  90             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
  91                     CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
  92             COMMON_USER_PPC64,
  93             128, 128,
  94             __setup_cpu_power3,
  95             COMMON_PPC64_FW
  96     },
  97     {   /* S-star */
  98             0xffff0000, 0x00370000, "RS64-IV (sstar)",
  99             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 100                     CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 101             COMMON_USER_PPC64,
 102             128, 128,
 103             __setup_cpu_power3,
 104             COMMON_PPC64_FW
 105     },
 106     {   /* Power4 */
 107             0xffff0000, 0x00350000, "POWER4 (gp)",
 108             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 109                     CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 110             COMMON_USER_PPC64,
 111             128, 128,
 112             __setup_cpu_power4,
 113             COMMON_PPC64_FW
 114     },
 115     {   /* Power4+ */
 116             0xffff0000, 0x00380000, "POWER4+ (gq)",
 117             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 118                     CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 119             COMMON_USER_PPC64,
 120             128, 128,
 121             __setup_cpu_power4,
 122             COMMON_PPC64_FW
 123     },
 124     {   /* PPC970 */
 125             0xffff0000, 0x00390000, "PPC970",
 126             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 127                     CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 128                     CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 129             COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
 130             128, 128,
 131             __setup_cpu_ppc970,
 132             COMMON_PPC64_FW
 133     },
 134     {   /* PPC970FX */
 135             0xffff0000, 0x003c0000, "PPC970FX",
 136             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 137                     CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 138                     CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 139             COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
 140             128, 128,
 141             __setup_cpu_ppc970,
 142             COMMON_PPC64_FW
 143     },
 144     {   /* Power5 */
 145             0xffff0000, 0x003a0000, "POWER5 (gr)",
 146             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 147                     CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
 148                     CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
 149                     CPU_FTR_MMCRA_SIHV,
 150             COMMON_USER_PPC64,
 151             128, 128,
 152             __setup_cpu_power4,
 153             COMMON_PPC64_FW
 154     },
 155     {   /* Power5 */
 156             0xffff0000, 0x003b0000, "POWER5 (gs)",
 157             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 158                     CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
 159                     CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
 160                     CPU_FTR_MMCRA_SIHV,
 161             COMMON_USER_PPC64,
 162             128, 128,
 163             __setup_cpu_power4,
 164             COMMON_PPC64_FW
 165     },
 166     {   /* BE DD1.x  */
 167             0xffff0000, 0x00700000, "Broadband Engine",
 168             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 169                     CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 170                     CPU_FTR_SMT,
 171             COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
 172             128, 128,
 173             __setup_cpu_be,
 174             COMMON_PPC64_FW
 175     },
 176     {   /* default match */
 177             0x00000000, 0x00000000, "POWER4 (compatible)",
 178             CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 179                     CPU_FTR_PPCAS_ARCH_V2,
 180             COMMON_USER_PPC64,
 181             128, 128,
 182             __setup_cpu_power4,
 183             COMMON_PPC64_FW
 184     }
 185 };
 186
 187 firmware_feature_t firmware_features_table[FIRMWARE_MAX_FEATURES] = {
 188     {FW_FEATURE_PFT,            "hcall-pft"},
 189     {FW_FEATURE_TCE,            "hcall-tce"},
 190     {FW_FEATURE_SPRG0,          "hcall-sprg0"},
 191     {FW_FEATURE_DABR,           "hcall-dabr"},
 192     {FW_FEATURE_COPY,           "hcall-copy"},
 193     {FW_FEATURE_ASR,            "hcall-asr"},
 194     {FW_FEATURE_DEBUG,          "hcall-debug"},
 195     {FW_FEATURE_PERF,           "hcall-perf"},
 196     {FW_FEATURE_DUMP,           "hcall-dump"},
 197     {FW_FEATURE_INTERRUPT,      "hcall-interrupt"},
 198     {FW_FEATURE_MIGRATE,        "hcall-migrate"},
 199     {FW_FEATURE_PERFMON,        "hcall-perfmon"},
 200     {FW_FEATURE_CRQ,            "hcall-crq"},
 201     {FW_FEATURE_VIO,            "hcall-vio"},
 202     {FW_FEATURE_RDMA,           "hcall-rdma"},
 203     {FW_FEATURE_LLAN,           "hcall-lLAN"},
 204     {FW_FEATURE_BULK,           "hcall-bulk"},
 205     {FW_FEATURE_XDABR,          "hcall-xdabr"},
 206     {FW_FEATURE_MULTITCE,       "hcall-multi-tce"},
 207     {FW_FEATURE_SPLPAR,         "hcall-splpar"},
 208 };