3 * Copyright (C) 2001 MontaVista Software, ppopov@mvista.com
4 * Copied and modified Carsten Langgaard's time.c
6 * Carsten Langgaard, carstenl@mips.com
7 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
9 * ########################################################################
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 * ########################################################################
26 * Setting up the clock on the MIPS boards.
28 * Update. Always configure the kernel with CONFIG_NEW_TIME_C. This
29 * will use the user interface gettimeofday() functions from the
30 * arch/mips/kernel/time.c, and we provide the clock interrupt processing
31 * and the timer offset compute functions. If CONFIG_PM is selected,
32 * we also ensure the 32KHz timer is available. -- Dan
35 #include <linux/types.h>
36 #include <linux/init.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/sched.h>
39 #include <linux/spinlock.h>
40 #include <linux/hardirq.h>
42 #include <asm/compiler.h>
43 #include <asm/mipsregs.h>
44 #include <asm/ptrace.h>
46 #include <asm/div64.h>
47 #include <asm/mach-au1x00/au1000.h>
49 #include <linux/mc146818rtc.h>
50 #include <linux/timex.h>
52 static unsigned long r4k_offset; /* Amount to increment compare reg each time */
53 static unsigned long r4k_cur; /* What counter should be at next timer irq */
55 extern int allow_au1k_wait; /* default off for CP0 Counter */
57 /* Cycle counter value at the previous timer interrupt.. */
58 static unsigned int timerhi = 0, timerlo = 0;
61 #if HZ < 100 || HZ > 1000
62 #error "unsupported HZ value! Must be in [100,1000]"
64 #define MATCH20_INC (328*100/HZ) /* magic number 328 is for HZ=100... */
65 extern void startup_match20_interrupt(irqreturn_t (*handler)(int, void *));
66 static unsigned long last_pc0, last_match20;
69 static DEFINE_SPINLOCK(time_lock);
71 static inline void ack_r4ktimer(unsigned long newval)
73 write_c0_compare(newval);
77 * There are a lot of conceptually broken versions of the MIPS timer interrupt
78 * handler floating around. This one is rather different, but the algorithm
79 * is provably more robust.
83 void mips_timer_interrupt(void)
89 kstat_this_cpu.irqs[irq]++;
95 count = read_c0_count();
96 timerhi += (count < timerlo); /* Wrap around */
99 kstat_this_cpu.irqs[irq]++;
102 update_process_times(user_mode(get_irq_regs()));
104 r4k_cur += r4k_offset;
105 ack_r4ktimer(r4k_cur);
107 } while (((unsigned long)read_c0_count()
108 - r4k_cur) < 0x7fffffff);
119 irqreturn_t counter0_irq(int irq, void *dev_id)
123 static int jiffie_drift = 0;
125 if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
126 /* should never happen! */
127 printk(KERN_WARNING "counter 0 w status error\n");
131 pc0 = au_readl(SYS_TOYREAD);
132 if (pc0 < last_match20) {
133 /* counter overflowed */
134 time_elapsed = (0xffffffff - last_match20) + pc0;
137 time_elapsed = pc0 - last_match20;
140 while (time_elapsed > 0) {
143 update_process_times(user_mode(get_irq_regs()));
145 time_elapsed -= MATCH20_INC;
146 last_match20 += MATCH20_INC;
151 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
154 /* our counter ticks at 10.009765625 ms/tick, we we're running
155 * almost 10uS too slow per tick.
158 if (jiffie_drift >= 999) {
160 do_timer(1); /* increment jiffies by one */
162 update_process_times(user_mode(get_irq_regs()));
169 /* When we wakeup from sleep, we have to "catch up" on all of the
170 * timer ticks we have missed.
173 wakeup_counter0_adjust(void)
178 pc0 = au_readl(SYS_TOYREAD);
179 if (pc0 < last_match20) {
180 /* counter overflowed */
181 time_elapsed = (0xffffffff - last_match20) + pc0;
184 time_elapsed = pc0 - last_match20;
187 while (time_elapsed > 0) {
188 time_elapsed -= MATCH20_INC;
189 last_match20 += MATCH20_INC;
193 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
198 /* This is just for debugging to set the timer for a sleep delay.
201 wakeup_counter0_set(int ticks)
205 pc0 = au_readl(SYS_TOYREAD);
207 au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2);
212 /* I haven't found anyone that doesn't use a 12 MHz source clock,
213 * but just in case.....
215 #ifdef CONFIG_AU1000_SRC_CLK
216 #define AU1000_SRC_CLK CONFIG_AU1000_SRC_CLK
218 #define AU1000_SRC_CLK 12000000
222 * We read the real processor speed from the PLL. This is important
223 * because it is more accurate than computing it from the 32KHz
224 * counter, if it exists. If we don't have an accurate processor
225 * speed, all of the peripherals that derive their clocks based on
226 * this advertised speed will introduce error and sometimes not work
227 * properly. This function is futher convoluted to still allow configurations
228 * to do that in case they have really, really old silicon with a
229 * write-only PLL register, that we need the 32KHz when power management
230 * "wait" is enabled, and we need to detect if the 32KHz isn't present
231 * but requested......got it? :-) -- Dan
233 unsigned long cal_r4koff(void)
236 unsigned long cpu_speed;
238 unsigned long counter;
240 spin_lock_irqsave(&time_lock, flags);
242 /* Power management cares if we don't have a 32KHz counter.
245 counter = au_readl(SYS_COUNTER_CNTRL);
246 if (counter & SYS_CNTRL_E0) {
247 int trim_divide = 16;
249 au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
251 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
252 /* RTC now ticks at 32.768/16 kHz */
253 au_writel(trim_divide-1, SYS_RTCTRIM);
254 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
256 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
257 au_writel (0, SYS_TOYWRITE);
258 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
260 #if defined(CONFIG_AU1000_USE32K)
262 unsigned long start, end;
264 start = au_readl(SYS_RTCREAD);
266 /* wait for the beginning of a new tick
268 while (au_readl(SYS_RTCREAD) < start);
270 /* Start r4k counter.
276 end = start + (32768 / trim_divide)/2;
278 while (end > au_readl(SYS_RTCREAD));
280 count = read_c0_count();
281 cpu_speed = count * 2;
284 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
286 count = cpu_speed / 2;
290 /* The 32KHz oscillator isn't running, so assume there
291 * isn't one and grab the processor speed from the PLL.
292 * NOTE: some old silicon doesn't allow reading the PLL.
294 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
295 count = cpu_speed / 2;
298 mips_hpt_frequency = count;
299 // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
300 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
301 spin_unlock_irqrestore(&time_lock, flags);
302 return (cpu_speed / HZ);
305 /* This is for machines which generate the exact clock. */
306 #define USECS_PER_JIFFY (1000000/HZ)
307 #define USECS_PER_JIFFY_FRAC (0x100000000LL*1000000/HZ&0xffffffff)
310 div64_32(unsigned long v1, unsigned long v2, unsigned long v3)
313 do_div64_32(r0, v1, v2, v3);
317 static unsigned long do_fast_cp0_gettimeoffset(void)
320 unsigned long res, tmp;
323 /* Last jiffy when do_fast_gettimeoffset() was called. */
324 static unsigned long last_jiffies=0;
325 unsigned long quotient;
328 * Cached "1/(clocks per usec)*2^32" value.
329 * It has to be recalculated once each jiffy.
331 static unsigned long cached_quotient=0;
335 quotient = cached_quotient;
337 if (tmp && last_jiffies != tmp) {
339 if (last_jiffies != 0) {
340 r0 = div64_32(timerhi, timerlo, tmp);
341 quotient = div64_32(USECS_PER_JIFFY, USECS_PER_JIFFY_FRAC, r0);
342 cached_quotient = quotient;
346 /* Get last timer tick in absolute kernel time */
347 count = read_c0_count();
349 /* .. relative to previous jiffy (32 bits is enough) */
352 __asm__("multu\t%1,%2\n\t"
355 : "r" (count), "r" (quotient)
356 : "hi", "lo", GCC_REG_ACCUM);
359 * Due to possible jiffies inconsistencies, we need to check
360 * the result so that we'll get a timer that is monotonic.
362 if (res >= USECS_PER_JIFFY)
363 res = USECS_PER_JIFFY-1;
369 static unsigned long do_fast_pm_gettimeoffset(void)
372 unsigned long offset;
374 pc0 = au_readl(SYS_TOYREAD);
376 offset = pc0 - last_pc0;
377 if (offset > 2*MATCH20_INC) {
378 printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",
379 (unsigned)offset, (unsigned)last_pc0,
380 (unsigned)last_match20, (unsigned)pc0);
382 offset = (unsigned long)((offset * 305) / 10);
387 void __init plat_timer_setup(struct irqaction *irq)
389 unsigned int est_freq;
391 printk("calculating r4koff... ");
392 r4k_offset = cal_r4koff();
393 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
395 //est_freq = 2*r4k_offset*HZ;
396 est_freq = r4k_offset*HZ;
397 est_freq += 5000; /* round */
398 est_freq -= est_freq%10000;
399 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
400 (est_freq%1000000)*100/1000000);
401 set_au1x00_speed(est_freq);
402 set_au1x00_lcd_clock(); // program the LCD clock
404 r4k_cur = (read_c0_count() + r4k_offset);
405 write_c0_compare(r4k_cur);
409 * setup counter 0, since it keeps ticking after a
410 * 'wait' instruction has been executed. The CP0 timer and
411 * counter 1 do NOT continue running after 'wait'
413 * It's too early to call request_irq() here, so we handle
414 * counter 0 interrupt as a special irq and it doesn't show
415 * up under /proc/interrupts.
417 * Check to ensure we really have a 32KHz oscillator before
420 if (no_au1xxx_32khz) {
421 unsigned int c0_status;
423 printk("WARNING: no 32KHz clock found.\n");
424 do_gettimeoffset = do_fast_cp0_gettimeoffset;
426 /* Ensure we get CPO_COUNTER interrupts.
428 c0_status = read_c0_status();
429 c0_status |= IE_IRQ5;
430 write_c0_status(c0_status);
433 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
434 au_writel(0, SYS_TOYWRITE);
435 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
437 au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
438 au_writel(~0, SYS_WAKESRC);
440 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
442 /* setup match20 to interrupt once every HZ */
443 last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
444 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
446 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
447 startup_match20_interrupt(counter0_irq);
449 do_gettimeoffset = do_fast_pm_gettimeoffset;
451 /* We can use the real 'wait' instruction.
457 /* We have to do this here instead of in timer_init because
458 * the generic code in arch/mips/kernel/time.c will write
459 * over our function pointer.
461 do_gettimeoffset = do_fast_cp0_gettimeoffset;
465 void __init au1xxx_time_init(void)