4 * Copyright (C) 1999 Silicon Graphics, Inc.
5 * Copyright (C) Vijay Chander (vijay@engr.sgi.com)
6 * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
7 * Copyright (C) 2000 Hewlett-Packard Co.
8 * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 2002 Intel Corp.
10 * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
12 #ifndef _ASM_IA64_MCA_ASM_H
13 #define _ASM_IA64_MCA_ASM_H
24 * This macro converts a instruction virtual address to a physical address
25 * Right now for simulation purposes the virtual addresses are
26 * direct mapped to physical addresses.
27 * 1. Lop off bits 61 thru 63 in the virtual address
29 #define INST_VA_TO_PA(addr) \
30 dep addr = 0, addr, 61, 3
32 * This macro converts a data virtual address to a physical address
33 * Right now for simulation purposes the virtual addresses are
34 * direct mapped to physical addresses.
35 * 1. Lop off bits 61 thru 63 in the virtual address
37 #define DATA_VA_TO_PA(addr) \
40 * This macro converts a data physical address to a virtual address
41 * Right now for simulation purposes the virtual addresses are
42 * direct mapped to physical addresses.
43 * 1. Put 0x7 in bits 61 thru 63.
45 #define DATA_PA_TO_VA(addr,temp) \
47 dep addr = temp, addr, 61, 3
49 #define GET_THIS_PADDR(reg, var) \
50 mov reg = IA64_KR(PER_CPU_DATA);; \
51 addl reg = THIS_CPU(var), reg
54 * This macro jumps to the instruction at the given virtual address
55 * and starts execution in physical mode with all the address
56 * translations turned off.
57 * 1. Save the current psr
58 * 2. Make sure that all the upper 32 bits are off
60 * 3. Clear the interrupt enable and interrupt state collection bits
61 * in the psr before updating the ipsr and iip.
63 * 4. Turn off the instruction, data and rse translation bits of the psr
64 * and store the new value into ipsr
65 * Also make sure that the interrupts are disabled.
66 * Ensure that we are in little endian mode.
67 * [psr.{rt, it, dt, i, be} = 0]
69 * 5. Get the physical address corresponding to the virtual address
70 * of the next instruction bundle and put it in iip.
71 * (Using magic numbers 24 and 40 in the deposint instruction since
72 * the IA64_SDK code directly maps to lower 24bits as physical address
73 * from a virtual address).
75 * 6. Do an rfi to move the values from ipsr to psr and iip to ip.
77 #define PHYSICAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
80 dep old_psr = 0, old_psr, 32, 32; \
85 mov temp2 = ar.bspstore; \
87 DATA_VA_TO_PA(temp2); \
89 mov temp1 = ar.rnat; \
91 mov ar.bspstore = temp2; \
93 mov ar.rnat = temp1; \
98 dep temp2 = 0, temp2, PSR_IC, 2; \
103 dep temp1 = 0, temp1, 32, 32; \
105 dep temp1 = 0, temp1, PSR_IT, 1; \
107 dep temp1 = 0, temp1, PSR_DT, 1; \
109 dep temp1 = 0, temp1, PSR_RT, 1; \
111 dep temp1 = 0, temp1, PSR_I, 1; \
113 dep temp1 = 0, temp1, PSR_IC, 1; \
115 dep temp1 = -1, temp1, PSR_MC, 1; \
117 mov cr.ipsr = temp1; \
119 LOAD_PHYSICAL(p0, temp2, start_addr); \
121 mov cr.iip = temp2; \
136 * This macro jumps to the instruction at the given virtual address
137 * and starts execution in virtual mode with all the address
138 * translations turned on.
139 * 1. Get the old saved psr
141 * 2. Clear the interrupt state collection bit in the current psr.
143 * 3. Set the instruction translation bit back in the old psr
144 * Note we have to do this since we are right now saving only the
145 * lower 32-bits of old psr.(Also the old psr has the data and
146 * rse translation bits on)
148 * 4. Set ipsr to this old_psr with "it" bit set and "bn" = 1.
150 * 5. Reset the current thread pointer (r13).
152 * 6. Set iip to the virtual address of the next instruction bundle.
154 * 7. Do an rfi to move ipsr to psr and iip to ip.
157 #define VIRTUAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
160 mov old_psr = temp2; \
162 dep temp2 = 0, temp2, PSR_IC, 2; \
169 mov temp2 = ar.bspstore; \
171 DATA_PA_TO_VA(temp2,temp1); \
173 mov temp1 = ar.rnat; \
175 mov ar.bspstore = temp2; \
177 mov ar.rnat = temp1; \
179 mov temp1 = old_psr; \
183 dep temp1 = temp2, temp1, PSR_IC, 1; \
185 dep temp1 = temp2, temp1, PSR_IT, 1; \
187 dep temp1 = temp2, temp1, PSR_DT, 1; \
189 dep temp1 = temp2, temp1, PSR_RT, 1; \
191 dep temp1 = temp2, temp1, PSR_BN, 1; \
194 mov cr.ipsr = temp1; \
195 movl temp2 = start_addr; \
197 mov cr.iip = temp2; \
199 DATA_PA_TO_VA(sp, temp1); \
200 DATA_PA_TO_VA(gp, temp2); \
210 * The following offsets capture the order in which the
211 * RSE related registers from the old context are
212 * saved onto the new stack frame.
214 * +-----------------------+
215 * |NDIRTY [BSP - BSPSTORE]|
216 * +-----------------------+
218 * +-----------------------+
220 * +-----------------------+
222 * +-----------------------+
224 * +-----------------------+
226 * +-----------------------+ <-------- Bottom of new stack frame
228 #define rse_rsc_offset 0
229 #define rse_pfs_offset (rse_rsc_offset+0x08)
230 #define rse_ifs_offset (rse_pfs_offset+0x08)
231 #define rse_bspstore_offset (rse_ifs_offset+0x08)
232 #define rse_rnat_offset (rse_bspstore_offset+0x08)
233 #define rse_ndirty_offset (rse_rnat_offset+0x08)
238 * 1. Save old RSC onto the new stack frame
239 * 2. Save PFS onto new stack frame
240 * 3. Cover the old frame and start a new frame.
241 * 4. Save IFS onto new stack frame
242 * 5. Save the old BSPSTORE on the new stack frame
243 * 6. Save the old RNAT on the new stack frame
244 * 7. Write BSPSTORE with the new backing store pointer
245 * 8. Read and save the new BSP to calculate the #dirty registers
246 * NOTE: Look at pages 11-10, 11-11 in PRM Vol 2
248 #define rse_switch_context(temp,p_stackframe,p_bspstore) \
251 st8 [p_stackframe]=temp,8;; \
253 st8 [p_stackframe]=temp,8; \
256 st8 [p_stackframe]=temp,8;; \
257 mov temp=ar.bspstore;; \
258 st8 [p_stackframe]=temp,8;; \
260 st8 [p_stackframe]=temp,8; \
261 mov ar.bspstore=p_bspstore;; \
263 sub temp=temp,p_bspstore;; \
264 st8 [p_stackframe]=temp,8;;
268 * 1. Allocate a zero-sized frame
269 * 2. Store the number of dirty registers RSC.loadrs field
270 * 3. Issue a loadrs to insure that any registers from the interrupted
271 * context which were saved on the new stack frame have been loaded
272 * back into the stacked registers
273 * 4. Restore BSPSTORE
280 #define rse_return_context(psr_mask_reg,temp,p_stackframe) \
282 alloc temp=ar.pfs,0,0,0,0; \
283 add p_stackframe=rse_ndirty_offset,p_stackframe;; \
284 ld8 temp=[p_stackframe];; \
288 add p_stackframe=-rse_ndirty_offset+rse_bspstore_offset,p_stackframe;;\
289 ld8 temp=[p_stackframe];; \
290 mov ar.bspstore=temp;; \
291 add p_stackframe=-rse_bspstore_offset+rse_rnat_offset,p_stackframe;;\
292 ld8 temp=[p_stackframe];; \
294 add p_stackframe=-rse_rnat_offset+rse_pfs_offset,p_stackframe;; \
295 ld8 temp=[p_stackframe];; \
297 add p_stackframe=-rse_pfs_offset+rse_ifs_offset,p_stackframe;; \
298 ld8 temp=[p_stackframe];; \
300 add p_stackframe=-rse_ifs_offset+rse_rsc_offset,p_stackframe;; \
301 ld8 temp=[p_stackframe];; \
304 or temp=temp,psr_mask_reg;; \
307 add temp=0x30,temp;; \
312 #endif /* _ASM_IA64_MCA_ASM_H */