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   1 /*
   2  *  Driver for the IDT RC32434 (Korina) on-chip ethernet controller.
   3  *
   4  *  Copyright 2004 IDT Inc. (rischelp@idt.com)
   5  *  Copyright 2006 Felix Fietkau <nbd@openwrt.org>
   6  *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  14  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  15  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  16  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  17  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  19  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  21  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  *  You should have received a copy of the  GNU General Public License along
  25  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  26  *  675 Mass Ave, Cambridge, MA 02139, USA.
  27  *
  28  *  Writing to a DMA status register:
  29  *
  30  *  When writing to the status register, you should mask the bit you have
  31  *  been testing the status register with. Both Tx and Rx DMA registers
  32  *  should stick to this procedure.
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/kernel.h>
  37 #include <linux/moduleparam.h>
  38 #include <linux/sched.h>
  39 #include <linux/ctype.h>
  40 #include <linux/types.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/init.h>
  43 #include <linux/ioport.h>
  44 #include <linux/in.h>
  45 #include <linux/slab.h>
  46 #include <linux/string.h>
  47 #include <linux/delay.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/etherdevice.h>
  50 #include <linux/skbuff.h>
  51 #include <linux/errno.h>
  52 #include <linux/platform_device.h>
  53 #include <linux/mii.h>
  54 #include <linux/ethtool.h>
  55 #include <linux/crc32.h>
  56
  57 #include <asm/bootinfo.h>
  58 #include <asm/system.h>
  59 #include <asm/bitops.h>
  60 #include <asm/pgtable.h>
  61 #include <asm/segment.h>
  62 #include <asm/io.h>
  63 #include <asm/dma.h>
  64
  65 #include <asm/mach-rc32434/rb.h>
  66 #include <asm/mach-rc32434/rc32434.h>
  67 #include <asm/mach-rc32434/eth.h>
  68 #include <asm/mach-rc32434/dma_v.h>
  69
  70 #define DRV_NAME        "korina"
  71 #define DRV_VERSION     "0.10"
  72 #define DRV_RELDATE     "04Mar2008"
  73
  74 #define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
  75                                    ((dev)->dev_addr[1]))
  76 #define STATION_ADDRESS_LOW(dev)  (((dev)->dev_addr[2] << 24) | \
  77                                    ((dev)->dev_addr[3] << 16) | \
  78                                    ((dev)->dev_addr[4] << 8)  | \
  79                                    ((dev)->dev_addr[5]))
  80
  81 #define MII_CLOCK 1250000       /* no more than 2.5MHz */
  82
  83 /* the following must be powers of two */
  84 #define KORINA_NUM_RDS  64  /* number of receive descriptors */
  85 #define KORINA_NUM_TDS  64  /* number of transmit descriptors */
  86
  87 /* KORINA_RBSIZE is the hardware's default maximum receive
  88  * frame size in bytes. Having this hardcoded means that there
  89  * is no support for MTU sizes greater than 1500. */
  90 #define KORINA_RBSIZE   1536 /* size of one resource buffer = Ether MTU */
  91 #define KORINA_RDS_MASK (KORINA_NUM_RDS - 1)
  92 #define KORINA_TDS_MASK (KORINA_NUM_TDS - 1)
  93 #define RD_RING_SIZE    (KORINA_NUM_RDS * sizeof(struct dma_desc))
  94 #define TD_RING_SIZE    (KORINA_NUM_TDS * sizeof(struct dma_desc))
  95
  96 #define TX_TIMEOUT      (6000 * HZ / 1000)
  97
  98 enum chain_status { desc_filled, desc_empty };
  99 #define IS_DMA_FINISHED(X)   (((X) & (DMA_DESC_FINI)) != 0)
 100 #define IS_DMA_DONE(X)   (((X) & (DMA_DESC_DONE)) != 0)
 101 #define RCVPKT_LENGTH(X)     (((X) & ETH_RX_LEN) >> ETH_RX_LEN_BIT)
 102
 103 /* Information that need to be kept for each board. */
 104 struct korina_private {
 105         struct eth_regs *eth_regs;
 106         struct dma_reg *rx_dma_regs;
 107         struct dma_reg *tx_dma_regs;
 108         struct dma_desc *td_ring; /* transmit descriptor ring */
 109         struct dma_desc *rd_ring; /* receive descriptor ring  */
 110
 111         struct sk_buff *tx_skb[KORINA_NUM_TDS];
 112         struct sk_buff *rx_skb[KORINA_NUM_RDS];
 113
 114         int rx_next_done;
 115         int rx_chain_head;
 116         int rx_chain_tail;
 117         enum chain_status rx_chain_status;
 118
 119         int tx_next_done;
 120         int tx_chain_head;
 121         int tx_chain_tail;
 122         enum chain_status tx_chain_status;
 123         int tx_count;
 124         int tx_full;
 125
 126         int rx_irq;
 127         int tx_irq;
 128         int ovr_irq;
 129         int und_irq;
 130
 131         spinlock_t lock;        /* NIC xmit lock */
 132
 133         int dma_halt_cnt;
 134         int dma_run_cnt;
 135         struct napi_struct napi;
 136         struct mii_if_info mii_if;
 137         struct net_device *dev;
 138         int phy_addr;
 139 };
 140
 141 extern unsigned int idt_cpu_freq;
 142
 143 static inline void korina_start_dma(struct dma_reg *ch, u32 dma_addr)
 144 {
 145         writel(0, &ch->dmandptr);
 146         writel(dma_addr, &ch->dmadptr);
 147 }
 148
 149 static inline void korina_abort_dma(struct net_device *dev,
 150                                         struct dma_reg *ch)
 151 {
 152        if (readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
 153                writel(0x10, &ch->dmac);
 154
 155                while (!(readl(&ch->dmas) & DMA_STAT_HALT))
 156                        dev->trans_start = jiffies;
 157
 158                writel(0, &ch->dmas);
 159        }
 160
 161        writel(0, &ch->dmadptr);
 162        writel(0, &ch->dmandptr);
 163 }
 164
 165 static inline void korina_chain_dma(struct dma_reg *ch, u32 dma_addr)
 166 {
 167         writel(dma_addr, &ch->dmandptr);
 168 }
 169
 170 static void korina_abort_tx(struct net_device *dev)
 171 {
 172         struct korina_private *lp = netdev_priv(dev);
 173
 174         korina_abort_dma(dev, lp->tx_dma_regs);
 175 }
 176
 177 static void korina_abort_rx(struct net_device *dev)
 178 {
 179         struct korina_private *lp = netdev_priv(dev);
 180
 181         korina_abort_dma(dev, lp->rx_dma_regs);
 182 }
 183
 184 static void korina_start_rx(struct korina_private *lp,
 185                                         struct dma_desc *rd)
 186 {
 187         korina_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
 188 }
 189
 190 static void korina_chain_rx(struct korina_private *lp,
 191                                         struct dma_desc *rd)
 192 {
 193         korina_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
 194 }
 195
 196 /* transmit packet */
 197 static int korina_send_packet(struct sk_buff *skb, struct net_device *dev)
 198 {
 199         struct korina_private *lp = netdev_priv(dev);
 200         unsigned long flags;
 201         u32 length;
 202         u32 chain_prev, chain_next;
 203         struct dma_desc *td;
 204
 205         spin_lock_irqsave(&lp->lock, flags);
 206
 207         td = &lp->td_ring[lp->tx_chain_tail];
 208
 209         /* stop queue when full, drop pkts if queue already full */
 210         if (lp->tx_count >= (KORINA_NUM_TDS - 2)) {
 211                 lp->tx_full = 1;
 212
 213                 if (lp->tx_count == (KORINA_NUM_TDS - 2))
 214                         netif_stop_queue(dev);
 215                 else {
 216                         dev->stats.tx_dropped++;
 217                         dev_kfree_skb_any(skb);
 218                         spin_unlock_irqrestore(&lp->lock, flags);
 219
 220                         return NETDEV_TX_BUSY;
 221                 }
 222         }
 223
 224         lp->tx_count++;
 225
 226         lp->tx_skb[lp->tx_chain_tail] = skb;
 227
 228         length = skb->len;
 229         dma_cache_wback((u32)skb->data, skb->len);
 230
 231         /* Setup the transmit descriptor. */
 232         dma_cache_inv((u32) td, sizeof(*td));
 233         td->ca = CPHYSADDR(skb->data);
 234         chain_prev = (lp->tx_chain_tail - 1) & KORINA_TDS_MASK;
 235         chain_next = (lp->tx_chain_tail + 1) & KORINA_TDS_MASK;
 236
 237         if (readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
 238                 if (lp->tx_chain_status == desc_empty) {
 239                         /* Update tail */
 240                         td->control = DMA_COUNT(length) |
 241                                         DMA_DESC_COF | DMA_DESC_IOF;
 242                         /* Move tail */
 243                         lp->tx_chain_tail = chain_next;
 244                         /* Write to NDPTR */
 245                         writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
 246                                         &lp->tx_dma_regs->dmandptr);
 247                         /* Move head to tail */
 248                         lp->tx_chain_head = lp->tx_chain_tail;
 249                 } else {
 250                         /* Update tail */
 251                         td->control = DMA_COUNT(length) |
 252                                         DMA_DESC_COF | DMA_DESC_IOF;
 253                         /* Link to prev */
 254                         lp->td_ring[chain_prev].control &=
 255                                         ~DMA_DESC_COF;
 256                         /* Link to prev */
 257                         lp->td_ring[chain_prev].link =  CPHYSADDR(td);
 258                         /* Move tail */
 259                         lp->tx_chain_tail = chain_next;
 260                         /* Write to NDPTR */
 261                         writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
 262                                         &(lp->tx_dma_regs->dmandptr));
 263                         /* Move head to tail */
 264                         lp->tx_chain_head = lp->tx_chain_tail;
 265                         lp->tx_chain_status = desc_empty;
 266                 }
 267         } else {
 268                 if (lp->tx_chain_status == desc_empty) {
 269                         /* Update tail */
 270                         td->control = DMA_COUNT(length) |
 271                                         DMA_DESC_COF | DMA_DESC_IOF;
 272                         /* Move tail */
 273                         lp->tx_chain_tail = chain_next;
 274                         lp->tx_chain_status = desc_filled;
 275                 } else {
 276                         /* Update tail */
 277                         td->control = DMA_COUNT(length) |
 278                                         DMA_DESC_COF | DMA_DESC_IOF;
 279                         lp->td_ring[chain_prev].control &=
 280                                         ~DMA_DESC_COF;
 281                         lp->td_ring[chain_prev].link =  CPHYSADDR(td);
 282                         lp->tx_chain_tail = chain_next;
 283                 }
 284         }
 285         dma_cache_wback((u32) td, sizeof(*td));
 286
 287         dev->trans_start = jiffies;
 288         spin_unlock_irqrestore(&lp->lock, flags);
 289
 290         return NETDEV_TX_OK;
 291 }
 292
 293 static int mdio_read(struct net_device *dev, int mii_id, int reg)
 294 {
 295         struct korina_private *lp = netdev_priv(dev);
 296         int ret;
 297
 298         mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8);
 299
 300         writel(0, &lp->eth_regs->miimcfg);
 301         writel(0, &lp->eth_regs->miimcmd);
 302         writel(mii_id | reg, &lp->eth_regs->miimaddr);
 303         writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd);
 304
 305         ret = (int)(readl(&lp->eth_regs->miimrdd));
 306         return ret;
 307 }
 308
 309 static void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
 310 {
 311         struct korina_private *lp = netdev_priv(dev);
 312
 313         mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8);
 314
 315         writel(0, &lp->eth_regs->miimcfg);
 316         writel(1, &lp->eth_regs->miimcmd);
 317         writel(mii_id | reg, &lp->eth_regs->miimaddr);
 318         writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd);
 319         writel(val, &lp->eth_regs->miimwtd);
 320 }
 321
 322 /* Ethernet Rx DMA interrupt */
 323 static irqreturn_t korina_rx_dma_interrupt(int irq, void *dev_id)
 324 {
 325         struct net_device *dev = dev_id;
 326         struct korina_private *lp = netdev_priv(dev);
 327         u32 dmas, dmasm;
 328         irqreturn_t retval;
 329
 330         dmas = readl(&lp->rx_dma_regs->dmas);
 331         if (dmas & (DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR)) {
 332                 dmasm = readl(&lp->rx_dma_regs->dmasm);
 333                 writel(dmasm | (DMA_STAT_DONE |
 334                                 DMA_STAT_HALT | DMA_STAT_ERR),
 335                                 &lp->rx_dma_regs->dmasm);
 336
 337                 netif_rx_schedule(&lp->napi);
 338
 339                 if (dmas & DMA_STAT_ERR)
 340                         printk(KERN_ERR DRV_NAME "%s: DMA error\n", dev->name);
 341
 342                 retval = IRQ_HANDLED;
 343         } else
 344                 retval = IRQ_NONE;
 345
 346         return retval;
 347 }
 348
 349 static int korina_rx(struct net_device *dev, int limit)
 350 {
 351         struct korina_private *lp = netdev_priv(dev);
 352         struct dma_desc *rd = &lp->rd_ring[lp->rx_next_done];
 353         struct sk_buff *skb, *skb_new;
 354         u8 *pkt_buf;
 355         u32 devcs, pkt_len, dmas;
 356         int count;
 357
 358         dma_cache_inv((u32)rd, sizeof(*rd));
 359
 360         for (count = 0; count < limit; count++) {
 361                 skb = lp->rx_skb[lp->rx_next_done];
 362                 skb_new = NULL;
 363
 364                 devcs = rd->devcs;
 365
 366                 if ((KORINA_RBSIZE - (u32)DMA_COUNT(rd->control)) == 0)
 367                         break;
 368
 369                 /* Update statistics counters */
 370                 if (devcs & ETH_RX_CRC)
 371                         dev->stats.rx_crc_errors++;
 372                 if (devcs & ETH_RX_LOR)
 373                         dev->stats.rx_length_errors++;
 374                 if (devcs & ETH_RX_LE)
 375                         dev->stats.rx_length_errors++;
 376                 if (devcs & ETH_RX_OVR)
 377                         dev->stats.rx_over_errors++;
 378                 if (devcs & ETH_RX_CV)
 379                         dev->stats.rx_frame_errors++;
 380                 if (devcs & ETH_RX_CES)
 381                         dev->stats.rx_length_errors++;
 382                 if (devcs & ETH_RX_MP)
 383                         dev->stats.multicast++;
 384
 385                 if ((devcs & ETH_RX_LD) != ETH_RX_LD) {
 386                         /* check that this is a whole packet
 387                          * WARNING: DMA_FD bit incorrectly set
 388                          * in Rc32434 (errata ref #077) */
 389                         dev->stats.rx_errors++;
 390                         dev->stats.rx_dropped++;
 391                 } else if ((devcs & ETH_RX_ROK)) {
 392                         pkt_len = RCVPKT_LENGTH(devcs);
 393
 394                         /* must be the (first and) last
 395                          * descriptor then */
 396                         pkt_buf = (u8 *)lp->rx_skb[lp->rx_next_done]->data;
 397
 398                         /* invalidate the cache */
 399                         dma_cache_inv((unsigned long)pkt_buf, pkt_len - 4);
 400
 401                         /* Malloc up new buffer. */
 402                         skb_new = netdev_alloc_skb(dev, KORINA_RBSIZE + 2);
 403
 404                         if (!skb_new)
 405                                 break;
 406                         /* Do not count the CRC */
 407                         skb_put(skb, pkt_len - 4);
 408                         skb->protocol = eth_type_trans(skb, dev);
 409
 410                         /* Pass the packet to upper layers */
 411                         netif_receive_skb(skb);
 412                         dev->stats.rx_packets++;
 413                         dev->stats.rx_bytes += pkt_len;
 414
 415                         /* Update the mcast stats */
 416                         if (devcs & ETH_RX_MP)
 417                                 dev->stats.multicast++;
 418
 419                         /* 16 bit align */
 420                         skb_reserve(skb_new, 2);
 421
 422                         lp->rx_skb[lp->rx_next_done] = skb_new;
 423                 }
 424
 425                 rd->devcs = 0;
 426
 427                 /* Restore descriptor's curr_addr */
 428                 if (skb_new)
 429                         rd->ca = CPHYSADDR(skb_new->data);
 430                 else
 431                         rd->ca = CPHYSADDR(skb->data);
 432
 433                 rd->control = DMA_COUNT(KORINA_RBSIZE) |
 434                         DMA_DESC_COD | DMA_DESC_IOD;
 435                 lp->rd_ring[(lp->rx_next_done - 1) &
 436                         KORINA_RDS_MASK].control &=
 437                         ~DMA_DESC_COD;
 438
 439                 lp->rx_next_done = (lp->rx_next_done + 1) & KORINA_RDS_MASK;
 440                 dma_cache_wback((u32)rd, sizeof(*rd));
 441                 rd = &lp->rd_ring[lp->rx_next_done];
 442                 writel(~DMA_STAT_DONE, &lp->rx_dma_regs->dmas);
 443         }
 444
 445         dmas = readl(&lp->rx_dma_regs->dmas);
 446
 447         if (dmas & DMA_STAT_HALT) {
 448                 writel(~(DMA_STAT_HALT | DMA_STAT_ERR),
 449                                 &lp->rx_dma_regs->dmas);
 450
 451                 lp->dma_halt_cnt++;
 452                 rd->devcs = 0;
 453                 skb = lp->rx_skb[lp->rx_next_done];
 454                 rd->ca = CPHYSADDR(skb->data);
 455                 dma_cache_wback((u32)rd, sizeof(*rd));
 456                 korina_chain_rx(lp, rd);
 457         }
 458
 459         return count;
 460 }
 461
 462 static int korina_poll(struct napi_struct *napi, int budget)
 463 {
 464         struct korina_private *lp =
 465                 container_of(napi, struct korina_private, napi);
 466         struct net_device *dev = lp->dev;
 467         int work_done;
 468
 469         work_done = korina_rx(dev, budget);
 470         if (work_done < budget) {
 471                 netif_rx_complete(napi);
 472
 473                 writel(readl(&lp->rx_dma_regs->dmasm) &
 474                         ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
 475                         &lp->rx_dma_regs->dmasm);
 476         }
 477         return work_done;
 478 }
 479
 480 /*
 481  * Set or clear the multicast filter for this adaptor.
 482  */
 483 static void korina_multicast_list(struct net_device *dev)
 484 {
 485         struct korina_private *lp = netdev_priv(dev);
 486         unsigned long flags;
 487         struct dev_mc_list *dmi = dev->mc_list;
 488         u32 recognise = ETH_ARC_AB;     /* always accept broadcasts */
 489         int i;
 490
 491         /* Set promiscuous mode */
 492         if (dev->flags & IFF_PROMISC)
 493                 recognise |= ETH_ARC_PRO;
 494
 495         else if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 4))
 496                 /* All multicast and broadcast */
 497                 recognise |= ETH_ARC_AM;
 498
 499         /* Build the hash table */
 500         if (dev->mc_count > 4) {
 501                 u16 hash_table[4];
 502                 u32 crc;
 503
 504                 for (i = 0; i < 4; i++)
 505                         hash_table[i] = 0;
 506
 507                 for (i = 0; i < dev->mc_count; i++) {
 508                         char *addrs = dmi->dmi_addr;
 509
 510                         dmi = dmi->next;
 511
 512                         if (!(*addrs & 1))
 513                                 continue;
 514
 515                         crc = ether_crc_le(6, addrs);
 516                         crc >>= 26;
 517                         hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
 518                 }
 519                 /* Accept filtered multicast */
 520                 recognise |= ETH_ARC_AFM;
 521
 522                 /* Fill the MAC hash tables with their values */
 523                 writel((u32)(hash_table[1] << 16 | hash_table[0]),
 524                                         &lp->eth_regs->ethhash0);
 525                 writel((u32)(hash_table[3] << 16 | hash_table[2]),
 526                                         &lp->eth_regs->ethhash1);
 527         }
 528
 529         spin_lock_irqsave(&lp->lock, flags);
 530         writel(recognise, &lp->eth_regs->etharc);
 531         spin_unlock_irqrestore(&lp->lock, flags);
 532 }
 533
 534 static void korina_tx(struct net_device *dev)
 535 {
 536         struct korina_private *lp = netdev_priv(dev);
 537         struct dma_desc *td = &lp->td_ring[lp->tx_next_done];
 538         u32 devcs;
 539         u32 dmas;
 540
 541         spin_lock(&lp->lock);
 542
 543         /* Process all desc that are done */
 544         while (IS_DMA_FINISHED(td->control)) {
 545                 if (lp->tx_full == 1) {
 546                         netif_wake_queue(dev);
 547                         lp->tx_full = 0;
 548                 }
 549
 550                 devcs = lp->td_ring[lp->tx_next_done].devcs;
 551                 if ((devcs & (ETH_TX_FD | ETH_TX_LD)) !=
 552                                 (ETH_TX_FD | ETH_TX_LD)) {
 553                         dev->stats.tx_errors++;
 554                         dev->stats.tx_dropped++;
 555
 556                         /* Should never happen */
 557                         printk(KERN_ERR DRV_NAME "%s: split tx ignored\n",
 558                                                         dev->name);
 559                 } else if (devcs & ETH_TX_TOK) {
 560                         dev->stats.tx_packets++;
 561                         dev->stats.tx_bytes +=
 562                                         lp->tx_skb[lp->tx_next_done]->len;
 563                 } else {
 564                         dev->stats.tx_errors++;
 565                         dev->stats.tx_dropped++;
 566
 567                         /* Underflow */
 568                         if (devcs & ETH_TX_UND)
 569                                 dev->stats.tx_fifo_errors++;
 570
 571                         /* Oversized frame */
 572                         if (devcs & ETH_TX_OF)
 573                                 dev->stats.tx_aborted_errors++;
 574
 575                         /* Excessive deferrals */
 576                         if (devcs & ETH_TX_ED)
 577                                 dev->stats.tx_carrier_errors++;
 578
 579                         /* Collisions: medium busy */
 580                         if (devcs & ETH_TX_EC)
 581                                 dev->stats.collisions++;
 582
 583                         /* Late collision */
 584                         if (devcs & ETH_TX_LC)
 585                                 dev->stats.tx_window_errors++;
 586                 }
 587
 588                 /* We must always free the original skb */
 589                 if (lp->tx_skb[lp->tx_next_done]) {
 590                         dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
 591                         lp->tx_skb[lp->tx_next_done] = NULL;
 592                 }
 593
 594                 lp->td_ring[lp->tx_next_done].control = DMA_DESC_IOF;
 595                 lp->td_ring[lp->tx_next_done].devcs = ETH_TX_FD | ETH_TX_LD;
 596                 lp->td_ring[lp->tx_next_done].link = 0;
 597                 lp->td_ring[lp->tx_next_done].ca = 0;
 598                 lp->tx_count--;
 599
 600                 /* Go on to next transmission */
 601                 lp->tx_next_done = (lp->tx_next_done + 1) & KORINA_TDS_MASK;
 602                 td = &lp->td_ring[lp->tx_next_done];
 603
 604         }
 605
 606         /* Clear the DMA status register */
 607         dmas = readl(&lp->tx_dma_regs->dmas);
 608         writel(~dmas, &lp->tx_dma_regs->dmas);
 609
 610         writel(readl(&lp->tx_dma_regs->dmasm) &
 611                         ~(DMA_STAT_FINI | DMA_STAT_ERR),
 612                         &lp->tx_dma_regs->dmasm);
 613
 614         spin_unlock(&lp->lock);
 615 }
 616
 617 static irqreturn_t
 618 korina_tx_dma_interrupt(int irq, void *dev_id)
 619 {
 620         struct net_device *dev = dev_id;
 621         struct korina_private *lp = netdev_priv(dev);
 622         u32 dmas, dmasm;
 623         irqreturn_t retval;
 624
 625         dmas = readl(&lp->tx_dma_regs->dmas);
 626
 627         if (dmas & (DMA_STAT_FINI | DMA_STAT_ERR)) {
 628                 dmasm = readl(&lp->tx_dma_regs->dmasm);
 629                 writel(dmasm | (DMA_STAT_FINI | DMA_STAT_ERR),
 630                                 &lp->tx_dma_regs->dmasm);
 631
 632                 korina_tx(dev);
 633
 634                 if (lp->tx_chain_status == desc_filled &&
 635                         (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
 636                         writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
 637                                 &(lp->tx_dma_regs->dmandptr));
 638                         lp->tx_chain_status = desc_empty;
 639                         lp->tx_chain_head = lp->tx_chain_tail;
 640                         dev->trans_start = jiffies;
 641                 }
 642                 if (dmas & DMA_STAT_ERR)
 643                         printk(KERN_ERR DRV_NAME "%s: DMA error\n", dev->name);
 644
 645                 retval = IRQ_HANDLED;
 646         } else
 647                 retval = IRQ_NONE;
 648
 649         return retval;
 650 }
 651
 652
 653 static void korina_check_media(struct net_device *dev, unsigned int init_media)
 654 {
 655         struct korina_private *lp = netdev_priv(dev);
 656
 657         mii_check_media(&lp->mii_if, 0, init_media);
 658
 659         if (lp->mii_if.full_duplex)
 660                 writel(readl(&lp->eth_regs->ethmac2) | ETH_MAC2_FD,
 661                                                 &lp->eth_regs->ethmac2);
 662         else
 663                 writel(readl(&lp->eth_regs->ethmac2) & ~ETH_MAC2_FD,
 664                                                 &lp->eth_regs->ethmac2);
 665 }
 666
 667 static void korina_set_carrier(struct mii_if_info *mii)
 668 {
 669         if (mii->force_media) {
 670                 /* autoneg is off: Link is always assumed to be up */
 671                 if (!netif_carrier_ok(mii->dev))
 672                         netif_carrier_on(mii->dev);
 673         } else  /* Let MMI library update carrier status */
 674                 korina_check_media(mii->dev, 0);
 675 }
 676
 677 static int korina_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 678 {
 679         struct korina_private *lp = netdev_priv(dev);
 680         struct mii_ioctl_data *data = if_mii(rq);
 681         int rc;
 682
 683         if (!netif_running(dev))
 684                 return -EINVAL;
 685         spin_lock_irq(&lp->lock);
 686         rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
 687         spin_unlock_irq(&lp->lock);
 688         korina_set_carrier(&lp->mii_if);
 689
 690         return rc;
 691 }
 692
 693 /* ethtool helpers */
 694 static void netdev_get_drvinfo(struct net_device *dev,
 695                         struct ethtool_drvinfo *info)
 696 {
 697         struct korina_private *lp = netdev_priv(dev);
 698
 699         strcpy(info->driver, DRV_NAME);
 700         strcpy(info->version, DRV_VERSION);
 701         strcpy(info->bus_info, lp->dev->name);
 702 }
 703
 704 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 705 {
 706         struct korina_private *lp = netdev_priv(dev);
 707         int rc;
 708
 709         spin_lock_irq(&lp->lock);
 710         rc = mii_ethtool_gset(&lp->mii_if, cmd);
 711         spin_unlock_irq(&lp->lock);
 712
 713         return rc;
 714 }
 715
 716 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 717 {
 718         struct korina_private *lp = netdev_priv(dev);
 719         int rc;
 720
 721         spin_lock_irq(&lp->lock);
 722         rc = mii_ethtool_sset(&lp->mii_if, cmd);
 723         spin_unlock_irq(&lp->lock);
 724         korina_set_carrier(&lp->mii_if);
 725
 726         return rc;
 727 }
 728
 729 static u32 netdev_get_link(struct net_device *dev)
 730 {
 731         struct korina_private *lp = netdev_priv(dev);
 732
 733         return mii_link_ok(&lp->mii_if);
 734 }
 735
 736 static struct ethtool_ops netdev_ethtool_ops = {
 737         .get_drvinfo            = netdev_get_drvinfo,
 738         .get_settings           = netdev_get_settings,
 739         .set_settings           = netdev_set_settings,
 740         .get_link               = netdev_get_link,
 741 };
 742
 743 static void korina_alloc_ring(struct net_device *dev)
 744 {
 745         struct korina_private *lp = netdev_priv(dev);
 746         struct sk_buff *skb;
 747         int i;
 748
 749         /* Initialize the transmit descriptors */
 750         for (i = 0; i < KORINA_NUM_TDS; i++) {
 751                 lp->td_ring[i].control = DMA_DESC_IOF;
 752                 lp->td_ring[i].devcs = ETH_TX_FD | ETH_TX_LD;
 753                 lp->td_ring[i].ca = 0;
 754                 lp->td_ring[i].link = 0;
 755         }
 756         lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail =
 757                         lp->tx_full = lp->tx_count = 0;
 758         lp->tx_chain_status = desc_empty;
 759
 760         /* Initialize the receive descriptors */
 761         for (i = 0; i < KORINA_NUM_RDS; i++) {
 762                 skb = dev_alloc_skb(KORINA_RBSIZE + 2);
 763                 if (!skb)
 764                         break;
 765                 skb_reserve(skb, 2);
 766                 lp->rx_skb[i] = skb;
 767                 lp->rd_ring[i].control = DMA_DESC_IOD |
 768                                 DMA_COUNT(KORINA_RBSIZE);
 769                 lp->rd_ring[i].devcs = 0;
 770                 lp->rd_ring[i].ca = CPHYSADDR(skb->data);
 771                 lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
 772         }
 773
 774         /* loop back receive descriptors, so the last
 775          * descriptor points to the first one */
 776         lp->rd_ring[i - 1].link = CPHYSADDR(&lp->rd_ring[0]);
 777         lp->rd_ring[i - 1].control |= DMA_DESC_COD;
 778
 779         lp->rx_next_done  = 0;
 780         lp->rx_chain_head = 0;
 781         lp->rx_chain_tail = 0;
 782         lp->rx_chain_status = desc_empty;
 783 }
 784
 785 static void korina_free_ring(struct net_device *dev)
 786 {
 787         struct korina_private *lp = netdev_priv(dev);
 788         int i;
 789
 790         for (i = 0; i < KORINA_NUM_RDS; i++) {
 791                 lp->rd_ring[i].control = 0;
 792                 if (lp->rx_skb[i])
 793                         dev_kfree_skb_any(lp->rx_skb[i]);
 794                 lp->rx_skb[i] = NULL;
 795         }
 796
 797         for (i = 0; i < KORINA_NUM_TDS; i++) {
 798                 lp->td_ring[i].control = 0;
 799                 if (lp->tx_skb[i])
 800                         dev_kfree_skb_any(lp->tx_skb[i]);
 801                 lp->tx_skb[i] = NULL;
 802         }
 803 }
 804
 805 /*
 806  * Initialize the RC32434 ethernet controller.
 807  */
 808 static int korina_init(struct net_device *dev)
 809 {
 810         struct korina_private *lp = netdev_priv(dev);
 811
 812         /* Disable DMA */
 813         korina_abort_tx(dev);
 814         korina_abort_rx(dev);
 815
 816         /* reset ethernet logic */
 817         writel(0, &lp->eth_regs->ethintfc);
 818         while ((readl(&lp->eth_regs->ethintfc) & ETH_INT_FC_RIP))
 819                 dev->trans_start = jiffies;
 820
 821         /* Enable Ethernet Interface */
 822         writel(ETH_INT_FC_EN, &lp->eth_regs->ethintfc);
 823
 824         /* Allocate rings */
 825         korina_alloc_ring(dev);
 826
 827         writel(0, &lp->rx_dma_regs->dmas);
 828         /* Start Rx DMA */
 829         korina_start_rx(lp, &lp->rd_ring[0]);
 830
 831         writel(readl(&lp->tx_dma_regs->dmasm) &
 832                         ~(DMA_STAT_FINI | DMA_STAT_ERR),
 833                         &lp->tx_dma_regs->dmasm);
 834         writel(readl(&lp->rx_dma_regs->dmasm) &
 835                         ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
 836                         &lp->rx_dma_regs->dmasm);
 837
 838         /* Accept only packets destined for this Ethernet device address */
 839         writel(ETH_ARC_AB, &lp->eth_regs->etharc);
 840
 841         /* Set all Ether station address registers to their initial values */
 842         writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
 843         writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
 844
 845         writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
 846         writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
 847
 848         writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
 849         writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
 850
 851         writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
 852         writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
 853
 854
 855         /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
 856         writel(ETH_MAC2_PE | ETH_MAC2_CEN | ETH_MAC2_FD,
 857                         &lp->eth_regs->ethmac2);
 858
 859         /* Back to back inter-packet-gap */
 860         writel(0x15, &lp->eth_regs->ethipgt);
 861         /* Non - Back to back inter-packet-gap */
 862         writel(0x12, &lp->eth_regs->ethipgr);
 863
 864         /* Management Clock Prescaler Divisor
 865          * Clock independent setting */
 866         writel(((idt_cpu_freq) / MII_CLOCK + 1) & ~1,
 867                        &lp->eth_regs->ethmcp);
 868
 869         /* don't transmit until fifo contains 48b */
 870         writel(48, &lp->eth_regs->ethfifott);
 871
 872         writel(ETH_MAC1_RE, &lp->eth_regs->ethmac1);
 873
 874         napi_enable(&lp->napi);
 875         netif_start_queue(dev);
 876
 877         return 0;
 878 }
 879
 880 /*
 881  * Restart the RC32434 ethernet controller.
 882  * FIXME: check the return status where we call it
 883  */
 884 static int korina_restart(struct net_device *dev)
 885 {
 886         struct korina_private *lp = netdev_priv(dev);
 887         int ret;
 888
 889         /*
 890          * Disable interrupts
 891          */
 892         disable_irq(lp->rx_irq);
 893         disable_irq(lp->tx_irq);
 894         disable_irq(lp->ovr_irq);
 895         disable_irq(lp->und_irq);
 896
 897         writel(readl(&lp->tx_dma_regs->dmasm) |
 898                                 DMA_STAT_FINI | DMA_STAT_ERR,
 899                                 &lp->tx_dma_regs->dmasm);
 900         writel(readl(&lp->rx_dma_regs->dmasm) |
 901                                 DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR,
 902                                 &lp->rx_dma_regs->dmasm);
 903
 904         korina_free_ring(dev);
 905
 906         napi_disable(&lp->napi);
 907
 908         ret = korina_init(dev);
 909         if (ret < 0) {
 910                 printk(KERN_ERR DRV_NAME "%s: cannot restart device\n",
 911                                                                 dev->name);
 912                 return ret;
 913         }
 914         korina_multicast_list(dev);
 915
 916         enable_irq(lp->und_irq);
 917         enable_irq(lp->ovr_irq);
 918         enable_irq(lp->tx_irq);
 919         enable_irq(lp->rx_irq);
 920
 921         return ret;
 922 }
 923
 924 static void korina_clear_and_restart(struct net_device *dev, u32 value)
 925 {
 926         struct korina_private *lp = netdev_priv(dev);
 927
 928         netif_stop_queue(dev);
 929         writel(value, &lp->eth_regs->ethintfc);
 930         korina_restart(dev);
 931 }
 932
 933 /* Ethernet Tx Underflow interrupt */
 934 static irqreturn_t korina_und_interrupt(int irq, void *dev_id)
 935 {
 936         struct net_device *dev = dev_id;
 937         struct korina_private *lp = netdev_priv(dev);
 938         unsigned int und;
 939
 940         spin_lock(&lp->lock);
 941
 942         und = readl(&lp->eth_regs->ethintfc);
 943
 944         if (und & ETH_INT_FC_UND)
 945                 korina_clear_and_restart(dev, und & ~ETH_INT_FC_UND);
 946
 947         spin_unlock(&lp->lock);
 948
 949         return IRQ_HANDLED;
 950 }
 951
 952 static void korina_tx_timeout(struct net_device *dev)
 953 {
 954         struct korina_private *lp = netdev_priv(dev);
 955         unsigned long flags;
 956
 957         spin_lock_irqsave(&lp->lock, flags);
 958         korina_restart(dev);
 959         spin_unlock_irqrestore(&lp->lock, flags);
 960 }
 961
 962 /* Ethernet Rx Overflow interrupt */
 963 static irqreturn_t
 964 korina_ovr_interrupt(int irq, void *dev_id)
 965 {
 966         struct net_device *dev = dev_id;
 967         struct korina_private *lp = netdev_priv(dev);
 968         unsigned int ovr;
 969
 970         spin_lock(&lp->lock);
 971         ovr = readl(&lp->eth_regs->ethintfc);
 972
 973         if (ovr & ETH_INT_FC_OVR)
 974                 korina_clear_and_restart(dev, ovr & ~ETH_INT_FC_OVR);
 975
 976         spin_unlock(&lp->lock);
 977
 978         return IRQ_HANDLED;
 979 }
 980
 981 #ifdef CONFIG_NET_POLL_CONTROLLER
 982 static void korina_poll_controller(struct net_device *dev)
 983 {
 984         disable_irq(dev->irq);
 985         korina_tx_dma_interrupt(dev->irq, dev);
 986         enable_irq(dev->irq);
 987 }
 988 #endif
 989
 990 static int korina_open(struct net_device *dev)
 991 {
 992         struct korina_private *lp = netdev_priv(dev);
 993         int ret;
 994
 995         /* Initialize */
 996         ret = korina_init(dev);
 997         if (ret < 0) {
 998                 printk(KERN_ERR DRV_NAME "%s: cannot open device\n", dev->name);
 999                 goto out;
1000         }
1001
1002         /* Install the interrupt handler
1003          * that handles the Done Finished
1004          * Ovr and Und Events */
1005         ret = request_irq(lp->rx_irq, &korina_rx_dma_interrupt,
1006                         IRQF_DISABLED, "Korina ethernet Rx", dev);
1007         if (ret < 0) {
1008                 printk(KERN_ERR DRV_NAME "%s: unable to get Rx DMA IRQ %d\n",
1009                     dev->name, lp->rx_irq);
1010                 goto err_release;
1011         }
1012         ret = request_irq(lp->tx_irq, &korina_tx_dma_interrupt,
1013                         IRQF_DISABLED, "Korina ethernet Tx", dev);
1014         if (ret < 0) {
1015                 printk(KERN_ERR DRV_NAME "%s: unable to get Tx DMA IRQ %d\n",
1016                     dev->name, lp->tx_irq);
1017                 goto err_free_rx_irq;
1018         }
1019
1020         /* Install handler for overrun error. */
1021         ret = request_irq(lp->ovr_irq, &korina_ovr_interrupt,
1022                         IRQF_DISABLED, "Ethernet Overflow", dev);
1023         if (ret < 0) {
1024                 printk(KERN_ERR DRV_NAME"%s: unable to get OVR IRQ %d\n",
1025                     dev->name, lp->ovr_irq);
1026                 goto err_free_tx_irq;
1027         }
1028
1029         /* Install handler for underflow error. */
1030         ret = request_irq(lp->und_irq, &korina_und_interrupt,
1031                         IRQF_DISABLED, "Ethernet Underflow", dev);
1032         if (ret < 0) {
1033                 printk(KERN_ERR DRV_NAME "%s: unable to get UND IRQ %d\n",
1034                     dev->name, lp->und_irq);
1035                 goto err_free_ovr_irq;
1036         }
1037 out:
1038         return ret;
1039
1040 err_free_ovr_irq:
1041         free_irq(lp->ovr_irq, dev);
1042 err_free_tx_irq:
1043         free_irq(lp->tx_irq, dev);
1044 err_free_rx_irq:
1045         free_irq(lp->rx_irq, dev);
1046 err_release:
1047         korina_free_ring(dev);
1048         goto out;
1049 }
1050
1051 static int korina_close(struct net_device *dev)
1052 {
1053         struct korina_private *lp = netdev_priv(dev);
1054         u32 tmp;
1055
1056         /* Disable interrupts */
1057         disable_irq(lp->rx_irq);
1058         disable_irq(lp->tx_irq);
1059         disable_irq(lp->ovr_irq);
1060         disable_irq(lp->und_irq);
1061
1062         korina_abort_tx(dev);
1063         tmp = readl(&lp->tx_dma_regs->dmasm);
1064         tmp = tmp | DMA_STAT_FINI | DMA_STAT_ERR;
1065         writel(tmp, &lp->tx_dma_regs->dmasm);
1066
1067         korina_abort_rx(dev);
1068         tmp = readl(&lp->rx_dma_regs->dmasm);
1069         tmp = tmp | DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR;
1070         writel(tmp, &lp->rx_dma_regs->dmasm);
1071
1072         korina_free_ring(dev);
1073
1074         napi_disable(&lp->napi);
1075
1076         free_irq(lp->rx_irq, dev);
1077         free_irq(lp->tx_irq, dev);
1078         free_irq(lp->ovr_irq, dev);
1079         free_irq(lp->und_irq, dev);
1080
1081         return 0;
1082 }
1083
1084 static int korina_probe(struct platform_device *pdev)
1085 {
1086         struct korina_device *bif = platform_get_drvdata(pdev);
1087         struct korina_private *lp;
1088         struct net_device *dev;
1089         struct resource *r;
1090         int rc;
1091
1092         dev = alloc_etherdev(sizeof(struct korina_private));
1093         if (!dev) {
1094                 printk(KERN_ERR DRV_NAME ": alloc_etherdev failed\n");
1095                 return -ENOMEM;
1096         }
1097         SET_NETDEV_DEV(dev, &pdev->dev);
1098         lp = netdev_priv(dev);
1099
1100         bif->dev = dev;
1101         memcpy(dev->dev_addr, bif->mac, 6);
1102
1103         lp->rx_irq = platform_get_irq_byname(pdev, "korina_rx");
1104         lp->tx_irq = platform_get_irq_byname(pdev, "korina_tx");
1105         lp->ovr_irq = platform_get_irq_byname(pdev, "korina_ovr");
1106         lp->und_irq = platform_get_irq_byname(pdev, "korina_und");
1107
1108         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_regs");
1109         dev->base_addr = r->start;
1110         lp->eth_regs = ioremap_nocache(r->start, r->end - r->start);
1111         if (!lp->eth_regs) {
1112                 printk(KERN_ERR DRV_NAME "cannot remap registers\n");
1113                 rc = -ENXIO;
1114                 goto probe_err_out;
1115         }
1116
1117         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_rx");
1118         lp->rx_dma_regs = ioremap_nocache(r->start, r->end - r->start);
1119         if (!lp->rx_dma_regs) {
1120                 printk(KERN_ERR DRV_NAME "cannot remap Rx DMA registers\n");
1121                 rc = -ENXIO;
1122                 goto probe_err_dma_rx;
1123         }
1124
1125         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_tx");
1126         lp->tx_dma_regs = ioremap_nocache(r->start, r->end - r->start);
1127         if (!lp->tx_dma_regs) {
1128                 printk(KERN_ERR DRV_NAME "cannot remap Tx DMA registers\n");
1129                 rc = -ENXIO;
1130                 goto probe_err_dma_tx;
1131         }
1132
1133         lp->td_ring = kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1134         if (!lp->td_ring) {
1135                 printk(KERN_ERR DRV_NAME "cannot allocate descriptors\n");
1136                 rc = -ENXIO;
1137                 goto probe_err_td_ring;
1138         }
1139
1140         dma_cache_inv((unsigned long)(lp->td_ring),
1141                         TD_RING_SIZE + RD_RING_SIZE);
1142
1143         /* now convert TD_RING pointer to KSEG1 */
1144         lp->td_ring = (struct dma_desc *)KSEG1ADDR(lp->td_ring);
1145         lp->rd_ring = &lp->td_ring[KORINA_NUM_TDS];
1146
1147         spin_lock_init(&lp->lock);
1148         /* just use the rx dma irq */
1149         dev->irq = lp->rx_irq;
1150         lp->dev = dev;
1151
1152         dev->open = korina_open;
1153         dev->stop = korina_close;
1154         dev->hard_start_xmit = korina_send_packet;
1155         dev->set_multicast_list = &korina_multicast_list;
1156         dev->ethtool_ops = &netdev_ethtool_ops;
1157         dev->tx_timeout = korina_tx_timeout;
1158         dev->watchdog_timeo = TX_TIMEOUT;
1159         dev->do_ioctl = &korina_ioctl;
1160 #ifdef CONFIG_NET_POLL_CONTROLLER
1161         dev->poll_controller = korina_poll_controller;
1162 #endif
1163         netif_napi_add(dev, &lp->napi, korina_poll, 64);
1164
1165         lp->phy_addr = (((lp->rx_irq == 0x2c? 1:0) << 8) | 0x05);
1166         lp->mii_if.dev = dev;
1167         lp->mii_if.mdio_read = mdio_read;
1168         lp->mii_if.mdio_write = mdio_write;
1169         lp->mii_if.phy_id = lp->phy_addr;
1170         lp->mii_if.phy_id_mask = 0x1f;
1171         lp->mii_if.reg_num_mask = 0x1f;
1172
1173         rc = register_netdev(dev);
1174         if (rc < 0) {
1175                 printk(KERN_ERR DRV_NAME
1176                         ": cannot register net device %d\n", rc);
1177                 goto probe_err_register;
1178         }
1179 out:
1180         return rc;
1181
1182 probe_err_register:
1183         kfree(lp->td_ring);
1184 probe_err_td_ring:
1185         iounmap(lp->tx_dma_regs);
1186 probe_err_dma_tx:
1187         iounmap(lp->rx_dma_regs);
1188 probe_err_dma_rx:
1189         iounmap(lp->eth_regs);
1190 probe_err_out:
1191         free_netdev(dev);
1192         goto out;
1193 }
1194
1195 static int korina_remove(struct platform_device *pdev)
1196 {
1197         struct korina_device *bif = platform_get_drvdata(pdev);
1198         struct korina_private *lp = netdev_priv(bif->dev);
1199
1200         iounmap(lp->eth_regs);
1201         iounmap(lp->rx_dma_regs);
1202         iounmap(lp->tx_dma_regs);
1203
1204         platform_set_drvdata(pdev, NULL);
1205         unregister_netdev(bif->dev);
1206         free_netdev(bif->dev);
1207
1208         return 0;
1209 }
1210
1211 static struct platform_driver korina_driver = {
1212         .driver.name = "korina",
1213         .probe = korina_probe,
1214         .remove = korina_remove,
1215 };
1216
1217 static int __init korina_init_module(void)
1218 {
1219         return platform_driver_register(&korina_driver);
1220 }
1221
1222 static void korina_cleanup_module(void)
1223 {
1224         return platform_driver_unregister(&korina_driver);
1225 }
1226
1227 module_init(korina_init_module);
1228 module_exit(korina_cleanup_module);
1229
1230 MODULE_AUTHOR("Philip Rischel <rischelp@idt.com>");
1231 MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>");
1232 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
1233 MODULE_DESCRIPTION("IDT RC32434 (Korina) Ethernet driver");
1234 MODULE_LICENSE("GPL");