git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 1993-2003 NVIDIA, Corporation
   3  * Copyright 2006 Dave Airlie
   4  * Copyright 2007 Maarten Maathuis
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include <assert.h>
  31 #include "xf86.h"
  32 #include "os.h"
  33 #include "mibank.h"
  34 #include "globals.h"
  35 #include "xf86.h"
  36 #include "xf86Priv.h"
  37 #include "xf86DDC.h"
  38 #include "mipointer.h"
  39 #include "windowstr.h"
  40 #include <randrstr.h>
  41 #include <X11/extensions/render.h>
  42
  43 #include "xf86Crtc.h"
  44 #include "nv_include.h"
  45
  46 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  47 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  48 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  49 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  50 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  51 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  52 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  53 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  54
  55 static uint32_t NVCrtcReadCRTC(xf86CrtcPtr crtc, uint32_t reg)
  56 {
  57         ScrnInfoPtr pScrn = crtc->scrn;
  58         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  59         NVPtr pNv = NVPTR(pScrn);
  60
  61         return NVReadCRTC(pNv, nv_crtc->head, reg);
  62 }
  63
  64 static void NVCrtcWriteCRTC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  65 {
  66         ScrnInfoPtr pScrn = crtc->scrn;
  67         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  68         NVPtr pNv = NVPTR(pScrn);
  69
  70         NVWriteCRTC(pNv, nv_crtc->head, reg, val);
  71 }
  72
  73 static uint32_t NVCrtcReadRAMDAC(xf86CrtcPtr crtc, uint32_t reg)
  74 {
  75         ScrnInfoPtr pScrn = crtc->scrn;
  76         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  77         NVPtr pNv = NVPTR(pScrn);
  78
  79         return NVReadRAMDAC(pNv, nv_crtc->head, reg);
  80 }
  81
  82 static void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  83 {
  84         ScrnInfoPtr pScrn = crtc->scrn;
  85         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  86         NVPtr pNv = NVPTR(pScrn);
  87
  88         NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
  89 }
  90
  91 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool lock)
  92 {
  93         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  94         ScrnInfoPtr pScrn = crtc->scrn;
  95         NVPtr pNv = NVPTR(pScrn);
  96
  97         if (pNv->twoHeads)
  98                 NVSetOwner(pScrn, nv_crtc->head);
  99         NVLockVgaCrtc(pNv, nv_crtc->head, lock);
 100 }
 101
 102 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 103 /* They are only valid for NV4x, appearantly reordered for NV5x */
 104 /* gpu pll: 0x4000 + 0x4004
 105  * unknown pll: 0x4008 + 0x400c
 106  * vpll1: 0x4010 + 0x4014
 107  * vpll2: 0x4018 + 0x401c
 108  * unknown pll: 0x4020 + 0x4024
 109  * unknown pll: 0x4038 + 0x403c
 110  * Some of the unknown's are probably memory pll's.
 111  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 112  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 113  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 114  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 115  *     bit8: A switch that turns of the second divider and multiplier off.
 116  *     bit12: Also a switch, i haven't seen it yet.
 117  *     bit16-19: p-divider
 118  *     but 28-31: Something related to the mode that is used (see bit8).
 119  * 2) bit0-7: m-divider (a)
 120  *     bit8-15: n-multiplier (a)
 121  *     bit16-23: m-divider (b)
 122  *     bit24-31: n-multiplier (b)
 123  */
 124
 125 /* Modifying the gpu pll for example requires:
 126  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 127  * This is not needed for the vpll's which have their own bits.
 128  */
 129
 130 static void nv_crtc_save_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 131 {
 132         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 133         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 134         NVPtr pNv = NVPTR(crtc->scrn);
 135
 136         if (nv_crtc->head) {
 137                 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 138                 if (pNv->twoStagePLL)
 139                         regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 140         } else {
 141                 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 142                 if (pNv->twoStagePLL)
 143                         regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 144         }
 145         if (pNv->twoHeads)
 146                 state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 147         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 148         if (pNv->Architecture == NV_ARCH_40)
 149                 state->reg580 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_580);
 150 }
 151
 152 static void nv_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 153 {
 154         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 155         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 156         ScrnInfoPtr pScrn = crtc->scrn;
 157         NVPtr pNv = NVPTR(pScrn);
 158         uint32_t savedc040 = 0;
 159
 160         /* This sequence is important, the NV28 is very sensitive in this area. */
 161         /* Keep pllsel last and sel_clk first. */
 162         if (pNv->twoHeads) {
 163                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_SEL_CLK %08X\n", state->sel_clk);
 164                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
 165         }
 166
 167         if (pNv->Architecture == NV_ARCH_40) {
 168                 savedc040 = nvReadMC(pNv, 0xc040);
 169
 170                 /* for vpll1 change bits 16 and 17 are disabled */
 171                 /* for vpll2 change bits 18 and 19 are disabled */
 172                 nvWriteMC(pNv, 0xc040, savedc040 & ~(3 << (16 + nv_crtc->head * 2)));
 173         }
 174
 175         if (nv_crtc->head) {
 176                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL2 %08X\n", regp->vpll_a);
 177                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, regp->vpll_a);
 178                 if (pNv->twoStagePLL) {
 179                         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL2_B %08X\n", regp->vpll_b);
 180                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, regp->vpll_b);
 181                 }
 182         } else {
 183                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL %08X\n", regp->vpll_a);
 184                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, regp->vpll_a);
 185                 if (pNv->twoStagePLL) {
 186                         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL_B %08X\n", regp->vpll_b);
 187                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, regp->vpll_b);
 188                 }
 189         }
 190
 191         if (pNv->Architecture == NV_ARCH_40) {
 192                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_580 %08X\n", state->reg580);
 193                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
 194
 195                 /* We need to wait a while */
 196                 usleep(5000);
 197                 nvWriteMC(pNv, 0xc040, savedc040);
 198         }
 199
 200         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_PLL_SELECT %08X\n", state->pllsel);
 201         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 202 }
 203
 204 /* Calculate extended mode parameters (SVGA) and save in a mode state structure */
 205 static void nv_crtc_calc_state_ext(xf86CrtcPtr crtc, DisplayModePtr mode, int dot_clock)
 206 {
 207         ScrnInfoPtr pScrn = crtc->scrn;
 208         NVPtr pNv = NVPTR(pScrn);
 209         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 210         RIVA_HW_STATE *state = &pNv->ModeReg;
 211         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 212         struct pll_lims pll_lim;
 213         int NM1 = 0xbeef, NM2 = 0, log2P = 0, VClk = 0;
 214         uint32_t g70_pll_special_bits = 0;
 215         Bool nv4x_single_stage_pll_mode = FALSE;
 216         uint32_t arbitration0, arbitration1;
 217
 218         if (!get_pll_limits(pScrn, nv_crtc->head ? VPLL2 : VPLL1, &pll_lim))
 219                 return;
 220
 221         if (pNv->twoStagePLL || pNv->NVArch == 0x30 || pNv->NVArch == 0x35) {
 222                 if (dot_clock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* use a single VCO */
 223                         nv4x_single_stage_pll_mode = TRUE;
 224                         /* Turn the second set of divider and multiplier off */
 225                         /* Bogus data, the same nvidia uses */
 226                         NM2 = 0x11f;
 227                         VClk = getMNP_single(pScrn, &pll_lim, dot_clock, &NM1, &log2P);
 228                 } else
 229                         VClk = getMNP_double(pScrn, &pll_lim, dot_clock, &NM1, &NM2, &log2P);
 230         } else
 231                 VClk = getMNP_single(pScrn, &pll_lim, dot_clock, &NM1, &log2P);
 232
 233         /* Are these all the (relevant) G70 cards? */
 234         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 235                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 236                 /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 237                 if (nv4x_single_stage_pll_mode)
 238                         g70_pll_special_bits = 0x1;
 239                 else
 240                         g70_pll_special_bits = 0x3;
 241         }
 242
 243         if (pNv->NVArch == 0x30 || pNv->NVArch == 0x35)
 244                 /* See nvregisters.xml for details. */
 245                 regp->vpll_a = (NM2 & (0x18 << 8)) << 13 | (NM2 & (0x7 << 8)) << 11 | log2P << 16 | NV30_RAMDAC_ENABLE_VCO2 | (NM2 & 7) << 4 | NM1;
 246         else
 247                 regp->vpll_a = g70_pll_special_bits << 30 | log2P << 16 | NM1;
 248         regp->vpll_b = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 249
 250         if (nv4x_single_stage_pll_mode) {
 251                 if (nv_crtc->head == 0)
 252                         state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 253                 else
 254                         state->reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 255         } else {
 256                 if (nv_crtc->head == 0)
 257                         state->reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 258                 else
 259                         state->reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 260         }
 261
 262         /* The NV40 seems to have more similarities to NV3x than other NV4x */
 263         if (pNv->NVArch < 0x41)
 264                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL |
 265                                  NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
 266         /* The blob uses this always, so let's do the same */
 267         if (pNv->Architecture == NV_ARCH_40)
 268                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
 269
 270         if (nv_crtc->head == 1) {
 271                 if (!nv4x_single_stage_pll_mode)
 272                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 273                 else
 274                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 275                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
 276         } else {
 277                 if (!nv4x_single_stage_pll_mode)
 278                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 279                 else
 280                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 281                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
 282         }
 283
 284         if ((!pNv->twoStagePLL && pNv->NVArch != 0x30 && pNv->NVArch != 0x35) || nv4x_single_stage_pll_mode)
 285                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n %d m %d log2p %d\n", NM1 >> 8, NM1 & 0xff, log2P);
 286         else
 287                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P);
 288
 289         if (pNv->Architecture == NV_ARCH_04) {
 290                 nv4UpdateArbitrationSettings(VClk, pScrn->bitsPerPixel,
 291                                              &arbitration0, &arbitration1, pNv);
 292
 293                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 294                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 295                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 296         } else {
 297                 uint32_t CursorStart = nv_crtc->head ? pNv->Cursor2->offset : pNv->Cursor->offset;
 298
 299                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 300                     ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 301                         arbitration0 = 128;
 302                         arbitration1 = 0x0480;
 303                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 304                          ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2))
 305                         nForceUpdateArbitrationSettings(VClk, pScrn->bitsPerPixel,
 306                                                         &arbitration0,
 307                                                         &arbitration1, pNv);
 308                 else if (pNv->Architecture < NV_ARCH_30)
 309                         nv10UpdateArbitrationSettings(VClk, pScrn->bitsPerPixel,
 310                                                       &arbitration0,
 311                                                       &arbitration1, pNv);
 312                 else
 313                         nv30UpdateArbitrationSettings(pNv, &arbitration0,
 314                                                       &arbitration1);
 315
 316                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 317                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 318                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 319         }
 320
 321         if (mode->Flags & V_DBLSCAN)
 322                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 323
 324         regp->CRTC[NV_VGA_CRTCX_FIFO0] = arbitration0;
 325         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = arbitration1 & 0xff;
 326         if (pNv->Architecture >= NV_ARCH_30)
 327                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = arbitration1 >> 8;
 328 }
 329
 330 static void
 331 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
 332 {
 333         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 334         ScrnInfoPtr pScrn = crtc->scrn;
 335         NVPtr pNv = NVPTR(pScrn);
 336         unsigned char seq1 = 0, crtc17 = 0;
 337         unsigned char crtc1A;
 338
 339         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_dpms is called for CRTC %d with mode %d.\n", nv_crtc->head, mode);
 340
 341         if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
 342                 return;
 343
 344         nv_crtc->last_dpms = mode;
 345
 346         if (pNv->twoHeads)
 347                 NVSetOwner(pScrn, nv_crtc->head);
 348
 349         crtc1A = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
 350         switch(mode) {
 351                 case DPMSModeStandby:
 352                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
 353                 seq1 = 0x20;
 354                 crtc17 = 0x80;
 355                 crtc1A |= 0x80;
 356                 break;
 357         case DPMSModeSuspend:
 358                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
 359                 seq1 = 0x20;
 360                 crtc17 = 0x80;
 361                 crtc1A |= 0x40;
 362                 break;
 363         case DPMSModeOff:
 364                 /* Screen: Off; HSync: Off, VSync: Off */
 365                 seq1 = 0x20;
 366                 crtc17 = 0x00;
 367                 crtc1A |= 0xC0;
 368                 break;
 369         case DPMSModeOn:
 370         default:
 371                 /* Screen: On; HSync: On, VSync: On */
 372                 seq1 = 0x00;
 373                 crtc17 = 0x80;
 374                 break;
 375         }
 376
 377         NVVgaSeqReset(pNv, nv_crtc->head, true);
 378         /* Each head has it's own sequencer, so we can turn it off when we want */
 379         seq1 |= (NVReadVgaSeq(pNv, nv_crtc->head, 0x01) & ~0x20);
 380         NVWriteVgaSeq(pNv, nv_crtc->head, 0x1, seq1);
 381         crtc17 |= (NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_MODECTL) & ~0x80);
 382         usleep(10000);
 383         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_MODECTL, crtc17);
 384         NVVgaSeqReset(pNv, nv_crtc->head, false);
 385
 386         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1, crtc1A);
 387 }
 388
 389 static Bool
 390 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
 391                      DisplayModePtr adjusted_mode)
 392 {
 393         return TRUE;
 394 }
 395
 396 static void
 397 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 398 {
 399         ScrnInfoPtr pScrn = crtc->scrn;
 400         NVPtr pNv = NVPTR(pScrn);
 401         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 402         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 403
 404         /* Calculate our timings */
 405         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
 406         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
 407         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
 408         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
 409         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
 410         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
 411         int vertDisplay         = mode->CrtcVDisplay                    - 1;
 412         int vertStart           = mode->CrtcVSyncStart          - 1;
 413         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
 414         int vertTotal           = mode->CrtcVTotal                      - 2;
 415         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
 416         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
 417
 418         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 419         bool fp_output = false;
 420         int i;
 421
 422         for (i = 0; i < xf86_config->num_output; i++) {
 423                 xf86OutputPtr output = xf86_config->output[i];
 424                 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 425
 426                 if (output->crtc == crtc && (nv_encoder->dcb->type == OUTPUT_LVDS ||
 427                                              nv_encoder->dcb->type == OUTPUT_TMDS))
 428                         fp_output = true;
 429         }
 430
 431         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Mode clock: %d\n", mode->Clock);
 432         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Adjusted mode clock: %d\n", adjusted_mode->Clock);
 433
 434         if (fp_output) {
 435                 vertStart = vertTotal - 3;
 436                 vertEnd = vertTotal - 2;
 437                 vertBlankStart = vertStart;
 438                 horizStart = horizTotal - 5;
 439                 horizEnd = horizTotal - 2;
 440                 horizBlankEnd = horizTotal + 4;
 441                 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10)
 442                         /* This reportedly works around some video overlay bandwidth problems */
 443                         horizTotal += 2;
 444         }
 445
 446         if (mode->Flags & V_INTERLACE)
 447                 vertTotal |= 1;
 448
 449 #if 0
 450         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
 451         ErrorF("horizStart: 0x%X \n", horizStart);
 452         ErrorF("horizEnd: 0x%X \n", horizEnd);
 453         ErrorF("horizTotal: 0x%X \n", horizTotal);
 454         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
 455         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
 456         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
 457         ErrorF("vertStart: 0x%X \n", vertStart);
 458         ErrorF("vertEnd: 0x%X \n", vertEnd);
 459         ErrorF("vertTotal: 0x%X \n", vertTotal);
 460         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
 461         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
 462 #endif
 463
 464         /*
 465         * compute correct Hsync & Vsync polarity
 466         */
 467         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
 468                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
 469
 470                 regp->MiscOutReg = 0x23;
 471                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
 472                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
 473         } else {
 474                 int VDisplay = mode->VDisplay;
 475                 if (mode->Flags & V_DBLSCAN)
 476                         VDisplay *= 2;
 477                 if (mode->VScan > 1)
 478                         VDisplay *= mode->VScan;
 479                 if (VDisplay < 400)
 480                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
 481                 else if (VDisplay < 480)
 482                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
 483                 else if (VDisplay < 768)
 484                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
 485                 else
 486                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
 487         }
 488
 489         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
 490
 491         /*
 492         * Time Sequencer
 493         */
 494         regp->Sequencer[0] = 0x00;
 495         /* 0x20 disables the sequencer */
 496         if (mode->Flags & V_CLKDIV2)
 497                 regp->Sequencer[1] = 0x29;
 498         else
 499                 regp->Sequencer[1] = 0x21;
 500         regp->Sequencer[2] = 0x0F;
 501         regp->Sequencer[3] = 0x00;                     /* Font select */
 502         regp->Sequencer[4] = 0x0E;                             /* Misc */
 503
 504         /*
 505         * CRTC Controller
 506         */
 507         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
 508         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
 509         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
 510         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
 511                                 | SetBit(7);
 512         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
 513         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
 514                                 | SetBitField(horizEnd,4:0,4:0);
 515         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
 516         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
 517                                 | SetBitField(vertDisplay,8:8,1:1)
 518                                 | SetBitField(vertStart,8:8,2:2)
 519                                 | SetBitField(vertBlankStart,8:8,3:3)
 520                                 | SetBit(4)
 521                                 | SetBitField(vertTotal,9:9,5:5)
 522                                 | SetBitField(vertDisplay,9:9,6:6)
 523                                 | SetBitField(vertStart,9:9,7:7);
 524         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
 525         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
 526                                 | SetBit(6)
 527                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
 528         regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0x00;
 529         regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0x00;
 530         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
 531         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
 532         regp->CRTC[0xe] = 0x00;
 533         regp->CRTC[0xf] = 0x00;
 534         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
 535         /* What is the meaning of bit5, it is empty in the vga spec. */
 536         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
 537         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
 538         /* framebuffer can be larger than crtc scanout area. */
 539         regp->CRTC[NV_VGA_CRTCX_PITCHL] = pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8;
 540         regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x00;
 541         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
 542         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
 543         /* 0x80 enables the sequencer, we don't want that */
 544         regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
 545         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
 546
 547         /*
 548          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
 549          */
 550
 551         /* framebuffer can be larger than crtc scanout area. */
 552         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = ((pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8) & 0x700) >> 3;
 553         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = mode->CrtcHDisplay < 1280 ? 0x04 : 0x00;
 554         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
 555                                 | SetBitField(vertBlankStart,10:10,3:3)
 556                                 | SetBitField(vertStart,10:10,2:2)
 557                                 | SetBitField(vertDisplay,10:10,1:1)
 558                                 | SetBitField(vertTotal,10:10,0:0);
 559
 560         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
 561                                 | SetBitField(horizDisplay,8:8,1:1)
 562                                 | SetBitField(horizBlankStart,8:8,2:2)
 563                                 | SetBitField(horizStart,8:8,3:3);
 564
 565         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
 566                                 | SetBitField(vertDisplay,11:11,2:2)
 567                                 | SetBitField(vertStart,11:11,4:4)
 568                                 | SetBitField(vertBlankStart,11:11,6:6);
 569
 570         if(mode->Flags & V_INTERLACE) {
 571                 horizTotal = (horizTotal >> 1) & ~1;
 572                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
 573                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
 574         } else
 575                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
 576
 577         /*
 578         * Graphics Display Controller
 579         */
 580         regp->Graphics[0] = 0x00;
 581         regp->Graphics[1] = 0x00;
 582         regp->Graphics[2] = 0x00;
 583         regp->Graphics[3] = 0x00;
 584         regp->Graphics[4] = 0x00;
 585         regp->Graphics[5] = 0x40; /* 256 color mode */
 586         regp->Graphics[6] = 0x05; /* map 64k mem + graphic mode */
 587         regp->Graphics[7] = 0x0F;
 588         regp->Graphics[8] = 0xFF;
 589
 590         regp->Attribute[0]  = 0x00; /* standard colormap translation */
 591         regp->Attribute[1]  = 0x01;
 592         regp->Attribute[2]  = 0x02;
 593         regp->Attribute[3]  = 0x03;
 594         regp->Attribute[4]  = 0x04;
 595         regp->Attribute[5]  = 0x05;
 596         regp->Attribute[6]  = 0x06;
 597         regp->Attribute[7]  = 0x07;
 598         regp->Attribute[8]  = 0x08;
 599         regp->Attribute[9]  = 0x09;
 600         regp->Attribute[10] = 0x0A;
 601         regp->Attribute[11] = 0x0B;
 602         regp->Attribute[12] = 0x0C;
 603         regp->Attribute[13] = 0x0D;
 604         regp->Attribute[14] = 0x0E;
 605         regp->Attribute[15] = 0x0F;
 606         regp->Attribute[16] = 0x01; /* Enable graphic mode */
 607         /* Non-vga */
 608         regp->Attribute[17] = 0x00;
 609         regp->Attribute[18] = 0x0F; /* enable all color planes */
 610         regp->Attribute[19] = 0x00;
 611         regp->Attribute[20] = 0x00;
 612 }
 613
 614 /**
 615  * Sets up registers for the given mode/adjusted_mode pair.
 616  *
 617  * The clocks, CRTCs and outputs attached to this CRTC must be off.
 618  *
 619  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
 620  * be easily turned on/off after this.
 621  */
 622 static void
 623 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode)
 624 {
 625         ScrnInfoPtr pScrn = crtc->scrn;
 626         NVPtr pNv = NVPTR(pScrn);
 627         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 628         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 629         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
 630         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 631         bool lvds_output = false, tmds_output = false;
 632         int i;
 633
 634         for (i = 0; i < xf86_config->num_output; i++) {
 635                 xf86OutputPtr output = xf86_config->output[i];
 636                 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 637
 638                 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_LVDS)
 639                         lvds_output = true;
 640                 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_TMDS)
 641                         tmds_output = true;
 642         }
 643
 644         /* Registers not directly related to the (s)vga mode */
 645
 646         /* bit2 = 0 -> fine pitched crtc granularity */
 647         /* The rest disables double buffering on CRTC access */
 648         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
 649
 650         /* the blob sometimes sets |= 0x10 (which is the same as setting |=
 651          * 1 << 30 on 0x60.830), for no apparent reason */
 652         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
 653         if (tmds_output && pNv->Architecture < NV_ARCH_40)
 654                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
 655
 656         /* What is the meaning of this register? */
 657         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
 658         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
 659
 660         regp->head = 0;
 661         /* Except for rare conditions I2C is enabled on the primary crtc */
 662         if (nv_crtc->head == 0)
 663                 regp->head |= NV_CRTC_FSEL_I2C;
 664         /* Set overlay to desired crtc. */
 665         if (pNv->overlayAdaptor) {
 666                 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
 667                 if (pPriv->overlayCRTC == nv_crtc->head)
 668                         regp->head |= NV_CRTC_FSEL_OVERLAY;
 669         }
 670
 671         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
 672         /* This fixes my cursor corruption issue */
 673         regp->cursorConfig = 0x0;
 674         if(mode->Flags & V_DBLSCAN)
 675                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
 676         if (pNv->alphaCursor) {
 677                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32BPP |
 678                                       NV_CRTC_CURSOR_CONFIG_64PIXELS |
 679                                       NV_CRTC_CURSOR_CONFIG_64LINES |
 680                                       NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND;
 681         } else
 682                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES;
 683
 684         /* Unblock some timings */
 685         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
 686         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
 687
 688         /* What is the purpose of this register? */
 689         /* 0x14 may be disabled? */
 690         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
 691
 692         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
 693         if (lvds_output)
 694                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
 695         else if (tmds_output)
 696                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
 697         else
 698                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
 699
 700         /* These values seem to vary */
 701         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
 702         regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = savep->CRTC[NV_VGA_CRTCX_SCRATCH4];
 703
 704         regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
 705
 706         /* What does this do?:
 707          * bit0: crtc0
 708          * bit6: lvds
 709          * bit7: (only in X)
 710          */
 711         if (nv_crtc->head == 0)
 712                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x81;
 713         else
 714                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x80;
 715
 716         if (lvds_output)
 717                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x40;
 718
 719         /* The blob seems to take the current value from crtc 0, add 4 to that
 720          * and reuse the old value for crtc 1 */
 721         regp->CRTC[NV_VGA_CRTCX_52] = pNv->SavedReg.crtc_reg[0].CRTC[NV_VGA_CRTCX_52];
 722         if (!nv_crtc->head)
 723                 regp->CRTC[NV_VGA_CRTCX_52] += 4;
 724
 725         regp->unk830 = mode->CrtcVDisplay - 3;
 726         regp->unk834 = mode->CrtcVDisplay - 1;
 727
 728         if (pNv->twoHeads)
 729                 /* This is what the blob does */
 730                 regp->unk850 = NVReadCRTC(pNv, 0, NV_CRTC_0850);
 731
 732         /* Never ever modify gpio, unless you know very well what you're doing */
 733         regp->gpio = NVReadCRTC(pNv, 0, NV_CRTC_GPIO);
 734
 735         if (pNv->twoHeads)
 736                 regp->gpio_ext = NVReadCRTC(pNv, 0, NV_CRTC_GPIO_EXT);
 737
 738         regp->config = 0x2; /* HSYNC mode */
 739
 740         /* Some misc regs */
 741         if (pNv->Architecture == NV_ARCH_40) {
 742                 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
 743                 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
 744         }
 745
 746         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pScrn->depth + 1) / 8;
 747         /* Enable slaved mode */
 748         if (lvds_output || tmds_output)
 749                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
 750
 751         /* Generic PRAMDAC regs */
 752
 753         if (pNv->Architecture >= NV_ARCH_10)
 754                 /* Only bit that bios and blob set. */
 755                 regp->nv10_cursync = (1 << 25);
 756
 757         switch (pScrn->depth) {
 758                 case 24:
 759                 case 15:
 760                         regp->general = 0x00100130;
 761                         break;
 762                 case 16:
 763                 default:
 764                         regp->general = 0x00101130;
 765                         break;
 766         }
 767         if (pNv->alphaCursor)
 768                 /* PIPE_LONG mode, something to do with the size of the cursor? */
 769                 regp->general |= 1 << 29;
 770
 771         regp->unk_630 = 0; /* turn off green mode (tv test pattern?) */
 772
 773         /* Some values the blob sets */
 774         regp->unk_a20 = 0x0;
 775         regp->unk_a24 = 0xfffff;
 776         regp->unk_a34 = 0x1;
 777 }
 778
 779 /* this could be set in nv_output, but would require some rework of load/save */
 780 static void
 781 nv_crtc_mode_set_fp_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 782 {
 783         ScrnInfoPtr pScrn = crtc->scrn;
 784         NVPtr pNv = NVPTR(pScrn);
 785         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 786         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 787         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
 788         struct nouveau_encoder *nv_encoder = NULL;
 789         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 790         bool is_fp = false;
 791         bool is_lvds = false;
 792         uint32_t mode_ratio, panel_ratio;
 793         int i;
 794
 795         for (i = 0; i < xf86_config->num_output; i++) {
 796                 xf86OutputPtr output = xf86_config->output[i];
 797                 /* assuming one fp output per crtc seems ok */
 798                 nv_encoder = to_nouveau_encoder(output);
 799
 800                 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_LVDS)
 801                         is_lvds = true;
 802                 if (is_lvds || (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_TMDS)) {
 803                         is_fp = true;
 804                         break;
 805                 }
 806         }
 807         if (!is_fp)
 808                 return;
 809
 810         regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
 811         regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
 812         if ((adjusted_mode->HSyncStart - adjusted_mode->HDisplay) >= pNv->VBIOS.digital_min_front_porch)
 813                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
 814         else
 815                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - pNv->VBIOS.digital_min_front_porch - 1;
 816         regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
 817         regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
 818         regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
 819         regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
 820
 821         regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
 822         regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
 823         regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
 824         regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
 825         regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
 826         regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
 827         regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
 828
 829         /*
 830         * bit0: positive vsync
 831         * bit4: positive hsync
 832         * bit8: enable center mode
 833         * bit9: enable native mode
 834         * bit24: 12/24 bit interface (12bit=on, 24bit=off)
 835         * bit26: a bit sometimes seen on some g70 cards
 836         * bit28: fp display enable bit
 837         * bit31: set for dual link LVDS
 838         */
 839
 840         regp->fp_control = (savep->fp_control & 0x04100000) |
 841                            NV_RAMDAC_FP_CONTROL_DISPEN_POS;
 842
 843         /* Deal with vsync/hsync polarity */
 844         /* LVDS screens do set this, but modes with +ve syncs are very rare */
 845         if (adjusted_mode->Flags & V_PVSYNC)
 846                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
 847         if (adjusted_mode->Flags & V_PHSYNC)
 848                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
 849
 850         if (nv_encoder->scaling_mode == SCALE_PANEL ||
 851             nv_encoder->scaling_mode == SCALE_NOSCALE) /* panel needs to scale */
 852                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
 853         /* This is also true for panel scaling, so we must put the panel scale check first */
 854         else if (mode->HDisplay == adjusted_mode->HDisplay &&
 855                  mode->VDisplay == adjusted_mode->VDisplay) /* native mode */
 856                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
 857         else /* gpu needs to scale */
 858                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
 859
 860         if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
 861                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_WIDTH_12;
 862
 863         if (is_lvds && pNv->VBIOS.fp.dual_link)
 864                 regp->fp_control |= (8 << 28);
 865
 866         /* Use the generic value, and enable x-scaling, y-scaling, and the TMDS enable bit */
 867         regp->debug_0 = 0x01101191;
 868         /* We want automatic scaling */
 869         regp->debug_1 = 0;
 870         /* This can override HTOTAL and VTOTAL */
 871         regp->debug_2 = 0;
 872
 873         /* Use 20.12 fixed point format to avoid floats */
 874         mode_ratio = (1 << 12) * mode->HDisplay / mode->VDisplay;
 875         panel_ratio = (1 << 12) * adjusted_mode->HDisplay / adjusted_mode->VDisplay;
 876         /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
 877          * get treated the same as SCALE_FULLSCREEN */
 878         if (nv_encoder->scaling_mode == SCALE_ASPECT && mode_ratio != panel_ratio) {
 879                 uint32_t diff, scale;
 880
 881                 if (mode_ratio < panel_ratio) {
 882                         /* vertical needs to expand to glass size (automatic)
 883                          * horizontal needs to be scaled at vertical scale factor
 884                          * to maintain aspect */
 885
 886                         scale = (1 << 12) * mode->VDisplay / adjusted_mode->VDisplay;
 887                         regp->debug_1 = 1 << 12 | ((scale >> 1) & 0xfff);
 888
 889                         /* restrict area of screen used, horizontally */
 890                         diff = adjusted_mode->HDisplay -
 891                                adjusted_mode->VDisplay * mode_ratio / (1 << 12);
 892                         regp->fp_horiz_regs[REG_DISP_VALID_START] += diff / 2;
 893                         regp->fp_horiz_regs[REG_DISP_VALID_END] -= diff / 2;
 894                 }
 895
 896                 if (mode_ratio > panel_ratio) {
 897                         /* horizontal needs to expand to glass size (automatic)
 898                          * vertical needs to be scaled at horizontal scale factor
 899                          * to maintain aspect */
 900
 901                         scale = (1 << 12) * mode->HDisplay / adjusted_mode->HDisplay;
 902                         regp->debug_1 = 1 << 28 | ((scale >> 1) & 0xfff) << 16;
 903
 904                         /* restrict area of screen used, vertically */
 905                         diff = adjusted_mode->VDisplay -
 906                                (1 << 12) * adjusted_mode->HDisplay / mode_ratio;
 907                         regp->fp_vert_regs[REG_DISP_VALID_START] += diff / 2;
 908                         regp->fp_vert_regs[REG_DISP_VALID_END] -= diff / 2;
 909                 }
 910         }
 911
 912         /* Flatpanel support needs at least a NV10 */
 913         if (pNv->twoHeads) {
 914                 /* Output property. */
 915                 if (nv_encoder && nv_encoder->dithering) {
 916                         if (pNv->NVArch == 0x11)
 917                                 regp->dither = savep->dither | 0x00010000;
 918                         else {
 919                                 int i;
 920                                 regp->dither = savep->dither | 0x00000001;
 921                                 for (i = 0; i < 3; i++) {
 922                                         regp->dither_regs[i] = 0xe4e4e4e4;
 923                                         regp->dither_regs[i + 3] = 0x44444444;
 924                                 }
 925                         }
 926                 } else {
 927                         if (pNv->NVArch != 0x11) {
 928                                 /* reset them */
 929                                 int i;
 930                                 for (i = 0; i < 3; i++) {
 931                                         regp->dither_regs[i] = savep->dither_regs[i];
 932                                         regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
 933                                 }
 934                         }
 935                         regp->dither = savep->dither;
 936                 }
 937         } else
 938                 regp->dither = savep->dither;
 939 }
 940
 941 /**
 942  * Sets up registers for the given mode/adjusted_mode pair.
 943  *
 944  * The clocks, CRTCs and outputs attached to this CRTC must be off.
 945  *
 946  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
 947  * be easily turned on/off after this.
 948  */
 949 static void
 950 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 951                  DisplayModePtr adjusted_mode,
 952                  int x, int y)
 953 {
 954         ScrnInfoPtr pScrn = crtc->scrn;
 955         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 956         NVPtr pNv = NVPTR(pScrn);
 957
 958         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_mode_set is called for CRTC %d.\n", nv_crtc->head);
 959
 960         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
 961         xf86PrintModeline(pScrn->scrnIndex, mode);
 962         if (pNv->twoHeads)
 963                 NVSetOwner(pScrn, nv_crtc->head);
 964
 965         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
 966
 967         /* calculated in output_prepare, nv40 needs it written before calculating PLLs */
 968         if (pNv->Architecture == NV_ARCH_40) {
 969                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_SEL_CLK %08X\n", pNv->ModeReg.sel_clk);
 970                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
 971         }
 972         nv_crtc_mode_set_regs(crtc, mode);
 973         nv_crtc_mode_set_fp_regs(crtc, mode, adjusted_mode);
 974         nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->Clock);
 975
 976         NVVgaProtect(pNv, nv_crtc->head, true);
 977         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
 978         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
 979         nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
 980         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
 981         nv_crtc_load_state_pll(crtc, &pNv->ModeReg);
 982
 983         NVVgaProtect(pNv, nv_crtc->head, false);
 984
 985         NVCrtcSetBase(crtc, x, y);
 986
 987 #if X_BYTE_ORDER == X_BIG_ENDIAN
 988         /* turn on LFB swapping */
 989         {
 990                 unsigned char tmp;
 991
 992                 tmp = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SWAPPING);
 993                 tmp |= (1 << 7);
 994                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SWAPPING, tmp);
 995         }
 996 #endif
 997 }
 998
 999 static void nv_crtc_save(xf86CrtcPtr crtc)
1000 {
1001         ScrnInfoPtr pScrn = crtc->scrn;
1002         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1003         NVPtr pNv = NVPTR(pScrn);
1004
1005         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_save is called for CRTC %d.\n", nv_crtc->head);
1006
1007         /* We just came back from terminal, so unlock */
1008         NVCrtcLockUnlock(crtc, FALSE);
1009
1010         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
1011         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
1012         nv_crtc_save_state_palette(crtc, &pNv->SavedReg);
1013         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
1014         nv_crtc_save_state_pll(crtc, &pNv->SavedReg);
1015
1016         /* init some state to saved value */
1017         pNv->ModeReg.reg580 = pNv->SavedReg.reg580;
1018         pNv->ModeReg.sel_clk = pNv->SavedReg.sel_clk & ~(0x5 << 16);
1019         pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_VGA_CRTCX_LCD] = pNv->SavedReg.crtc_reg[nv_crtc->head].CRTC[NV_VGA_CRTCX_LCD];
1020 }
1021
1022 static void nv_crtc_restore(xf86CrtcPtr crtc)
1023 {
1024         ScrnInfoPtr pScrn = crtc->scrn;
1025         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1026         NVPtr pNv = NVPTR(pScrn);
1027         RIVA_HW_STATE *state;
1028         NVCrtcRegPtr savep;
1029
1030         state = &pNv->SavedReg;
1031         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1032
1033         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_restore is called for CRTC %d.\n", nv_crtc->head);
1034
1035         /* Just to be safe */
1036         NVCrtcLockUnlock(crtc, FALSE);
1037
1038         NVVgaProtect(pNv, nv_crtc->head, true);
1039         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
1040         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
1041         nv_crtc_load_state_palette(crtc, &pNv->SavedReg);
1042         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1043         nv_crtc_load_state_pll(crtc, &pNv->SavedReg);
1044         NVVgaProtect(pNv, nv_crtc->head, false);
1045
1046         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1047 }
1048
1049 static void nv_crtc_prepare(xf86CrtcPtr crtc)
1050 {
1051         ScrnInfoPtr pScrn = crtc->scrn;
1052         NVPtr pNv = NVPTR(pScrn);
1053         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1054
1055         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_prepare is called for CRTC %d.\n", nv_crtc->head);
1056
1057         /* Just in case */
1058         NVCrtcLockUnlock(crtc, 0);
1059
1060         crtc->funcs->dpms(crtc, DPMSModeOff);
1061
1062         /* Sync the engine before adjust mode */
1063         if (pNv->EXADriverPtr) {
1064                 exaMarkSync(pScrn->pScreen);
1065                 exaWaitSync(pScrn->pScreen);
1066         }
1067
1068         NVBlankScreen(pScrn, nv_crtc->head, true);
1069
1070         /* Some more preperation. */
1071         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
1072         if (pNv->Architecture == NV_ARCH_40) {
1073                 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1074                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1075         }
1076 }
1077
1078 static void nv_crtc_commit(xf86CrtcPtr crtc)
1079 {
1080         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1081         ScrnInfoPtr pScrn = crtc->scrn;
1082         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_commit for CRTC %d.\n", nv_crtc->head);
1083
1084         crtc->funcs->dpms (crtc, DPMSModeOn);
1085
1086         if (crtc->scrn->pScreen != NULL) {
1087                 NVPtr pNv = NVPTR(crtc->scrn);
1088
1089                 xf86_reload_cursors (crtc->scrn->pScreen);
1090                 if (!pNv->alphaCursor) {
1091                         /* this works round the fact that xf86_reload_cursors
1092                          * will quite happily show the hw cursor when it knows
1093                          * the hardware can't do alpha, and the current cursor
1094                          * has an alpha channel
1095                          */
1096                         xf86ForceHWCursor(crtc->scrn->pScreen, 1);
1097                         xf86ForceHWCursor(crtc->scrn->pScreen, 0);
1098                 }
1099         }
1100 }
1101
1102 static void nv_crtc_destroy(xf86CrtcPtr crtc)
1103 {
1104         xfree(to_nouveau_crtc(crtc));
1105 }
1106
1107 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1108 {
1109         return FALSE;
1110 }
1111
1112 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1113 {
1114 }
1115
1116 static void
1117 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
1118                                         int size)
1119 {
1120         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1121         ScrnInfoPtr pScrn = crtc->scrn;
1122         NVPtr pNv = NVPTR(pScrn);
1123         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1124         int i, j;
1125
1126         switch (pScrn->depth) {
1127         case 15:
1128                 /* R5G5B5 */
1129                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
1130                 for (i = 0; i < 32; i++)
1131                         for (j = 0; j < 8; j++) {
1132                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1133                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
1134                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1135                         }
1136                 break;
1137         case 16:
1138                 /* R5G6B5 */
1139                 /* First deal with the 5 bit colors */
1140                 for (i = 0; i < 32; i++)
1141                         for (j = 0; j < 8; j++) {
1142                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1143                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1144                         }
1145                 /* Now deal with the 6 bit color */
1146                 for (i = 0; i < 64; i++)
1147                         for (j = 0; j < 4; j++)
1148                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
1149                 break;
1150         default:
1151                 /* R8G8B8 */
1152                 for (i = 0; i < 256; i++) {
1153                         regp->DAC[i * 3] = red[i] >> 8;
1154                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
1155                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
1156                 }
1157                 break;
1158         }
1159
1160         nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
1161 }
1162
1163 /**
1164  * Allocates memory for a locked-in-framebuffer shadow of the given
1165  * width and height for this CRTC's rotated shadow framebuffer.
1166  */
1167
1168 static void *
1169 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
1170 {
1171         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1172         ScrnInfoPtr pScrn = crtc->scrn;
1173 #if !NOUVEAU_EXA_PIXMAPS
1174         ScreenPtr pScreen = pScrn->pScreen;
1175 #endif /* !NOUVEAU_EXA_PIXMAPS */
1176         NVPtr pNv = NVPTR(pScrn);
1177         void *offset;
1178
1179         unsigned long rotate_pitch;
1180         int size, align = 64;
1181
1182         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_shadow_allocate is called.\n");
1183
1184         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1185         size = rotate_pitch * height;
1186
1187         assert(nv_crtc->shadow == NULL);
1188 #if NOUVEAU_EXA_PIXMAPS
1189         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
1190                         align, size, &nv_crtc->shadow)) {
1191                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to allocate memory for shadow buffer!\n");
1192                 return NULL;
1193         }
1194
1195         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
1196                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1197                                 "Failed to map shadow buffer.\n");
1198                 return NULL;
1199         }
1200
1201         offset = nv_crtc->shadow->map;
1202 #else
1203         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
1204         if (nv_crtc->shadow == NULL) {
1205                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1206                         "Couldn't allocate shadow memory for rotated CRTC.\n");
1207                 return NULL;
1208         }
1209         offset = pNv->FB->map + nv_crtc->shadow->offset;
1210 #endif /* NOUVEAU_EXA_PIXMAPS */
1211
1212         return offset;
1213 }
1214
1215 /**
1216  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
1217  */
1218 static PixmapPtr
1219 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
1220 {
1221         ScrnInfoPtr pScrn = crtc->scrn;
1222 #if NOUVEAU_EXA_PIXMAPS
1223         ScreenPtr pScreen = pScrn->pScreen;
1224         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1225 #endif /* NOUVEAU_EXA_PIXMAPS */
1226         unsigned long rotate_pitch;
1227         PixmapPtr rotate_pixmap;
1228 #if NOUVEAU_EXA_PIXMAPS
1229         struct nouveau_pixmap *nvpix;
1230 #endif /* NOUVEAU_EXA_PIXMAPS */
1231
1232         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_shadow_create is called.\n");
1233
1234         if (!data)
1235                 data = crtc->funcs->shadow_allocate (crtc, width, height);
1236
1237         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1238
1239 #if NOUVEAU_EXA_PIXMAPS
1240         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
1241         rotate_pixmap = pScreen->CreatePixmap(pScreen,
1242                                                                 0, /* width */
1243                                                                 0, /* height */
1244         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
1245                                                                 pScrn->depth,
1246                                                                 0);
1247         #else
1248                                                                 pScrn->depth);
1249         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
1250 #else
1251         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
1252                                                                 width, height,
1253                                                                 pScrn->depth,
1254                                                                 pScrn->bitsPerPixel,
1255                                                                 rotate_pitch,
1256                                                                 data);
1257 #endif /* NOUVEAU_EXA_PIXMAPS */
1258
1259         if (rotate_pixmap == NULL) {
1260                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1261                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
1262         }
1263
1264 #if NOUVEAU_EXA_PIXMAPS
1265         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1266         if (!nvpix) {
1267                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No initial shadow private available for rotation.\n");
1268         } else {
1269                 nvpix->bo = nv_crtc->shadow;
1270                 nvpix->mapped = TRUE;
1271         }
1272
1273         /* Modify the pixmap to actually be the one we need. */
1274         pScreen->ModifyPixmapHeader(rotate_pixmap,
1275                                         width,
1276                                         height,
1277                                         pScrn->depth,
1278                                         pScrn->bitsPerPixel,
1279                                         rotate_pitch,
1280                                         data);
1281
1282         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1283         if (!nvpix || !nvpix->bo)
1284                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No final shadow private available for rotation.\n");
1285 #endif /* NOUVEAU_EXA_PIXMAPS */
1286
1287         return rotate_pixmap;
1288 }
1289
1290 static void
1291 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
1292 {
1293         ScrnInfoPtr pScrn = crtc->scrn;
1294         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1295         ScreenPtr pScreen = pScrn->pScreen;
1296
1297         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_shadow_destroy is called.\n");
1298
1299         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
1300                 pScreen->DestroyPixmap(rotate_pixmap);
1301         }
1302
1303 #if !NOUVEAU_EXA_PIXMAPS
1304         if (data && nv_crtc->shadow) {
1305                 exaOffscreenFree(pScreen, nv_crtc->shadow);
1306         }
1307 #endif /* !NOUVEAU_EXA_PIXMAPS */
1308
1309         nv_crtc->shadow = NULL;
1310 }
1311
1312 static const xf86CrtcFuncsRec nv_crtc_funcs = {
1313         .dpms = nv_crtc_dpms,
1314         .save = nv_crtc_save,
1315         .restore = nv_crtc_restore,
1316         .mode_fixup = nv_crtc_mode_fixup,
1317         .mode_set = nv_crtc_mode_set,
1318         .prepare = nv_crtc_prepare,
1319         .commit = nv_crtc_commit,
1320         .destroy = nv_crtc_destroy,
1321         .lock = nv_crtc_lock,
1322         .unlock = nv_crtc_unlock,
1323         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
1324         .set_cursor_position = nv_crtc_set_cursor_position,
1325         .show_cursor = nv_crtc_show_cursor,
1326         .hide_cursor = nv_crtc_hide_cursor,
1327         .load_cursor_argb = nv_crtc_load_cursor_argb,
1328         .gamma_set = nv_crtc_gamma_set,
1329         .shadow_create = nv_crtc_shadow_create,
1330         .shadow_allocate = nv_crtc_shadow_allocate,
1331         .shadow_destroy = nv_crtc_shadow_destroy,
1332 };
1333
1334 void
1335 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
1336 {
1337         NVPtr pNv = NVPTR(pScrn);
1338         static xf86CrtcFuncsRec crtcfuncs;
1339         xf86CrtcPtr crtc;
1340         struct nouveau_crtc *nv_crtc;
1341         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[crtc_num];
1342         int i;
1343
1344         crtcfuncs = nv_crtc_funcs;
1345
1346         /* NV04-NV10 doesn't support alpha cursors */
1347         if (pNv->NVArch < 0x11) {
1348                 crtcfuncs.set_cursor_colors = nv_crtc_set_cursor_colors;
1349                 crtcfuncs.load_cursor_image = nv_crtc_load_cursor_image;
1350                 crtcfuncs.load_cursor_argb = NULL;
1351         }
1352         if (pNv->NoAccel) {
1353                 crtcfuncs.shadow_create = NULL;
1354                 crtcfuncs.shadow_allocate = NULL;
1355                 crtcfuncs.shadow_destroy = NULL;
1356         }
1357
1358         crtc = xf86CrtcCreate(pScrn, &crtcfuncs);
1359         if (crtc == NULL)
1360                 return;
1361
1362         nv_crtc = xnfcalloc (sizeof (struct nouveau_crtc), 1);
1363         nv_crtc->head = crtc_num;
1364         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1365
1366         crtc->driver_private = nv_crtc;
1367
1368         /* Initialise the default LUT table. */
1369         for (i = 0; i < 256; i++) {
1370                 regp->DAC[i*3] = i;
1371                 regp->DAC[(i*3)+1] = i;
1372                 regp->DAC[(i*3)+2] = i;
1373         }
1374
1375         NVCrtcLockUnlock(crtc, FALSE);
1376 }
1377
1378 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1379 {
1380         ScrnInfoPtr pScrn = crtc->scrn;
1381         NVPtr pNv = NVPTR(pScrn);
1382         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1383         int i;
1384         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1385
1386         NVWritePVIO(pNv, nv_crtc->head, VGA_MISC_OUT_W, regp->MiscOutReg);
1387
1388         for (i = 0; i < 5; i++)
1389                 NVWriteVgaSeq(pNv, nv_crtc->head, i, regp->Sequencer[i]);
1390
1391         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
1392         NVWriteVgaCrtc(pNv, nv_crtc->head, 17, regp->CRTC[17] & ~0x80);
1393
1394         for (i = 0; i < 25; i++)
1395                 NVWriteVgaCrtc(pNv, nv_crtc->head, i, regp->CRTC[i]);
1396
1397         for (i = 0; i < 9; i++)
1398                 NVWriteVgaGr(pNv, nv_crtc->head, i, regp->Graphics[i]);
1399
1400         NVSetEnablePalette(pNv, nv_crtc->head, true);
1401         for (i = 0; i < 21; i++)
1402                 NVWriteVgaAttr(pNv, nv_crtc->head, i, regp->Attribute[i]);
1403
1404         NVSetEnablePalette(pNv, nv_crtc->head, false);
1405 }
1406
1407 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
1408 {
1409         ScrnInfoPtr pScrn = crtc->scrn;
1410         NVPtr pNv = NVPTR(pScrn);
1411         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1412         NVCrtcRegPtr regp;
1413         int i;
1414
1415         regp = &state->crtc_reg[nv_crtc->head];
1416
1417         if (pNv->Architecture >= NV_ARCH_10) {
1418                 if (pNv->twoHeads)
1419                         /* setting FSEL *must* come before CRTCX_LCD, as writing CRTCX_LCD sets some
1420                          * bits (16 & 17) in FSEL that should not be overwritten by writing FSEL */
1421                         NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, regp->head);
1422
1423                 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
1424                 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
1425                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
1426                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
1427                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1428                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1429                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1430                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1431                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
1432
1433                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
1434                 NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
1435                 NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
1436                 NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
1437                 if (pNv->Architecture == NV_ARCH_40) {
1438                         NVCrtcWriteCRTC(crtc, NV_CRTC_0850, regp->unk850);
1439                         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO_EXT, regp->gpio_ext);
1440                 }
1441
1442                 if (pNv->Architecture == NV_ARCH_40) {
1443                         uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1444                         if (regp->config == 0x2) /* enhanced "horizontal only" non-vga mode */
1445                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 | 0x10000);
1446                         else
1447                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1448                 }
1449         }
1450
1451         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
1452         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio);
1453
1454         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
1455         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
1456         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
1457         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
1458         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
1459         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
1460         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
1461         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
1462         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
1463         if (pNv->Architecture >= NV_ARCH_30)
1464                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
1465
1466         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
1467         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
1468         if (pNv->Architecture == NV_ARCH_40) /* HW bug */
1469                 nv_crtc_fix_nv40_hw_cursor(pScrn, nv_crtc->head);
1470         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
1471         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
1472
1473         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
1474         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
1475         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SCRATCH4, regp->CRTC[NV_VGA_CRTCX_SCRATCH4]);
1476         if (pNv->Architecture >= NV_ARCH_10) {
1477                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
1478                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
1479                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
1480                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
1481         }
1482         /* NV11 and NV20 stop at 0x52. */
1483         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1484                 if (override)
1485                         for (i = 0; i < 0x10; i++)
1486                                 NVWriteVgaCrtc5758(pNv, nv_crtc->head, i, regp->CR58[i]);
1487
1488                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
1489                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
1490
1491                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
1492
1493                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
1494                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
1495         }
1496
1497         if (override)
1498                 NVCrtcWriteCRTC(crtc, NV_CRTC_START, regp->fb_start);
1499
1500         /* Setting 1 on this value gives you interrupts for every vblank period. */
1501         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_EN_0, 0);
1502         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
1503 }
1504
1505 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1506 {
1507         ScrnInfoPtr pScrn = crtc->scrn;
1508         NVPtr pNv = NVPTR(pScrn);
1509         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1510         int i;
1511         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1512
1513         regp->MiscOutReg = NVReadPVIO(pNv, nv_crtc->head, VGA_MISC_OUT_R);
1514
1515         for (i = 0; i < 25; i++)
1516                 regp->CRTC[i] = NVReadVgaCrtc(pNv, nv_crtc->head, i);
1517
1518         NVSetEnablePalette(pNv, nv_crtc->head, true);
1519         for (i = 0; i < 21; i++)
1520                 regp->Attribute[i] = NVReadVgaAttr(pNv, nv_crtc->head, i);
1521         NVSetEnablePalette(pNv, nv_crtc->head, false);
1522
1523         for (i = 0; i < 9; i++)
1524                 regp->Graphics[i] = NVReadVgaGr(pNv, nv_crtc->head, i);
1525
1526         for (i = 0; i < 5; i++)
1527                 regp->Sequencer[i] = NVReadVgaSeq(pNv, nv_crtc->head, i);
1528 }
1529
1530 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1531 {
1532         ScrnInfoPtr pScrn = crtc->scrn;
1533         NVPtr pNv = NVPTR(pScrn);
1534         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1535         NVCrtcRegPtr regp;
1536         int i;
1537
1538         regp = &state->crtc_reg[nv_crtc->head];
1539
1540         regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD);
1541         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT0);
1542         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1);
1543         regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LSR);
1544         regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_PIXEL);
1545         regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_HEB);
1546         regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO1);
1547
1548         regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO0);
1549         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM);
1550         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_BUFFER);
1551         if (pNv->Architecture >= NV_ARCH_30)
1552                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM_NV30);
1553         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL0);
1554         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL1);
1555         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL2);
1556         regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_INTERLACE);
1557
1558         if (pNv->Architecture >= NV_ARCH_10) {
1559                 regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
1560                 regp->unk834 = NVCrtcReadCRTC(crtc, NV_CRTC_0834);
1561                 if (pNv->Architecture == NV_ARCH_40) {
1562                         regp->unk850 = NVCrtcReadCRTC(crtc, NV_CRTC_0850);
1563                         regp->gpio_ext = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO_EXT);
1564                 }
1565                 if (pNv->twoHeads) {
1566                         regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL);
1567                         regp->crtcOwner = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_OWNER);
1568                 }
1569                 regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG);
1570         }
1571
1572         regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO);
1573         regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
1574
1575         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_26);
1576         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_3B);
1577         regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SCRATCH4);
1578         if (pNv->Architecture >= NV_ARCH_10) {
1579                 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_EXTRA);
1580                 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_45);
1581                 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_4B);
1582                 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_52);
1583         }
1584         /* NV11 and NV20 don't have this, they stop at 0x52. */
1585         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1586                 for (i = 0; i < 0x10; i++)
1587                         regp->CR58[i] = NVReadVgaCrtc5758(pNv, nv_crtc->head, i);
1588
1589                 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_59);
1590                 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_HTIMING);
1591                 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_VTIMING);
1592
1593                 regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_85);
1594                 regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_86);
1595         }
1596
1597         regp->fb_start = NVCrtcReadCRTC(crtc, NV_CRTC_START);
1598 }
1599
1600 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1601 {
1602         ScrnInfoPtr pScrn = crtc->scrn;
1603         NVPtr pNv = NVPTR(pScrn);
1604         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1605         NVCrtcRegPtr regp;
1606         int i;
1607
1608         regp = &state->crtc_reg[nv_crtc->head];
1609
1610         regp->general = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL);
1611
1612         if (pNv->twoHeads) {
1613                 if (pNv->NVArch >= 0x17)
1614                         regp->unk_630 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_630);
1615                 regp->fp_control        = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_CONTROL);
1616                 regp->debug_0   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0);
1617                 regp->debug_1   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1);
1618                 regp->debug_2   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2);
1619
1620                 regp->unk_a20 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A20);
1621                 regp->unk_a24 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A24);
1622                 regp->unk_a34 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A34);
1623         }
1624
1625         if (pNv->NVArch == 0x11) {
1626                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_DITHER_NV11);
1627         } else if (pNv->twoHeads) {
1628                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DITHER);
1629                 for (i = 0; i < 3; i++) {
1630                         regp->dither_regs[i] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4);
1631                         regp->dither_regs[i + 3] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4);
1632                 }
1633         }
1634         if (pNv->Architecture >= NV_ARCH_10)
1635                 regp->nv10_cursync = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC);
1636
1637         /* The regs below are 0 for non-flatpanels, so you can load and save them */
1638
1639         for (i = 0; i < 7; i++) {
1640                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
1641                 regp->fp_horiz_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1642         }
1643
1644         for (i = 0; i < 7; i++) {
1645                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
1646                 regp->fp_vert_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1647         }
1648 }
1649
1650 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1651 {
1652         ScrnInfoPtr pScrn = crtc->scrn;
1653         NVPtr pNv = NVPTR(pScrn);
1654         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1655         NVCrtcRegPtr regp;
1656         int i;
1657
1658         regp = &state->crtc_reg[nv_crtc->head];
1659
1660         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL, regp->general);
1661
1662         if (pNv->twoHeads) {
1663                 if (pNv->NVArch >= 0x17)
1664                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_630, regp->unk_630);
1665                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_CONTROL, regp->fp_control);
1666                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
1667                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
1668                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
1669                 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
1670                         uint32_t reg890 = NVCrtcReadRAMDAC(crtc, NV30_RAMDAC_890);
1671                         NVCrtcWriteRAMDAC(crtc, NV30_RAMDAC_89C, reg890);
1672                 }
1673
1674                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A20, regp->unk_a20);
1675                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A24, regp->unk_a24);
1676                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A34, regp->unk_a34);
1677         }
1678
1679         if (pNv->NVArch == 0x11)
1680                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_DITHER_NV11, regp->dither);
1681         else if (pNv->twoHeads) {
1682                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DITHER, regp->dither);
1683                 for (i = 0; i < 3; i++) {
1684                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4, regp->dither_regs[i]);
1685                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4, regp->dither_regs[i + 3]);
1686                 }
1687         }
1688         if (pNv->Architecture >= NV_ARCH_10)
1689                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
1690
1691         /* The regs below are 0 for non-flatpanels, so you can load and save them */
1692
1693         for (i = 0; i < 7; i++) {
1694                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
1695                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_horiz_regs[i]);
1696         }
1697
1698         for (i = 0; i < 7; i++) {
1699                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
1700                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_vert_regs[i]);
1701         }
1702 }
1703
1704 void NVCrtcSetBase(xf86CrtcPtr crtc, int x, int y)
1705 {
1706         ScrnInfoPtr pScrn = crtc->scrn;
1707         NVPtr pNv = NVPTR(pScrn);
1708         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1709         uint32_t start = (y * pScrn->displayWidth + x) * pScrn->bitsPerPixel / 8;
1710
1711         if (crtc->rotatedData != NULL) /* we do not exist on the real framebuffer */
1712 #if NOUVEAU_EXA_PIXMAPS
1713                 start = nv_crtc->shadow->offset;
1714 #else
1715                 start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
1716 #endif
1717         else
1718                 start += pNv->FB->offset;
1719
1720         /* 30 bits addresses in 32 bits according to haiku */
1721         NVCrtcWriteCRTC(crtc, NV_CRTC_START, start & 0xfffffffc);
1722
1723         crtc->x = x;
1724         crtc->y = y;
1725 }
1726
1727 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1728 {
1729         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1730         NVPtr pNv = NVPTR(crtc->scrn);
1731         uint32_t mmiobase = nv_crtc->head ? NV_PDIO1_OFFSET : NV_PDIO0_OFFSET;
1732         int i;
1733
1734         VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff);
1735         VGA_WR08(pNv->REGS, VGA_DAC_READ_ADDR + mmiobase, 0x0);
1736
1737         for (i = 0; i < 768; i++) {
1738                 state->crtc_reg[nv_crtc->head].DAC[i] = NV_RD08(pNv->REGS, VGA_DAC_DATA + mmiobase);
1739                 DDXMMIOH("nv_crtc_save_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
1740         }
1741
1742         NVSetEnablePalette(pNv, nv_crtc->head, false);
1743 }
1744 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1745 {
1746         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1747         NVPtr pNv = NVPTR(crtc->scrn);
1748         uint32_t mmiobase = nv_crtc->head ? NV_PDIO1_OFFSET : NV_PDIO0_OFFSET;
1749         int i;
1750
1751         VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff);
1752         VGA_WR08(pNv->REGS, VGA_DAC_WRITE_ADDR + mmiobase, 0x0);
1753
1754         for (i = 0; i < 768; i++) {
1755                 DDXMMIOH("nv_crtc_load_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
1756                 NV_WR08(pNv->REGS, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
1757         }
1758
1759         NVSetEnablePalette(pNv, nv_crtc->head, false);
1760 }