git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 1993-2003 NVIDIA, Corporation
   3  * Copyright 2006 Dave Airlie
   4  * Copyright 2007 Maarten Maathuis
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "nv_include.h"
  27
  28 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  29 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  30 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  31 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  32 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  33 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  34 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  35 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  36
  37 static uint32_t NVCrtcReadCRTC(xf86CrtcPtr crtc, uint32_t reg)
  38 {
  39         ScrnInfoPtr pScrn = crtc->scrn;
  40         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  41         NVPtr pNv = NVPTR(pScrn);
  42
  43         return NVReadCRTC(pNv, nv_crtc->head, reg);
  44 }
  45
  46 static void NVCrtcWriteCRTC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  47 {
  48         ScrnInfoPtr pScrn = crtc->scrn;
  49         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  50         NVPtr pNv = NVPTR(pScrn);
  51
  52         NVWriteCRTC(pNv, nv_crtc->head, reg, val);
  53 }
  54
  55 static uint32_t NVCrtcReadRAMDAC(xf86CrtcPtr crtc, uint32_t reg)
  56 {
  57         ScrnInfoPtr pScrn = crtc->scrn;
  58         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  59         NVPtr pNv = NVPTR(pScrn);
  60
  61         return NVReadRAMDAC(pNv, nv_crtc->head, reg);
  62 }
  63
  64 static void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  65 {
  66         ScrnInfoPtr pScrn = crtc->scrn;
  67         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  68         NVPtr pNv = NVPTR(pScrn);
  69
  70         NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
  71 }
  72
  73 static void crtc_rd_cio_state(xf86CrtcPtr crtc, NVCrtcRegPtr crtcstate, int index)
  74 {
  75         crtcstate->CRTC[index] = NVReadVgaCrtc(NVPTR(crtc->scrn),
  76                                                to_nouveau_crtc(crtc)->head,
  77                                                index);
  78 }
  79
  80 static void crtc_wr_cio_state(xf86CrtcPtr crtc, NVCrtcRegPtr crtcstate, int index)
  81 {
  82         NVWriteVgaCrtc(NVPTR(crtc->scrn), to_nouveau_crtc(crtc)->head, index,
  83                        crtcstate->CRTC[index]);
  84 }
  85
  86 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
  87 /* They are only valid for NV4x, appearantly reordered for NV5x */
  88 /* gpu pll: 0x4000 + 0x4004
  89  * unknown pll: 0x4008 + 0x400c
  90  * vpll1: 0x4010 + 0x4014
  91  * vpll2: 0x4018 + 0x401c
  92  * unknown pll: 0x4020 + 0x4024
  93  * unknown pll: 0x4038 + 0x403c
  94  * Some of the unknown's are probably memory pll's.
  95  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
  96  * 1 and 2 refer to the registers of each pair. There is only one post divider.
  97  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
  98  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
  99  *     bit8: A switch that turns of the second divider and multiplier off.
 100  *     bit12: Also a switch, i haven't seen it yet.
 101  *     bit16-19: p-divider
 102  *     but 28-31: Something related to the mode that is used (see bit8).
 103  * 2) bit0-7: m-divider (a)
 104  *     bit8-15: n-multiplier (a)
 105  *     bit16-23: m-divider (b)
 106  *     bit24-31: n-multiplier (b)
 107  */
 108
 109 /* Modifying the gpu pll for example requires:
 110  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 111  * This is not needed for the vpll's which have their own bits.
 112  */
 113
 114 static void nv_crtc_save_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 115 {
 116         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 117         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 118         NVPtr pNv = NVPTR(crtc->scrn);
 119
 120         if (nv_crtc->head) {
 121                 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 122                 if (pNv->twoStagePLL)
 123                         regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 124         } else {
 125                 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 126                 if (pNv->twoStagePLL)
 127                         regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 128         }
 129         if (pNv->twoHeads)
 130                 state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 131         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 132         if (pNv->Architecture == NV_ARCH_40)
 133                 state->reg580 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_580);
 134 }
 135
 136 static void nv_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 137 {
 138         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 139         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 140         ScrnInfoPtr pScrn = crtc->scrn;
 141         NVPtr pNv = NVPTR(pScrn);
 142         uint32_t savedc040 = 0;
 143
 144         /* This sequence is important, the NV28 is very sensitive in this area. */
 145         /* Keep pllsel last and sel_clk first. */
 146         if (pNv->twoHeads)
 147                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
 148
 149         if (pNv->Architecture == NV_ARCH_40) {
 150                 savedc040 = nvReadMC(pNv, 0xc040);
 151
 152                 /* for vpll1 change bits 16 and 17 are disabled */
 153                 /* for vpll2 change bits 18 and 19 are disabled */
 154                 nvWriteMC(pNv, 0xc040, savedc040 & ~(3 << (16 + nv_crtc->head * 2)));
 155         }
 156
 157         if (nv_crtc->head) {
 158                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, regp->vpll_a);
 159                 if (pNv->twoStagePLL)
 160                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, regp->vpll_b);
 161         } else {
 162                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, regp->vpll_a);
 163                 if (pNv->twoStagePLL)
 164                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, regp->vpll_b);
 165         }
 166
 167         if (pNv->Architecture == NV_ARCH_40) {
 168                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
 169
 170                 /* We need to wait a while */
 171                 usleep(5000);
 172                 nvWriteMC(pNv, 0xc040, savedc040);
 173         }
 174
 175         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_PLL_SELECT %08X\n", state->pllsel);
 176         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 177 }
 178
 179 static void nv_crtc_cursor_set(xf86CrtcPtr crtc)
 180 {
 181         NVPtr pNv = NVPTR(crtc->scrn);
 182         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 183         uint32_t cursor_start;
 184         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 185
 186         if (pNv->Architecture == NV_ARCH_04)
 187                 cursor_start = 0x5E00 << 2;
 188         else
 189                 cursor_start = nv_crtc->head ? pNv->Cursor2->offset : pNv->Cursor->offset;
 190
 191         regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = cursor_start >> 17;
 192         if (pNv->Architecture != NV_ARCH_04)
 193                 regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] |= NV_CIO_CRE_HCUR_ASI;
 194         regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = (cursor_start >> 11) << 2;
 195         if (crtc->mode.Flags & V_DBLSCAN)
 196                 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= NV_CIO_CRE_HCUR_ADDR1_CUR_DBL;
 197         regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = cursor_start >> 24;
 198
 199         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
 200         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
 201         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
 202         if (pNv->Architecture == NV_ARCH_40)
 203                 nv_fix_nv40_hw_cursor(pNv, nv_crtc->head);
 204 }
 205
 206 static void nv_crtc_calc_state_ext(xf86CrtcPtr crtc, DisplayModePtr mode, int dot_clock)
 207 {
 208         ScrnInfoPtr pScrn = crtc->scrn;
 209         NVPtr pNv = NVPTR(pScrn);
 210         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 211         RIVA_HW_STATE *state = &pNv->ModeReg;
 212         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 213         struct pll_lims pll_lim;
 214         int NM1 = 0xbeef, NM2 = 0, log2P = 0, VClk = 0;
 215         uint32_t g70_pll_special_bits = 0;
 216         bool nv4x_single_stage_pll_mode = false;
 217         uint8_t arbitration0;
 218         uint16_t arbitration1;
 219
 220         if (get_pll_limits(pScrn, nv_crtc->head ? VPLL2 : VPLL1, &pll_lim))
 221                 return;
 222
 223         if (pNv->twoStagePLL || pNv->NVArch == 0x30 || pNv->NVArch == 0x35) {
 224                 if (dot_clock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* use a single VCO */
 225                         nv4x_single_stage_pll_mode = true;
 226                         /* Turn the second set of divider and multiplier off */
 227                         /* Bogus data, the same nvidia uses */
 228                         NM2 = 0x11f;
 229                         VClk = getMNP_single(pScrn, &pll_lim, dot_clock, &NM1, &log2P);
 230                 } else
 231                         VClk = getMNP_double(pScrn, &pll_lim, dot_clock, &NM1, &NM2, &log2P);
 232         } else
 233                 VClk = getMNP_single(pScrn, &pll_lim, dot_clock, &NM1, &log2P);
 234
 235         /* Are these all the (relevant) G70 cards? */
 236         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 237                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 238                 /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 239                 if (nv4x_single_stage_pll_mode)
 240                         g70_pll_special_bits = 0x1;
 241                 else
 242                         g70_pll_special_bits = 0x3;
 243         }
 244
 245         if (pNv->NVArch == 0x30 || pNv->NVArch == 0x35)
 246                 /* See nvregisters.xml for details. */
 247                 regp->vpll_a = (NM2 & (0x18 << 8)) << 13 | (NM2 & (0x7 << 8)) << 11 | log2P << 16 | NV30_RAMDAC_ENABLE_VCO2 | (NM2 & 7) << 4 | NM1;
 248         else
 249                 regp->vpll_a = g70_pll_special_bits << 30 | log2P << 16 | NM1;
 250         regp->vpll_b = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 251
 252         if (nv4x_single_stage_pll_mode) {
 253                 if (nv_crtc->head == 0)
 254                         state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 255                 else
 256                         state->reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 257         } else {
 258                 if (nv_crtc->head == 0)
 259                         state->reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 260                 else
 261                         state->reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 262         }
 263
 264         /* The NV40 seems to have more similarities to NV3x than other NV4x */
 265         if (pNv->NVArch < 0x41)
 266                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL |
 267                                  NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
 268         /* The blob uses this always, so let's do the same */
 269         if (pNv->Architecture == NV_ARCH_40)
 270                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
 271
 272         if (nv_crtc->head == 1) {
 273                 if (!nv4x_single_stage_pll_mode)
 274                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 275                 else
 276                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 277                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
 278         } else {
 279                 if (!nv4x_single_stage_pll_mode)
 280                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 281                 else
 282                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 283                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
 284         }
 285
 286         if ((!pNv->twoStagePLL && pNv->NVArch != 0x30 && pNv->NVArch != 0x35) || nv4x_single_stage_pll_mode)
 287                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n %d m %d log2p %d\n", NM1 >> 8, NM1 & 0xff, log2P);
 288         else
 289                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P);
 290
 291         if (pNv->Architecture < NV_ARCH_30)
 292                 nv4_10UpdateArbitrationSettings(pScrn, VClk, pScrn->bitsPerPixel, &arbitration0, &arbitration1);
 293         else if ((pNv->Chipset & 0xfff0) == CHIPSET_C51 ||
 294                  (pNv->Chipset & 0xfff0) == CHIPSET_C512) {
 295                 arbitration0 = 128;
 296                 arbitration1 = 0x0480;
 297         } else
 298                 nv30UpdateArbitrationSettings(&arbitration0, &arbitration1);
 299
 300         regp->CRTC[NV_CIO_CRE_FF_INDEX] = arbitration0;
 301         regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arbitration1 & 0xff;
 302         if (pNv->Architecture >= NV_ARCH_30)
 303                 regp->CRTC[NV_CIO_CRE_47] = arbitration1 >> 8;
 304
 305         nv_crtc_cursor_set(crtc);
 306 }
 307
 308 static void
 309 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
 310 {
 311         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 312         ScrnInfoPtr pScrn = crtc->scrn;
 313         NVPtr pNv = NVPTR(pScrn);
 314         unsigned char seq1 = 0, crtc17 = 0;
 315         unsigned char crtc1A;
 316
 317         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting dpms mode %d on CRTC %d\n", mode, nv_crtc->head);
 318
 319         if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
 320                 return;
 321
 322         nv_crtc->last_dpms = mode;
 323
 324         if (pNv->twoHeads)
 325                 NVSetOwner(pNv, nv_crtc->head);
 326
 327         crtc1A = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX) & ~0xC0;
 328         switch(mode) {
 329                 case DPMSModeStandby:
 330                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
 331                 seq1 = 0x20;
 332                 crtc17 = 0x80;
 333                 crtc1A |= 0x80;
 334                 break;
 335         case DPMSModeSuspend:
 336                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
 337                 seq1 = 0x20;
 338                 crtc17 = 0x80;
 339                 crtc1A |= 0x40;
 340                 break;
 341         case DPMSModeOff:
 342                 /* Screen: Off; HSync: Off, VSync: Off */
 343                 seq1 = 0x20;
 344                 crtc17 = 0x00;
 345                 crtc1A |= 0xC0;
 346                 break;
 347         case DPMSModeOn:
 348         default:
 349                 /* Screen: On; HSync: On, VSync: On */
 350                 seq1 = 0x00;
 351                 crtc17 = 0x80;
 352                 break;
 353         }
 354
 355         NVVgaSeqReset(pNv, nv_crtc->head, true);
 356         /* Each head has it's own sequencer, so we can turn it off when we want */
 357         seq1 |= (NVReadVgaSeq(pNv, nv_crtc->head, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
 358         NVWriteVgaSeq(pNv, nv_crtc->head, NV_VIO_SR_CLOCK_INDEX, seq1);
 359         crtc17 |= (NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_MODE_INDEX) & ~0x80);
 360         usleep(10000);
 361         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_MODE_INDEX, crtc17);
 362         NVVgaSeqReset(pNv, nv_crtc->head, false);
 363
 364         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX, crtc1A);
 365 }
 366
 367 static Bool
 368 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
 369                      DisplayModePtr adjusted_mode)
 370 {
 371         return TRUE;
 372 }
 373
 374 static void
 375 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 376 {
 377         ScrnInfoPtr pScrn = crtc->scrn;
 378         NVPtr pNv = NVPTR(pScrn);
 379         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 380         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 381
 382         /* Calculate our timings */
 383         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
 384         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
 385         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
 386         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
 387         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
 388         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
 389         int vertDisplay         = mode->CrtcVDisplay                    - 1;
 390         int vertStart           = mode->CrtcVSyncStart          - 1;
 391         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
 392         int vertTotal           = mode->CrtcVTotal                      - 2;
 393         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
 394         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
 395
 396         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 397         bool fp_output = false;
 398         int i;
 399
 400         for (i = 0; i < xf86_config->num_output; i++) {
 401                 xf86OutputPtr output = xf86_config->output[i];
 402                 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 403
 404                 if (output->crtc == crtc && (nv_encoder->dcb->type == OUTPUT_LVDS ||
 405                                              nv_encoder->dcb->type == OUTPUT_TMDS))
 406                         fp_output = true;
 407         }
 408
 409         if (fp_output) {
 410                 vertStart = vertTotal - 3;
 411                 vertEnd = vertTotal - 2;
 412                 vertBlankStart = vertStart;
 413                 horizStart = horizTotal - 5;
 414                 horizEnd = horizTotal - 2;
 415                 horizBlankEnd = horizTotal + 4;
 416                 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10)
 417                         /* This reportedly works around some video overlay bandwidth problems */
 418                         horizTotal += 2;
 419         }
 420
 421         if (mode->Flags & V_INTERLACE)
 422                 vertTotal |= 1;
 423
 424 #if 0
 425         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
 426         ErrorF("horizStart: 0x%X \n", horizStart);
 427         ErrorF("horizEnd: 0x%X \n", horizEnd);
 428         ErrorF("horizTotal: 0x%X \n", horizTotal);
 429         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
 430         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
 431         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
 432         ErrorF("vertStart: 0x%X \n", vertStart);
 433         ErrorF("vertEnd: 0x%X \n", vertEnd);
 434         ErrorF("vertTotal: 0x%X \n", vertTotal);
 435         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
 436         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
 437 #endif
 438
 439         /*
 440         * compute correct Hsync & Vsync polarity
 441         */
 442         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
 443                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
 444
 445                 regp->MiscOutReg = 0x23;
 446                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
 447                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
 448         } else {
 449                 int VDisplay = mode->VDisplay;
 450                 if (mode->Flags & V_DBLSCAN)
 451                         VDisplay *= 2;
 452                 if (mode->VScan > 1)
 453                         VDisplay *= mode->VScan;
 454                 if (VDisplay < 400)
 455                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
 456                 else if (VDisplay < 480)
 457                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
 458                 else if (VDisplay < 768)
 459                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
 460                 else
 461                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
 462         }
 463
 464         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
 465
 466         /*
 467         * Time Sequencer
 468         */
 469         regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
 470         /* 0x20 disables the sequencer */
 471         if (mode->Flags & V_CLKDIV2)
 472                 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
 473         else
 474                 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
 475         regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
 476         regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
 477         regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
 478
 479         /*
 480         * CRTC Controller
 481         */
 482         regp->CRTC[NV_CIO_CR_HDT_INDEX]  = Set8Bits(horizTotal);
 483         regp->CRTC[NV_CIO_CR_HDE_INDEX]  = Set8Bits(horizDisplay);
 484         regp->CRTC[NV_CIO_CR_HBS_INDEX]  = Set8Bits(horizBlankStart);
 485         regp->CRTC[NV_CIO_CR_HBE_INDEX]  = SetBitField(horizBlankEnd,4:0,4:0)
 486                                 | SetBit(7);
 487         regp->CRTC[NV_CIO_CR_HRS_INDEX]  = Set8Bits(horizStart);
 488         regp->CRTC[NV_CIO_CR_HRE_INDEX]  = SetBitField(horizBlankEnd,5:5,7:7)
 489                                 | SetBitField(horizEnd,4:0,4:0);
 490         regp->CRTC[NV_CIO_CR_VDT_INDEX]  = SetBitField(vertTotal,7:0,7:0);
 491         regp->CRTC[NV_CIO_CR_OVL_INDEX]  = SetBitField(vertTotal,8:8,0:0)
 492                                 | SetBitField(vertDisplay,8:8,1:1)
 493                                 | SetBitField(vertStart,8:8,2:2)
 494                                 | SetBitField(vertBlankStart,8:8,3:3)
 495                                 | SetBit(4)
 496                                 | SetBitField(vertTotal,9:9,5:5)
 497                                 | SetBitField(vertDisplay,9:9,6:6)
 498                                 | SetBitField(vertStart,9:9,7:7);
 499         regp->CRTC[NV_CIO_CR_RSAL_INDEX]  = 0x00;
 500         regp->CRTC[NV_CIO_CR_CELL_HT_INDEX]  = SetBitField(vertBlankStart,9:9,5:5)
 501                                 | SetBit(6)
 502                                 | (mode->Flags & V_DBLSCAN) * NV_CIO_CR_CELL_HT_SCANDBL;
 503         regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
 504         regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
 505         regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
 506         regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
 507         regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
 508         regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
 509         regp->CRTC[NV_CIO_CR_VRS_INDEX] = Set8Bits(vertStart);
 510         /* What is the meaning of bit5, it is empty in the vga spec. */
 511         regp->CRTC[NV_CIO_CR_VRE_INDEX] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
 512         regp->CRTC[NV_CIO_CR_VDE_INDEX] = Set8Bits(vertDisplay);
 513         /* framebuffer can be larger than crtc scanout area. */
 514         regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8;
 515         regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
 516         regp->CRTC[NV_CIO_CR_VBS_INDEX] = Set8Bits(vertBlankStart);
 517         regp->CRTC[NV_CIO_CR_VBE_INDEX] = Set8Bits(vertBlankEnd);
 518         regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
 519         regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
 520
 521         /*
 522          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
 523          */
 524
 525         /* framebuffer can be larger than crtc scanout area. */
 526         regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = ((pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8) & 0x700) >> 3;
 527         regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->CrtcHDisplay < 1280 ? 0x04 : 0x00;
 528         regp->CRTC[NV_CIO_CRE_LSR_INDEX] = SetBitField(horizBlankEnd,6:6,4:4)
 529                                 | SetBitField(vertBlankStart,10:10,3:3)
 530                                 | SetBitField(vertStart,10:10,2:2)
 531                                 | SetBitField(vertDisplay,10:10,1:1)
 532                                 | SetBitField(vertTotal,10:10,0:0);
 533
 534         regp->CRTC[NV_CIO_CRE_HEB__INDEX] = SetBitField(horizTotal,8:8,0:0)
 535                                 | SetBitField(horizDisplay,8:8,1:1)
 536                                 | SetBitField(horizBlankStart,8:8,2:2)
 537                                 | SetBitField(horizStart,8:8,3:3);
 538
 539         regp->CRTC[NV_CIO_CRE_EBR_INDEX] = SetBitField(vertTotal,11:11,0:0)
 540                                 | SetBitField(vertDisplay,11:11,2:2)
 541                                 | SetBitField(vertStart,11:11,4:4)
 542                                 | SetBitField(vertBlankStart,11:11,6:6);
 543
 544         if(mode->Flags & V_INTERLACE) {
 545                 horizTotal = (horizTotal >> 1) & ~1;
 546                 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = Set8Bits(horizTotal);
 547                 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= SetBitField(horizTotal,8:8,4:4);
 548         } else
 549                 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff;  /* interlace off */
 550
 551         /*
 552         * Graphics Display Controller
 553         */
 554         regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
 555         regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
 556         regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
 557         regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
 558         regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
 559         regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
 560         regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
 561         regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
 562         regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
 563
 564         regp->Attribute[0]  = 0x00; /* standard colormap translation */
 565         regp->Attribute[1]  = 0x01;
 566         regp->Attribute[2]  = 0x02;
 567         regp->Attribute[3]  = 0x03;
 568         regp->Attribute[4]  = 0x04;
 569         regp->Attribute[5]  = 0x05;
 570         regp->Attribute[6]  = 0x06;
 571         regp->Attribute[7]  = 0x07;
 572         regp->Attribute[8]  = 0x08;
 573         regp->Attribute[9]  = 0x09;
 574         regp->Attribute[10] = 0x0A;
 575         regp->Attribute[11] = 0x0B;
 576         regp->Attribute[12] = 0x0C;
 577         regp->Attribute[13] = 0x0D;
 578         regp->Attribute[14] = 0x0E;
 579         regp->Attribute[15] = 0x0F;
 580         regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
 581         /* Non-vga */
 582         regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
 583         regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */
 584         regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
 585         regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
 586 }
 587
 588 /**
 589  * Sets up registers for the given mode/adjusted_mode pair.
 590  *
 591  * The clocks, CRTCs and outputs attached to this CRTC must be off.
 592  *
 593  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
 594  * be easily turned on/off after this.
 595  */
 596 static void
 597 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode)
 598 {
 599         ScrnInfoPtr pScrn = crtc->scrn;
 600         NVPtr pNv = NVPTR(pScrn);
 601         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 602         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 603         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
 604         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 605         bool lvds_output = false, tmds_output = false;
 606         int i;
 607
 608         for (i = 0; i < xf86_config->num_output; i++) {
 609                 xf86OutputPtr output = xf86_config->output[i];
 610                 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 611
 612                 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_LVDS)
 613                         lvds_output = true;
 614                 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_TMDS)
 615                         tmds_output = true;
 616         }
 617
 618         /* Registers not directly related to the (s)vga mode */
 619
 620         /* bit2 = 0 -> fine pitched crtc granularity */
 621         /* The rest disables double buffering on CRTC access */
 622         regp->CRTC[NV_CIO_CRE_21] = 0xfa;
 623
 624         /* the blob sometimes sets |= 0x10 (which is the same as setting |=
 625          * 1 << 30 on 0x60.830), for no apparent reason */
 626         regp->CRTC[NV_CIO_CRE_59] = 0x0;
 627         if (tmds_output && pNv->Architecture < NV_ARCH_40)
 628                 regp->CRTC[NV_CIO_CRE_59] |= 0x1;
 629
 630         /* What is the meaning of this register? */
 631         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
 632         regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
 633
 634         regp->head = 0;
 635         /* Except for rare conditions I2C is enabled on the primary crtc */
 636         if (nv_crtc->head == 0)
 637                 regp->head |= NV_CRTC_FSEL_I2C;
 638         /* Set overlay to desired crtc. */
 639         if (pNv->overlayAdaptor) {
 640                 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
 641                 if (pPriv->overlayCRTC == nv_crtc->head)
 642                         regp->head |= NV_CRTC_FSEL_OVERLAY;
 643         }
 644
 645         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
 646         /* This fixes my cursor corruption issue */
 647         regp->cursorConfig = 0x0;
 648         if(mode->Flags & V_DBLSCAN)
 649                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
 650         if (pNv->alphaCursor) {
 651                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32BPP |
 652                                       NV_CRTC_CURSOR_CONFIG_64PIXELS |
 653                                       NV_CRTC_CURSOR_CONFIG_64LINES |
 654                                       NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND;
 655         } else
 656                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES;
 657
 658         /* Unblock some timings */
 659         regp->CRTC[NV_CIO_CRE_53] = 0;
 660         regp->CRTC[NV_CIO_CRE_54] = 0;
 661
 662         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
 663         if (lvds_output)
 664                 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
 665         else if (tmds_output)
 666                 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
 667         else
 668                 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
 669
 670         /* These values seem to vary */
 671         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
 672         regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
 673
 674         regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
 675
 676         /* What does this do?:
 677          * bit0: crtc0
 678          * bit6: lvds
 679          * bit7: (only in X)
 680          */
 681         if (nv_crtc->head == 0)
 682                 regp->CRTC[NV_CIO_CRE_4B] = 0x81;
 683         else
 684                 regp->CRTC[NV_CIO_CRE_4B] = 0x80;
 685
 686         if (lvds_output)
 687                 regp->CRTC[NV_CIO_CRE_4B] |= 0x40;
 688
 689         /* The blob seems to take the current value from crtc 0, add 4 to that
 690          * and reuse the old value for crtc 1 */
 691         regp->CRTC[NV_CIO_CRE_52] = pNv->SavedReg.crtc_reg[0].CRTC[NV_CIO_CRE_52];
 692         if (!nv_crtc->head)
 693                 regp->CRTC[NV_CIO_CRE_52] += 4;
 694
 695         regp->unk830 = mode->CrtcVDisplay - 3;
 696         regp->unk834 = mode->CrtcVDisplay - 1;
 697
 698         if (pNv->twoHeads)
 699                 /* This is what the blob does */
 700                 regp->unk850 = NVReadCRTC(pNv, 0, NV_CRTC_0850);
 701
 702         /* Never ever modify gpio, unless you know very well what you're doing */
 703         regp->gpio = NVReadCRTC(pNv, 0, NV_CRTC_GPIO);
 704
 705         if (pNv->twoHeads)
 706                 regp->gpio_ext = NVReadCRTC(pNv, 0, NV_CRTC_GPIO_EXT);
 707
 708         regp->config = NV_PCRTC_CONFIG_START_ADDRESS_HSYNC;
 709
 710         /* Some misc regs */
 711         if (pNv->Architecture == NV_ARCH_40) {
 712                 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
 713                 regp->CRTC[NV_CIO_CRE_86] = 0x1;
 714         }
 715
 716         regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (pScrn->depth + 1) / 8;
 717         /* Enable slaved mode */
 718         if (lvds_output || tmds_output)
 719                 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
 720
 721         /* Generic PRAMDAC regs */
 722
 723         if (pNv->Architecture >= NV_ARCH_10)
 724                 /* Only bit that bios and blob set. */
 725                 regp->nv10_cursync = (1 << 25);
 726
 727         switch (pScrn->depth) {
 728                 case 24:
 729                 case 15:
 730                         regp->general = 0x00100130;
 731                         break;
 732                 case 16:
 733                 default:
 734                         regp->general = 0x00101130;
 735                         break;
 736         }
 737         if (pNv->alphaCursor)
 738                 /* PIPE_LONG mode, something to do with the size of the cursor? */
 739                 regp->general |= 1 << 29;
 740
 741         regp->unk_630 = 0; /* turn off green mode (tv test pattern?) */
 742
 743         /* Some values the blob sets */
 744         regp->unk_a20 = 0x0;
 745         regp->unk_a24 = 0xfffff;
 746         regp->unk_a34 = 0x1;
 747 }
 748
 749 /* this could be set in nv_output, but would require some rework of load/save */
 750 static void
 751 nv_crtc_mode_set_fp_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 752 {
 753         ScrnInfoPtr pScrn = crtc->scrn;
 754         NVPtr pNv = NVPTR(pScrn);
 755         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 756         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 757         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
 758         struct nouveau_encoder *nv_encoder = NULL;
 759         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 760         bool is_fp = false;
 761         bool is_lvds = false;
 762         uint32_t mode_ratio, panel_ratio;
 763         int i;
 764
 765         for (i = 0; i < xf86_config->num_output; i++) {
 766                 xf86OutputPtr output = xf86_config->output[i];
 767                 /* assuming one fp output per crtc seems ok */
 768                 nv_encoder = to_nouveau_encoder(output);
 769
 770                 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_LVDS)
 771                         is_lvds = true;
 772                 if (is_lvds || (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_TMDS)) {
 773                         is_fp = true;
 774                         break;
 775                 }
 776         }
 777         if (!is_fp)
 778                 return;
 779
 780         regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
 781         regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
 782         if ((adjusted_mode->HSyncStart - adjusted_mode->HDisplay) >= pNv->VBIOS.digital_min_front_porch)
 783                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
 784         else
 785                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - pNv->VBIOS.digital_min_front_porch - 1;
 786         regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
 787         regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
 788         regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
 789         regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
 790
 791         regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
 792         regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
 793         regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
 794         regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
 795         regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
 796         regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
 797         regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
 798
 799         /*
 800         * bit0: positive vsync
 801         * bit4: positive hsync
 802         * bit8: enable center mode
 803         * bit9: enable native mode
 804         * bit24: 12/24 bit interface (12bit=on, 24bit=off)
 805         * bit26: a bit sometimes seen on some g70 cards
 806         * bit28: fp display enable bit
 807         * bit31: set for dual link LVDS
 808         */
 809
 810         regp->fp_control = (savep->fp_control & 0x04100000) |
 811                            NV_RAMDAC_FP_CONTROL_DISPEN_POS;
 812
 813         /* Deal with vsync/hsync polarity */
 814         /* LVDS screens do set this, but modes with +ve syncs are very rare */
 815         if (adjusted_mode->Flags & V_PVSYNC)
 816                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
 817         if (adjusted_mode->Flags & V_PHSYNC)
 818                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
 819
 820         if (nv_encoder->scaling_mode == SCALE_PANEL ||
 821             nv_encoder->scaling_mode == SCALE_NOSCALE) /* panel needs to scale */
 822                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
 823         /* This is also true for panel scaling, so we must put the panel scale check first */
 824         else if (mode->HDisplay == adjusted_mode->HDisplay &&
 825                  mode->VDisplay == adjusted_mode->VDisplay) /* native mode */
 826                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
 827         else /* gpu needs to scale */
 828                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
 829
 830         if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
 831                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_WIDTH_12;
 832
 833         if (is_lvds && pNv->VBIOS.fp.dual_link)
 834                 regp->fp_control |= (8 << 28);
 835
 836         /* Use the generic value, and enable x-scaling, y-scaling, and the TMDS enable bit */
 837         regp->debug_0 = 0x01101191;
 838         /* We want automatic scaling */
 839         regp->debug_1 = 0;
 840         /* This can override HTOTAL and VTOTAL */
 841         regp->debug_2 = 0;
 842
 843         /* Use 20.12 fixed point format to avoid floats */
 844         mode_ratio = (1 << 12) * mode->HDisplay / mode->VDisplay;
 845         panel_ratio = (1 << 12) * adjusted_mode->HDisplay / adjusted_mode->VDisplay;
 846         /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
 847          * get treated the same as SCALE_FULLSCREEN */
 848         if (nv_encoder->scaling_mode == SCALE_ASPECT && mode_ratio != panel_ratio) {
 849                 uint32_t diff, scale;
 850
 851                 if (mode_ratio < panel_ratio) {
 852                         /* vertical needs to expand to glass size (automatic)
 853                          * horizontal needs to be scaled at vertical scale factor
 854                          * to maintain aspect */
 855
 856                         scale = (1 << 12) * mode->VDisplay / adjusted_mode->VDisplay;
 857                         regp->debug_1 = 1 << 12 | ((scale >> 1) & 0xfff);
 858
 859                         /* restrict area of screen used, horizontally */
 860                         diff = adjusted_mode->HDisplay -
 861                                adjusted_mode->VDisplay * mode_ratio / (1 << 12);
 862                         regp->fp_horiz_regs[REG_DISP_VALID_START] += diff / 2;
 863                         regp->fp_horiz_regs[REG_DISP_VALID_END] -= diff / 2;
 864                 }
 865
 866                 if (mode_ratio > panel_ratio) {
 867                         /* horizontal needs to expand to glass size (automatic)
 868                          * vertical needs to be scaled at horizontal scale factor
 869                          * to maintain aspect */
 870
 871                         scale = (1 << 12) * mode->HDisplay / adjusted_mode->HDisplay;
 872                         regp->debug_1 = 1 << 28 | ((scale >> 1) & 0xfff) << 16;
 873
 874                         /* restrict area of screen used, vertically */
 875                         diff = adjusted_mode->VDisplay -
 876                                (1 << 12) * adjusted_mode->HDisplay / mode_ratio;
 877                         regp->fp_vert_regs[REG_DISP_VALID_START] += diff / 2;
 878                         regp->fp_vert_regs[REG_DISP_VALID_END] -= diff / 2;
 879                 }
 880         }
 881
 882         /* Flatpanel support needs at least a NV10 */
 883         if (pNv->twoHeads) {
 884                 /* Output property. */
 885                 if (nv_encoder && nv_encoder->dithering) {
 886                         if (pNv->NVArch == 0x11)
 887                                 regp->dither = savep->dither | 0x00010000;
 888                         else {
 889                                 int i;
 890                                 regp->dither = savep->dither | 0x00000001;
 891                                 for (i = 0; i < 3; i++) {
 892                                         regp->dither_regs[i] = 0xe4e4e4e4;
 893                                         regp->dither_regs[i + 3] = 0x44444444;
 894                                 }
 895                         }
 896                 } else {
 897                         if (pNv->NVArch != 0x11) {
 898                                 /* reset them */
 899                                 int i;
 900                                 for (i = 0; i < 3; i++) {
 901                                         regp->dither_regs[i] = savep->dither_regs[i];
 902                                         regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
 903                                 }
 904                         }
 905                         regp->dither = savep->dither;
 906                 }
 907         } else
 908                 regp->dither = savep->dither;
 909 }
 910
 911 /**
 912  * Sets up registers for the given mode/adjusted_mode pair.
 913  *
 914  * The clocks, CRTCs and outputs attached to this CRTC must be off.
 915  *
 916  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
 917  * be easily turned on/off after this.
 918  */
 919 static void
 920 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 921                  DisplayModePtr adjusted_mode,
 922                  int x, int y)
 923 {
 924         ScrnInfoPtr pScrn = crtc->scrn;
 925         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 926         NVPtr pNv = NVPTR(pScrn);
 927
 928         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CTRC mode on CRTC %d:\n", nv_crtc->head);
 929         xf86PrintModeline(pScrn->scrnIndex, mode);
 930         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Output mode on CRTC %d:\n", nv_crtc->head);
 931         xf86PrintModeline(pScrn->scrnIndex, adjusted_mode);
 932
 933         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
 934
 935         /* calculated in output_prepare, nv40 needs it written before calculating PLLs */
 936         if (pNv->Architecture == NV_ARCH_40)
 937                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
 938         nv_crtc_mode_set_regs(crtc, mode);
 939         nv_crtc_mode_set_fp_regs(crtc, mode, adjusted_mode);
 940         nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->Clock);
 941
 942         NVVgaProtect(pNv, nv_crtc->head, true);
 943         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
 944         nv_crtc_load_state_ext(crtc, &pNv->ModeReg);
 945         nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
 946         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
 947         nv_crtc_load_state_pll(crtc, &pNv->ModeReg);
 948
 949         NVVgaProtect(pNv, nv_crtc->head, false);
 950
 951         NVCrtcSetBase(crtc, x, y);
 952
 953 #if X_BYTE_ORDER == X_BIG_ENDIAN
 954         /* turn on LFB swapping */
 955         {
 956                 uint8_t tmp = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RCR);
 957                 tmp |= NV_CIO_CRE_RCR_ENDIAN_BIG;
 958                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RCR, tmp);
 959         }
 960 #endif
 961 }
 962
 963 static void nv_crtc_save(xf86CrtcPtr crtc)
 964 {
 965         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 966         NVPtr pNv = NVPTR(crtc->scrn);
 967
 968         if (pNv->twoHeads)
 969                 NVSetOwner(pNv, nv_crtc->head);
 970
 971         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
 972         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
 973         nv_crtc_save_state_palette(crtc, &pNv->SavedReg);
 974         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
 975         nv_crtc_save_state_pll(crtc, &pNv->SavedReg);
 976
 977         /* init some state to saved value */
 978         pNv->ModeReg.reg580 = pNv->SavedReg.reg580;
 979         pNv->ModeReg.sel_clk = pNv->SavedReg.sel_clk & ~(0x5 << 16);
 980         pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_CIO_CRE_LCD__INDEX] = pNv->SavedReg.crtc_reg[nv_crtc->head].CRTC[NV_CIO_CRE_LCD__INDEX];
 981 }
 982
 983 static void nv_crtc_restore(xf86CrtcPtr crtc)
 984 {
 985         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 986         NVPtr pNv = NVPTR(crtc->scrn);
 987
 988         if (pNv->twoHeads)
 989                 NVSetOwner(pNv, nv_crtc->head);
 990
 991         NVVgaProtect(pNv, nv_crtc->head, true);
 992         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
 993         nv_crtc_load_state_ext(crtc, &pNv->SavedReg);
 994         nv_crtc_load_state_palette(crtc, &pNv->SavedReg);
 995         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
 996         nv_crtc_load_state_pll(crtc, &pNv->SavedReg);
 997         NVVgaProtect(pNv, nv_crtc->head, false);
 998
 999         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1000 }
1001
1002 static void nv_crtc_prepare(xf86CrtcPtr crtc)
1003 {
1004         ScrnInfoPtr pScrn = crtc->scrn;
1005         NVPtr pNv = NVPTR(pScrn);
1006         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1007
1008         if (pNv->twoHeads)
1009                 NVSetOwner(pNv, nv_crtc->head);
1010
1011         crtc->funcs->dpms(crtc, DPMSModeOff);
1012
1013         /* Sync the engine before adjust mode */
1014         if (pNv->EXADriverPtr) {
1015                 exaMarkSync(pScrn->pScreen);
1016                 exaWaitSync(pScrn->pScreen);
1017         }
1018
1019         NVBlankScreen(pNv, nv_crtc->head, true);
1020
1021         /* Some more preperation. */
1022         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
1023         if (pNv->Architecture == NV_ARCH_40) {
1024                 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1025                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1026         }
1027 }
1028
1029 static void nv_crtc_commit(xf86CrtcPtr crtc)
1030 {
1031         crtc->funcs->dpms (crtc, DPMSModeOn);
1032
1033         if (crtc->scrn->pScreen != NULL) {
1034                 NVPtr pNv = NVPTR(crtc->scrn);
1035
1036                 xf86_reload_cursors (crtc->scrn->pScreen);
1037                 if (!pNv->alphaCursor) {
1038                         /* this works round the fact that xf86_reload_cursors
1039                          * will quite happily show the hw cursor when it knows
1040                          * the hardware can't do alpha, and the current cursor
1041                          * has an alpha channel
1042                          */
1043                         xf86ForceHWCursor(crtc->scrn->pScreen, 1);
1044                         xf86ForceHWCursor(crtc->scrn->pScreen, 0);
1045                 }
1046         }
1047 }
1048
1049 static void nv_crtc_destroy(xf86CrtcPtr crtc)
1050 {
1051         xfree(to_nouveau_crtc(crtc));
1052 }
1053
1054 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1055 {
1056         return FALSE;
1057 }
1058
1059 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1060 {
1061 }
1062
1063 static void
1064 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
1065                                         int size)
1066 {
1067         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1068         ScrnInfoPtr pScrn = crtc->scrn;
1069         NVPtr pNv = NVPTR(pScrn);
1070         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1071         int i, j;
1072
1073         switch (pScrn->depth) {
1074         case 15:
1075                 /* R5G5B5 */
1076                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
1077                 for (i = 0; i < 32; i++)
1078                         for (j = 0; j < 8; j++) {
1079                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1080                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
1081                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1082                         }
1083                 break;
1084         case 16:
1085                 /* R5G6B5 */
1086                 /* First deal with the 5 bit colors */
1087                 for (i = 0; i < 32; i++)
1088                         for (j = 0; j < 8; j++) {
1089                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1090                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1091                         }
1092                 /* Now deal with the 6 bit color */
1093                 for (i = 0; i < 64; i++)
1094                         for (j = 0; j < 4; j++)
1095                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
1096                 break;
1097         default:
1098                 /* R8G8B8 */
1099                 for (i = 0; i < 256; i++) {
1100                         regp->DAC[i * 3] = red[i] >> 8;
1101                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
1102                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
1103                 }
1104                 break;
1105         }
1106
1107         nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
1108 }
1109
1110 /**
1111  * Allocates memory for a locked-in-framebuffer shadow of the given
1112  * width and height for this CRTC's rotated shadow framebuffer.
1113  */
1114
1115 static void *
1116 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
1117 {
1118         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1119         ScrnInfoPtr pScrn = crtc->scrn;
1120 #if !NOUVEAU_EXA_PIXMAPS
1121         ScreenPtr pScreen = pScrn->pScreen;
1122 #endif /* !NOUVEAU_EXA_PIXMAPS */
1123         NVPtr pNv = NVPTR(pScrn);
1124         void *offset;
1125
1126         unsigned long rotate_pitch;
1127         int size, align = 64;
1128
1129         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1130         size = rotate_pitch * height;
1131
1132         assert(nv_crtc->shadow == NULL);
1133 #if NOUVEAU_EXA_PIXMAPS
1134         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
1135                         align, size, &nv_crtc->shadow)) {
1136                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to allocate memory for shadow buffer!\n");
1137                 return NULL;
1138         }
1139
1140         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
1141                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1142                                 "Failed to map shadow buffer.\n");
1143                 return NULL;
1144         }
1145
1146         offset = nv_crtc->shadow->map;
1147 #else
1148         if (!pScreen) {
1149                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1150                            "Can't allocate shadow memory for rotated CRTC at server regeneration\n");
1151                 return NULL;
1152         }
1153         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
1154         if (nv_crtc->shadow == NULL) {
1155                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1156                         "Couldn't allocate shadow memory for rotated CRTC.\n");
1157                 return NULL;
1158         }
1159         offset = pNv->FB->map + nv_crtc->shadow->offset;
1160 #endif /* NOUVEAU_EXA_PIXMAPS */
1161
1162         return offset;
1163 }
1164
1165 /**
1166  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
1167  */
1168 static PixmapPtr
1169 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
1170 {
1171         ScrnInfoPtr pScrn = crtc->scrn;
1172 #if NOUVEAU_EXA_PIXMAPS
1173         ScreenPtr pScreen = pScrn->pScreen;
1174         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1175 #endif /* NOUVEAU_EXA_PIXMAPS */
1176         unsigned long rotate_pitch;
1177         PixmapPtr rotate_pixmap;
1178 #if NOUVEAU_EXA_PIXMAPS
1179         struct nouveau_pixmap *nvpix;
1180 #endif /* NOUVEAU_EXA_PIXMAPS */
1181
1182         if (!data)
1183                 data = crtc->funcs->shadow_allocate (crtc, width, height);
1184
1185         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1186
1187 #if NOUVEAU_EXA_PIXMAPS
1188         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
1189         rotate_pixmap = pScreen->CreatePixmap(pScreen,
1190                                                                 0, /* width */
1191                                                                 0, /* height */
1192         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
1193                                                                 pScrn->depth,
1194                                                                 0);
1195         #else
1196                                                                 pScrn->depth);
1197         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
1198 #else
1199         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
1200                                                                 width, height,
1201                                                                 pScrn->depth,
1202                                                                 pScrn->bitsPerPixel,
1203                                                                 rotate_pitch,
1204                                                                 data);
1205 #endif /* NOUVEAU_EXA_PIXMAPS */
1206
1207         if (rotate_pixmap == NULL) {
1208                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1209                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
1210         }
1211
1212 #if NOUVEAU_EXA_PIXMAPS
1213         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1214         if (!nvpix) {
1215                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No initial shadow private available for rotation.\n");
1216         } else {
1217                 nvpix->bo = nv_crtc->shadow;
1218                 nvpix->mapped = TRUE;
1219         }
1220
1221         /* Modify the pixmap to actually be the one we need. */
1222         pScreen->ModifyPixmapHeader(rotate_pixmap,
1223                                         width,
1224                                         height,
1225                                         pScrn->depth,
1226                                         pScrn->bitsPerPixel,
1227                                         rotate_pitch,
1228                                         data);
1229
1230         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1231         if (!nvpix || !nvpix->bo)
1232                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No final shadow private available for rotation.\n");
1233 #endif /* NOUVEAU_EXA_PIXMAPS */
1234
1235         return rotate_pixmap;
1236 }
1237
1238 static void
1239 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
1240 {
1241         ScrnInfoPtr pScrn = crtc->scrn;
1242         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1243         ScreenPtr pScreen = pScrn->pScreen;
1244
1245         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
1246                 pScreen->DestroyPixmap(rotate_pixmap);
1247         }
1248
1249 #if !NOUVEAU_EXA_PIXMAPS
1250         if (data && nv_crtc->shadow) {
1251                 exaOffscreenFree(pScreen, nv_crtc->shadow);
1252         }
1253 #endif /* !NOUVEAU_EXA_PIXMAPS */
1254
1255         nv_crtc->shadow = NULL;
1256 }
1257
1258 static const xf86CrtcFuncsRec nv_crtc_funcs = {
1259         .dpms = nv_crtc_dpms,
1260         .save = nv_crtc_save,
1261         .restore = nv_crtc_restore,
1262         .mode_fixup = nv_crtc_mode_fixup,
1263         .mode_set = nv_crtc_mode_set,
1264         .prepare = nv_crtc_prepare,
1265         .commit = nv_crtc_commit,
1266         .destroy = nv_crtc_destroy,
1267         .lock = nv_crtc_lock,
1268         .unlock = nv_crtc_unlock,
1269         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
1270         .set_cursor_position = nv_crtc_set_cursor_position,
1271         .show_cursor = nv_crtc_show_cursor,
1272         .hide_cursor = nv_crtc_hide_cursor,
1273         .load_cursor_argb = nv_crtc_load_cursor_argb,
1274         .gamma_set = nv_crtc_gamma_set,
1275         .shadow_create = nv_crtc_shadow_create,
1276         .shadow_allocate = nv_crtc_shadow_allocate,
1277         .shadow_destroy = nv_crtc_shadow_destroy,
1278 };
1279
1280 void
1281 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
1282 {
1283         NVPtr pNv = NVPTR(pScrn);
1284         static xf86CrtcFuncsRec crtcfuncs;
1285         xf86CrtcPtr crtc;
1286         struct nouveau_crtc *nv_crtc;
1287         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[crtc_num];
1288         int i;
1289
1290         crtcfuncs = nv_crtc_funcs;
1291
1292         /* NV04-NV10 doesn't support alpha cursors */
1293         if (pNv->NVArch < 0x11) {
1294                 crtcfuncs.set_cursor_colors = nv_crtc_set_cursor_colors;
1295                 crtcfuncs.load_cursor_image = nv_crtc_load_cursor_image;
1296                 crtcfuncs.load_cursor_argb = NULL;
1297         }
1298         if (pNv->NoAccel) {
1299                 crtcfuncs.shadow_create = NULL;
1300                 crtcfuncs.shadow_allocate = NULL;
1301                 crtcfuncs.shadow_destroy = NULL;
1302         }
1303
1304         if (!(crtc = xf86CrtcCreate(pScrn, &crtcfuncs)))
1305                 return;
1306
1307         if (!(nv_crtc = xcalloc(1, sizeof (struct nouveau_crtc)))) {
1308                 xf86CrtcDestroy(crtc);
1309                 return;
1310         }
1311
1312         nv_crtc->head = crtc_num;
1313         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1314
1315         crtc->driver_private = nv_crtc;
1316
1317         /* Initialise the default LUT table. */
1318         for (i = 0; i < 256; i++) {
1319                 regp->DAC[i*3] = i;
1320                 regp->DAC[(i*3)+1] = i;
1321                 regp->DAC[(i*3)+2] = i;
1322         }
1323 }
1324
1325 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1326 {
1327         ScrnInfoPtr pScrn = crtc->scrn;
1328         NVPtr pNv = NVPTR(pScrn);
1329         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1330         int i;
1331         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1332
1333         NVWritePRMVIO(pNv, nv_crtc->head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
1334
1335         for (i = 0; i < 5; i++)
1336                 NVWriteVgaSeq(pNv, nv_crtc->head, i, regp->Sequencer[i]);
1337
1338         for (i = 0; i < 25; i++)
1339                 crtc_wr_cio_state(crtc, regp, i);
1340
1341         for (i = 0; i < 9; i++)
1342                 NVWriteVgaGr(pNv, nv_crtc->head, i, regp->Graphics[i]);
1343
1344         NVSetEnablePalette(pNv, nv_crtc->head, true);
1345         for (i = 0; i < 21; i++)
1346                 NVWriteVgaAttr(pNv, nv_crtc->head, i, regp->Attribute[i]);
1347
1348         NVSetEnablePalette(pNv, nv_crtc->head, false);
1349 }
1350
1351 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1352 {
1353         ScrnInfoPtr pScrn = crtc->scrn;
1354         NVPtr pNv = NVPTR(pScrn);
1355         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1356         NVCrtcRegPtr regp;
1357         int i;
1358
1359         regp = &state->crtc_reg[nv_crtc->head];
1360
1361         if (pNv->Architecture >= NV_ARCH_10) {
1362                 if (pNv->twoHeads)
1363                         /* setting FSEL *must* come before CIO_CRE_LCD, as writing CIO_CRE_LCD sets some
1364                          * bits (16 & 17) in FSEL that should not be overwritten by writing FSEL */
1365                         NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, regp->head);
1366
1367                 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
1368                 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
1369                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
1370                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
1371                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1372                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1373                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1374                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1375                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
1376
1377                 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_21);
1378                 NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
1379                 NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
1380                 NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
1381                 if (pNv->Architecture == NV_ARCH_40) {
1382                         NVCrtcWriteCRTC(crtc, NV_CRTC_0850, regp->unk850);
1383                         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO_EXT, regp->gpio_ext);
1384                 }
1385
1386                 if (pNv->Architecture == NV_ARCH_40) {
1387                         uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1388                         if (regp->config == NV_PCRTC_CONFIG_START_ADDRESS_HSYNC)
1389                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 | 0x10000);
1390                         else
1391                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1392                 }
1393         }
1394
1395         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
1396         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio);
1397
1398         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
1399         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC1_INDEX);
1400         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_LSR_INDEX);
1401         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX);
1402         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_LCD__INDEX);
1403         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HEB__INDEX);
1404         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_ENH_INDEX);
1405         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
1406         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
1407         if (pNv->Architecture >= NV_ARCH_30)
1408                 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
1409
1410         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
1411         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
1412         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
1413         if (pNv->Architecture == NV_ARCH_40)
1414                 nv_fix_nv40_hw_cursor(pNv, nv_crtc->head);
1415         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_ILACE__INDEX);
1416
1417         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_SCRATCH3__INDEX);
1418         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_SCRATCH4__INDEX);
1419         if (pNv->Architecture >= NV_ARCH_10) {
1420                 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_EBR_INDEX);
1421                 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB);
1422                 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_4B);
1423                 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_52);
1424         }
1425         /* NV11 and NV20 stop at 0x52. */
1426         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1427                 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_53);
1428                 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_54);
1429
1430                 for (i = 0; i < 0x10; i++)
1431                         NVWriteVgaCrtc5758(pNv, nv_crtc->head, i, regp->CR58[i]);
1432                 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_59);
1433
1434                 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_85);
1435                 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_86);
1436         }
1437
1438         NVCrtcWriteCRTC(crtc, NV_CRTC_START, regp->fb_start);
1439
1440         /* Setting 1 on this value gives you interrupts for every vblank period. */
1441         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_EN_0, 0);
1442         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
1443 }
1444
1445 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1446 {
1447         ScrnInfoPtr pScrn = crtc->scrn;
1448         NVPtr pNv = NVPTR(pScrn);
1449         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1450         int i;
1451         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1452
1453         regp->MiscOutReg = NVReadPRMVIO(pNv, nv_crtc->head, NV_PRMVIO_MISC__READ);
1454
1455         for (i = 0; i < 25; i++)
1456                 crtc_rd_cio_state(crtc, regp, i);
1457
1458         NVSetEnablePalette(pNv, nv_crtc->head, true);
1459         for (i = 0; i < 21; i++)
1460                 regp->Attribute[i] = NVReadVgaAttr(pNv, nv_crtc->head, i);
1461         NVSetEnablePalette(pNv, nv_crtc->head, false);
1462
1463         for (i = 0; i < 9; i++)
1464                 regp->Graphics[i] = NVReadVgaGr(pNv, nv_crtc->head, i);
1465
1466         for (i = 0; i < 5; i++)
1467                 regp->Sequencer[i] = NVReadVgaSeq(pNv, nv_crtc->head, i);
1468 }
1469
1470 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1471 {
1472         ScrnInfoPtr pScrn = crtc->scrn;
1473         NVPtr pNv = NVPTR(pScrn);
1474         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1475         NVCrtcRegPtr regp;
1476         int i;
1477
1478         regp = &state->crtc_reg[nv_crtc->head];
1479
1480         crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_LCD__INDEX);
1481         crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
1482         crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_RPC1_INDEX);
1483         crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_LSR_INDEX);
1484         crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX);
1485         crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_HEB__INDEX);
1486         crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_ENH_INDEX);
1487
1488         crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
1489         crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
1490         crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_21);
1491         if (pNv->Architecture >= NV_ARCH_30)
1492                 crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_47);
1493         crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
1494         crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
1495         crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
1496         crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_ILACE__INDEX);
1497
1498         if (pNv->Architecture >= NV_ARCH_10) {
1499                 regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
1500                 regp->unk834 = NVCrtcReadCRTC(crtc, NV_CRTC_0834);
1501                 if (pNv->Architecture == NV_ARCH_40) {
1502                         regp->unk850 = NVCrtcReadCRTC(crtc, NV_CRTC_0850);
1503                         regp->gpio_ext = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO_EXT);
1504                 }
1505                 if (pNv->twoHeads)
1506                         regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL);
1507                 regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG);
1508         }
1509
1510         regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO);
1511         regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
1512
1513         crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_SCRATCH3__INDEX);
1514         crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_SCRATCH4__INDEX);
1515         if (pNv->Architecture >= NV_ARCH_10) {
1516                 crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_EBR_INDEX);
1517                 crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_CSB);
1518                 crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_4B);
1519                 crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_52);
1520         }
1521         /* NV11 and NV20 don't have this, they stop at 0x52. */
1522         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1523                 for (i = 0; i < 0x10; i++)
1524                         regp->CR58[i] = NVReadVgaCrtc5758(pNv, nv_crtc->head, i);
1525
1526                 crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_59);
1527                 crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_53);
1528                 crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_54);
1529
1530                 crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_85);
1531                 crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_86);
1532         }
1533
1534         regp->fb_start = NVCrtcReadCRTC(crtc, NV_CRTC_START);
1535 }
1536
1537 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1538 {
1539         ScrnInfoPtr pScrn = crtc->scrn;
1540         NVPtr pNv = NVPTR(pScrn);
1541         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1542         NVCrtcRegPtr regp;
1543         int i;
1544
1545         regp = &state->crtc_reg[nv_crtc->head];
1546
1547         regp->general = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL);
1548
1549         if (pNv->twoHeads) {
1550                 if (pNv->NVArch >= 0x17)
1551                         regp->unk_630 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_630);
1552                 regp->fp_control        = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_CONTROL);
1553                 regp->debug_0   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0);
1554                 regp->debug_1   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1);
1555                 regp->debug_2   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2);
1556
1557                 regp->unk_a20 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A20);
1558                 regp->unk_a24 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A24);
1559                 regp->unk_a34 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A34);
1560         }
1561
1562         if (pNv->NVArch == 0x11) {
1563                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_DITHER_NV11);
1564         } else if (pNv->twoHeads) {
1565                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DITHER);
1566                 for (i = 0; i < 3; i++) {
1567                         regp->dither_regs[i] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4);
1568                         regp->dither_regs[i + 3] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4);
1569                 }
1570         }
1571         if (pNv->Architecture >= NV_ARCH_10)
1572                 regp->nv10_cursync = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC);
1573
1574         /* The regs below are 0 for non-flatpanels, so you can load and save them */
1575
1576         for (i = 0; i < 7; i++) {
1577                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
1578                 regp->fp_horiz_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1579         }
1580
1581         for (i = 0; i < 7; i++) {
1582                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
1583                 regp->fp_vert_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1584         }
1585 }
1586
1587 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1588 {
1589         ScrnInfoPtr pScrn = crtc->scrn;
1590         NVPtr pNv = NVPTR(pScrn);
1591         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1592         NVCrtcRegPtr regp;
1593         int i;
1594
1595         regp = &state->crtc_reg[nv_crtc->head];
1596
1597         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL, regp->general);
1598
1599         if (pNv->twoHeads) {
1600                 if (pNv->NVArch >= 0x17)
1601                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_630, regp->unk_630);
1602                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_CONTROL, regp->fp_control);
1603                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
1604                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
1605                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
1606                 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
1607                         uint32_t reg890 = NVCrtcReadRAMDAC(crtc, NV30_RAMDAC_890);
1608                         NVCrtcWriteRAMDAC(crtc, NV30_RAMDAC_89C, reg890);
1609                 }
1610
1611                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A20, regp->unk_a20);
1612                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A24, regp->unk_a24);
1613                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A34, regp->unk_a34);
1614         }
1615
1616         if (pNv->NVArch == 0x11)
1617                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_DITHER_NV11, regp->dither);
1618         else if (pNv->twoHeads) {
1619                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DITHER, regp->dither);
1620                 for (i = 0; i < 3; i++) {
1621                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4, regp->dither_regs[i]);
1622                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4, regp->dither_regs[i + 3]);
1623                 }
1624         }
1625         if (pNv->Architecture >= NV_ARCH_10)
1626                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
1627
1628         /* The regs below are 0 for non-flatpanels, so you can load and save them */
1629
1630         for (i = 0; i < 7; i++) {
1631                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
1632                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_horiz_regs[i]);
1633         }
1634
1635         for (i = 0; i < 7; i++) {
1636                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
1637                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_vert_regs[i]);
1638         }
1639 }
1640
1641 void NVCrtcSetBase(xf86CrtcPtr crtc, int x, int y)
1642 {
1643         ScrnInfoPtr pScrn = crtc->scrn;
1644         NVPtr pNv = NVPTR(pScrn);
1645         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1646         uint32_t start = (y * pScrn->displayWidth + x) * pScrn->bitsPerPixel / 8;
1647
1648         if (crtc->rotatedData != NULL) /* we do not exist on the real framebuffer */
1649 #if NOUVEAU_EXA_PIXMAPS
1650                 start = nv_crtc->shadow->offset;
1651 #else
1652                 start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
1653 #endif
1654         else
1655                 start += pNv->FB->offset;
1656
1657         /* 30 bits addresses in 32 bits according to haiku */
1658         start &= ~3;
1659         pNv->ModeReg.crtc_reg[nv_crtc->head].fb_start = start;
1660         NVCrtcWriteCRTC(crtc, NV_CRTC_START, start);
1661
1662         crtc->x = x;
1663         crtc->y = y;
1664 }
1665
1666 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1667 {
1668         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1669         NVPtr pNv = NVPTR(crtc->scrn);
1670         int head_offset = nv_crtc->head * NV_PRMDIO_SIZE, i;
1671
1672         VGA_WR08(pNv->REGS, NV_PRMDIO_PIXEL_MASK + head_offset, NV_PRMDIO_PIXEL_MASK_MASK);
1673         VGA_WR08(pNv->REGS, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
1674
1675         for (i = 0; i < 768; i++) {
1676                 state->crtc_reg[nv_crtc->head].DAC[i] = NV_RD08(pNv->REGS, NV_PRMDIO_PALETTE_DATA + head_offset);
1677                 DDXMMIOH("nv_crtc_save_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PRMDIO_PALETTE_DATA + head_offset, state->crtc_reg[nv_crtc->head].DAC[i]);
1678         }
1679
1680         NVSetEnablePalette(pNv, nv_crtc->head, false);
1681 }
1682 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1683 {
1684         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1685         NVPtr pNv = NVPTR(crtc->scrn);
1686         int head_offset = nv_crtc->head * NV_PRMDIO_SIZE, i;
1687
1688         VGA_WR08(pNv->REGS, NV_PRMDIO_PIXEL_MASK + head_offset, NV_PRMDIO_PIXEL_MASK_MASK);
1689         VGA_WR08(pNv->REGS, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
1690
1691         for (i = 0; i < 768; i++) {
1692                 DDXMMIOH("nv_crtc_load_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PRMDIO_PALETTE_DATA + head_offset, state->crtc_reg[nv_crtc->head].DAC[i]);
1693                 NV_WR08(pNv->REGS, NV_PRMDIO_PALETTE_DATA + head_offset, state->crtc_reg[nv_crtc->head].DAC[i]);
1694         }
1695
1696         NVSetEnablePalette(pNv, nv_crtc->head, false);
1697 }