1 /* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */
3 * Copyright 1996-1997 David J. McKay
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
19 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
20 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nvreg.h,v 1.6 2002/01/25 21:56:06 tsi Exp $ */
29 #define NV_PMC_OFFSET 0x00000000
30 #define NV_PMC_SIZE 0x00001000
32 #define NV_PBUS_OFFSET 0x00001000
33 #define NV_PBUS_SIZE 0x00001000
35 #define NV_PFIFO_OFFSET 0x00002000
36 #define NV_PFIFO_SIZE 0x00002000
38 #define NV_HDIAG_OFFSET 0x00005000
39 #define NV_HDIAG_SIZE 0x00001000
41 #define NV_PRAM_OFFSET 0x00006000
42 #define NV_PRAM_SIZE 0x00001000
44 #define NV_PVIDEO_OFFSET 0x00008000
45 #define NV_PVIDEO_SIZE 0x00001000
47 #define NV_PTIMER_OFFSET 0x00009000
48 #define NV_PTIMER_SIZE 0x00001000
50 #define NV_PPM_OFFSET 0x0000A000
51 #define NV_PPM_SIZE 0x00001000
53 #define NV_PVGA_OFFSET 0x000A0000
54 #define NV_PVGA_SIZE 0x00020000
56 #define NV_PVIO0_OFFSET 0x000C0000
57 #define NV_PVIO_SIZE 0x00002000
58 #define NV_PVIO1_OFFSET 0x000C2000
60 #define NV_PFB_OFFSET 0x00100000
61 #define NV_PFB_SIZE 0x00001000
63 #define NV_PEXTDEV_OFFSET 0x00101000
64 #define NV_PEXTDEV_SIZE 0x00001000
66 #define NV_PME_OFFSET 0x00200000
67 #define NV_PME_SIZE 0x00001000
69 #define NV_PROM_OFFSET 0x00300000
70 #define NV_PROM_SIZE 0x00010000
72 #define NV_PGRAPH_OFFSET 0x00400000
73 #define NV_PGRAPH_SIZE 0x00010000
75 #define NV_PCRTC0_OFFSET 0x00600000
76 #define NV_PCRTC0_SIZE 0x00002000 /* empirical */
78 #define NV_PCIO0_OFFSET 0x00601000
79 #define NV_PCIO_SIZE 0x00002000
80 #define NV_PCIO1_OFFSET 0x00603000
82 #define NV50_DISPLAY_OFFSET 0x00610000
83 #define NV50_DISPLAY_SIZE 0x0000FFFF
85 #define NV_PRAMDAC0_OFFSET 0x00680000
86 #define NV_PRAMDAC0_SIZE 0x00002000
88 #define NV_PDIO0_OFFSET 0x00681000
89 #define NV_PDIO_SIZE 0x00002000
90 #define NV_PDIO1_OFFSET 0x00683000
92 #define NV_PRAMIN_OFFSET 0x00700000
93 #define NV_PRAMIN_SIZE 0x00100000
95 #define NV_FIFO_OFFSET 0x00800000
96 #define NV_FIFO_SIZE 0x00800000
98 #define CRTC_INDEX_COLOR 0x3d4
99 #define CRTC_DATA_COLOR 0x3d5
101 /* Nvidia CRTC indexed registers */
102 /* VGA standard registers: - from Haiku */
103 #define NV_VGA_CRTCX_HTOTAL 0x00
104 #define NV_VGA_CRTCX_HDISPE 0x01
105 #define NV_VGA_CRTCX_HBLANKS 0x02
106 #define NV_VGA_CRTCX_HBLANKE 0x03
107 #define NV_VGA_CRTCX_HSYNCS 0x04
108 #define NV_VGA_CRTCX_HSYNCE 0x05
109 #define NV_VGA_CRTCX_VTOTAL 0x06
110 #define NV_VGA_CRTCX_OVERFLOW 0x07
111 #define NV_VGA_CRTCX_PRROWSCN 0x08
112 #define NV_VGA_CRTCX_MAXSCLIN 0x09
113 #define NV_VGA_CRTCX_VGACURSTART 0x0a
114 #define NV_VGA_CRTCX_VGACUREND 0x0b
115 #define NV_VGA_CRTCX_FBSTADDH 0x0c
116 #define NV_VGA_CRTCX_FBSTADDL 0x0d
117 #define NV_VGA_CRTCX_VSYNCS 0x10
118 #define NV_VGA_CRTCX_VSYNCE 0x11
119 #define NV_VGA_CRTCX_VDISPE 0x12
120 #define NV_VGA_CRTCX_PITCHL 0x13
121 #define NV_VGA_CRTCX_UNDERLINE 0x14
122 #define NV_VGA_CRTCX_VBLANKS 0x15
123 #define NV_VGA_CRTCX_VBLANKE 0x16
124 #define NV_VGA_CRTCX_MODECTL 0x17
125 #define NV_VGA_CRTCX_LINECOMP 0x18
126 /* Extended VGA CRTC registers */
127 #define NV_VGA_CRTCX_REPAINT0 0x19
128 #define NV_VGA_CRTCX_REPAINT1 0x1a
129 #define NV_VGA_CRTCX_FIFO0 0x1b
130 #define NV_VGA_CRTCX_FIFO1 0x1c
131 #define NV_VGA_CRTCX_LOCK 0x1f
132 #define NV_VGA_CRTCX_FIFO_LWM 0x20
133 #define NV_VGA_CRTCX_BUFFER 0x21
134 #define NV_VGA_CRTCX_LSR 0x25
135 #define NV_VGA_CRTCX_26 0x26
136 #define NV_VGA_CRTCX_REVISION 0x27
137 #define NV_VGA_CRTCX_PIXEL 0x28
138 #define NV_VGA_CRTCX_HEB 0x2d
139 #define NV_VGA_CRTCX_2E 0x2e
140 #define NV_VGA_CRTCX_CURCTL2 0x2f
141 #define NV_VGA_CRTCX_CURCTL0 0x30
142 #define NV_VGA_CRTCX_CURCTL1 0x31
143 #define NV_VGA_CRTCX_LCD 0x33
144 #define NV_VGA_CRTCX_INTERLACE 0x39
145 #define NV_VGA_CRTCX_3B 0x3b
146 #define NV_VGA_CRTCX_SCRATCH4 0x3c
147 #define NV_VGA_CRTCX_EXTRA 0x41
148 #define NV_VGA_CRTCX_OWNER 0x44
149 #define NV_VGA_CRTCX_45 0x45
150 #define NV_VGA_CRTCX_SWAPPING 0x46
151 #define NV_VGA_CRTCX_FIFO_LWM_NV30 0x47
152 #define NV_VGA_CRTCX_4B 0x4b
153 #define NV_VGA_CRTCX_FP_HTIMING 0x53
154 #define NV_VGA_CRTCX_FP_VTIMING 0x54
155 #define NV_VGA_CRTCX_52 0x52
156 #define NV_VGA_CRTCX_55 0x55
157 #define NV_VGA_CRTCX_56 0x56
158 #define NV_VGA_CRTCX_57 0x57
159 #define NV_VGA_CRTCX_58 0x58
160 #define NV_VGA_CRTCX_59 0x59
161 #define NV_VGA_CRTCX_85 0x85
162 #define NV_VGA_CRTCX_86 0x86
164 #define NV_PMC_BOOT_0 0x00000000
165 #define NV_PMC_ENABLE 0x00000200
167 #define NV_PBUS_DEBUG_1 0x00001084
168 #define NV_PBUS_DEBUG_4 0x00001098
169 #define NV_PBUS_DEBUG_DUALHEAD_CTL 0x000010f0
170 #define NV_PBUS_POWERCTRL_1 0x00001584
171 #define NV_PBUS_POWERCTRL_2 0x00001588
172 #define NV_PBUS_POWERCTRL_4 0x00001590
173 #define NV_PBUS_PCI_NV_19 0x0000184C
174 #define NV_PBUS_PCI_NV_20 0x00001850
175 # define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED (0 << 0)
176 # define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED (1 << 0)
178 #define NV_PFIFO_RAMHT 0x00002210
180 #define NV_PFB_BOOT_0 0x00100000
181 #define NV_PFB_CFG0 0x00100200
182 #define NV_PFB_CFG1 0x00100204
183 #define NV_PFB_020C 0x0010020C
184 #define NV_PFB_REFCTRL 0x00100210
185 # define NV_PFB_REFCTRL_VALID_1 (1 << 31)
186 #define NV_PFB_PAD 0x0010021C
187 # define NV_PFB_PAD_CKE_NORMAL (1 << 0)
188 #define NV_PFB_TILE_NV10 0x00100240
189 #define NV_PFB_TILE_SIZE_NV10 0x00100244
190 #define NV_PFB_REF 0x001002D0
191 # define NV_PFB_REF_CMD_REFRESH (1 << 0)
192 #define NV_PFB_PRE 0x001002D4
193 # define NV_PFB_PRE_CMD_PRECHARGE (1 << 0)
194 #define NV_PFB_CLOSE_PAGE2 0x0010033C
195 #define NV_PFB_TILE_NV40 0x00100600
196 #define NV_PFB_TILE_SIZE_NV40 0x00100604
198 #define NV_PEXTDEV_BOOT_0 0x00101000
199 # define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT (1 << 15)
200 #define NV_PEXTDEV_BOOT_3 0x0010100c
202 #define NV_CRTC_INTR_0 0x00600100
203 # define NV_CRTC_INTR_VBLANK (1<<0)
204 #define NV_CRTC_INTR_EN_0 0x00600140
205 #define NV_CRTC_START 0x00600800
206 #define NV_CRTC_CONFIG 0x00600804
207 #define NV_CRTC_CURSOR_ADDRESS 0x0060080C
208 #define NV_CRTC_CURSOR_CONFIG 0x00600810
209 # define NV_CRTC_CURSOR_CONFIG_ENABLE (1 << 0)
210 # define NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN (1 << 4)
211 # define NV_CRTC_CURSOR_CONFIG_32BPP (1 << 12)
212 # define NV_CRTC_CURSOR_CONFIG_64PIXELS (1 << 16)
213 # define NV_CRTC_CURSOR_CONFIG_32LINES (1 << 25)
214 # define NV_CRTC_CURSOR_CONFIG_64LINES (1 << 26)
215 # define NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND (1 << 28)
217 #define NV_CRTC_GPIO 0x00600818
218 #define NV_CRTC_GPIO_EXT 0x0060081c
219 #define NV_CRTC_0830 0x00600830
220 #define NV_CRTC_0834 0x00600834
221 #define NV_CRTC_0850 0x00600850
222 #define NV_CRTC_FSEL 0x00600860
223 # define NV_CRTC_FSEL_I2C (1<<4)
224 # define NV_CRTC_FSEL_TVOUT1 (1<<8)
225 # define NV_CRTC_FSEL_TVOUT2 (2<<8)
226 # define NV_CRTC_FSEL_OVERLAY (1<<12)
228 #define NV_RAMDAC_CURSOR_POS 0x00680300
229 #define NV_RAMDAC_CURSOR_CTRL 0x00680320
230 #define NV_RAMDAC_CURSOR_DATA_LO 0x00680324
231 #define NV_RAMDAC_CURSOR_DATA_HI 0x00680328
232 #define NV_RAMDAC_NV10_CURSYNC 0x00680404
234 #define NV_RAMDAC_NVPLL 0x00680500
235 #define NV_RAMDAC_MPLL 0x00680504
236 #define NV_RAMDAC_VPLL 0x00680508
237 # define NV_RAMDAC_PLL_COEFF_MDIV 0x000000FF
238 # define NV_RAMDAC_PLL_COEFF_NDIV 0x0000FF00
239 # define NV_RAMDAC_PLL_COEFF_PDIV 0x00070000
240 # define NV30_RAMDAC_ENABLE_VCO2 (1 << 7)
242 #define NV_RAMDAC_PLL_SELECT 0x0068050c
243 /* Without this it will use vpll1 */
244 /* Maybe only for nv4x */
245 # define NV_RAMDAC_PLL_SELECT_USE_VPLL2_FALSE (0<<2)
246 # define NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE (1<<2)
247 # define NV_RAMDAC_PLL_SELECT_DLL_BYPASS (1<<4)
248 # define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_DEFAULT (0<<8)
249 # define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL (1<<8)
250 # define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL (2<<8)
251 # define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL (4<<8)
252 # define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL (7<<8)
253 # define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2 (8<<8)
254 # define NV_RAMDAC_PLL_SELECT_MPLL_BYPASS_FALSE (0<<12)
255 # define NV_RAMDAC_PLL_SELECT_MPLL_BYPASS_TRUE (1<<12)
256 # define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_NONE (0<<16)
257 # define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_VSCLK (1<<16)
258 # define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_PCLK (2<<16)
259 # define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_BOTH (3<<16)
260 # define NV_RAMDAC_PLL_SELECT_TVCLK_SOURCE_EXT (0<<20)
261 # define NV_RAMDAC_PLL_SELECT_TVCLK_SOURCE_VIP (1<<20)
262 # define NV_RAMDAC_PLL_SELECT_TVCLK_RATIO_DB1 (0<<24)
263 # define NV_RAMDAC_PLL_SELECT_TVCLK_RATIO_DB2 (1<<24)
264 # define NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB1 (0<<28)
265 # define NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 (1<<28)
266 # define NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB1 (0<<29)
267 # define NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2 (1<<29)
269 #define NV_RAMDAC_PLL_SETUP_CONTROL 0x00680510
270 #define NV_RAMDAC_PLL_TEST_COUNTER 0x00680514
271 #define NV_RAMDAC_PALETTE_TEST 0x00680518
272 #define NV_RAMDAC_VPLL2 0x00680520
273 #define NV_RAMDAC_SEL_CLK 0x00680524
274 #define NV_RAMDAC_DITHER_NV11 0x00680528
275 #define NV_RAMDAC_OUTPUT 0x0068052c
276 # define NV_RAMDAC_OUTPUT_DAC_ENABLE (1<<0)
277 # define NV_RAMDAC_OUTPUT_SELECT_CRTC1 (1<<8)
279 #define NV_RAMDAC_NVPLL_B 0x00680570
280 #define NV_RAMDAC_MPLL_B 0x00680574
281 #define NV_RAMDAC_VPLL_B 0x00680578
282 #define NV_RAMDAC_VPLL2_B 0x0068057c
283 /* Educated guess, should remain on for NV4x vpll's. */
284 # define NV31_RAMDAC_ENABLE_VCO2 (1 << 31)
286 #define NV_RAMDAC_580 0x00680580
287 /* This is not always activated, but only when VCLK_RATIO_DB1 is used */
288 # define NV_RAMDAC_580_VPLL1_ACTIVE (1<<8)
289 # define NV_RAMDAC_580_VPLL2_ACTIVE (1<<28)
291 #define NV_RAMDAC_594 0x00680594
292 #define NV_RAMDAC_GENERAL_CONTROL 0x00680600
293 #define NV_RAMDAC_TEST_CONTROL 0x00680608
294 #define NV_RAMDAC_TEST_DATA 0x00680610
295 #define NV_RAMDAC_630 0x00680630
296 /* This register is similar to TEST_CONTROL in the style of values */
297 #define NV_RAMDAC_670 0x00680670
299 #define NV_RAMDAC_TV_SETUP 0x00680700
300 #define NV_RAMDAC_TV_VBLANK_START 0x00680704
301 #define NV_RAMDAC_TV_VBLANK_END 0x00680708
302 #define NV_RAMDAC_TV_HBLANK_START 0x0068070c
303 #define NV_RAMDAC_TV_HBLANK_END 0x00680710
304 #define NV_RAMDAC_TV_BLANK_COLOR 0x00680714
305 #define NV_RAMDAC_TV_VTOTAL 0x00680720
306 #define NV_RAMDAC_TV_VSYNC_START 0x00680724
307 #define NV_RAMDAC_TV_VSYNC_END 0x00680728
308 #define NV_RAMDAC_TV_HTOTAL 0x0068072c
309 #define NV_RAMDAC_TV_HSYNC_START 0x00680730
310 #define NV_RAMDAC_TV_HSYNC_END 0x00680734
311 #define NV_RAMDAC_TV_SYNC_DELAY 0x00680738
313 #define REG_DISP_END 0
314 #define REG_DISP_TOTAL 1
315 #define REG_DISP_CRTC 2
316 #define REG_DISP_SYNC_START 3
317 #define REG_DISP_SYNC_END 4
318 #define REG_DISP_VALID_START 5
319 #define REG_DISP_VALID_END 6
321 #define NV_RAMDAC_FP_VDISP_END 0x00680800
322 #define NV_RAMDAC_FP_VTOTAL 0x00680804
323 #define NV_RAMDAC_FP_VCRTC 0x00680808
324 #define NV_RAMDAC_FP_VSYNC_START 0x0068080c
325 #define NV_RAMDAC_FP_VSYNC_END 0x00680810
326 #define NV_RAMDAC_FP_VVALID_START 0x00680814
327 #define NV_RAMDAC_FP_VVALID_END 0x00680818
328 #define NV_RAMDAC_FP_HDISP_END 0x00680820
329 #define NV_RAMDAC_FP_HTOTAL 0x00680824
330 #define NV_RAMDAC_FP_HCRTC 0x00680828
331 #define NV_RAMDAC_FP_HSYNC_START 0x0068082c
332 #define NV_RAMDAC_FP_HSYNC_END 0x00680830
333 #define NV_RAMDAC_FP_HVALID_START 0x00680834
334 #define NV_RAMDAC_FP_HVALID_END 0x00680838
336 #define NV_RAMDAC_FP_DITHER 0x0068083c
337 #define NV_RAMDAC_FP_CHECKSUM 0x00680840
338 #define NV_RAMDAC_FP_TEST_CONTROL 0x00680844
339 #define NV_RAMDAC_FP_CONTROL 0x00680848
340 # define NV_RAMDAC_FP_CONTROL_VSYNC_NEG (0 << 0)
341 # define NV_RAMDAC_FP_CONTROL_VSYNC_POS (1 << 0)
342 # define NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE (2 << 0)
343 # define NV_RAMDAC_FP_CONTROL_HSYNC_NEG (0 << 4)
344 # define NV_RAMDAC_FP_CONTROL_HSYNC_POS (1 << 4)
345 # define NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE (2 << 4)
346 # define NV_RAMDAC_FP_CONTROL_MODE_SCALE (0 << 8)
347 # define NV_RAMDAC_FP_CONTROL_MODE_CENTER (1 << 8)
348 # define NV_RAMDAC_FP_CONTROL_MODE_NATIVE (2 << 8)
349 # define NV_RAMDAC_FP_CONTROL_WIDTH_12 (1 << 24)
350 # define NV_RAMDAC_FP_CONTROL_DISPEN_POS (1 << 28)
351 # define NV_RAMDAC_FP_CONTROL_DISPEN_DISABLE (2 << 28)
352 #define NV_RAMDAC_FP_850 0x00680850
353 #define NV_RAMDAC_FP_85C 0x0068085c
355 #define NV_RAMDAC_FP_DEBUG_0 0x00680880
356 # define NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED (1 << 0)
357 # define NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED (1 << 4)
358 /* This doesn't seem to be essential for tmds, but still often set */
359 # define NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED (1 << 7)
360 # define NV_RAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK (1 << 28)
361 # define NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL (2 << 28)
362 # define NV_RAMDAC_FP_DEBUG_0_PWRDOWN_BOTH (3 << 28)
363 #define NV_RAMDAC_FP_DEBUG_1 0x00680884
364 #define NV_RAMDAC_FP_DEBUG_2 0x00680888
365 #define NV_RAMDAC_FP_DEBUG_3 0x0068088C
367 /* Some unknown regs, purely for NV30 it seems. */
368 #define NV30_RAMDAC_890 0x00680890
369 #define NV30_RAMDAC_894 0x00680894
370 #define NV30_RAMDAC_89C 0x0068089C
372 #define NV_RAMDAC_FP_TMDS_CONTROL 0x006808b0
373 # define NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE (1<<16)
374 #define NV_RAMDAC_FP_TMDS_DATA 0x006808b4
375 #define NV_RAMDAC_FP_TMDS_CONTROL_2 0x006808b8
376 # define NV_RAMDAC_FP_TMDS_CONTROL_2_WRITE_DISABLE (1<<16)
377 #define NV_RAMDAC_FP_TMDS_DATA_2 0x006808bc
379 /* Some kind of switch */
380 #define NV_RAMDAC_900 0x00680900
381 #define NV_RAMDAC_A20 0x00680A20
382 #define NV_RAMDAC_A24 0x00680A24
383 #define NV_RAMDAC_A34 0x00680A34
385 #define NV_PGRAPH_DEBUG_0 0x00400080
386 #define NV_PGRAPH_DEBUG_1 0x00400084
387 #define NV_PGRAPH_DEBUG_2_NV04 0x00400088
388 #define NV_PGRAPH_DEBUG_2 0x00400620
389 #define NV_PGRAPH_DEBUG_3 0x0040008c
390 #define NV_PGRAPH_DEBUG_4 0x00400090
391 #define NV_PGRAPH_INTR 0x00400100
392 #define NV_PGRAPH_INTR_EN 0x00400140
393 #define NV_PGRAPH_CTX_CONTROL 0x00400144
394 #define NV_PGRAPH_CTX_CONTROL_NV04 0x00400170
395 #define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C
396 #define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540
397 #define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544
398 #define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548
399 #define NV_PGRAPH_BETA_AND 0x00400608
400 #define NV_PGRAPH_LIMIT_VIOL_PIX 0x00400610
401 #define NV_PGRAPH_BOFFSET0 0x00400640
402 #define NV_PGRAPH_BOFFSET1 0x00400644
403 #define NV_PGRAPH_BOFFSET2 0x00400648
404 #define NV_PGRAPH_BLIMIT0 0x00400684
405 #define NV_PGRAPH_BLIMIT1 0x00400688
406 #define NV_PGRAPH_BLIMIT2 0x0040068c
407 #define NV_PGRAPH_STATUS 0x00400700
408 #define NV_PGRAPH_SURFACE 0x00400710
409 #define NV_PGRAPH_STATE 0x00400714
410 #define NV_PGRAPH_FIFO 0x00400720
411 #define NV_PGRAPH_PATTERN_SHAPE 0x00400810
412 #define NV_PGRAPH_TILE 0x00400b00
414 #define NV_PVIDEO_INTR_EN 0x00008140
415 #define NV_PVIDEO_BUFFER 0x00008700
416 #define NV_PVIDEO_STOP 0x00008704
417 #define NV_PVIDEO_UVPLANE_BASE(buff) (0x00008800+(buff)*4)
418 #define NV_PVIDEO_UVPLANE_LIMIT(buff) (0x00008808+(buff)*4)
419 #define NV_PVIDEO_UVPLANE_OFFSET_BUFF(buff) (0x00008820+(buff)*4)
420 #define NV_PVIDEO_BASE(buff) (0x00008900+(buff)*4)
421 #define NV_PVIDEO_LIMIT(buff) (0x00008908+(buff)*4)
422 #define NV_PVIDEO_LUMINANCE(buff) (0x00008910+(buff)*4)
423 #define NV_PVIDEO_CHROMINANCE(buff) (0x00008918+(buff)*4)
424 #define NV_PVIDEO_OFFSET_BUFF(buff) (0x00008920+(buff)*4)
425 #define NV_PVIDEO_SIZE_IN(buff) (0x00008928+(buff)*4)
426 #define NV_PVIDEO_POINT_IN(buff) (0x00008930+(buff)*4)
427 #define NV_PVIDEO_DS_DX(buff) (0x00008938+(buff)*4)
428 #define NV_PVIDEO_DT_DY(buff) (0x00008940+(buff)*4)
429 #define NV_PVIDEO_POINT_OUT(buff) (0x00008948+(buff)*4)
430 #define NV_PVIDEO_SIZE_OUT(buff) (0x00008950+(buff)*4)
431 #define NV_PVIDEO_FORMAT(buff) (0x00008958+(buff)*4)
432 # define NV_PVIDEO_FORMAT_PLANAR (1 << 0)
433 # define NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8 (1 << 16)
434 # define NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY (1 << 20)
435 # define NV_PVIDEO_FORMAT_MATRIX_ITURBT709 (1 << 24)
436 #define NV_PVIDEO_COLOR_KEY 0x00008B00
438 /* NV04 overlay defines from VIDIX & Haiku */
439 #define NV_PVIDEO_INTR_EN_0 0x00680140
440 #define NV_PVIDEO_STEP_SIZE 0x00680200
441 #define NV_PVIDEO_CONTROL_Y 0x00680204
442 #define NV_PVIDEO_CONTROL_X 0x00680208
443 #define NV_PVIDEO_BUFF0_START_ADDRESS 0x0068020c
444 #define NV_PVIDEO_BUFF0_PITCH_LENGTH 0x00680214
445 #define NV_PVIDEO_BUFF0_OFFSET 0x0068021c
446 #define NV_PVIDEO_BUFF1_START_ADDRESS 0x00680210
447 #define NV_PVIDEO_BUFF1_PITCH_LENGTH 0x00680218
448 #define NV_PVIDEO_BUFF1_OFFSET 0x00680220
449 #define NV_PVIDEO_OE_STATE 0x00680224
450 #define NV_PVIDEO_SU_STATE 0x00680228
451 #define NV_PVIDEO_RM_STATE 0x0068022c
452 #define NV_PVIDEO_WINDOW_START 0x00680230
453 #define NV_PVIDEO_WINDOW_SIZE 0x00680234
454 #define NV_PVIDEO_FIFO_THRES_SIZE 0x00680238
455 #define NV_PVIDEO_FIFO_BURST_LENGTH 0x0068023c
456 #define NV_PVIDEO_KEY 0x00680240
457 #define NV_PVIDEO_OVERLAY 0x00680244
458 #define NV_PVIDEO_RED_CSC_OFFSET 0x00680280
459 #define NV_PVIDEO_GREEN_CSC_OFFSET 0x00680284
460 #define NV_PVIDEO_BLUE_CSC_OFFSET 0x00680288
461 #define NV_PVIDEO_CSC_ADJUST 0x0068028c
463 /* These are the real registers, not the redirected ones */
464 #define NV40_VCLK1_A 0x4010
465 #define NV40_VCLK1_B 0x4014
466 #define NV40_VCLK2_A 0x4018
467 #define NV40_VCLK2_B 0x401c