git.oblomov.eu Git - nouveau/blob - src/nv_output.c

   1 /*
   2  * Copyright 2003 NVIDIA, Corporation
   3  * Copyright 2006 Dave Airlie
   4  * Copyright 2007 Maarten Maathuis
   5  * Copyright 2007-2008 Stuart Bennett
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  23  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "xf86.h"
  32 #include "os.h"
  33 #include "mibank.h"
  34 #include "globals.h"
  35 #include "xf86.h"
  36 #include "xf86Priv.h"
  37 #include "xf86DDC.h"
  38 #include "mipointer.h"
  39 #include "windowstr.h"
  40 #include <randrstr.h>
  41 #include <X11/extensions/render.h>
  42 #include "X11/Xatom.h"
  43
  44 #include "xf86Crtc.h"
  45 #include "nv_include.h"
  46
  47 #define MULTIPLE_ENCODERS(e) (e & (e - 1))
  48 #define FOR_EACH_ENCODER_IN_CONNECTOR(i, c, e)  for (i = 0; i < pNv->dcb_table.entries; i++)    \
  49                                                         if (c->possible_encoders & (1 << i) &&  \
  50                                                             (e = &pNv->encoders[i]))
  51
  52 static int nv_output_ramdac_offset(struct nouveau_encoder *nv_encoder)
  53 {
  54         int offset = 0;
  55
  56         if (nv_encoder->dcb->or & (8 | OUTPUT_C))
  57                 offset += 0x68;
  58         if (nv_encoder->dcb->or & (8 | OUTPUT_B))
  59                 offset += 0x2000;
  60
  61         return offset;
  62 }
  63
  64 static void dpms_update_fp_control(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
  65 {
  66         NVPtr pNv = NVPTR(pScrn);
  67         struct nouveau_crtc *nv_crtc;
  68         NVCrtcRegPtr regp;
  69         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
  70         int i;
  71
  72         if (mode == DPMSModeOn) {
  73                 nv_crtc = to_nouveau_crtc(crtc);
  74                 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
  75
  76                 nv_crtc->fp_users |= 1 << nv_encoder->dcb->index;
  77                 NVWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control & ~0x20000022);
  78         } else
  79                 for (i = 0; i <= pNv->twoHeads; i++) {
  80                         nv_crtc = to_nouveau_crtc(xf86_config->crtc[i]);
  81                         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
  82
  83                         nv_crtc->fp_users &= ~(1 << nv_encoder->dcb->index);
  84                         if (!nv_crtc->fp_users) {
  85                                 /* cut the FP output */
  86                                 regp->fp_control |= 0x20000022;
  87                                 NVWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
  88                         }
  89                 }
  90 }
  91
  92 static void nv_digital_output_prepare_sel_clk(NVPtr pNv, struct nouveau_encoder *nv_encoder, int head);
  93
  94 static void
  95 lvds_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
  96 {
  97         NVPtr pNv = NVPTR(pScrn);
  98
  99         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "lvds_encoder_dpms is called with mode %d\n", mode);
 100
 101         if (nv_encoder->last_dpms == mode)
 102                 return;
 103         nv_encoder->last_dpms = mode;
 104
 105         if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
 106                 /* when removing an output, crtc may not be set, but PANEL_OFF must still be run */
 107                 int head = nv_get_digital_bound_head(pNv, nv_encoder->dcb->or);
 108                 int pclk = nv_encoder->native_mode->Clock;
 109
 110                 if (crtc)
 111                         head = to_nouveau_crtc(crtc)->head;
 112
 113                 if (mode == DPMSModeOn)
 114                         call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_ON, pclk);
 115                 else
 116                         call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_OFF, pclk);
 117         }
 118
 119         dpms_update_fp_control(pScrn, nv_encoder, crtc, mode);
 120
 121         if (mode == DPMSModeOn)
 122                 nv_digital_output_prepare_sel_clk(pNv, nv_encoder, to_nouveau_crtc(crtc)->head);
 123         else {
 124                 pNv->ModeReg.sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 125                 pNv->ModeReg.sel_clk &= ~0xf0;
 126         }
 127         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
 128 }
 129
 130 static void
 131 vga_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 132 {
 133         NVPtr pNv = NVPTR(pScrn);
 134
 135         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vga_encoder_dpms is called with mode %d\n", mode);
 136
 137         if (nv_encoder->last_dpms == mode)
 138                 return;
 139         nv_encoder->last_dpms = mode;
 140
 141         if (pNv->twoHeads) {
 142                 uint32_t outputval = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder));
 143
 144                 if (mode == DPMSModeOff)
 145                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 146                                       outputval & ~NV_RAMDAC_OUTPUT_DAC_ENABLE);
 147                 else if (mode == DPMSModeOn)
 148                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 149                                       outputval | NV_RAMDAC_OUTPUT_DAC_ENABLE);
 150         }
 151 }
 152
 153 static void
 154 tmds_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 155 {
 156         NVPtr pNv = NVPTR(pScrn);
 157
 158         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "tmds_encoder_dpms is called with mode %d\n", mode);
 159
 160         if (nv_encoder->last_dpms == mode)
 161                 return;
 162         nv_encoder->last_dpms = mode;
 163
 164         dpms_update_fp_control(pScrn, nv_encoder, crtc, mode);
 165
 166         if (nv_encoder->dcb->location != LOC_ON_CHIP) {
 167                 struct nouveau_crtc *nv_crtc;
 168                 int i;
 169
 170                 if (mode == DPMSModeOn) {
 171                         nv_crtc = to_nouveau_crtc(crtc);
 172                         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD,
 173                                        pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_VGA_CRTCX_LCD]);
 174                 } else
 175                         for (i = 0; i <= pNv->twoHeads; i++)
 176                                 NVWriteVgaCrtc(pNv, i, NV_VGA_CRTCX_LCD,
 177                                                NVReadVgaCrtc(pNv, i, NV_VGA_CRTCX_LCD) & ~((nv_encoder->dcb->or << 4) & 0x30));
 178         }
 179 }
 180
 181 static void nv_output_dpms(xf86OutputPtr output, int mode)
 182 {
 183         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 184         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 185         ScrnInfoPtr pScrn = output->scrn;
 186         xf86CrtcPtr crtc = output->crtc;
 187         NVPtr pNv = NVPTR(pScrn);
 188         int i;
 189         void (* const encoder_dpms[4])(ScrnInfoPtr, struct nouveau_encoder *, xf86CrtcPtr, int) =
 190                 /* index matches DCB type */
 191                 { vga_encoder_dpms, NULL, tmds_encoder_dpms, lvds_encoder_dpms };
 192
 193         struct nouveau_encoder *nv_encoder_i;
 194         FOR_EACH_ENCODER_IN_CONNECTOR(i, nv_connector, nv_encoder_i)
 195                 if (nv_encoder_i != nv_encoder)
 196                         encoder_dpms[nv_encoder_i->dcb->type](pScrn, nv_encoder_i, crtc, DPMSModeOff);
 197
 198         encoder_dpms[nv_encoder->dcb->type](pScrn, nv_encoder, crtc, mode);
 199 }
 200
 201 void nv_encoder_save(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
 202 {
 203         NVPtr pNv = NVPTR(pScrn);
 204
 205         if (!nv_encoder->dcb)   /* uninitialised encoder */
 206                 return;
 207
 208         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_encoder_save is called.\n");
 209
 210         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
 211                 nv_encoder->restore.output = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder));
 212         if (nv_encoder->dcb->type == OUTPUT_TMDS || nv_encoder->dcb->type == OUTPUT_LVDS)
 213                 nv_encoder->restore.head = nv_get_digital_bound_head(pNv, nv_encoder->dcb->or);
 214 }
 215
 216 static uint32_t nv_get_clock_from_crtc(ScrnInfoPtr pScrn, RIVA_HW_STATE *state, uint8_t crtc)
 217 {
 218         NVPtr pNv = NVPTR(pScrn);
 219         struct pll_lims pll_lim;
 220         uint32_t vplla = state->crtc_reg[crtc].vpll_a;
 221         uint32_t vpllb = state->crtc_reg[crtc].vpll_b;
 222         bool nv40_single = pNv->Architecture == 0x40 &&
 223                            ((!crtc && state->reg580 & NV_RAMDAC_580_VPLL1_ACTIVE) ||
 224                             (crtc && state->reg580 & NV_RAMDAC_580_VPLL2_ACTIVE));
 225
 226         if (!get_pll_limits(pScrn, crtc ? VPLL2 : VPLL1, &pll_lim))
 227                 return 0;
 228
 229         return nv_decode_pll_highregs(pNv, vplla, vpllb, nv40_single, pll_lim.refclk);
 230 }
 231
 232 void nv_encoder_restore(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
 233 {
 234         NVPtr pNv = NVPTR(pScrn);
 235         int head = nv_encoder->restore.head;
 236
 237         if (!nv_encoder->dcb)   /* uninitialised encoder */
 238                 return;
 239
 240         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_encoder_restore is called.\n");
 241
 242         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
 243                 NVWriteRAMDAC(pNv, 0,
 244                               NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 245                               nv_encoder->restore.output);
 246         if (nv_encoder->dcb->type == OUTPUT_LVDS)
 247                 call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_ON,
 248                                  nv_encoder->native_mode->Clock);
 249         if (nv_encoder->dcb->type == OUTPUT_TMDS) {
 250                 int clock = nv_get_clock_from_crtc(pScrn, &pNv->SavedReg, head);
 251
 252                 run_tmds_table(pScrn, nv_encoder->dcb, head, clock);
 253         }
 254
 255         nv_encoder->last_dpms = NV_DPMS_CLEARED;
 256 }
 257
 258 static int nv_output_mode_valid(xf86OutputPtr output, DisplayModePtr mode)
 259 {
 260         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 261         NVPtr pNv = NVPTR(output->scrn);
 262
 263         if (!output->doubleScanAllowed && mode->Flags & V_DBLSCAN)
 264                 return MODE_NO_DBLESCAN;
 265         if (!output->interlaceAllowed && mode->Flags & V_INTERLACE)
 266                 return MODE_NO_INTERLACE;
 267
 268         if (nv_encoder->dcb->type == OUTPUT_ANALOG) {
 269                 if (mode->Clock > (pNv->twoStagePLL ? 400000 : 350000))
 270                         return MODE_CLOCK_HIGH;
 271                 if (mode->Clock < 12000)
 272                         return MODE_CLOCK_LOW;
 273         }
 274         if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS)
 275                 /* No modes > panel's native res */
 276                 if (mode->HDisplay > nv_encoder->native_mode->HDisplay ||
 277                     mode->VDisplay > nv_encoder->native_mode->VDisplay)
 278                         return MODE_PANEL;
 279         if (nv_encoder->dcb->type == OUTPUT_TMDS) {
 280                 if (nv_encoder->dcb->duallink_possible) {
 281                         if (mode->Clock > 330000) /* 2x165 MHz */
 282                                 return MODE_CLOCK_HIGH;
 283                 } else {
 284                         if (mode->Clock > 165000) /* 165 MHz */
 285                                 return MODE_CLOCK_HIGH;
 286                 }
 287         }
 288
 289         return MODE_OK;
 290 }
 291
 292 static Bool
 293 nv_output_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
 294                      DisplayModePtr adjusted_mode)
 295 {
 296         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 297         ScrnInfoPtr pScrn = output->scrn;
 298
 299         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_mode_fixup is called.\n");
 300
 301         /* For internal panels and gpu scaling on DVI we need the native mode */
 302         if (nv_encoder->dcb->type == OUTPUT_LVDS ||
 303             (nv_encoder->dcb->type == OUTPUT_TMDS && nv_encoder->scaling_mode != SCALE_PANEL)) {
 304                 adjusted_mode->HDisplay = nv_encoder->native_mode->HDisplay;
 305                 adjusted_mode->HSkew = nv_encoder->native_mode->HSkew;
 306                 adjusted_mode->HSyncStart = nv_encoder->native_mode->HSyncStart;
 307                 adjusted_mode->HSyncEnd = nv_encoder->native_mode->HSyncEnd;
 308                 adjusted_mode->HTotal = nv_encoder->native_mode->HTotal;
 309                 adjusted_mode->VDisplay = nv_encoder->native_mode->VDisplay;
 310                 adjusted_mode->VScan = nv_encoder->native_mode->VScan;
 311                 adjusted_mode->VSyncStart = nv_encoder->native_mode->VSyncStart;
 312                 adjusted_mode->VSyncEnd = nv_encoder->native_mode->VSyncEnd;
 313                 adjusted_mode->VTotal = nv_encoder->native_mode->VTotal;
 314                 adjusted_mode->Clock = nv_encoder->native_mode->Clock;
 315                 adjusted_mode->Flags = nv_encoder->native_mode->Flags;
 316
 317                 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
 318         }
 319
 320         return TRUE;
 321 }
 322
 323 static void
 324 nv_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 325 {
 326         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 327         ScrnInfoPtr pScrn = output->scrn;
 328         NVPtr pNv = NVPTR(pScrn);
 329         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(output->crtc);
 330
 331         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_mode_set is called.\n");
 332
 333         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
 334                 /* bit 16-19 are bits that are set on some G70 cards,
 335                  * but don't seem to have much effect */
 336                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 337                               nv_crtc->head << 8 | NV_RAMDAC_OUTPUT_DAC_ENABLE);
 338         if (nv_encoder->dcb->type == OUTPUT_TMDS)
 339                 run_tmds_table(pScrn, nv_encoder->dcb, nv_crtc->head, adjusted_mode->Clock);
 340         else if (nv_encoder->dcb->type == OUTPUT_LVDS)
 341                 call_lvds_script(pScrn, nv_encoder->dcb, nv_crtc->head, LVDS_RESET, adjusted_mode->Clock);
 342
 343         /* This could use refinement for flatpanels, but it should work this way */
 344         if (pNv->NVArch < 0x44)
 345                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + nv_output_ramdac_offset(nv_encoder), 0xf0000000);
 346         else
 347                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + nv_output_ramdac_offset(nv_encoder), 0x00100000);
 348 }
 349
 350 static Bool
 351 nv_load_detect(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
 352 {
 353         NVPtr pNv = NVPTR(pScrn);
 354         uint32_t testval, regoffset = nv_output_ramdac_offset(nv_encoder);
 355         uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, saved_rtest_ctrl, temp;
 356         int present = 0;
 357
 358 #define RGB_TEST_DATA(r,g,b) (r << 0 | g << 10 | b << 20)
 359         testval = RGB_TEST_DATA(0x140, 0x140, 0x140); /* 0x94050140 */
 360         if (pNv->VBIOS.dactestval)
 361                 testval = pNv->VBIOS.dactestval;
 362
 363         saved_rtest_ctrl = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset);
 364         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl & ~0x00010000);
 365
 366         if (pNv->NVArch >= 0x17) {
 367                 saved_powerctrl_2 = nvReadMC(pNv, NV_PBUS_POWERCTRL_2);
 368
 369                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);
 370                 if (regoffset == 0x68) {
 371                         saved_powerctrl_4 = nvReadMC(pNv, NV_PBUS_POWERCTRL_4);
 372                         nvWriteMC(pNv, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);
 373                 }
 374         }
 375
 376         usleep(4000);
 377
 378         saved_routput = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset);
 379         /* nv driver and nv31 use 0xfffffeee
 380          * nv34 and 6600 use 0xfffffece */
 381         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, saved_routput & 0xfffffece);
 382         usleep(1000);
 383
 384         temp = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset);
 385         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, temp | 1);
 386
 387         /* no regoffset on purpose */
 388         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_DATA, 1 << 31 | testval);
 389         temp = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL);
 390         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL, temp | 0x1000);
 391         usleep(1000);
 392
 393         present = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset) & (1 << 28);
 394
 395         /* no regoffset on purpose */
 396         temp = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL);
 397         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL, temp & 0xffffefff);
 398         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_DATA, 0);
 399
 400         /* bios does something more complex for restoring, but I think this is good enough */
 401         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, saved_routput);
 402         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl);
 403         if (pNv->NVArch >= 0x17) {
 404                 if (regoffset == 0x68)
 405                         nvWriteMC(pNv, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);
 406                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);
 407         }
 408
 409         if (present) {
 410                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Load detected on output %c\n", '@' + ffs(nv_encoder->dcb->or));
 411                 return TRUE;
 412         }
 413
 414         return FALSE;
 415 }
 416
 417 static xf86OutputStatus
 418 nv_output_detect(xf86OutputPtr output)
 419 {
 420         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 421         ScrnInfoPtr pScrn = output->scrn;
 422         NVPtr pNv = NVPTR(pScrn);
 423         struct nouveau_encoder *nv_encoder;
 424         xf86OutputStatus ret = XF86OutputStatusDisconnected;
 425
 426         struct nouveau_encoder *find_encoder_by_type(NVOutputType type)
 427         {
 428                 int i;
 429                 for (i = 0; i < pNv->dcb_table.entries; i++)
 430                         if (nv_connector->possible_encoders & (1 << i) &&
 431                             (type == OUTPUT_ANY || pNv->encoders[i].dcb->type == type))
 432                                 return &pNv->encoders[i];
 433                 return NULL;
 434         }
 435
 436         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_detect is called.\n");
 437
 438         if (nv_connector->pDDCBus &&
 439             (nv_connector->mon = xf86OutputGetEDID(output, nv_connector->pDDCBus),
 440              xf86OutputSetEDID(output, nv_connector->mon), nv_connector->mon)) {
 441                 if (MULTIPLE_ENCODERS(nv_connector->possible_encoders)) {
 442                         if (nv_connector->mon->features.input_type)
 443                                 nv_encoder = find_encoder_by_type(OUTPUT_TMDS);
 444                         else
 445                                 nv_encoder = find_encoder_by_type(OUTPUT_ANALOG);
 446                 } else
 447                         nv_encoder = find_encoder_by_type(OUTPUT_ANY);
 448                 ret = XF86OutputStatusConnected;
 449         } else if ((nv_encoder = find_encoder_by_type(OUTPUT_ANALOG))) {
 450                 /* we don't have a load det function for early cards */
 451                 if (!pNv->twoHeads || pNv->NVArch == 0x11)
 452                         ret = XF86OutputStatusUnknown;
 453                 else if (pNv->twoHeads && nv_load_detect(pScrn, nv_encoder))
 454                         ret = XF86OutputStatusConnected;
 455         } else if ((nv_encoder = find_encoder_by_type(OUTPUT_LVDS))) {
 456                 if (nv_encoder->dcb->lvdsconf.use_straps_for_mode &&
 457                     pNv->VBIOS.fp.native_mode)
 458                         ret = XF86OutputStatusConnected;
 459                 if (pNv->VBIOS.fp.edid) {
 460                         xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 461                                    "Will use hardcoded BIOS FP EDID\n");
 462                         nv_connector->mon = xf86InterpretEDID(pScrn->scrnIndex,
 463                                                            pNv->VBIOS.fp.edid);
 464                         xf86OutputSetEDID(output, nv_connector->mon);
 465                         ret = XF86OutputStatusConnected;
 466                 }
 467         }
 468
 469         return ret;
 470 }
 471
 472 static DisplayModePtr
 473 get_native_mode_from_edid(xf86OutputPtr output, DisplayModePtr edid_modes)
 474 {
 475         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 476         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 477         ScrnInfoPtr pScrn = output->scrn;
 478         int max_h_active = 0, max_v_active = 0;
 479         int i;
 480         DisplayModePtr mode;
 481
 482         for (i = 0; i < DET_TIMINGS; i++) {
 483                 /* We only look at detailed timings atm */
 484                 if (nv_connector->mon->det_mon[i].type != DT)
 485                         continue;
 486                 /* Selecting only based on width ok? */
 487                 if (nv_connector->mon->det_mon[i].section.d_timings.h_active > max_h_active) {
 488                         max_h_active = nv_connector->mon->det_mon[i].section.d_timings.h_active;
 489                         max_v_active = nv_connector->mon->det_mon[i].section.d_timings.v_active;
 490                 }
 491         }
 492         if (!(max_h_active && max_v_active)) {
 493                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No EDID detailed timings available, bailing out.\n");
 494                 return NULL;
 495         }
 496
 497         if (nv_encoder->native_mode) {
 498                 xfree(nv_encoder->native_mode);
 499                 nv_encoder->native_mode = NULL;
 500         }
 501
 502         for (mode = edid_modes; mode != NULL; mode = mode->next) {
 503                 if (mode->HDisplay == max_h_active &&
 504                         mode->VDisplay == max_v_active) {
 505                         /* Take the preferred mode when it exists. */
 506                         if (mode->type & M_T_PREFERRED) {
 507                                 nv_encoder->native_mode = xf86DuplicateMode(mode);
 508                                 break;
 509                         }
 510                         /* Find the highest refresh mode otherwise. */
 511                         if (!nv_encoder->native_mode || (mode->VRefresh > nv_encoder->native_mode->VRefresh)) {
 512                                 if (nv_encoder->native_mode)
 513                                         xfree(nv_encoder->native_mode);
 514                                 mode->type |= M_T_PREFERRED;
 515                                 nv_encoder->native_mode = xf86DuplicateMode(mode);
 516                         }
 517                 }
 518         }
 519
 520         return nv_encoder->native_mode;
 521 }
 522
 523 static DisplayModePtr
 524 nv_output_get_edid_modes(xf86OutputPtr output)
 525 {
 526         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 527         ScrnInfoPtr pScrn = output->scrn;
 528         DisplayModePtr edid_modes;
 529
 530         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_get_edid_modes is called.\n");
 531
 532         if (!(edid_modes = xf86OutputGetEDIDModes(output)))
 533                 return NULL;
 534
 535         if (nv_encoder->dcb->type == OUTPUT_TMDS || nv_encoder->dcb->type == OUTPUT_LVDS)
 536                 if (!get_native_mode_from_edid(output, edid_modes))
 537                         return NULL;
 538
 539         if (nv_encoder->dcb->type == OUTPUT_LVDS) {
 540                 static bool dual_link_correction_done = false;
 541
 542                 if (!dual_link_correction_done) {
 543                         parse_lvds_manufacturer_table(pScrn, &NVPTR(pScrn)->VBIOS, nv_encoder->native_mode->Clock);
 544                         dual_link_correction_done = true;
 545                 }
 546         }
 547
 548         return edid_modes;
 549 }
 550
 551 static void
 552 nv_output_destroy (xf86OutputPtr output)
 553 {
 554         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 555         struct nouveau_encoder *nv_encoder;
 556         ScrnInfoPtr pScrn = output->scrn;
 557         NVPtr pNv = NVPTR(output->scrn);
 558         int i;
 559
 560         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_destroy is called.\n");
 561
 562         if (!nv_connector)
 563                 return;
 564
 565         if (nv_connector->mon)
 566                 xfree(nv_connector->mon);
 567         FOR_EACH_ENCODER_IN_CONNECTOR(i, nv_connector, nv_encoder)
 568                 if (nv_encoder->native_mode)
 569                         xfree(nv_encoder->native_mode);
 570         xfree(nv_connector);
 571 }
 572
 573 static void nv_digital_output_prepare_sel_clk(NVPtr pNv, struct nouveau_encoder *nv_encoder, int head)
 574 {
 575         NVRegPtr state = &pNv->ModeReg;
 576         uint32_t bits1618 = nv_encoder->dcb->or & OUTPUT_A ? 0x10000 : 0x40000;
 577
 578         if (nv_encoder->dcb->location != LOC_ON_CHIP)
 579                 return;
 580
 581         /* SEL_CLK is only used on the primary ramdac
 582          * It toggles spread spectrum PLL output and sets the bindings of PLLs
 583          * to heads on digital outputs
 584          */
 585         if (head)
 586                 state->sel_clk |= bits1618;
 587         else
 588                 state->sel_clk &= ~bits1618;
 589
 590         /* nv30:
 591          *      bit 0           NVClk spread spectrum on/off
 592          *      bit 2           MemClk spread spectrum on/off
 593          *      bit 4           PixClk1 spread spectrum on/off toggle
 594          *      bit 6           PixClk2 spread spectrum on/off toggle
 595          *
 596          * nv40 (observations from bios behaviour and mmio traces):
 597          *      bits 4&6        as for nv30
 598          *      bits 5&7        head dependent as for bits 4&6, but do not appear with 4&6;
 599          *                      maybe a different spread mode
 600          *      bits 8&10       seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
 601          *      The logic behind turning spread spectrum on/off in the first place,
 602          *      and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
 603          *      entry has the necessary info)
 604          */
 605         if (nv_encoder->dcb->type == OUTPUT_LVDS && pNv->SavedReg.sel_clk & 0xf0) {
 606                 int shift = (pNv->SavedReg.sel_clk & 0x50) ? 0 : 1;
 607
 608                 state->sel_clk &= ~0xf0;
 609                 state->sel_clk |= (head ? 0x40 : 0x10) << shift;
 610         }
 611 }
 612
 613 static void
 614 nv_output_prepare(xf86OutputPtr output)
 615 {
 616         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 617         ScrnInfoPtr pScrn = output->scrn;
 618         NVPtr pNv = NVPTR(output->scrn);
 619         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(output->crtc);
 620         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 621
 622         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_prepare is called.\n");
 623
 624         output->funcs->dpms(output, DPMSModeOff);
 625
 626         /* calculate some output specific CRTC regs now, so that they can be written in nv_crtc_set_mode */
 627         if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS)
 628                 nv_digital_output_prepare_sel_clk(pNv, nv_encoder, nv_crtc->head);
 629
 630         /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f etc.) which we don't alter */
 631         if (!(regp->CRTC[NV_VGA_CRTCX_LCD] & 0x44)) {
 632                 if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS) {
 633                         regp->CRTC[NV_VGA_CRTCX_LCD] &= ~0x30;
 634                         regp->CRTC[NV_VGA_CRTCX_LCD] |= 0x3;
 635                         if (nv_crtc->head == 0)
 636                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= 0x8;
 637                         else
 638                                 regp->CRTC[NV_VGA_CRTCX_LCD] &= ~0x8;
 639                         if (nv_encoder->dcb->location != LOC_ON_CHIP)
 640                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (nv_encoder->dcb->or << 4) & 0x30;
 641                 } else
 642                         regp->CRTC[NV_VGA_CRTCX_LCD] = 0;
 643         }
 644 }
 645
 646 static void
 647 nv_output_commit(xf86OutputPtr output)
 648 {
 649         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 650         ScrnInfoPtr pScrn = output->scrn;
 651         xf86CrtcPtr crtc = output->crtc;
 652         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 653
 654         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_commit is called.\n");
 655
 656         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Output %s is running on CRTC %d using output %c\n", output->name, nv_crtc->head, '@' + ffs(nv_encoder->dcb->or));
 657
 658         output->funcs->dpms(output, DPMSModeOn);
 659 }
 660
 661 /*
 662  * Several scaling modes exist, let the user choose.
 663  */
 664 #define SCALING_MODE_NAME "SCALING_MODE"
 665 static const struct {
 666         char *name;
 667         enum scaling_modes mode;
 668 } scaling_mode[] = {
 669         { "panel", SCALE_PANEL },
 670         { "fullscreen", SCALE_FULLSCREEN },
 671         { "aspect", SCALE_ASPECT },
 672         { "noscale", SCALE_NOSCALE },
 673         { NULL, SCALE_INVALID}
 674 };
 675 static Atom scaling_mode_atom;
 676
 677 #define DITHERING_MODE_NAME "DITHERING"
 678 static Atom dithering_atom;
 679
 680 static void
 681 nv_output_create_resources(xf86OutputPtr output)
 682 {
 683         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 684         ScrnInfoPtr pScrn = output->scrn;
 685         INT32 dithering_range[2] = { 0, 1 };
 686         int error, i;
 687
 688         /* no properties for vga */
 689         if (nv_encoder->dcb->type == OUTPUT_ANALOG)
 690                 return;
 691
 692         /*
 693          * Setup scaling mode property.
 694          */
 695         scaling_mode_atom = MakeAtom(SCALING_MODE_NAME, sizeof(SCALING_MODE_NAME) - 1, TRUE);
 696
 697         error = RRConfigureOutputProperty(output->randr_output,
 698                                         scaling_mode_atom, TRUE, FALSE, FALSE,
 699                                         0, NULL);
 700
 701         if (error != 0) {
 702                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 703                         "RRConfigureOutputProperty error, %d\n", error);
 704         }
 705
 706         char *existing_scale_name = NULL;
 707         for (i = 0; scaling_mode[i].name; i++)
 708                 if (scaling_mode[i].mode == nv_encoder->scaling_mode)
 709                         existing_scale_name = scaling_mode[i].name;
 710
 711         error = RRChangeOutputProperty(output->randr_output, scaling_mode_atom,
 712                                         XA_STRING, 8, PropModeReplace,
 713                                         strlen(existing_scale_name),
 714                                         existing_scale_name, FALSE, TRUE);
 715
 716         if (error != 0) {
 717                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 718                         "Failed to set scaling mode, %d\n", error);
 719         }
 720
 721         /*
 722          * Setup dithering property.
 723          */
 724         dithering_atom = MakeAtom(DITHERING_MODE_NAME, sizeof(DITHERING_MODE_NAME) - 1, TRUE);
 725
 726         error = RRConfigureOutputProperty(output->randr_output,
 727                                         dithering_atom, TRUE, TRUE, FALSE,
 728                                         2, dithering_range);
 729
 730         if (error != 0) {
 731                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 732                         "RRConfigureOutputProperty error, %d\n", error);
 733         }
 734
 735         /* promote bool into int32 to make RandR DIX and big endian happy */
 736         int32_t existing_dither = nv_encoder->dithering;
 737         error = RRChangeOutputProperty(output->randr_output, dithering_atom,
 738                                         XA_INTEGER, 32, PropModeReplace, 1,
 739                                         &existing_dither, FALSE, TRUE);
 740
 741         if (error != 0) {
 742                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 743                         "Failed to set dithering mode, %d\n", error);
 744         }
 745 }
 746
 747 static Bool
 748 nv_output_set_property(xf86OutputPtr output, Atom property,
 749                                 RRPropertyValuePtr value)
 750 {
 751         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 752
 753         if (property == scaling_mode_atom) {
 754                 int32_t ret;
 755                 char *name = NULL;
 756
 757                 if (value->type != XA_STRING || value->format != 8)
 758                         return FALSE;
 759
 760                 name = (char *) value->data;
 761
 762                 /* Match a string to a scaling mode */
 763                 ret = nv_scaling_mode_lookup(name, value->size);
 764                 if (ret == SCALE_INVALID)
 765                         return FALSE;
 766
 767                 /* LVDS must always use gpu scaling. */
 768                 if (ret == SCALE_PANEL && nv_encoder->dcb->type == OUTPUT_LVDS)
 769                         return FALSE;
 770
 771                 nv_encoder->scaling_mode = ret;
 772         } else if (property == dithering_atom) {
 773                 if (value->type != XA_INTEGER || value->format != 32)
 774                         return FALSE;
 775
 776                 int32_t val = *(int32_t *) value->data;
 777
 778                 if (val < 0 || val > 1)
 779                         return FALSE;
 780
 781                 nv_encoder->dithering = val;
 782         }
 783
 784         return TRUE;
 785 }
 786
 787 static const xf86OutputFuncsRec nv_output_funcs = {
 788         .dpms = nv_output_dpms,
 789         .mode_valid = nv_output_mode_valid,
 790         .mode_fixup = nv_output_mode_fixup,
 791         .mode_set = nv_output_mode_set,
 792         .detect = nv_output_detect,
 793         .get_modes = nv_output_get_edid_modes,
 794         .destroy = nv_output_destroy,
 795         .prepare = nv_output_prepare,
 796         .commit = nv_output_commit,
 797         .create_resources = nv_output_create_resources,
 798         .set_property = nv_output_set_property,
 799 };
 800
 801 static DisplayModePtr
 802 nv_lvds_output_get_modes(xf86OutputPtr output)
 803 {
 804         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 805         ScrnInfoPtr pScrn = output->scrn;
 806         NVPtr pNv = NVPTR(pScrn);
 807         DisplayModePtr modes;
 808
 809         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_lvds_output_get_modes is called.\n");
 810
 811         if ((modes = nv_output_get_edid_modes(output)))
 812                 return modes;
 813
 814         if (!nv_encoder->dcb->lvdsconf.use_straps_for_mode || pNv->VBIOS.fp.native_mode == NULL)
 815                 return NULL;
 816
 817         if (nv_encoder->native_mode)
 818                 xfree(nv_encoder->native_mode);
 819         nv_encoder->native_mode = xf86DuplicateMode(pNv->VBIOS.fp.native_mode);
 820
 821         return xf86DuplicateMode(pNv->VBIOS.fp.native_mode);
 822 }
 823
 824 static const xf86OutputFuncsRec nv_lvds_output_funcs = {
 825         .dpms = nv_output_dpms,
 826         .mode_valid = nv_output_mode_valid,
 827         .mode_fixup = nv_output_mode_fixup,
 828         .mode_set = nv_output_mode_set,
 829         .detect = nv_output_detect,
 830         .get_modes = nv_lvds_output_get_modes,
 831         .destroy = nv_output_destroy,
 832         .prepare = nv_output_prepare,
 833         .commit = nv_output_commit,
 834         .create_resources = nv_output_create_resources,
 835         .set_property = nv_output_set_property,
 836 };
 837
 838 static void
 839 nv_add_output(ScrnInfoPtr pScrn, struct dcb_entry *dcbent, const xf86OutputFuncsRec *output_funcs, char *outputname)
 840 {
 841         NVPtr pNv = NVPTR(pScrn);
 842         xf86OutputPtr output;
 843         struct nouveau_connector *nv_connector;
 844         struct nouveau_encoder *nv_encoder = &pNv->encoders[dcbent->index];
 845
 846         if (!(output = xf86OutputCreate(pScrn, output_funcs, outputname)))
 847                 return;
 848         if (!(nv_connector = xnfcalloc(sizeof (struct nouveau_connector), 1)))
 849                 return;
 850
 851         output->driver_private = nv_connector;
 852
 853         if (dcbent->i2c_index < 0xf && pNv->pI2CBus[dcbent->i2c_index] == NULL)
 854                 NV_I2CInit(pScrn, &pNv->pI2CBus[dcbent->i2c_index], pNv->dcb_table.i2c_read[dcbent->i2c_index], xstrdup(outputname));
 855         nv_connector->pDDCBus = pNv->pI2CBus[dcbent->i2c_index];
 856         nv_connector->possible_encoders = 1 << dcbent->index;
 857         nv_connector->nv_encoder = nv_encoder;
 858         nv_encoder->dcb = dcbent;
 859         nv_encoder->last_dpms = NV_DPMS_CLEARED;
 860
 861         nv_encoder->dithering = (pNv->FPDither || (nv_encoder->dcb->type == OUTPUT_LVDS && !pNv->VBIOS.fp.if_is_24bit));
 862         if (pNv->fpScaler) /* GPU Scaling */
 863                 nv_encoder->scaling_mode = SCALE_ASPECT;
 864         else if (nv_encoder->dcb->type == OUTPUT_LVDS)
 865                 nv_encoder->scaling_mode = SCALE_NOSCALE;
 866         else
 867                 nv_encoder->scaling_mode = SCALE_PANEL;
 868         if (xf86GetOptValString(pNv->Options, OPTION_SCALING_MODE)) {
 869                 nv_encoder->scaling_mode = nv_scaling_mode_lookup(xf86GetOptValString(pNv->Options, OPTION_SCALING_MODE), -1);
 870                 if (nv_encoder->scaling_mode == SCALE_INVALID)
 871                         nv_encoder->scaling_mode = SCALE_ASPECT; /* default */
 872         }
 873
 874         output->possible_crtcs = dcbent->heads;
 875         if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS) {
 876                 output->doubleScanAllowed = false;
 877                 output->interlaceAllowed = false;
 878         } else {
 879                 output->doubleScanAllowed = true;
 880                 if (pNv->Architecture == NV_ARCH_20 ||
 881                    (pNv->Architecture == NV_ARCH_10 &&
 882                     (pNv->Chipset & 0x0ff0) != CHIPSET_NV10 &&
 883                     (pNv->Chipset & 0x0ff0) != CHIPSET_NV15))
 884                         /* HW is broken */
 885                         output->interlaceAllowed = false;
 886                 else
 887                         output->interlaceAllowed = true;
 888         }
 889 }
 890
 891 void NvSetupOutputs(ScrnInfoPtr pScrn)
 892 {
 893         NVPtr pNv = NVPTR(pScrn);
 894         uint16_t connectors[0x10];
 895         struct dcb_entry *dcbent;
 896         int i, vga_count = 0, dvia_count = 0, dvid_count = 0, lvds_count = 0;
 897
 898         if (!(pNv->encoders = xnfcalloc(pNv->dcb_table.entries, sizeof (struct nouveau_encoder))))
 899                 return;
 900
 901         memset(pNv->pI2CBus, 0, sizeof(pNv->pI2CBus));
 902         memset(connectors, 0, sizeof (connectors));
 903
 904         for (i = 0; i < pNv->dcb_table.entries; i++) {
 905                 dcbent = &pNv->dcb_table.entry[i];
 906
 907                 if (dcbent->type == OUTPUT_TV)
 908                         continue;
 909                 if (dcbent->type > 3) {
 910                         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DCB type %d not known\n", dcbent->type);
 911                         continue;
 912                 }
 913
 914                 connectors[dcbent->i2c_index] |= 1 << i;
 915         }
 916
 917         for (i = 0; i < pNv->dcb_table.entries; i++) {
 918                 int i2c_index = pNv->dcb_table.entry[i].i2c_index;
 919                 uint16_t encoders = connectors[i2c_index];
 920                 char outputname[20];
 921                 xf86OutputFuncsRec const *funcs = &nv_output_funcs;
 922
 923                 if (!encoders)
 924                         continue;
 925
 926                 dcbent = &pNv->dcb_table.entry[i];
 927
 928                 switch (dcbent->type) {
 929                 case OUTPUT_ANALOG:
 930                         if (!MULTIPLE_ENCODERS(encoders))
 931                                 sprintf(outputname, "VGA-%d", vga_count++);
 932                         else
 933                                 sprintf(outputname, "DVI-A-%d", dvia_count++);
 934                         break;
 935                 case OUTPUT_TMDS:
 936                         sprintf(outputname, "DVI-D-%d", dvid_count++);
 937                         break;
 938                 case OUTPUT_LVDS:
 939                         sprintf(outputname, "LVDS-%d", lvds_count++);
 940                         funcs = &nv_lvds_output_funcs;
 941                         break;
 942                 }
 943
 944                 nv_add_output(pScrn, dcbent, funcs, outputname);
 945         }
 946 }