2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2008 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "nv_include.h"
28 #if defined(__FreeBSD__) || defined(__NetBSD__)
29 #define bswap_16 bswap16
30 #define bswap_32 bswap32
36 /* FIXME: put these somewhere */
37 #define SEQ_INDEX VGA_SEQ_INDEX
38 #define NV_VGA_CRTCX_OWNER_HEADA 0x0
39 #define NV_VGA_CRTCX_OWNER_HEADB 0x3
40 #define FEATURE_MOBILE 0x10
44 static int crtchead = 0;
46 /* this will need remembering across a suspend */
47 static uint32_t saved_nv_pfb_cfg0;
54 static uint16_t le16_to_cpu(const uint16_t x)
56 #if X_BYTE_ORDER == X_BIG_ENDIAN
63 static uint32_t le32_to_cpu(const uint32_t x)
65 #if X_BYTE_ORDER == X_BIG_ENDIAN
72 static bool nv_cksum(const uint8_t *data, unsigned int length)
74 /* there's a few checksums in the BIOS, so here's a generic checking function */
78 for (i = 0; i < length; i++)
87 static int score_vbios(ScrnInfoPtr pScrn, const uint8_t *data)
89 /* check for BIOS signature */
90 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
91 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
92 "... BIOS signature not found\n");
96 if (nv_cksum(data, data[2] * 512)) {
97 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
98 "... BIOS checksum invalid\n");
99 /* probably ought to set a do_not_execute flag for table parsing here,
100 * assuming most BIOSen are valid */
103 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "... appears to be valid\n");
108 static void load_vbios_prom(NVPtr pNv, uint8_t *data)
112 /* enable ROM access */
113 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED);
114 for (i = 0; i < NV_PROM_SIZE; i++) {
115 /* according to nvclock, we need that to work around a 6600GT/6800LE bug */
116 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
117 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
118 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
119 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
120 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
122 /* disable ROM access */
123 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
126 static void load_vbios_pramin(NVPtr pNv, uint8_t *data)
128 uint32_t old_bar0_pramin = 0;
131 if (pNv->Architecture >= NV_ARCH_50) {
132 uint32_t vbios_vram = (NV_RD32(pNv->REGS, 0x619f04) & ~0xff) << 8;
135 vbios_vram = (NV_RD32(pNv->REGS, 0x1700) << 16) + 0xf0000;
137 old_bar0_pramin = NV_RD32(pNv->REGS, 0x1700);
138 NV_WR32(pNv->REGS, 0x1700, vbios_vram >> 16);
141 for (i = 0; i < NV_PROM_SIZE; i++)
142 data[i] = NV_RD08(pNv->REGS, NV_PRAMIN_OFFSET + i);
144 if (pNv->Architecture >= NV_ARCH_50)
145 NV_WR32(pNv->REGS, 0x1700, old_bar0_pramin);
148 static void load_vbios_pci(NVPtr pNv, uint8_t *data)
150 #if XSERVER_LIBPCIACCESS
151 pci_device_read_rom(pNv->PciInfo, data);
153 xf86ReadPciBIOS(0, pNv->PciTag, 0, data, NV_PROM_SIZE);
157 static bool NVShadowVBIOS(ScrnInfoPtr pScrn, uint8_t *data)
159 NVPtr pNv = NVPTR(pScrn);
162 void (*loadbios)(NVPtr, uint8_t *);
165 { "PROM", load_vbios_prom },
166 { "PRAMIN", load_vbios_pramin },
168 { "PCI ROM", load_vbios_pci }
173 for (i = 0; i < sizeof(method) / sizeof(struct methods); i++) {
174 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
175 "Attempting to load BIOS image from %s\n", method[i].desc);
176 method[i].loadbios(pNv, data);
177 if ((method[i].score = score_vbios(pScrn, data)) == 2)
181 for (i = 0; i < sizeof(method) / sizeof(struct methods); i++)
182 if (method[i].score == 1) {
183 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
184 "Using BIOS image from %s\n", method[i].desc);
185 method[i].loadbios(pNv, data);
197 int length_multiplier;
198 bool (*handler)(ScrnInfoPtr pScrn, bios_t *, uint16_t, init_exec_t *);
207 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec);
209 #define MACRO_INDEX_SIZE 2
211 #define CONDITION_SIZE 12
212 #define IO_FLAG_CONDITION_SIZE 9
213 #define MEM_INIT_SIZE 66
215 static void still_alive(void)
221 static int nv_valid_reg(ScrnInfoPtr pScrn, uint32_t reg)
223 NVPtr pNv = NVPTR(pScrn);
225 /* C51 has misaligned regs on purpose. Marvellous */
226 if ((reg & 0x3 && pNv->VBIOS.chip_version != 0x51) ||
227 (reg & 0x2 && pNv->VBIOS.chip_version == 0x51)) {
228 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
229 "========== misaligned reg 0x%08X ==========\n", reg);
233 #define WITHIN(x,y,z) ((x>=y)&&(x<=y+z))
234 if (WITHIN(reg,NV_PMC_OFFSET,NV_PMC_SIZE))
236 if (WITHIN(reg,NV_PBUS_OFFSET,NV_PBUS_SIZE))
238 if (WITHIN(reg,NV_PFIFO_OFFSET,NV_PFIFO_SIZE))
240 if (pNv->VBIOS.chip_version >= 0x80 && WITHIN(reg, NV50_DISPLAY_OFFSET, NV50_DISPLAY_SIZE))
242 /* maybe a little large, but it will do for the moment. */
243 if (pNv->VBIOS.chip_version >= 0x80 && WITHIN(reg, 0x1000, 0xEFFF))
245 if (pNv->VBIOS.chip_version >= 0x30 && WITHIN(reg,0x4000,0x600))
247 if (pNv->VBIOS.chip_version >= 0x40 && WITHIN(reg,0xc000,0x48))
249 if (pNv->VBIOS.chip_version >= 0x17 && reg == 0x0000d204)
251 if (pNv->VBIOS.chip_version >= 0x40) {
252 if (reg == 0x00011014 || reg == 0x00020328)
254 if (WITHIN(reg,0x88000,NV_PBUS_SIZE)) /* new PBUS */
257 if (WITHIN(reg,NV_PFB_OFFSET,NV_PFB_SIZE))
259 if (WITHIN(reg,NV_PEXTDEV_OFFSET,NV_PEXTDEV_SIZE))
261 if (WITHIN(reg,NV_PCRTC0_OFFSET,NV_PCRTC0_SIZE * 2))
263 if (WITHIN(reg,NV_PRAMDAC0_OFFSET,NV_PRAMDAC0_SIZE * 2))
265 if (pNv->VBIOS.chip_version >= 0x17 && reg == 0x0070fff0)
267 if (pNv->VBIOS.chip_version == 0x51 && WITHIN(reg,NV_PRAMIN_OFFSET,NV_PRAMIN_SIZE))
271 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
272 "========== unknown reg 0x%08X ==========\n", reg);
277 static bool nv_valid_idx_port(ScrnInfoPtr pScrn, uint16_t port)
279 /* if adding more ports here, the read/write functions below will need
280 * updating so that the correct mmio range (PCIO, PDIO, PVIO) is used
281 * for the port in question
283 if (port == CRTC_INDEX_COLOR)
285 if (port == SEQ_INDEX)
288 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
289 "========== unknown indexed io port 0x%04X ==========\n", port);
294 static bool nv_valid_port(ScrnInfoPtr pScrn, uint16_t port)
296 /* if adding more ports here, the read/write functions below will need
297 * updating so that the correct mmio range (PCIO, PDIO, PVIO) is used
298 * for the port in question
300 if (port == VGA_ENABLE)
303 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
304 "========== unknown io port 0x%04X ==========\n", port);
309 static uint32_t nv32_rd(ScrnInfoPtr pScrn, uint32_t reg)
311 NVPtr pNv = NVPTR(pScrn);
314 if (!nv_valid_reg(pScrn, reg))
317 /* C51 sometimes uses regs with bit0 set in the address. For these
318 * cases there should exist a translation in a BIOS table to an IO
319 * port address which the BIOS uses for accessing the reg
321 * These only seem to appear for the power control regs to a flat panel
322 * and in C51 mmio traces the normal regs for 0x1308 and 0x1310 are
323 * used - hence the mask below. An S3 suspend-resume mmio trace from a
324 * C51 will be required to see if this is true for the power microcode
325 * in 0x14.., or whether the direct IO port access method is needed
330 data = NV_RD32(pNv->REGS, reg);
333 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
334 " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
339 static void nv32_wr(ScrnInfoPtr pScrn, uint32_t reg, uint32_t data)
341 NVPtr pNv = NVPTR(pScrn);
343 if (!nv_valid_reg(pScrn, reg))
346 /* see note in nv32_rd */
353 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
354 " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
356 if (pNv->VBIOS.execute) {
358 NV_WR32(pNv->REGS, reg, data);
362 static uint8_t nv_idx_port_rd(ScrnInfoPtr pScrn, uint16_t port, uint8_t index)
364 NVPtr pNv = NVPTR(pScrn);
367 if (!nv_valid_idx_port(pScrn, port))
370 if (port == SEQ_INDEX)
371 data = NVReadVgaSeq(pNv, crtchead, index);
372 else /* assume CRTC_INDEX_COLOR */
373 data = NVReadVgaCrtc(pNv, crtchead, index);
376 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
377 " Indexed IO read: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
378 port, index, crtchead, data);
383 static void nv_idx_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t index, uint8_t data)
385 NVPtr pNv = NVPTR(pScrn);
387 if (!nv_valid_idx_port(pScrn, port))
390 /* The current head is maintained in a file scope variable crtchead.
391 * We trap changes to CRTCX_OWNER and update the head variable
392 * and hence the register set written.
393 * As CRTCX_OWNER only exists on CRTC0, we update crtchead to head0
394 * in advance of the write, and to head1 after the write
396 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data != NV_VGA_CRTCX_OWNER_HEADB)
400 nv_idx_port_rd(pScrn, port, index);
402 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
403 " Indexed IO write: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
404 port, index, crtchead, data);
406 if (pNv->VBIOS.execute) {
408 if (port == SEQ_INDEX)
409 NVWriteVgaSeq(pNv, crtchead, index, data);
410 else /* assume CRTC_INDEX_COLOR */
411 NVWriteVgaCrtc(pNv, crtchead, index, data);
414 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data == NV_VGA_CRTCX_OWNER_HEADB)
418 static uint8_t nv_port_rd(ScrnInfoPtr pScrn, uint16_t port)
420 NVPtr pNv = NVPTR(pScrn);
423 if (!nv_valid_port(pScrn, port))
426 data = NVReadPVIO(pNv, crtchead, port);
429 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
430 " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
431 port, crtchead, data);
436 static void nv_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t data)
438 NVPtr pNv = NVPTR(pScrn);
440 if (!nv_valid_port(pScrn, port))
444 nv_port_rd(pScrn, port);
446 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
447 " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
448 port, crtchead, data);
450 if (pNv->VBIOS.execute) {
452 NVWritePVIO(pNv, crtchead, port, data);
456 #define ACCESS_UNLOCK 0
457 #define ACCESS_LOCK 1
458 static void crtc_access(ScrnInfoPtr pScrn, bool lock)
460 NVPtr pNv = NVPTR(pScrn);
463 NVSetOwner(pScrn, 0);
464 NVLockVgaCrtc(pNv, 0, lock);
466 NVSetOwner(pScrn, 1);
467 NVLockVgaCrtc(pNv, 1, lock);
468 NVSetOwner(pScrn, crtchead);
472 static bool io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, uint8_t cond)
474 /* The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
475 * for the CRTC index; 1 byte for the mask to apply to the value
476 * retrieved from the CRTC; 1 byte for the shift right to apply to the
477 * masked CRTC value; 2 bytes for the offset to the flag array, to
478 * which the shifted value is added; 1 byte for the mask applied to the
479 * value read from the flag array; and 1 byte for the value to compare
480 * against the masked byte from the flag table.
483 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
484 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[condptr])));
485 uint8_t crtcindex = bios->data[condptr + 2];
486 uint8_t mask = bios->data[condptr + 3];
487 uint8_t shift = bios->data[condptr + 4];
488 uint16_t flagarray = le16_to_cpu(*((uint16_t *)(&bios->data[condptr + 5])));
489 uint8_t flagarraymask = bios->data[condptr + 7];
490 uint8_t cmpval = bios->data[condptr + 8];
494 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
495 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, Cmpval: 0x%02X\n",
496 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
498 data = nv_idx_port_rd(pScrn, crtcport, crtcindex);
500 data = bios->data[flagarray + ((data & mask) >> shift)];
501 data &= flagarraymask;
504 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
505 "0x%04X: Checking if 0x%02X equals 0x%02X\n",
506 offset, data, cmpval);
514 int getMNP_single(ScrnInfoPtr pScrn, struct pll_lims *pll_lim, int clk, int *bestNM, int *bestlog2P)
516 /* Find M, N and P for a single stage PLL
518 * Note that some bioses (NV3x) have lookup tables of precomputed MNP
519 * values, but we're too lazy to use those atm
521 * "clk" parameter in kHz
522 * returns calculated clock
525 bios_t *bios = &NVPTR(pScrn)->VBIOS;
526 int minvco = pll_lim->vco1.minfreq, maxvco = pll_lim->vco1.maxfreq;
527 int minM = pll_lim->vco1.min_m, maxM = pll_lim->vco1.max_m;
528 int minN = pll_lim->vco1.min_n, maxN = pll_lim->vco1.max_n;
529 int minU = pll_lim->vco1.min_inputfreq, maxU = pll_lim->vco1.max_inputfreq;
531 int crystal = pll_lim->refclk;
534 int delta, bestdelta = INT_MAX;
537 /* this division verified for nv20, nv18, nv28 (Haiku), and nv34 */
538 /* possibly correlated with introduction of 27MHz crystal */
539 if (bios->chip_version <= 0x16 || bios->chip_version == 0x20) {
545 } else if (bios->chip_version < 0x40) {
553 } else /* nv4x may be subject to the nv17+ limits, but assume not for now */
556 if ((clk << maxlog2P) < minvco) {
557 minvco = clk << maxlog2P;
560 if (clk + clk/200 > maxvco) /* +0.5% */
561 maxvco = clk + clk/200;
563 /* NV34 goes maxlog2P->0, NV20 goes 0->maxlog2P */
564 for (log2P = 0; log2P <= maxlog2P; log2P++) {
573 for (M = minM; M <= maxM; M++) {
574 if (crystal/M < minU)
576 if (crystal/M > maxU)
579 /* add crystal/2 to round better */
580 N = (clkP * M + crystal/2) / crystal;
587 /* more rounding additions */
588 calcclk = ((N * crystal + P/2) / P + M/2) / M;
589 delta = abs(calcclk - clk);
590 /* we do an exhaustive search rather than terminating
591 * on an optimality condition...
593 if (delta < bestdelta) {
596 *bestNM = N << 8 | M;
598 if (delta == 0) /* except this one */
607 int getMNP_double(ScrnInfoPtr pScrn, struct pll_lims *pll_lim, int clk, int *bestNM1, int *bestNM2, int *bestlog2P)
609 /* Find M, N and P for a two stage PLL
611 * Note that some bioses (NV30+) have lookup tables of precomputed MNP
612 * values, but we're too lazy to use those atm
614 * "clk" parameter in kHz
615 * returns calculated clock
618 int minvco1 = pll_lim->vco1.minfreq, maxvco1 = pll_lim->vco1.maxfreq;
619 int minvco2 = pll_lim->vco2.minfreq, maxvco2 = pll_lim->vco2.maxfreq;
620 int minU1 = pll_lim->vco1.min_inputfreq, minU2 = pll_lim->vco2.min_inputfreq;
621 int maxU1 = pll_lim->vco1.max_inputfreq, maxU2 = pll_lim->vco2.max_inputfreq;
622 int minM1 = pll_lim->vco1.min_m, maxM1 = pll_lim->vco1.max_m;
623 int minN1 = pll_lim->vco1.min_n, maxN1 = pll_lim->vco1.max_n;
624 int minM2 = pll_lim->vco2.min_m, maxM2 = pll_lim->vco2.max_m;
625 int minN2 = pll_lim->vco2.min_n, maxN2 = pll_lim->vco2.max_n;
626 int crystal = pll_lim->refclk;
627 bool fixedgain2 = (minM2 == maxM2 && minN2 == maxN2);
628 int M1, N1, M2, N2, log2P;
629 int clkP, calcclk1, calcclk2, calcclkout;
630 int delta, bestdelta = INT_MAX;
633 int vco2 = (maxvco2 - maxvco2/200) / 2;
634 for (log2P = 0; clk && log2P < 6 && clk <= (vco2 >> log2P); log2P++) /* log2P is maximum of 6 */
638 if (maxvco2 < clk + clk/200) /* +0.5% */
639 maxvco2 = clk + clk/200;
641 for (M1 = minM1; M1 <= maxM1; M1++) {
642 if (crystal/M1 < minU1)
644 if (crystal/M1 > maxU1)
647 for (N1 = minN1; N1 <= maxN1; N1++) {
648 calcclk1 = crystal * N1 / M1;
649 if (calcclk1 < minvco1)
651 if (calcclk1 > maxvco1)
654 for (M2 = minM2; M2 <= maxM2; M2++) {
655 if (calcclk1/M2 < minU2)
657 if (calcclk1/M2 > maxU2)
660 /* add calcclk1/2 to round better */
661 N2 = (clkP * M2 + calcclk1/2) / calcclk1;
668 if (NVPTR(pScrn)->VBIOS.chip_version < 0x60)
669 if (N2/M2 < 4 || N2/M2 > 10)
672 calcclk2 = calcclk1 * N2 / M2;
673 if (calcclk2 < minvco2)
675 if (calcclk2 > maxvco2)
680 calcclkout = calcclk2 >> log2P;
681 delta = abs(calcclkout - clk);
682 /* we do an exhaustive search rather than terminating
683 * on an optimality condition...
685 if (delta < bestdelta) {
687 bestclk = calcclkout;
688 *bestNM1 = N1 << 8 | M1;
689 *bestNM2 = N2 << 8 | M2;
691 if (delta == 0) /* except this one */
701 static void setPLL_single(ScrnInfoPtr pScrn, uint32_t reg, int NM, int log2P)
703 bios_t *bios = &NVPTR(pScrn)->VBIOS;
704 uint32_t oldpll = nv32_rd(pScrn, reg);
705 uint32_t pll = (oldpll & 0xfff80000) | log2P << 16 | NM;
706 uint32_t saved_powerctrl_1 = 0;
707 int shift_powerctrl_1 = -4;
710 return; /* already set */
712 /* nv18 doesn't change POWERCTRL_1 for VPLL*; does gf4 need special-casing? */
713 if (bios->chip_version >= 0x17 && bios->chip_version != 0x20) {
715 case NV_RAMDAC_VPLL2:
716 shift_powerctrl_1 += 4;
718 shift_powerctrl_1 += 4;
720 shift_powerctrl_1 += 4;
721 case NV_RAMDAC_NVPLL:
722 shift_powerctrl_1 += 4;
725 if (shift_powerctrl_1 >= 0) {
726 saved_powerctrl_1 = nv32_rd(pScrn, NV_PBUS_POWERCTRL_1);
727 nv32_wr(pScrn, NV_PBUS_POWERCTRL_1, (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 1 << shift_powerctrl_1);
732 nv32_wr(pScrn, reg, (oldpll & 0xffff0000) | NM);
738 /* then write P as well */
739 nv32_wr(pScrn, reg, pll);
741 if (shift_powerctrl_1 >= 0)
742 nv32_wr(pScrn, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
745 static void setPLL_double_highregs(ScrnInfoPtr pScrn, uint32_t reg1, int NM1, int NM2, int log2P)
747 bios_t *bios = &NVPTR(pScrn)->VBIOS;
748 bool nv3035 = bios->chip_version == 0x30 || bios->chip_version == 0x35;
749 uint32_t reg2 = reg1 + ((reg1 == NV_RAMDAC_VPLL2) ? 0x5c : 0x70);
750 uint32_t oldpll1 = nv32_rd(pScrn, reg1), oldpll2 = !nv3035 ? nv32_rd(pScrn, reg2) : 0;
751 uint32_t pll1 = (oldpll1 & 0xfff80000) | log2P << 16 | NM1;
752 uint32_t pll2 = !nv3035 ? (oldpll2 & 0x7fff0000) | 1 << 31 | NM2 : 0;
753 uint32_t saved_powerctrl_1 = 0, savedc040 = 0, maskc040 = ~0;
754 int shift_powerctrl_1 = -1;
755 bool single_stage = !NM2 || (((NM2 >> 8) & 0xff) == (NM2 & 0xff));
758 pll1 = (pll1 & 0xfcc7ffff) | (NM2 & (0x18 << 8)) << 13 | (NM2 & (0x7 << 8)) << 11 | 8 << 4 | (NM2 & 7) << 4;
760 if (oldpll1 == pll1 && oldpll2 == pll2)
761 return; /* already set */
763 if (reg1 == NV_RAMDAC_NVPLL) {
764 shift_powerctrl_1 = 0;
765 maskc040 = ~(3 << 20);
767 if (reg1 == NV_RAMDAC_MPLL) {
768 shift_powerctrl_1 = 4;
769 maskc040 = ~(3 << 22);
771 if (shift_powerctrl_1 >= 0) {
772 saved_powerctrl_1 = nv32_rd(pScrn, NV_PBUS_POWERCTRL_1);
773 nv32_wr(pScrn, NV_PBUS_POWERCTRL_1, (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 1 << shift_powerctrl_1);
776 if (bios->chip_version >= 0x40) {
777 savedc040 = nv32_rd(pScrn, 0xc040);
778 nv32_wr(pScrn, 0xc040, savedc040 & maskc040);
781 if (reg1 == NV_RAMDAC_VPLL)
782 nv32_wr(pScrn, NV_RAMDAC_580, nv32_rd(pScrn, NV_RAMDAC_580) & ~NV_RAMDAC_580_VPLL1_ACTIVE);
783 if (reg1 == NV_RAMDAC_VPLL2)
784 nv32_wr(pScrn, NV_RAMDAC_580, nv32_rd(pScrn, NV_RAMDAC_580) & ~NV_RAMDAC_580_VPLL2_ACTIVE);
786 if (reg1 == NV_RAMDAC_VPLL)
787 nv32_wr(pScrn, NV_RAMDAC_580, nv32_rd(pScrn, NV_RAMDAC_580) | NV_RAMDAC_580_VPLL1_ACTIVE);
788 if (reg1 == NV_RAMDAC_VPLL2)
789 nv32_wr(pScrn, NV_RAMDAC_580, nv32_rd(pScrn, NV_RAMDAC_580) | NV_RAMDAC_580_VPLL2_ACTIVE);
795 nv32_wr(pScrn, reg2, pll2);
796 nv32_wr(pScrn, reg1, pll1);
798 if (shift_powerctrl_1 >= 0) {
799 nv32_wr(pScrn, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
800 if (bios->chip_version >= 0x40)
801 nv32_wr(pScrn, 0xc040, savedc040);
805 static void setPLL_double_lowregs(ScrnInfoPtr pScrn, uint32_t NMNMreg, int NM1, int NM2, int log2P)
807 /* When setting PLLs, there is a merry game of disabling and enabling
808 * various bits of hardware during the process. This function is a
809 * synthesis of six nv40 traces, nearly each card doing a subtly
810 * different thing. With luck all the necessary bits for each card are
811 * combined herein. Without luck it deviates from each card's formula
812 * so as to not work on any :)
815 uint32_t Preg = NMNMreg - 4;
816 uint32_t oldPval = nv32_rd(pScrn, Preg);
817 uint32_t NMNM = NM2 << 16 | NM1;
818 uint32_t Pval = (oldPval & ((Preg == 0x4020) ? ~(0x11 << 16) : ~(1 << 16))) | 0xc << 28 | log2P << 16;
819 uint32_t saved4600 = 0;
820 /* some cards have different maskc040s */
821 uint32_t maskc040 = ~(3 << 14), savedc040;
822 bool single_stage = !NM2 || (((NM2 >> 8) & 0xff) == (NM2 & 0xff));
824 if (nv32_rd(pScrn, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
830 maskc040 = ~(0xc << 24);
832 if (Preg == 0x4020) {
833 struct pll_lims pll_lim;
836 if (!get_pll_limits(pScrn, Preg, &pll_lim))
839 Pval2 = log2P + pll_lim.log2p_bias;
840 if (Pval2 > pll_lim.max_log2p_bias)
841 Pval2 = pll_lim.max_log2p_bias;
842 Pval |= 1 << 28 | Pval2 << 20;
844 saved4600 = nv32_rd(pScrn, 0x4600);
845 nv32_wr(pScrn, 0x4600, saved4600 | 8 << 28);
848 Pval |= (Preg == 0x4020) ? 1 << 12 : 1 << 8;
850 nv32_wr(pScrn, Preg, oldPval | 1 << 28);
851 nv32_wr(pScrn, Preg, Pval & ~(4 << 28));
852 if (Preg == 0x4020) {
854 nv32_wr(pScrn, 0x4020, Pval & ~(0xc << 28));
855 nv32_wr(pScrn, 0x4038, Pval & ~(0xc << 28));
858 savedc040 = nv32_rd(pScrn, 0xc040);
859 nv32_wr(pScrn, 0xc040, savedc040 & maskc040);
861 nv32_wr(pScrn, NMNMreg, NMNM);
862 if (NMNMreg == 0x4024)
863 nv32_wr(pScrn, 0x403c, NMNM);
865 nv32_wr(pScrn, Preg, Pval);
866 if (Preg == 0x4020) {
868 nv32_wr(pScrn, 0x4020, Pval);
869 nv32_wr(pScrn, 0x4038, Pval);
870 nv32_wr(pScrn, 0x4600, saved4600);
873 nv32_wr(pScrn, 0xc040, savedc040);
875 if (Preg == 0x4020) {
876 nv32_wr(pScrn, 0x4020, Pval & ~(1 << 28));
877 nv32_wr(pScrn, 0x4038, Pval & ~(1 << 28));
881 static void setPLL(ScrnInfoPtr pScrn, bios_t *bios, uint32_t reg, uint32_t clk)
884 struct pll_lims pll_lim;
885 int NM1 = 0xbeef, NM2 = 0xdead, log2P;
887 /* high regs (such as in the mac g5 table) are not -= 4 */
888 if (!get_pll_limits(pScrn, reg > 0x405c ? reg : reg - 4, &pll_lim))
891 if (bios->chip_version >= 0x40 || bios->chip_version == 0x30 ||
892 bios->chip_version == 0x31 || bios->chip_version == 0x35 ||
893 bios->chip_version == 0x36) {
894 getMNP_double(pScrn, &pll_lim, clk, &NM1, &NM2, &log2P);
896 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
897 "Could not find a suitable set of coefficients, giving up\n");
901 setPLL_double_highregs(pScrn, reg, NM1, NM2, log2P);
903 setPLL_double_lowregs(pScrn, reg, NM1, NM2, log2P);
905 getMNP_single(pScrn, &pll_lim, clk, &NM1, &log2P);
906 setPLL_single(pScrn, reg, NM1, log2P);
911 static bool init_prog(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
913 /* INIT_PROG opcode: 0x31
915 * offset (8 bit): opcode
916 * offset + 1 (32 bit): reg
917 * offset + 5 (32 bit): and mask
918 * offset + 9 (8 bit): shift right
919 * offset + 10 (8 bit): number of configurations
920 * offset + 11 (32 bit): register
921 * offset + 15 (32 bit): configuration 1
924 * Starting at offset + 15 there are "number of configurations"
925 * 32 bit values. To find out which configuration value to use
926 * read "CRTC reg" on the CRTC controller with index "CRTC index"
927 * and bitwise AND this value with "and mask" and then bit shift the
928 * result "shift right" bits to the right.
929 * Assign "register" with appropriate configuration value.
932 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
933 CARD32 and = *((CARD32 *) (&bios->data[offset + 5]));
934 CARD8 shiftr = *((CARD8 *) (&bios->data[offset + 9]));
935 CARD8 nr = *((CARD8 *) (&bios->data[offset + 10]));
936 CARD32 reg2 = *((CARD32 *) (&bios->data[offset + 11]));
938 CARD32 configval, tmp;
940 if (iexec->execute) {
941 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%04X\n", offset,
944 tmp = nv32_rd(pScrn, reg);
945 configuration = (tmp & and) >> shiftr;
947 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONFIGURATION TO USE: 0x%02X\n",
948 offset, configuration);
950 if (configuration <= nr) {
953 *((CARD32 *) (&bios->data[offset + 15 + configuration * 4]));
955 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%08X, VALUE: 0x%08X\n", offset,
958 tmp = nv32_rd(pScrn, reg2);
959 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n",
961 nv32_wr(pScrn, reg2, configval);
968 static bool init_io_restrict_prog(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
970 /* INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
972 * offset (8 bit): opcode
973 * offset + 1 (16 bit): CRTC port
974 * offset + 3 (8 bit): CRTC index
975 * offset + 4 (8 bit): mask
976 * offset + 5 (8 bit): shift
977 * offset + 6 (8 bit): count
978 * offset + 7 (32 bit): register
979 * offset + 11 (32 bit): configuration 1
982 * Starting at offset + 11 there are "count" 32 bit values.
983 * To find out which value to use read index "CRTC index" on "CRTC port",
984 * AND this value with "mask" and then bit shift right "shift" bits.
985 * Read the appropriate value using this index and write to "register"
988 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
989 uint8_t crtcindex = bios->data[offset + 3];
990 uint8_t mask = bios->data[offset + 4];
991 uint8_t shift = bios->data[offset + 5];
992 uint8_t count = bios->data[offset + 6];
993 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
1000 if (DEBUGLEVEL >= 6)
1001 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1002 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1003 offset, crtcport, crtcindex, mask, shift, count, reg);
1005 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1006 if (config > count) {
1007 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1008 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1009 offset, config, count);
1013 configval = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
1015 if (DEBUGLEVEL >= 6)
1016 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1017 "0x%04X: Writing config %02X\n", offset, config);
1019 nv32_wr(pScrn, reg, configval);
1024 static bool init_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1026 /* INIT_REPEAT opcode: 0x33 ('3')
1028 * offset (8 bit): opcode
1029 * offset + 1 (8 bit): count
1031 * Execute script following this opcode up to INIT_REPEAT_END
1035 uint8_t count = bios->data[offset + 1];
1038 /* no iexec->execute check by design */
1040 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1041 "0x%04X: REPEATING FOLLOWING SEGMENT %d TIMES\n",
1044 iexec->repeat = true;
1046 /* count - 1, as the script block will execute once when we leave this
1047 * opcode -- this is compatible with bios behaviour as:
1048 * a) the block is always executed at least once, even if count == 0
1049 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
1052 for (i = 0; i < count - 1; i++)
1053 parse_init_table(pScrn, bios, offset + 2, iexec);
1055 iexec->repeat = false;
1060 static bool init_io_restrict_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1062 /* INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
1064 * offset (8 bit): opcode
1065 * offset + 1 (16 bit): CRTC port
1066 * offset + 3 (8 bit): CRTC index
1067 * offset + 4 (8 bit): mask
1068 * offset + 5 (8 bit): shift
1069 * offset + 6 (8 bit): IO flag condition index
1070 * offset + 7 (8 bit): count
1071 * offset + 8 (32 bit): register
1072 * offset + 12 (16 bit): frequency 1
1075 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
1076 * Set PLL register "register" to coefficients for frequency n,
1077 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1078 * "mask" and shifted right by "shift". If "IO flag condition index" > 0,
1079 * and condition met, double frequency before setting it.
1082 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1083 uint8_t crtcindex = bios->data[offset + 3];
1084 uint8_t mask = bios->data[offset + 4];
1085 uint8_t shift = bios->data[offset + 5];
1086 int8_t io_flag_condition_idx = bios->data[offset + 6];
1087 uint8_t count = bios->data[offset + 7];
1088 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 8])));
1092 if (!iexec->execute)
1095 if (DEBUGLEVEL >= 6)
1096 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1097 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, IO Flag Condition: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1098 offset, crtcport, crtcindex, mask, shift, io_flag_condition_idx, count, reg);
1100 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1101 if (config > count) {
1102 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1103 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1104 offset, config, count);
1108 freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 12 + config * 2])));
1110 if (io_flag_condition_idx > 0) {
1111 if (io_flag_condition(pScrn, bios, offset, io_flag_condition_idx)) {
1112 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1113 "0x%04X: CONDITION FULFILLED - FREQ DOUBLED\n", offset);
1116 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1117 "0x%04X: CONDITION IS NOT FULFILLED. FREQ UNCHANGED\n", offset);
1120 if (DEBUGLEVEL >= 6)
1121 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1122 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1123 offset, reg, config, freq);
1125 setPLL(pScrn, bios, reg, freq * 10);
1130 static bool init_end_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1132 /* INIT_END_REPEAT opcode: 0x36 ('6')
1134 * offset (8 bit): opcode
1136 * Marks the end of the block for INIT_REPEAT to repeat
1139 /* no iexec->execute check by design */
1141 /* iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1142 * we're not in repeat mode
1150 static bool init_copy(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1152 /* INIT_COPY opcode: 0x37 ('7')
1154 * offset (8 bit): opcode
1155 * offset + 1 (32 bit): register
1156 * offset + 5 (8 bit): shift
1157 * offset + 6 (8 bit): srcmask
1158 * offset + 7 (16 bit): CRTC port
1159 * offset + 9 (8 bit): CRTC index
1160 * offset + 10 (8 bit): mask
1162 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1163 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC port
1166 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1167 uint8_t shift = bios->data[offset + 5];
1168 uint8_t srcmask = bios->data[offset + 6];
1169 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 7])));
1170 uint8_t crtcindex = bios->data[offset + 9];
1171 uint8_t mask = bios->data[offset + 10];
1175 if (!iexec->execute)
1178 if (DEBUGLEVEL >= 6)
1179 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1180 "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1181 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1183 data = nv32_rd(pScrn, reg);
1188 data <<= (0x100 - shift);
1192 crtcdata = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) | (uint8_t)data;
1193 nv_idx_port_wr(pScrn, crtcport, crtcindex, crtcdata);
1198 static bool init_not(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1200 /* INIT_NOT opcode: 0x38 ('8')
1202 * offset (8 bit): opcode
1204 * Invert the current execute / no-execute condition (i.e. "else")
1207 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1208 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1210 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1211 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", offset);
1213 iexec->execute = !iexec->execute;
1217 static bool init_io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1219 /* INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1221 * offset (8 bit): opcode
1222 * offset + 1 (8 bit): condition number
1224 * Check condition "condition number" in the IO flag condition table.
1225 * If condition not met skip subsequent opcodes until condition is
1226 * inverted (INIT_NOT), or we hit INIT_RESUME
1229 uint8_t cond = bios->data[offset + 1];
1231 if (!iexec->execute)
1234 if (io_flag_condition(pScrn, bios, offset, cond))
1235 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1236 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
1238 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1239 "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
1240 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1241 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1242 iexec->execute = false;
1248 static bool init_idx_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1250 /* INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1252 * offset (8 bit): opcode
1253 * offset + 1 (32 bit): control register
1254 * offset + 5 (32 bit): data register
1255 * offset + 9 (32 bit): mask
1256 * offset + 13 (32 bit): data
1257 * offset + 17 (8 bit): count
1258 * offset + 18 (8 bit): address 1
1259 * offset + 19 (8 bit): data 1
1262 * For each of "count" address and data pairs, write "data n" to "data register",
1263 * read the current value of "control register", and write it back once ANDed
1264 * with "mask", ORed with "data", and ORed with "address n"
1267 uint32_t controlreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1268 uint32_t datareg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1269 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1270 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 13])));
1271 uint8_t count = bios->data[offset + 17];
1275 if (!iexec->execute)
1278 if (DEBUGLEVEL >= 6)
1279 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1280 "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1281 offset, controlreg, datareg, mask, data, count);
1283 for (i = 0; i < count; i++) {
1284 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1285 uint8_t instdata = bios->data[offset + 19 + i * 2];
1287 if (DEBUGLEVEL >= 6)
1288 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1289 "0x%04X: Address: 0x%02X, Data: 0x%02X\n", offset, instaddress, instdata);
1291 nv32_wr(pScrn, datareg, instdata);
1292 value = (nv32_rd(pScrn, controlreg) & mask) | data | instaddress;
1293 nv32_wr(pScrn, controlreg, value);
1299 static bool init_io_restrict_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1301 /* INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1303 * offset (8 bit): opcode
1304 * offset + 1 (16 bit): CRTC port
1305 * offset + 3 (8 bit): CRTC index
1306 * offset + 4 (8 bit): mask
1307 * offset + 5 (8 bit): shift
1308 * offset + 6 (8 bit): count
1309 * offset + 7 (32 bit): register
1310 * offset + 11 (32 bit): frequency 1
1313 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1314 * Set PLL register "register" to coefficients for frequency n,
1315 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1316 * "mask" and shifted right by "shift".
1319 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1320 uint8_t crtcindex = bios->data[offset + 3];
1321 uint8_t mask = bios->data[offset + 4];
1322 uint8_t shift = bios->data[offset + 5];
1323 uint8_t count = bios->data[offset + 6];
1324 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
1328 if (!iexec->execute)
1331 if (DEBUGLEVEL >= 6)
1332 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1333 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1334 offset, crtcport, crtcindex, mask, shift, count, reg);
1339 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1340 if (config > count) {
1341 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1342 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1343 offset, config, count);
1347 freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
1349 if (DEBUGLEVEL >= 6)
1350 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1351 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1352 offset, reg, config, freq);
1354 setPLL(pScrn, bios, reg, freq);
1359 static bool init_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1361 /* INIT_PLL2 opcode: 0x4B ('K')
1363 * offset (8 bit): opcode
1364 * offset + 1 (32 bit): register
1365 * offset + 5 (32 bit): freq
1367 * Set PLL register "register" to coefficients for frequency "freq"
1370 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1371 uint32_t freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1373 if (!iexec->execute)
1376 if (DEBUGLEVEL >= 6)
1377 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1378 "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1381 setPLL(pScrn, bios, reg, freq);
1386 static uint32_t get_tmds_index_reg(ScrnInfoPtr pScrn, uint8_t mlv)
1388 /* For mlv < 0x80, it is an index into a table of TMDS base addresses
1389 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
1390 * to index a table of offsets to the basic 0x6808b0 address
1391 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
1392 * to index a table of offsets to the basic 0x6808b0 address, and then flip the offset by 8
1395 NVPtr pNv = NVPTR(pScrn);
1396 const int pramdac_offset[13] = {0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000};
1397 const uint32_t pramdac_table[4] = {0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8};
1400 /* here we assume that the DCB table has already been parsed */
1403 /* This register needs to be written to set index for reading CR58 */
1404 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_57, 0);
1405 dcb_entry = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_58);
1406 if (dcb_entry > pNv->dcb_table.entries) {
1407 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1408 "CR58 doesn't have a valid DCB entry currently (%02X)\n", dcb_entry);
1411 dacoffset = pramdac_offset[pNv->dcb_table.entry[dcb_entry].or];
1414 return (0x6808b0 + dacoffset);
1416 if (mlv > (sizeof(pramdac_table) / sizeof(uint32_t))) {
1417 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1418 "Magic Lookup Value too big (%02X)\n", mlv);
1421 return pramdac_table[mlv];
1425 static bool init_tmds(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1427 /* INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1429 * offset (8 bit): opcode
1430 * offset + 1 (8 bit): magic lookup value
1431 * offset + 2 (8 bit): TMDS address
1432 * offset + 3 (8 bit): mask
1433 * offset + 4 (8 bit): data
1435 * Read the data reg for TMDS address "TMDS address", AND it with mask
1436 * and OR it with data, then write it back
1437 * "magic lookup value" determines which TMDS base address register is used --
1438 * see get_tmds_index_reg()
1441 uint8_t mlv = bios->data[offset + 1];
1442 uint32_t tmdsaddr = bios->data[offset + 2];
1443 uint8_t mask = bios->data[offset + 3];
1444 uint8_t data = bios->data[offset + 4];
1445 uint32_t reg, value;
1447 if (!iexec->execute)
1450 if (DEBUGLEVEL >= 6)
1451 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1452 "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1453 offset, mlv, tmdsaddr, mask, data);
1455 if (!(reg = get_tmds_index_reg(pScrn, mlv)))
1458 nv32_wr(pScrn, reg, tmdsaddr | 0x10000);
1459 value = (nv32_rd(pScrn, reg + 4) & mask) | data;
1460 nv32_wr(pScrn, reg + 4, value);
1461 nv32_wr(pScrn, reg, tmdsaddr);
1466 static bool init_zm_tmds_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1468 /* INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1470 * offset (8 bit): opcode
1471 * offset + 1 (8 bit): magic lookup value
1472 * offset + 2 (8 bit): count
1473 * offset + 3 (8 bit): addr 1
1474 * offset + 4 (8 bit): data 1
1477 * For each of "count" TMDS address and data pairs write "data n" to "addr n"
1478 * "magic lookup value" determines which TMDS base address register is used --
1479 * see get_tmds_index_reg()
1482 uint8_t mlv = bios->data[offset + 1];
1483 uint8_t count = bios->data[offset + 2];
1487 if (!iexec->execute)
1490 if (DEBUGLEVEL >= 6)
1491 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1492 "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1493 offset, mlv, count);
1495 if (!(reg = get_tmds_index_reg(pScrn, mlv)))
1498 for (i = 0; i < count; i++) {
1499 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1500 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1502 nv32_wr(pScrn, reg + 4, tmdsdata);
1503 nv32_wr(pScrn, reg, tmdsaddr);
1509 static bool init_cr_idx_adr_latch(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1511 /* INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1513 * offset (8 bit): opcode
1514 * offset + 1 (8 bit): CRTC index1
1515 * offset + 2 (8 bit): CRTC index2
1516 * offset + 3 (8 bit): baseaddr
1517 * offset + 4 (8 bit): count
1518 * offset + 5 (8 bit): data 1
1521 * For each of "count" address and data pairs, write "baseaddr + n" to
1522 * "CRTC index1" and "data n" to "CRTC index2"
1523 * Once complete, restore initial value read from "CRTC index1"
1525 uint8_t crtcindex1 = bios->data[offset + 1];
1526 uint8_t crtcindex2 = bios->data[offset + 2];
1527 uint8_t baseaddr = bios->data[offset + 3];
1528 uint8_t count = bios->data[offset + 4];
1529 uint8_t oldaddr, data;
1532 if (!iexec->execute)
1535 if (DEBUGLEVEL >= 6)
1536 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1537 "0x%04X: Index1: 0x%02X, Index2: 0x%02X, BaseAddr: 0x%02X, Count: 0x%02X\n",
1538 offset, crtcindex1, crtcindex2, baseaddr, count);
1540 oldaddr = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex1);
1542 for (i = 0; i < count; i++) {
1543 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, baseaddr + i);
1545 data = bios->data[offset + 5 + i];
1546 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex2, data);
1549 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, oldaddr);
1554 static bool init_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1556 /* INIT_CR opcode: 0x52 ('R')
1558 * offset (8 bit): opcode
1559 * offset + 1 (8 bit): CRTC index
1560 * offset + 2 (8 bit): mask
1561 * offset + 3 (8 bit): data
1563 * Assign the value of at "CRTC index" ANDed with mask and ORed with data
1564 * back to "CRTC index"
1567 uint8_t crtcindex = bios->data[offset + 1];
1568 uint8_t mask = bios->data[offset + 2];
1569 uint8_t data = bios->data[offset + 3];
1572 if (!iexec->execute)
1575 if (DEBUGLEVEL >= 6)
1576 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1577 "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1578 offset, crtcindex, mask, data);
1580 value = (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex) & mask) | data;
1581 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, value);
1586 static bool init_zm_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1588 /* INIT_ZM_CR opcode: 0x53 ('S')
1590 * offset (8 bit): opcode
1591 * offset + 1 (8 bit): CRTC index
1592 * offset + 2 (8 bit): value
1594 * Assign "value" to CRTC register with index "CRTC index".
1597 uint8_t crtcindex = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1598 uint8_t data = bios->data[offset + 2];
1600 if (!iexec->execute)
1603 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, data);
1608 static bool init_zm_cr_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1610 /* INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1612 * offset (8 bit): opcode
1613 * offset + 1 (8 bit): count
1614 * offset + 2 (8 bit): CRTC index 1
1615 * offset + 3 (8 bit): value 1
1618 * For "count", assign "value n" to CRTC register with index "CRTC index n".
1621 uint8_t count = bios->data[offset + 1];
1624 if (!iexec->execute)
1627 for (i = 0; i < count; i++)
1628 init_zm_cr(pScrn, bios, offset + 2 + 2 * i - 1, iexec);
1633 static bool init_condition_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1635 /* INIT_CONDITION_TIME opcode: 0x56 ('V')
1637 * offset (8 bit): opcode
1638 * offset + 1 (8 bit): condition number
1639 * offset + 2 (8 bit): retries / 50
1641 * Check condition "condition number" in the condition table.
1642 * The condition table entry has 4 bytes for the address of the
1643 * register to check, 4 bytes for a mask and 4 for a test value.
1644 * If condition not met sleep for 2ms, and repeat upto "retries" times.
1645 * If still not met after retries, clear execution flag for this table.
1648 uint8_t cond = bios->data[offset + 1];
1649 uint16_t retries = bios->data[offset + 2];
1650 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
1651 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
1652 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
1653 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
1656 if (!iexec->execute)
1661 if (DEBUGLEVEL >= 6)
1662 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1663 "0x%04X: Cond: 0x%02X, Retries: 0x%02X\n", offset, cond, retries);
1665 for (; retries > 0; retries--) {
1666 data = nv32_rd(pScrn, reg) & mask;
1668 if (DEBUGLEVEL >= 6)
1669 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1670 "0x%04X: Checking if 0x%08X equals 0x%08X\n",
1671 offset, data, cmpval);
1673 if (data != cmpval) {
1674 if (DEBUGLEVEL >= 6)
1675 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1676 "0x%04X: Condition not met, sleeping for 2ms\n", offset);
1679 if (DEBUGLEVEL >= 6)
1680 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1681 "0x%04X: Condition met, continuing\n", offset);
1686 if (data != cmpval) {
1687 if (DEBUGLEVEL >= 6)
1688 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1689 "0x%04X: Condition still not met, skiping following opcodes\n", offset);
1690 iexec->execute = false;
1696 static bool init_zm_reg_sequence(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1698 /* INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1700 * offset (8 bit): opcode
1701 * offset + 1 (32 bit): base register
1702 * offset + 5 (8 bit): count
1703 * offset + 6 (32 bit): value 1
1706 * Starting at offset + 6 there are "count" 32 bit values.
1707 * For "count" iterations set "base register" + 4 * current_iteration
1708 * to "value current_iteration"
1711 uint32_t basereg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1712 uint32_t count = bios->data[offset + 5];
1715 if (!iexec->execute)
1718 if (DEBUGLEVEL >= 6)
1719 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1720 "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1721 offset, basereg, count);
1723 for (i = 0; i < count; i++) {
1724 uint32_t reg = basereg + i * 4;
1725 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + i * 4])));
1727 nv32_wr(pScrn, reg, data);
1734 static bool init_indirect_reg(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1736 /* INIT_INDIRECT_REG opcode: 0x5A
1738 * offset (8 bit): opcode
1739 * offset + 1 (32 bit): register
1740 * offset + 5 (16 bit): adress offset (in bios)
1742 * Lookup value at offset data in the bios and write it to reg
1744 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
1745 CARD16 data = le16_to_cpu(*((CARD16 *) (&bios->data[offset + 5])));
1746 CARD32 data2 = bios->data[data];
1748 if (iexec->execute) {
1749 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1750 "0x%04X: REG: 0x%04X, DATA AT: 0x%04X, VALUE IS: 0x%08X\n",
1751 offset, reg, data, data2);
1753 if (DEBUGLEVEL >= 6) {
1755 tmpval = nv32_rd(pScrn, reg);
1756 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n", offset, tmpval);
1759 nv32_wr(pScrn, reg, data2);
1765 static bool init_sub_direct(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1767 /* INIT_SUB_DIRECT opcode: 0x5B ('[')
1769 * offset (8 bit): opcode
1770 * offset + 1 (16 bit): subroutine offset (in bios)
1772 * Calls a subroutine that will execute commands until INIT_DONE
1776 uint16_t sub_offset = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1778 if (!iexec->execute)
1781 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: EXECUTING SUB-ROUTINE AT 0x%04X\n",
1782 offset, sub_offset);
1784 parse_init_table(pScrn, bios, sub_offset, iexec);
1786 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: END OF SUB-ROUTINE AT 0x%04X\n",
1787 offset, sub_offset);
1792 static bool init_copy_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1794 /* INIT_COPY_NV_REG opcode: 0x5F ('_')
1796 * offset (8 bit): opcode
1797 * offset + 1 (32 bit): src reg
1798 * offset + 5 (8 bit): shift
1799 * offset + 6 (32 bit): src mask
1800 * offset + 10 (32 bit): xor
1801 * offset + 14 (32 bit): dst reg
1802 * offset + 18 (32 bit): dst mask
1804 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1805 * "src mask", then XOR with "xor". Write this OR'd with
1806 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1809 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1810 uint8_t shift = bios->data[offset + 5];
1811 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1812 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1813 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1814 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1815 uint32_t srcvalue, dstvalue;
1817 if (!iexec->execute)
1820 if (DEBUGLEVEL >= 6)
1821 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1822 "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1823 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1825 srcvalue = nv32_rd(pScrn, srcreg);
1830 srcvalue <<= (0x100 - shift);
1832 srcvalue = (srcvalue & srcmask) ^ xor;
1834 dstvalue = nv32_rd(pScrn, dstreg) & dstmask;
1836 nv32_wr(pScrn, dstreg, dstvalue | srcvalue);
1841 static bool init_zm_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1843 /* INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1845 * offset (8 bit): opcode
1846 * offset + 1 (16 bit): CRTC port
1847 * offset + 3 (8 bit): CRTC index
1848 * offset + 4 (8 bit): data
1850 * Write "data" to index "CRTC index" of "CRTC port"
1852 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1853 uint8_t crtcindex = bios->data[offset + 3];
1854 uint8_t data = bios->data[offset + 4];
1856 if (!iexec->execute)
1859 nv_idx_port_wr(pScrn, crtcport, crtcindex, data);
1864 static bool init_compute_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1866 /* INIT_COMPUTE_MEM opcode: 0x63 ('c')
1868 * offset (8 bit): opcode
1870 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
1871 * that the hardware can correctly calculate how much VRAM it has
1872 * (and subsequently report that value in 0x10020C)
1874 * The implementation of this opcode in general consists of two parts:
1875 * 1) determination of the memory bus width
1876 * 2) determination of how many of the card's RAM pads have ICs attached
1878 * 1) is done by a cunning combination of writes to offsets 0x1c and
1879 * 0x3c in the framebuffer, and seeing whether the written values are
1880 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
1882 * 2) is done by a cunning combination of writes to an offset slightly
1883 * less than the maximum memory reported by 0x10020C, then seeing if
1884 * the test pattern can be read back. This then affects bits 12-15 of
1887 * In this context a "cunning combination" may include multiple reads
1888 * and writes to varying locations, often alternating the test pattern
1889 * and 0, doubtless to make sure buffers are filled, residual charges
1890 * on tracks are removed etc.
1892 * Unfortunately, the "cunning combination"s mentioned above, and the
1893 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
1896 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
1897 * we started was correct, and use that instead
1900 /* no iexec->execute check by design */
1902 /* on every card I've seen, this step gets done for us earlier in the init scripts
1903 uint8_t crdata = nv_idx_port_rd(pScrn, SEQ_INDEX, 0x01);
1904 nv_idx_port_wr(pScrn, SEQ_INDEX, 0x01, crdata | 0x20);
1907 /* this also has probably been done in the scripts, but an mmio trace of
1908 * s3 resume shows nvidia doing it anyway (unlike the SEQ_INDEX write)
1910 nv32_wr(pScrn, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
1912 /* write back the saved configuration value */
1913 nv32_wr(pScrn, NV_PFB_CFG0, saved_nv_pfb_cfg0);
1918 static bool init_reset(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1920 /* INIT_RESET opcode: 0x65 ('e')
1922 * offset (8 bit): opcode
1923 * offset + 1 (32 bit): register
1924 * offset + 5 (32 bit): value1
1925 * offset + 9 (32 bit): value2
1927 * Assign "value1" to "register", then assign "value2" to "register"
1930 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1931 uint32_t value1 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1932 uint32_t value2 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1933 uint32_t pci_nv_19, pci_nv_20;
1935 /* no iexec->execute check by design */
1937 pci_nv_19 = nv32_rd(pScrn, NV_PBUS_PCI_NV_19);
1938 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, 0);
1939 nv32_wr(pScrn, reg, value1);
1943 nv32_wr(pScrn, reg, value2);
1944 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, pci_nv_19);
1946 pci_nv_20 = nv32_rd(pScrn, NV_PBUS_PCI_NV_20);
1947 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
1948 nv32_wr(pScrn, NV_PBUS_PCI_NV_20, pci_nv_20);
1953 static bool init_configure_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1955 /* INIT_CONFIGURE_MEM opcode: 0x66 ('f')
1957 * offset (8 bit): opcode
1959 * Equivalent to INIT_DONE on bios version 3 or greater.
1960 * For early bios versions, sets up the memory registers, using values
1961 * taken from the memory init table
1964 /* no iexec->execute check by design */
1966 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_SCRATCH4) >> 4);
1967 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
1970 if (bios->major_version > 2)
1973 nv_idx_port_wr(pScrn, SEQ_INDEX, 0x01, nv_idx_port_rd(pScrn, SEQ_INDEX, 0x01) | 0x20);
1975 if (bios->data[meminitoffs] & 1)
1976 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
1978 for (reg = le32_to_cpu(*(uint32_t *)&bios->data[seqtbloffs]);
1980 reg = le32_to_cpu(*(uint32_t *)&bios->data[seqtbloffs += 4])) {
1984 data = NV_PFB_PRE_CMD_PRECHARGE;
1987 data = NV_PFB_PAD_CKE_NORMAL;
1990 data = NV_PFB_REF_CMD_REFRESH;
1993 data = le32_to_cpu(*(uint32_t *)&bios->data[meminitdata]);
1995 if (data == 0xffffffff)
1999 nv32_wr(pScrn, reg, data);
2005 static bool init_configure_clk(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2007 /* INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2009 * offset (8 bit): opcode
2011 * Equivalent to INIT_DONE on bios version 3 or greater.
2012 * For early bios versions, sets up the NVClk and MClk PLLs, using
2013 * values taken from the memory init table
2016 /* no iexec->execute check by design */
2018 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_SCRATCH4) >> 4);
2021 if (bios->major_version > 2)
2024 clock = le16_to_cpu(*(uint16_t *)&bios->data[meminitoffs + 4]) * 10;
2025 setPLL(pScrn, bios, NV_RAMDAC_NVPLL, clock);
2027 clock = le16_to_cpu(*(uint16_t *)&bios->data[meminitoffs + 2]) * 10;
2028 if (bios->data[meminitoffs] & 1) /* DDR */
2030 setPLL(pScrn, bios, NV_RAMDAC_MPLL, clock);
2035 static bool init_configure_preinit(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2037 /* INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2039 * offset (8 bit): opcode
2041 * Equivalent to INIT_DONE on bios version 3 or greater.
2042 * For early bios versions, does early init, loading ram and crystal
2043 * configuration from straps into CR3C
2046 /* no iexec->execute check by design */
2048 uint32_t straps = nv32_rd(pScrn, NV_PEXTDEV_BOOT_0);
2049 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6));
2051 if (bios->major_version > 2)
2054 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_SCRATCH4, cr3c);
2059 static bool init_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2061 /* INIT_IO opcode: 0x69 ('i')
2063 * offset (8 bit): opcode
2064 * offset + 1 (16 bit): CRTC port
2065 * offset + 3 (8 bit): mask
2066 * offset + 4 (8 bit): data
2068 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2071 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2072 uint8_t mask = bios->data[offset + 3];
2073 uint8_t data = bios->data[offset + 4];
2075 if (!iexec->execute)
2078 if (DEBUGLEVEL >= 6)
2079 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2080 "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2081 offset, crtcport, mask, data);
2083 nv_port_wr(pScrn, crtcport, (nv_port_rd(pScrn, crtcport) & mask) | data);
2088 static bool init_sub(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2090 /* INIT_SUB opcode: 0x6B ('k')
2092 * offset (8 bit): opcode
2093 * offset + 1 (8 bit): script number
2095 * Execute script number "script number", as a subroutine
2098 uint8_t sub = bios->data[offset + 1];
2100 if (!iexec->execute)
2103 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2104 "0x%04X: EXECUTING SUB-SCRIPT %d\n", offset, sub);
2106 parse_init_table(pScrn, bios,
2107 le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + sub * 2]))),
2110 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2111 "0x%04X: END OF SUB-SCRIPT %d\n", offset, sub);
2116 static bool init_ram_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2118 /* INIT_RAM_CONDITION opcode: 0x6D ('m')
2120 * offset (8 bit): opcode
2121 * offset + 1 (8 bit): mask
2122 * offset + 2 (8 bit): cmpval
2124 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval".
2125 * If condition not met skip subsequent opcodes until condition is
2126 * inverted (INIT_NOT), or we hit INIT_RESUME
2129 uint8_t mask = bios->data[offset + 1];
2130 uint8_t cmpval = bios->data[offset + 2];
2133 if (!iexec->execute)
2136 data = nv32_rd(pScrn, NV_PFB_BOOT_0) & mask;
2138 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2139 "0x%04X: Checking if 0x%08X equals 0x%08X\n", offset, data, cmpval);
2142 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2143 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
2145 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2146 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2147 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2148 iexec->execute = false;
2154 static bool init_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2156 /* INIT_NV_REG opcode: 0x6E ('n')
2158 * offset (8 bit): opcode
2159 * offset + 1 (32 bit): register
2160 * offset + 5 (32 bit): mask
2161 * offset + 9 (32 bit): data
2163 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2166 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2167 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2168 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
2170 if (!iexec->execute)
2173 if (DEBUGLEVEL >= 6)
2174 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2175 "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2176 offset, reg, mask, data);
2178 nv32_wr(pScrn, reg, (nv32_rd(pScrn, reg) & mask) | data);
2183 static bool init_macro(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2185 /* INIT_MACRO opcode: 0x6F ('o')
2187 * offset (8 bit): opcode
2188 * offset + 1 (8 bit): macro number
2190 * Look up macro index "macro number" in the macro index table.
2191 * The macro index table entry has 1 byte for the index in the macro table,
2192 * and 1 byte for the number of times to repeat the macro.
2193 * The macro table entry has 4 bytes for the register address and
2194 * 4 bytes for the value to write to that register
2197 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2198 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2199 uint8_t macro_tbl_idx = bios->data[tmp];
2200 uint8_t count = bios->data[tmp + 1];
2204 if (!iexec->execute)
2207 if (DEBUGLEVEL >= 6)
2208 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2209 "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, Count: 0x%02X\n",
2210 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2212 for (i = 0; i < count; i++) {
2213 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2215 reg = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr])));
2216 data = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr + 4])));
2218 nv32_wr(pScrn, reg, data);
2224 static bool init_done(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2226 /* INIT_DONE opcode: 0x71 ('q')
2228 * offset (8 bit): opcode
2230 * End the current script
2233 /* mild retval abuse to stop parsing this table */
2237 static bool init_resume(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2239 /* INIT_RESUME opcode: 0x72 ('r')
2241 * offset (8 bit): opcode
2243 * End the current execute / no-execute condition
2249 iexec->execute = true;
2250 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2251 "0x%04X: ---- EXECUTING FOLLOWING COMMANDS ----\n", offset);
2257 static bool init_ram_condition2(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
2259 /* INIT_RAM_CONDITION2 opcode: 0x73
2261 * offset (8 bit): opcode
2262 * offset + 1 (8 bit): and mask
2263 * offset + 2 (8 bit): cmpval
2265 * Test if (NV_EXTDEV_BOOT & and mask) matches cmpval
2267 NVPtr pNv = NVPTR(pScrn);
2268 CARD32 and = *((CARD32 *) (&bios->data[offset + 1]));
2269 CARD32 cmpval = *((CARD32 *) (&bios->data[offset + 5]));
2272 if (iexec->execute) {
2273 data=(nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT))∧
2275 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2276 "0x%04X: CHECKING IF REGVAL: 0x%08X equals COND: 0x%08X\n",
2277 offset, data, cmpval);
2279 if (data == cmpval) {
2280 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2281 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n",
2284 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2285 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2286 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2287 iexec->execute = false;
2294 static bool init_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2296 /* INIT_TIME opcode: 0x74 ('t')
2298 * offset (8 bit): opcode
2299 * offset + 1 (16 bit): time
2301 * Sleep for "time" microseconds.
2304 uint16_t time = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2306 if (!iexec->execute)
2309 if (DEBUGLEVEL >= 6)
2310 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2311 "0x%04X: Sleeping for 0x%04X microseconds\n", offset, time);
2318 static bool init_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2320 /* INIT_CONDITION opcode: 0x75 ('u')
2322 * offset (8 bit): opcode
2323 * offset + 1 (8 bit): condition number
2325 * Check condition "condition number" in the condition table.
2326 * The condition table entry has 4 bytes for the address of the
2327 * register to check, 4 bytes for a mask and 4 for a test value.
2328 * If condition not met skip subsequent opcodes until condition is
2329 * inverted (INIT_NOT), or we hit INIT_RESUME
2332 uint8_t cond = bios->data[offset + 1];
2333 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
2334 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
2335 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
2336 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
2339 if (!iexec->execute)
2342 if (DEBUGLEVEL >= 6)
2343 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2344 "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X, Cmpval: 0x%08X\n",
2345 offset, cond, reg, mask, cmpval);
2347 data = nv32_rd(pScrn, reg) & mask;
2349 if (DEBUGLEVEL >= 6)
2350 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2351 "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2352 offset, data, cmpval);
2354 if (data == cmpval) {
2355 if (DEBUGLEVEL >= 6)
2356 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2357 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
2359 if (DEBUGLEVEL >= 6)
2360 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2361 "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2362 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2363 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2364 iexec->execute = false;
2370 static bool init_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2372 /* INIT_INDEX_IO opcode: 0x78 ('x')
2374 * offset (8 bit): opcode
2375 * offset + 1 (16 bit): CRTC port
2376 * offset + 3 (8 bit): CRTC index
2377 * offset + 4 (8 bit): mask
2378 * offset + 5 (8 bit): data
2380 * Read value at index "CRTC index" on "CRTC port", AND with "mask", OR with "data", write-back
2383 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2384 uint8_t crtcindex = bios->data[offset + 3];
2385 uint8_t mask = bios->data[offset + 4];
2386 uint8_t data = bios->data[offset + 5];
2389 if (!iexec->execute)
2392 if (DEBUGLEVEL >= 6)
2393 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2394 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
2395 offset, crtcport, crtcindex, mask, data);
2397 value = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) | data;
2398 nv_idx_port_wr(pScrn, crtcport, crtcindex, value);
2403 static bool init_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2405 /* INIT_PLL opcode: 0x79 ('y')
2407 * offset (8 bit): opcode
2408 * offset + 1 (32 bit): register
2409 * offset + 5 (16 bit): freq
2411 * Set PLL register "register" to coefficients for frequency (10kHz) "freq"
2414 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2415 uint16_t freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 5])));
2417 if (!iexec->execute)
2420 if (DEBUGLEVEL >= 6)
2421 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2422 "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n",
2425 setPLL(pScrn, bios, reg, freq * 10);
2430 static bool init_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2432 /* INIT_ZM_REG opcode: 0x7A ('z')
2434 * offset (8 bit): opcode
2435 * offset + 1 (32 bit): register
2436 * offset + 5 (32 bit): value
2438 * Assign "value" to "register"
2441 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2442 uint32_t value = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2444 if (!iexec->execute)
2447 nv32_wr(pScrn, reg, value);
2452 static bool init_8e(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2454 /* INIT_8E opcode: 0x8E ('')
2456 * offset (8 bit): opcode
2458 * The purpose of this opcode is unclear (being for nv50 cards), and
2459 * the literal functionality can be seen in the code below.
2461 * A brief synopsis is that for each entry in a table pointed to by the
2462 * DCB table header, depending on the settings of various bits, various
2463 * other bits in registers 0xe100, 0xe104, and 0xe108, are set or
2467 uint16_t dcbptr = le16_to_cpu(*(uint16_t *)&bios->data[0x36]);
2468 uint16_t init8etblptr = le16_to_cpu(*(uint16_t *)&bios->data[dcbptr + 10]);
2469 uint8_t headerlen = bios->data[init8etblptr + 1];
2470 uint8_t entries = bios->data[init8etblptr + 2];
2471 uint8_t recordlen = bios->data[init8etblptr + 3];
2475 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2476 "No Display Configuration Block pointer found\n");
2479 if (bios->data[dcbptr] != 0x40) {
2480 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2481 "DCB table not version 4.0\n");
2484 if (!init8etblptr) {
2485 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
2486 "Invalid pointer to INIT_8E table\n");
2490 for (i = 0; i < entries; i++) {
2491 uint32_t entry = le32_to_cpu(*(uint32_t *)&bios->data[init8etblptr + headerlen + recordlen * i]);
2492 int shift = (entry & 0x1f) * 4;
2494 uint32_t reg = 0xe104;
2497 if ((entry & 0xff00) == 0xff00)
2506 mask = ~(3 << shift);
2507 if (entry & (1 << 24))
2508 data = (entry >> 21);
2510 data = (entry >> 19);
2511 data = ((data & 3) ^ 2) << shift;
2513 if (DEBUGLEVEL >= 6)
2514 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2515 "0x%04X: Entry: 0x%08X, Reg: 0x%08X, Shift: 0x%02X, Mask: 0x%08X, Data: 0x%08X\n",
2516 offset, entry, reg, shift, mask, data);
2518 nv32_wr(pScrn, reg, (nv32_rd(pScrn, reg) & mask) | data);
2521 shift = entry & 0x1f;
2523 mask = ~(1 << 16 | 1);
2524 mask = mask << shift | mask >> (32 - shift);
2526 if ((entry & (3 << 25)) == (1 << 25))
2528 if ((entry & (3 << 25)) == (2 << 25))
2532 if (DEBUGLEVEL >= 6)
2533 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2534 "0x%04X: Entry: 0x%08X, Reg: 0x%08X, Shift: 0x%02X, Mask: 0x%08X, Data: 0x%08X\n",
2535 offset, entry, reg, shift, mask, data);
2537 nv32_wr(pScrn, reg, (nv32_rd(pScrn, reg) & mask) | data);
2543 /* hack to avoid moving the itbl_entry array before this function */
2544 int init_ram_restrict_zm_reg_group_blocklen = 0;
2546 static bool init_ram_restrict_zm_reg_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2548 /* INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2550 * offset (8 bit): opcode
2551 * offset + 1 (32 bit): reg
2552 * offset + 5 (8 bit): regincrement
2553 * offset + 6 (8 bit): count
2554 * offset + 7 (32 bit): value 1,1
2557 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2558 * ram_restrict_table_ptr. The value read from here is 'n', and
2559 * "value 1,n" gets written to "reg". This repeats "count" times and on
2560 * each iteration 'm', "reg" increases by "regincrement" and
2561 * "value m,n" is used. The extent of n is limited by a number read
2562 * from the 'M' BIT table, herein called "blocklen"
2565 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2566 uint8_t regincrement = bios->data[offset + 5];
2567 uint8_t count = bios->data[offset + 6];
2568 uint32_t strap_ramcfg, data;
2573 /* previously set by 'M' BIT table */
2574 blocklen = init_ram_restrict_zm_reg_group_blocklen;
2576 if (!iexec->execute)
2580 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2581 "0x%04X: Zero block length - has the M table been parsed?\n", offset);
2585 strap_ramcfg = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2586 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2588 if (DEBUGLEVEL >= 6)
2589 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2590 "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2591 offset, reg, regincrement, count, strap_ramcfg, index);
2593 for (i = 0; i < count; i++) {
2594 data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7 + index * 4 + blocklen * i])));
2596 nv32_wr(pScrn, reg, data);
2598 reg += regincrement;
2604 static bool init_copy_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2606 /* INIT_COPY_ZM_REG opcode: 0x90 ('')
2608 * offset (8 bit): opcode
2609 * offset + 1 (32 bit): src reg
2610 * offset + 5 (32 bit): dst reg
2612 * Put contents of "src reg" into "dst reg"
2615 uint32_t srcreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2616 uint32_t dstreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2618 if (!iexec->execute)
2621 nv32_wr(pScrn, dstreg, nv32_rd(pScrn, srcreg));
2626 static bool init_zm_reg_group_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2628 /* INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2630 * offset (8 bit): opcode
2631 * offset + 1 (32 bit): dst reg
2632 * offset + 5 (8 bit): count
2633 * offset + 6 (32 bit): data 1
2636 * For each of "count" values write "data n" to "dst reg"
2639 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2640 uint8_t count = bios->data[offset + 5];
2643 if (!iexec->execute)
2646 for (i = 0; i < count; i++) {
2647 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + 4 * i])));
2648 nv32_wr(pScrn, reg, data);
2654 static bool init_reserved(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2656 /* INIT_RESERVED opcode: 0x92 ('')
2658 * offset (8 bit): opcode
2660 * Seemingly does nothing
2666 static init_tbl_entry_t itbl_entry[] = {
2667 /* command name , id , length , offset , mult , command handler */
2668 // { "INIT_PROG" , 0x31, 15 , 10 , 4 , init_prog },
2669 { "INIT_IO_RESTRICT_PROG" , 0x32, 11 , 6 , 4 , init_io_restrict_prog },
2670 { "INIT_REPEAT" , 0x33, 2 , 0 , 0 , init_repeat },
2671 { "INIT_IO_RESTRICT_PLL" , 0x34, 12 , 7 , 2 , init_io_restrict_pll },
2672 { "INIT_END_REPEAT" , 0x36, 1 , 0 , 0 , init_end_repeat },
2673 { "INIT_COPY" , 0x37, 11 , 0 , 0 , init_copy },
2674 { "INIT_NOT" , 0x38, 1 , 0 , 0 , init_not },
2675 { "INIT_IO_FLAG_CONDITION" , 0x39, 2 , 0 , 0 , init_io_flag_condition },
2676 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, 18 , 17 , 2 , init_idx_addr_latched },
2677 { "INIT_IO_RESTRICT_PLL2" , 0x4A, 11 , 6 , 4 , init_io_restrict_pll2 },
2678 { "INIT_PLL2" , 0x4B, 9 , 0 , 0 , init_pll2 },
2679 /* { "INIT_I2C_BYTE" , 0x4C, x , x , x , init_i2c_byte }, */
2680 /* { "INIT_ZM_I2C_BYTE" , 0x4D, x , x , x , init_zm_i2c_byte }, */
2681 /* { "INIT_ZM_I2C" , 0x4E, x , x , x , init_zm_i2c }, */
2682 { "INIT_TMDS" , 0x4F, 5 , 0 , 0 , init_tmds },
2683 { "INIT_ZM_TMDS_GROUP" , 0x50, 3 , 2 , 2 , init_zm_tmds_group },
2684 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, 5 , 4 , 1 , init_cr_idx_adr_latch },
2685 { "INIT_CR" , 0x52, 4 , 0 , 0 , init_cr },
2686 { "INIT_ZM_CR" , 0x53, 3 , 0 , 0 , init_zm_cr },
2687 { "INIT_ZM_CR_GROUP" , 0x54, 2 , 1 , 2 , init_zm_cr_group },
2688 { "INIT_CONDITION_TIME" , 0x56, 3 , 0 , 0 , init_condition_time },
2689 { "INIT_ZM_REG_SEQUENCE" , 0x58, 6 , 5 , 4 , init_zm_reg_sequence },
2690 // { "INIT_INDIRECT_REG" , 0x5A, 7 , 0 , 0 , init_indirect_reg },
2691 { "INIT_SUB_DIRECT" , 0x5B, 3 , 0 , 0 , init_sub_direct },
2692 { "INIT_COPY_NV_REG" , 0x5F, 22 , 0 , 0 , init_copy_nv_reg },
2693 { "INIT_ZM_INDEX_IO" , 0x62, 5 , 0 , 0 , init_zm_index_io },
2694 { "INIT_COMPUTE_MEM" , 0x63, 1 , 0 , 0 , init_compute_mem },
2695 { "INIT_RESET" , 0x65, 13 , 0 , 0 , init_reset },
2696 { "INIT_CONFIGURE_MEM" , 0x66, 1 , 0 , 0 , init_configure_mem },
2697 { "INIT_CONFIGURE_CLK" , 0x67, 1 , 0 , 0 , init_configure_clk },
2698 { "INIT_CONFIGURE_PREINIT" , 0x68, 1 , 0 , 0 , init_configure_preinit },
2699 { "INIT_IO" , 0x69, 5 , 0 , 0 , init_io },
2700 { "INIT_SUB" , 0x6B, 2 , 0 , 0 , init_sub },
2701 { "INIT_RAM_CONDITION" , 0x6D, 3 , 0 , 0 , init_ram_condition },
2702 { "INIT_NV_REG" , 0x6E, 13 , 0 , 0 , init_nv_reg },
2703 { "INIT_MACRO" , 0x6F, 2 , 0 , 0 , init_macro },
2704 { "INIT_DONE" , 0x71, 1 , 0 , 0 , init_done },
2705 { "INIT_RESUME" , 0x72, 1 , 0 , 0 , init_resume },
2706 // { "INIT_RAM_CONDITION2" , 0x73, 9 , 0 , 0 , init_ram_condition2 },
2707 { "INIT_TIME" , 0x74, 3 , 0 , 0 , init_time },
2708 { "INIT_CONDITION" , 0x75, 2 , 0 , 0 , init_condition },
2709 /* { "INIT_IO_CONDITION" , 0x76, x , x , x , init_io_condition }, */
2710 { "INIT_INDEX_IO" , 0x78, 6 , 0 , 0 , init_index_io },
2711 { "INIT_PLL" , 0x79, 7 , 0 , 0 , init_pll },
2712 { "INIT_ZM_REG" , 0x7A, 9 , 0 , 0 , init_zm_reg },
2713 { "INIT_8E" , 0x8E, 1 , 0 , 0 , init_8e },
2714 /* INIT_RAM_RESTRICT_ZM_REG_GROUP's mult is loaded by M table in BIT */
2715 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, 7 , 6 , 0 , init_ram_restrict_zm_reg_group },
2716 { "INIT_COPY_ZM_REG" , 0x90, 9 , 0 , 0 , init_copy_zm_reg },
2717 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, 6 , 5 , 4 , init_zm_reg_group_addr_latched },
2718 { "INIT_RESERVED" , 0x92, 1 , 0 , 0 , init_reserved },
2719 { 0 , 0 , 0 , 0 , 0 , 0 }
2722 static unsigned int get_init_table_entry_length(bios_t *bios, unsigned int offset, int i)
2724 /* Calculates the length of a given init table entry. */
2725 return itbl_entry[i].length + bios->data[offset + itbl_entry[i].length_offset]*itbl_entry[i].length_multiplier;
2728 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec)
2730 /* Parses all commands in a init table. */
2732 /* We start out executing all commands found in the
2733 * init table. Some op codes may change the status
2734 * of this variable to SKIP, which will cause
2735 * the following op codes to perform no operation until
2736 * the value is changed back to EXECUTE.
2742 /* Loop until INIT_DONE causes us to break out of the loop
2743 * (or until offset > bios length just in case... )
2744 * (and no more than 10000 iterations just in case... ) */
2745 while ((offset < bios->length) && (count++ < 10000)) {
2746 id = bios->data[offset];
2748 /* Find matching id in itbl_entry */
2749 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
2752 if (itbl_entry[i].name) {
2753 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ (0x%02X) - %s ]\n",
2754 offset, itbl_entry[i].id, itbl_entry[i].name);
2756 /* execute eventual command handler */
2757 if (itbl_entry[i].handler)
2758 if (!(*itbl_entry[i].handler)(pScrn, bios, offset, iexec))
2761 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2762 "0x%04X: Init table command not found: 0x%02X\n", offset, id);
2766 /* Add the offset of the current command including all data
2767 * of that command. The offset will then be pointing on the
2770 offset += get_init_table_entry_length(bios, offset, i);
2774 static void parse_init_tables(ScrnInfoPtr pScrn, bios_t *bios)
2776 /* Loops and calls parse_init_table() for each present table. */
2780 init_exec_t iexec = {true, false};
2782 while ((table = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + i]))))) {
2783 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2784 "0x%04X: Parsing init table %d\n", table, i / 2);
2785 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2786 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", table);
2788 parse_init_table(pScrn, bios, table, &iexec);
2793 static void link_head_and_output(ScrnInfoPtr pScrn, struct dcb_entry *dcbent, int head)
2795 /* The BIOS scripts don't do this for us, sadly
2796 * Luckily we do know the values ;-)
2798 * head < 0 indicates we wish to force a setting with the overrideval
2799 * (for VT restore etc.)
2802 NVPtr pNv = NVPTR(pScrn);
2803 int ramdac = (dcbent->or & OUTPUT_C) >> 2;
2804 uint8_t tmds04 = 0x80;
2809 if (dcbent->type == OUTPUT_LVDS)
2812 nv_write_tmds(pNv, dcbent->or, 0, 0x04, tmds04);
2814 if (dcbent->type == OUTPUT_LVDS && pNv->VBIOS.fp.dual_link)
2815 nv_write_tmds(pNv, dcbent->or, 1, 0x04, tmds04 ^ 0x08);
2818 static uint16_t clkcmptable(bios_t *bios, uint16_t clktable, int pxclk)
2820 int compare_record_len, i = 0;
2821 uint16_t compareclk, scriptptr = 0;
2823 if (bios->major_version < 5) /* pre BIT */
2824 compare_record_len = 3;
2826 compare_record_len = 4;
2829 compareclk = le16_to_cpu(*((uint16_t *)&bios->data[clktable + compare_record_len * i]));
2830 if (pxclk >= compareclk * 10) {
2831 if (bios->major_version < 5) {
2832 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
2833 scriptptr = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + tmdssub * 2])));
2835 scriptptr = le16_to_cpu(*((uint16_t *)&bios->data[clktable + 2 + compare_record_len * i]));
2839 } while (compareclk);
2844 static void rundigitaloutscript(ScrnInfoPtr pScrn, uint16_t scriptptr, struct dcb_entry *dcbent, int head)
2846 bios_t *bios = &NVPTR(pScrn)->VBIOS;
2847 init_exec_t iexec = {true, false};
2849 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing digital output script table\n", scriptptr);
2850 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER,
2851 head ? NV_VGA_CRTCX_OWNER_HEADB : NV_VGA_CRTCX_OWNER_HEADA);
2852 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_57, 0);
2853 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_58, dcbent->index);
2854 parse_init_table(pScrn, bios, scriptptr, &iexec);
2856 link_head_and_output(pScrn, dcbent, head);
2859 static void call_lvds_manufacturer_script(ScrnInfoPtr pScrn, struct dcb_entry *dcbent, int head, enum LVDS_script script)
2861 NVPtr pNv = NVPTR(pScrn);
2862 bios_t *bios = &pNv->VBIOS;
2863 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
2864 uint16_t scriptofs = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + sub * 2])));
2866 if (!bios->fp.xlated_entry || !sub || !scriptofs)
2869 rundigitaloutscript(pScrn, scriptofs, dcbent, head);
2871 if (script == LVDS_PANEL_OFF)
2872 /* off-on delay in ms */
2873 usleep(le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.xlated_entry + 7]));
2875 /* Powerbook specific quirks */
2876 if (script == LVDS_RESET && ((pNv->Chipset & 0xffff) == 0x0179 || (pNv->Chipset & 0xffff) == 0x0329))
2877 nv_write_tmds(pNv, dcbent->or, 0, 0x02, 0x72);
2878 if ((pNv->Chipset & 0xffff) == 0x0179 || (pNv->Chipset & 0xffff) == 0x0189 || (pNv->Chipset & 0xffff) == 0x0329) {
2879 if (script == LVDS_PANEL_ON) {
2880 nv32_wr(pScrn, NV_PBUS_DEBUG_DUALHEAD_CTL, nv32_rd(pScrn, NV_PBUS_DEBUG_DUALHEAD_CTL) | (1 << 31));
2881 nv32_wr(pScrn, NV_CRTC_GPIO_EXT, nv32_rd(pScrn, NV_CRTC_GPIO_EXT) | 1);
2883 if (script == LVDS_PANEL_OFF) {
2884 nv32_wr(pScrn, NV_PBUS_DEBUG_DUALHEAD_CTL, nv32_rd(pScrn, NV_PBUS_DEBUG_DUALHEAD_CTL) & ~(1 << 31));
2885 nv32_wr(pScrn, NV_CRTC_GPIO_EXT, nv32_rd(pScrn, NV_CRTC_GPIO_EXT) & ~3);
2891 static void run_lvds_table(ScrnInfoPtr pScrn, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
2893 /* The BIT LVDS table's header has the information to setup the
2894 * necessary registers. Following the standard 4 byte header are:
2895 * A bitmask byte and a dual-link transition pxclk value for use in
2896 * selecting the init script when not using straps; 4 script pointers
2897 * for panel power, selected by output and on/off; and 8 table pointers
2898 * for panel init, the needed one determined by output, and bits in the
2899 * conf byte. These tables are similar to the TMDS tables, consisting
2900 * of a list of pxclks and script pointers.
2903 NVPtr pNv = NVPTR(pScrn);
2904 bios_t *bios = &pNv->VBIOS;
2905 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
2906 uint16_t scriptptr = 0, clktable;
2907 uint8_t clktableptr = 0;
2909 /* for now we assume version 3.0 table - g80 support will need some changes */
2914 case LVDS_BACKLIGHT_ON:
2916 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
2918 case LVDS_BACKLIGHT_OFF:
2919 case LVDS_PANEL_OFF:
2920 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
2923 if (dcbent->lvdsconf.use_straps_for_mode) {
2924 if (bios->fp.dual_link)
2926 if (bios->fp.BITbit1)
2929 uint8_t fallback = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
2930 int fallbackcmpval = (dcbent->or == 4) ? 4 : 1;
2932 if (bios->fp.dual_link) {
2934 fallbackcmpval *= 2;
2936 if (fallbackcmpval & fallback)
2940 /* adding outputset * 8 may not be correct */
2941 clktable = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 15 + clktableptr * 2 + outputset * 8]);
2943 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Pixel clock comparison table not found\n");
2946 scriptptr = clkcmptable(bios, clktable, pxclk);
2950 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "LVDS output init script not found\n");
2953 rundigitaloutscript(pScrn, scriptptr, dcbent, head);
2956 void call_lvds_script(ScrnInfoPtr pScrn, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
2958 /* LVDS operations are multiplexed in an effort to present a single API
2959 * which works with two vastly differing underlying structures.
2960 * This acts as the demux
2963 bios_t *bios = &NVPTR(pScrn)->VBIOS;
2964 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
2965 uint32_t sel_clk_binding;
2966 static int last_invoc = 0;
2968 if (last_invoc == (script << 1 | head) || !lvds_ver)
2971 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
2972 call_lvds_script(pScrn, dcbent, head, LVDS_RESET, pxclk);
2973 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
2974 call_lvds_script(pScrn, dcbent, head, LVDS_PANEL_OFF, pxclk);
2976 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Calling LVDS script %d:\n", script);
2978 /* don't let script change pll->head binding */
2979 sel_clk_binding = nv32_rd(pScrn, NV_RAMDAC_SEL_CLK) & 0x50000;
2981 if (lvds_ver < 0x30)
2982 call_lvds_manufacturer_script(pScrn, dcbent, head, script);
2984 run_lvds_table(pScrn, dcbent, head, script, pxclk);
2986 last_invoc = (script << 1 | head);
2988 nv32_wr(pScrn, NV_RAMDAC_SEL_CLK, (nv32_rd(pScrn, NV_RAMDAC_SEL_CLK) & ~0x50000) | sel_clk_binding);
2989 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
2990 nv32_wr(pScrn, NV_PBUS_POWERCTRL_2, 0);
2994 uint16_t fptablepointer;
2995 uint16_t fpxlatetableptr;
2999 struct lvdstableheader {
3000 uint8_t lvds_ver, headerlen, recordlen;
3003 static void parse_lvds_manufacturer_table_header(ScrnInfoPtr pScrn, bios_t *bios, struct lvdstableheader *lth)
3005 /* BMP version (0xa) LVDS table has a simple header of version and
3006 * record length. The BIT LVDS table has the typical BIT table header:
3007 * version byte, header length byte, record length byte, and a byte for
3008 * the maximum number of records that can be held in the table */
3010 uint8_t lvds_ver, headerlen, recordlen;
3012 memset(lth, 0, sizeof(struct lvdstableheader));
3014 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3015 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3016 "Pointer to LVDS manufacturer table invalid\n");
3020 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3023 case 0x0a: /* pre NV40 */
3025 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3027 case 0x30: /* NV4x */
3028 case 0x40: /* G80/G90 */
3029 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3030 if (headerlen < 0x1f) {
3031 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3032 "LVDS table header not understood\n");
3035 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3038 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3039 "LVDS table revision %d.%d not currently supported\n",
3040 lvds_ver >> 4, lvds_ver & 0xf);
3044 lth->lvds_ver = lvds_ver;
3045 lth->headerlen = headerlen;
3046 lth->recordlen = recordlen;
3049 static void parse_fp_mode_table(ScrnInfoPtr pScrn, bios_t *bios, struct fppointers *fpp)
3052 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
3054 struct lvdstableheader lth;
3056 DisplayModePtr mode;
3058 if (fpp->fptablepointer == 0x0) {
3059 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3060 "Pointer to flat panel table invalid\n");
3064 fptable = &bios->data[fpp->fptablepointer];
3065 fptable_ver = fptable[0];
3067 switch (fptable_ver) {
3068 /* BMP version 0x5.0x11 BIOSen have version 1 like tables, but no version field,
3069 * and miss one of the spread spectrum/PWM bytes.
3070 * This could affect early GF2Go parts (not seen any appropriate ROMs though).
3071 * Here we assume that a version of 0x05 matches this case (combining with a
3072 * BMP version check would be better), as the common case for the panel type
3073 * field is 0x0005, and that is in fact what we are reading the first byte of. */
3074 case 0x05: /* some NV10, 11, 15, 16 */
3078 case 0x10: /* some NV15/16, and NV11+ */
3082 case 0x20: /* NV40+ */
3083 headerlen = fptable[1];
3084 recordlen = fptable[2];
3085 fpentries = fptable[3];
3086 /* fptable[4] is the minimum RAMDAC_FP_HCRTC->RAMDAC_FP_HSYNC_START gap.
3087 * Only seen 0x4b (=75) which is what is used in nv_crtc.c anyway,
3088 * so we're not using this table value for now
3093 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3094 "FP table revision %d.%d not currently supported\n",
3095 fptable_ver >> 4, fptable_ver & 0xf);
3099 parse_lvds_manufacturer_table_header(pScrn, bios, <h);
3101 switch (lth.lvds_ver) {
3103 /* make sure to match the 0xff strapping check below */
3104 if ((bios->fp.strapping & 0xf) == 0xf)
3105 bios->data[fpp->fpxlatetableptr + 0xf] = 0xf;
3109 fpp->fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + lth.headerlen + 1;
3110 fpp->xlatwidth = lth.recordlen;
3112 if (fpp->fpxlatetableptr == 0x0) {
3113 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3114 "Pointer to flat panel xlat table invalid\n");
3118 fpindex = bios->data[fpp->fpxlatetableptr + bios->fp.strapping * fpp->xlatwidth];
3119 bios->fp.strapping |= fpindex << 4;
3120 if (fpindex > fpentries) {
3121 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3122 "Bad flat panel table index\n");
3126 /* reserved values - means that ddc or hard coded edid should be used */
3127 if (bios->fp.strapping == 0xff) {
3128 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Ignoring FP table\n");
3132 if (!(mode = xcalloc(1, sizeof(DisplayModeRec))))
3135 modeofs = headerlen + recordlen * fpindex + ofs;
3136 mode->Clock = le16_to_cpu(*(uint16_t *)&fptable[modeofs]) * 10;
3137 mode->HDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 4] + 1);
3138 mode->HSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 10] + 1);
3139 mode->HSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 12] + 1);
3140 mode->HTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 14] + 1);
3141 mode->VDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 18] + 1);
3142 mode->VSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 24] + 1);
3143 mode->VSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 26] + 1);
3144 mode->VTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 28] + 1);
3145 mode->Flags |= (fptable[modeofs + 30] & 0x10) ? V_PHSYNC : V_NHSYNC;
3146 mode->Flags |= (fptable[modeofs + 30] & 0x1) ? V_PVSYNC : V_NVSYNC;
3149 * bytes 1-2 are "panel type", including bits on whether Colour/mono, single/dual link, and type (TFT etc.)
3150 * bytes 3-6 are bits per colour in RGBX
3153 * 13-14 is HValid Start
3154 * 15-16 is HValid End
3155 * bytes 38-39 relate to spread spectrum settings
3156 * bytes 40-43 are something to do with PWM */
3158 mode->prev = mode->next = NULL;
3159 mode->status = MODE_OK;
3160 mode->type = M_T_DRIVER | M_T_PREFERRED;
3161 xf86SetModeDefaultName(mode);
3163 // if (XF86_CRTC_CONFIG_PTR(pScrn)->debug_modes) {
3164 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3165 "Found flat panel mode in BIOS tables:\n");
3166 xf86PrintModeline(pScrn->scrnIndex, mode);
3169 bios->fp.native_mode = mode;
3172 void parse_lvds_manufacturer_table(ScrnInfoPtr pScrn, bios_t *bios, int pxclk)
3174 /* The LVDS table header is (mostly) described in
3175 * parse_lvds_manufacturer_table_header(): the BIT header additionally
3176 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
3177 * straps are not being used for the panel, this specifies the frequency
3178 * at which modes should be set up in the dual link style.
3180 * Following the header, the BMP (ver 0xa) table has several records,
3181 * indexed by a seperate xlat table, indexed in turn by the fp strap in
3182 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
3183 * numbers for use by INIT_SUB which controlled panel init and power,
3184 * and finally a dword of ms to sleep between power off and on
3187 * In the BIT versions, the table following the header serves as an
3188 * integrated config and xlat table: the records in the table are
3189 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
3190 * two bytes - the first as a config byte, the second for indexing the
3191 * fp mode table pointed to by the BIT 'D' table
3193 * Due to the stage at which DDC is used in X's DDX design, the EDID res
3194 * for a panel isn't known at init, so the tests against the pixel clock
3195 * in the EDID case for selection of the correct table entry and setting
3196 * of the dual link flag cannot be done until later - this function may
3197 * be called at runtime with a non-zero pxclk argument to perform these
3201 unsigned int lvdsmanufacturerindex = 0;
3202 struct lvdstableheader lth;
3205 parse_lvds_manufacturer_table_header(pScrn, bios, <h);
3207 switch (lth.lvds_ver) {
3208 case 0: /* header parsing failed */
3210 case 0x0a: /* pre NV40 */
3211 lvdsmanufacturerindex = bios->data[bios->fp.fpxlatemanufacturertableptr + (bios->fp.strapping & 0xf)];
3213 /* we're done if this isn't the EDID panel case */
3214 if (pxclk == 0 || (bios->fp.strapping & 0xf) != 0xf)
3217 /* change in behaviour guessed at nv30; see datapoints below */
3218 if (bios->chip_version < 0x30) {
3219 /* nv17 behaviour */
3220 lvdsmanufacturerindex = bios->fp.if_is_24bit ? 2 : 0;
3221 if (pxclk >= bios->fp.duallink_transition_clk)
3222 lvdsmanufacturerindex++;
3224 /* nv31, nv34 behaviour */
3225 lvdsmanufacturerindex = 0;
3226 if (pxclk >= bios->fp.duallink_transition_clk)
3227 lvdsmanufacturerindex = 2;
3228 if (pxclk >= 140000)
3229 lvdsmanufacturerindex = 3;
3232 /* nvidia set the high nibble of (cr57=f, cr58) to
3233 * lvdsmanufacturerindex in this case; we don't */
3235 case 0x30: /* NV4x */
3236 lvdsmanufacturerindex = bios->fp.strapping & 0xf;
3238 case 0x40: /* G80/G90 */
3240 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3241 "LVDS table revision not currently supported\n");
3245 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
3246 switch (lth.lvds_ver) {
3248 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
3249 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
3250 bios->fp.dual_link = bios->data[lvdsofs] & 4;
3251 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
3252 bios->fp.if_is_24bit = bios->data[lvdsofs] & 16;
3255 /* My money would be on there being a 24 bit interface bit in this table,
3256 * but I have no example of a laptop bios with a 24 bit panel to confirm that.
3257 * Hence we shout loudly if any bit other than bit 0 is set (I've not even
3260 if (bios->data[lvdsofs] > 1)
3261 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3262 "You have a very unusual laptop display; please report it\n");
3263 /* no sign of the "power off for reset" or "reset for panel on" bits, but it's safer to assume we should */
3264 bios->fp.power_off_for_reset = true;
3265 bios->fp.reset_after_pclk_change = true;
3266 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3267 bios->fp.BITbit1 = bios->data[lvdsofs] & 2;
3268 bios->fp.duallink_transition_clk = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3272 /* set dual_link flag for EDID case */
3273 if ((bios->fp.strapping & 0xf) == 0xf && pxclk) {
3274 if (pxclk >= bios->fp.duallink_transition_clk)
3275 bios->fp.dual_link = true;
3277 bios->fp.dual_link = false;
3281 void run_tmds_table(ScrnInfoPtr pScrn, struct dcb_entry *dcbent, int head, int pxclk)
3283 /* the pxclk parameter is in kHz
3285 * This runs the TMDS regs setting code found on BIT bios cards
3287 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
3288 * ffs(or) == 3, use the second.
3291 NVPtr pNv = NVPTR(pScrn);
3292 bios_t *bios = &pNv->VBIOS;
3293 uint16_t clktable = 0, scriptptr;
3294 uint32_t sel_clk_binding;
3296 if (dcbent->location != LOC_ON_CHIP)
3299 switch (ffs(dcbent->or)) {
3301 clktable = bios->tmds.output0_script_ptr;
3305 clktable = bios->tmds.output1_script_ptr;
3310 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Pixel clock comparison table not found\n");
3314 scriptptr = clkcmptable(bios, clktable, pxclk);
3317 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "TMDS output init script not found\n");
3321 /* don't let script change pll->head binding */
3322 sel_clk_binding = nv32_rd(pScrn, NV_RAMDAC_SEL_CLK) & 0x50000;
3323 rundigitaloutscript(pScrn, scriptptr, dcbent, head);
3324 nv32_wr(pScrn, NV_RAMDAC_SEL_CLK, (nv32_rd(pScrn, NV_RAMDAC_SEL_CLK) & ~0x50000) | sel_clk_binding);
3327 static int get_fp_strap(ScrnInfoPtr pScrn, bios_t *bios)
3329 /* the fp strap is normally dictated by the "User Strap" in
3330 * PEXTDEV_BOOT_0[20:16], but when bit 2 of the Internal_Flags struct
3331 * at 0x48 is set, the user strap gets overriden by the PCI subsystem
3332 * ID during POST, but not before the previous user strap has been
3333 * committed to CR58 for CR57=0xf on head A, which may be read and used
3337 if (bios->data[0x48] & 0x4)
3338 return (NVReadVgaCrtc5758(NVPTR(pScrn), 0, 0xf) & 0xf);
3340 return ((nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 16) & 0xf);
3343 static void parse_bios_version(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset)
3345 /* offset + 0 (8 bits): Micro version
3346 * offset + 1 (8 bits): Minor version
3347 * offset + 2 (8 bits): Chip version
3348 * offset + 3 (8 bits): Major version
3351 bios->major_version = bios->data[offset + 3];
3352 bios->chip_version = bios->data[offset + 2];
3353 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios version %02x.%02x.%02x.%02x\n",
3354 bios->data[offset + 3], bios->data[offset + 2],
3355 bios->data[offset + 1], bios->data[offset]);
3358 bool get_pll_limits(ScrnInfoPtr pScrn, uint32_t limit_match, struct pll_lims *pll_lim)
3362 * Version 0x10: NV31
3363 * One byte header (version), one record of 24 bytes
3364 * Version 0x11: NV36 - Not implemented
3365 * Seems to have same record style as 0x10, but 3 records rather than 1
3366 * Version 0x20: Found on Geforce 6 cards
3367 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
3368 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
3369 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
3370 * length in general, some (integrated) have an extra configuration byte
3373 NVPtr pNv = NVPTR(pScrn);
3374 bios_t *bios = &pNv->VBIOS;
3375 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
3377 uint32_t crystal_strap_mask, crystal_straps;
3379 if (!bios->pll_limit_tbl_ptr) {
3380 if (bios->chip_version >= 0x40 || bios->chip_version == 0x31 || bios->chip_version == 0x36) {
3381 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Pointer to PLL limits table invalid\n");
3385 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
3387 if (DEBUGLEVEL >= 7)
3388 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3389 "Found PLL limits table version 0x%X\n", pll_lim_ver);
3392 crystal_strap_mask = 1 << 6;
3393 /* open coded pNv->twoHeads test */
3394 if (bios->chip_version > 0x10 && bios->chip_version != 0x15 &&
3395 bios->chip_version != 0x1a && bios->chip_version != 0x20)
3396 crystal_strap_mask |= 1 << 22;
3397 crystal_straps = nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & crystal_strap_mask;
3399 switch (pll_lim_ver) {
3400 /* we use version 0 to indicate a pre limit table bios (single stage pll)
3401 * and load the hard coded limits instead */
3405 case 0x11: /* strictly v0x11 has 3 entries, but the last two don't seem to get used */
3413 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
3414 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
3415 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
3418 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3419 "PLL limits table revision not currently supported\n");
3423 /* initialize all members to zero */
3424 memset(pll_lim, 0, sizeof(struct pll_lims));
3426 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
3427 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex;
3429 pll_lim->vco1.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs])));
3430 pll_lim->vco1.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 4])));
3431 pll_lim->vco2.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 8])));
3432 pll_lim->vco2.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 12])));
3433 pll_lim->vco1.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 16])));
3434 pll_lim->vco2.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 20])));
3435 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
3437 /* these values taken from nv30/31/36 */
3438 pll_lim->vco1.min_n = 0x1;
3439 if (bios->chip_version == 0x36)
3440 pll_lim->vco1.min_n = 0x5;
3441 pll_lim->vco1.max_n = 0xff;
3442 pll_lim->vco1.min_m = 0x1;
3443 pll_lim->vco1.max_m = 0xd;
3444 pll_lim->vco2.min_n = 0x4;
3445 /* on nv30, 31, 36 (i.e. all cards with two stage PLLs with this
3446 * table version (apart from nv35)), N2 is compared to
3447 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
3450 pll_lim->vco2.max_n = 0x28;
3451 if (bios->chip_version == 0x30 || bios->chip_version == 0x35)
3452 /* only 5 bits available for N2 on nv30/35 */
3453 pll_lim->vco2.max_n = 0x1f;
3454 pll_lim->vco2.min_m = 0x1;
3455 pll_lim->vco2.max_m = 0x4;
3456 } else if (pll_lim_ver) { /* ver 0x20, 0x21 */
3457 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
3458 uint32_t reg = 0; /* default match */
3461 /* first entry is default match, if nothing better. warn if reg field nonzero */
3462 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs])))
3463 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3464 "Default PLL limit entry has non-zero register field\n");
3466 if (limit_match > MAX_PLL_TYPES)
3467 /* we've been passed a reg as the match */
3469 else /* limit match is a pll type */
3470 for (i = 1; i < entries && !reg; i++) {
3471 uint32_t cmpreg = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + recordlen * i])));
3473 if (limit_match == NVPLL && (cmpreg == NV_RAMDAC_NVPLL || cmpreg == 0x4000))
3475 if (limit_match == MPLL && (cmpreg == NV_RAMDAC_MPLL || cmpreg == 0x4020))
3477 if (limit_match == VPLL1 && (cmpreg == NV_RAMDAC_VPLL || cmpreg == 0x4010))
3479 if (limit_match == VPLL2 && (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018))
3483 for (i = 1; i < entries; i++)
3484 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs + recordlen * i])) == reg) {
3489 plloffs += recordlen * pllindex;
3491 if (DEBUGLEVEL >= 6)
3492 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Loading PLL limits for reg 0x%08x\n",
3493 pllindex ? reg : 0);
3495 /* frequencies are stored in tables in MHz, kHz are more useful, so we convert */
3497 /* What output frequencies can each VCO generate? */
3498 pll_lim->vco1.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 4]))) * 1000;
3499 pll_lim->vco1.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 6]))) * 1000;
3500 pll_lim->vco2.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 8]))) * 1000;
3501 pll_lim->vco2.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 10]))) * 1000;
3503 /* What input frequencies do they accept (past the m-divider)? */
3504 pll_lim->vco1.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 12]))) * 1000;
3505 pll_lim->vco2.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 14]))) * 1000;
3506 pll_lim->vco1.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 16]))) * 1000;
3507 pll_lim->vco2.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 18]))) * 1000;
3509 /* What values are accepted as multiplier and divider? */
3510 pll_lim->vco1.min_n = bios->data[plloffs + 20];
3511 pll_lim->vco1.max_n = bios->data[plloffs + 21];
3512 pll_lim->vco1.min_m = bios->data[plloffs + 22];
3513 pll_lim->vco1.max_m = bios->data[plloffs + 23];
3514 pll_lim->vco2.min_n = bios->data[plloffs + 24];
3515 pll_lim->vco2.max_n = bios->data[plloffs + 25];
3516 pll_lim->vco2.min_m = bios->data[plloffs + 26];
3517 pll_lim->vco2.max_m = bios->data[plloffs + 27];
3519 pll_lim->unk1c = bios->data[plloffs + 28];
3520 pll_lim->max_log2p_bias = bios->data[plloffs + 29];
3521 pll_lim->log2p_bias = bios->data[plloffs + 30];
3523 if (recordlen > 0x22)
3524 pll_lim->refclk = le32_to_cpu(*((uint32_t *)&bios->data[plloffs + 31]));
3526 if (recordlen > 0x23)
3527 if (bios->data[plloffs + 35])
3528 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3529 "Bits set in PLL configuration byte (%x)\n", bios->data[plloffs + 35]);
3531 /* C51 special not seen elsewhere */
3532 if (bios->chip_version == 0x51 && !pll_lim->refclk) {
3533 uint32_t sel_clk = nv32_rd(pScrn, NV_RAMDAC_SEL_CLK);
3535 if (((limit_match == NV_RAMDAC_VPLL || limit_match == VPLL1) && sel_clk & 0x20) ||
3536 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) {
3537 if (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_REVISION) < 0xa3)
3538 pll_lim->refclk = 200000;
3540 pll_lim->refclk = 25000;
3545 /* By now any valid limit table ought to have set a max frequency for
3546 * vco1, so if it's zero it's either a pre limit table bios, or one
3547 * with an empty limit table (seen on nv18)
3549 if (!pll_lim->vco1.maxfreq) {
3550 pll_lim->vco1.minfreq = bios->fminvco;
3551 pll_lim->vco1.maxfreq = bios->fmaxvco;
3552 pll_lim->vco1.min_inputfreq = 0;
3553 pll_lim->vco1.max_inputfreq = INT_MAX;
3554 pll_lim->vco1.min_n = 0x1;
3555 pll_lim->vco1.max_n = 0xff;
3556 pll_lim->vco1.min_m = 0x1;
3557 if (crystal_straps == 0) {
3558 /* nv05 does this, nv11 doesn't, nv10 unknown */
3559 if (bios->chip_version < 0x11)
3560 pll_lim->vco1.min_m = 0x7;
3561 pll_lim->vco1.max_m = 0xd;
3563 if (bios->chip_version < 0x11)
3564 pll_lim->vco1.min_m = 0x8;
3565 pll_lim->vco1.max_m = 0xe;
3569 if (!pll_lim->refclk)
3570 switch (crystal_straps) {
3572 pll_lim->refclk = 13500;
3575 pll_lim->refclk = 14318;
3578 pll_lim->refclk = 27000;
3580 case (1 << 22 | 1 << 6):
3581 pll_lim->refclk = 25000;
3585 #if 0 /* for easy debugging */
3586 ErrorF("pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
3587 ErrorF("pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
3588 ErrorF("pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
3589 ErrorF("pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
3591 ErrorF("pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
3592 ErrorF("pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
3593 ErrorF("pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
3594 ErrorF("pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
3596 ErrorF("pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
3597 ErrorF("pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
3598 ErrorF("pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
3599 ErrorF("pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
3600 ErrorF("pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
3601 ErrorF("pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
3602 ErrorF("pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
3603 ErrorF("pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
3605 ErrorF("pll.unk1c: %d\n", pll_lim->unk1c);
3606 ErrorF("pll.max_log2p_bias: %d\n", pll_lim->max_log2p_bias);
3607 ErrorF("pll.log2p_bias: %d\n", pll_lim->log2p_bias);
3609 ErrorF("pll.refclk: %d\n", pll_lim->refclk);
3615 static int parse_bit_C_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3617 /* offset + 8 (16 bits): PLL limits table pointer
3619 * There's more in here, but that's unknown.
3622 if (bitentry->length < 10) {
3623 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand BIT C table\n");
3627 bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
3632 static int parse_bit_display_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3634 /* Parses the flat panel table segment that the bit entry points to.
3635 * Starting at bitentry->offset:
3637 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte records beginning with a freq
3638 * offset + 2 (16 bits): mode table pointer
3641 struct fppointers fpp;
3643 if (bitentry->length != 4) {
3644 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand BIT display table\n");
3648 memset(&fpp, 0, sizeof(struct fppointers));
3649 fpp.fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
3651 parse_fp_mode_table(pScrn, bios, &fpp);
3656 static unsigned int parse_bit_init_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3658 /* Parses the init table segment that the bit entry points to.
3659 * Starting at bitentry->offset:
3661 * offset + 0 (16 bits): init script tables pointer
3662 * offset + 2 (16 bits): macro index table pointer
3663 * offset + 4 (16 bits): macro table pointer
3664 * offset + 6 (16 bits): condition table pointer
3665 * offset + 8 (16 bits): io condition table pointer
3666 * offset + 10 (16 bits): io flag condition table pointer
3667 * offset + 12 (16 bits): init function table pointer
3671 if (bitentry->length < 14) {
3672 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand init table\n");
3676 bios->init_script_tbls_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3677 bios->macro_index_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
3678 bios->macro_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 4])));
3679 bios->condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 6])));
3680 bios->io_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
3681 bios->io_flag_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 10])));
3682 bios->init_function_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 12])));
3687 static int parse_bit_i_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3689 /* BIT 'i' (info?) table
3691 * offset + 0 (32 bits): BIOS version dword (as in B table)
3692 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
3693 * offset + 13 (16 bits): pointer to table containing DAC load detection comparison values
3695 * There's other things in the table, purpose unknown
3698 uint16_t daccmpoffset;
3699 uint8_t dacversion, dacheaderlen;
3701 if (bitentry->length < 6) {
3702 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3703 "BIT i table not long enough for BIOS version and feature byte\n");
3707 parse_bios_version(pScrn, bios, bitentry->offset);
3709 /* bit 4 seems to indicate a mobile bios, other bits possibly as for BMP feature byte */
3710 bios->feature_byte = bios->data[bitentry->offset + 5];
3712 if (bitentry->length < 15) {
3713 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3714 "BIT i table not long enough for DAC load detection comparison table\n");
3718 daccmpoffset = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 13])));
3720 /* doesn't exist on g80 */
3724 /* The first value in the table, following the header, is the comparison value
3725 * Purpose of subsequent values unknown -- TV load detection?
3728 dacversion = bios->data[daccmpoffset];
3729 dacheaderlen = bios->data[daccmpoffset + 1];
3731 if (dacversion != 0x00 && dacversion != 0x10) {
3732 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3733 "DAC load detection comparison table version %d.%d not known\n",
3734 dacversion >> 4, dacversion & 0xf);
3737 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3738 "DAC load detection comparison table version %x found\n", dacversion);
3740 bios->dactestval = le32_to_cpu(*((uint32_t *)(&bios->data[daccmpoffset + dacheaderlen])));
3745 static int parse_bit_lvds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3747 /* Parses the LVDS table segment that the bit entry points to.
3748 * Starting at bitentry->offset:
3750 * offset + 0 (16 bits): LVDS strap xlate table pointer
3753 if (bitentry->length != 2) {
3754 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand BIT LVDS table\n");
3758 /* no idea if it's still called the LVDS manufacturer table, but the concept's close enough */
3759 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3760 bios->fp.strapping = get_fp_strap(pScrn, bios);
3762 parse_lvds_manufacturer_table(pScrn, bios, 0);
3767 static int parse_bit_M_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3769 /* offset + 2 (8 bits): number of options in an INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
3770 * offset + 3 (16 bits): pointer to strap xlate table for RAM restrict option selection
3772 * There's a bunch of bits in this table other than the RAM restrict
3773 * stuff that we don't use - their use currently unknown
3778 /* Older bios versions don't have a sufficiently long table for what we want */
3779 if (bitentry->length < 0x5)
3782 /* set up multiplier for INIT_RAM_RESTRICT_ZM_REG_GROUP */
3783 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != 0x8f); i++)
3785 itbl_entry[i].length_multiplier = bios->data[bitentry->offset + 2] * 4;
3786 init_ram_restrict_zm_reg_group_blocklen = itbl_entry[i].length_multiplier;
3788 bios->ram_restrict_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 3])));
3793 static int parse_bit_tmds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3795 /* Parses the pointer to the TMDS table
3797 * Starting at bitentry->offset:
3799 * offset + 0 (16 bits): TMDS table pointer
3801 * The TMDS table is typically found just before the DCB table, with a
3802 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
3805 * At offset +7 is a pointer to a script, which I don't know how to run yet
3806 * At offset +9 is a pointer to another script, likewise
3807 * Offset +11 has a pointer to a table where the first word is a pxclk
3808 * frequency and the second word a pointer to a script, which should be
3809 * run if the comparison pxclk frequency is less than the pxclk desired.
3810 * This repeats for decreasing comparison frequencies
3811 * Offset +13 has a pointer to a similar table
3812 * The selection of table (and possibly +7/+9 script) is dictated by
3813 * "or" from the DCB.
3816 uint16_t tmdstableptr, script1, script2;
3818 if (bitentry->length != 2) {
3819 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand BIT TMDS table\n");
3823 tmdstableptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3825 if (tmdstableptr == 0x0) {
3826 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Pointer to TMDS table invalid\n");
3830 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found TMDS table revision %d.%d\n",
3831 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
3833 /* These two scripts are odd: they don't seem to get run even when they are not stubbed */
3834 script1 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 7]));
3835 script2 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 9]));
3836 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
3837 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "TMDS table script pointers not stubbed\n");
3839 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 11]));
3840 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 13]));
3845 static void parse_bit_structure(ScrnInfoPtr pScrn, bios_t *bios, const uint16_t bitoffset)
3847 int entries = bios->data[bitoffset + 4];
3848 /* parse i first, I next (which needs C & M before it), and L before D */
3849 char parseorder[] = "iCMILDT";
3850 bit_entry_t bitentry;
3853 for (i = 0; i < sizeof(parseorder); i++) {
3854 for (j = 0, offset = bitoffset + 6; j < entries; j++, offset += 6) {
3855 bitentry.id[0] = bios->data[offset];
3856 bitentry.id[1] = bios->data[offset + 1];
3857 bitentry.length = le16_to_cpu(*((uint16_t *)&bios->data[offset + 2]));
3858 bitentry.offset = le16_to_cpu(*((uint16_t *)&bios->data[offset + 4]));
3860 if (bitentry.id[0] != parseorder[i])
3863 switch (bitentry.id[0]) {
3865 parse_bit_C_tbl_entry(pScrn, bios, &bitentry);
3868 if (bios->feature_byte & FEATURE_MOBILE)
3869 parse_bit_display_tbl_entry(pScrn, bios, &bitentry);
3872 parse_bit_init_tbl_entry(pScrn, bios, &bitentry);
3873 parse_init_tables(pScrn, bios);
3875 case 'i': /* info? */
3876 parse_bit_i_tbl_entry(pScrn, bios, &bitentry);
3879 if (bios->feature_byte & FEATURE_MOBILE)
3880 parse_bit_lvds_tbl_entry(pScrn, bios, &bitentry);
3882 case 'M': /* memory? */
3883 parse_bit_M_tbl_entry(pScrn, bios, &bitentry);
3886 parse_bit_tmds_tbl_entry(pScrn, bios, &bitentry);
3893 static void parse_bmp_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset)
3895 /* Parse the BMP structure for useful things
3897 * offset + 5: BMP major version
3898 * offset + 6: BMP minor version
3899 * offset + 10: BCD encoded BIOS version
3901 * offset + 18: init script table pointer (for bios versions < 5.10h)
3902 * offset + 20: extra init script table pointer (for bios versions < 5.10h)
3904 * offset + 24: memory init table pointer (used on early bios versions)
3905 * offset + 26: SDR memory sequencing setup data table
3906 * offset + 28: DDR memory sequencing setup data table
3908 * offset + 54: index of I2C CRTC pair to use for CRT output
3909 * offset + 55: index of I2C CRTC pair to use for TV output
3910 * offset + 56: index of I2C CRTC pair to use for flat panel output
3911 * offset + 58: write CRTC index for I2C pair 0
3912 * offset + 59: read CRTC index for I2C pair 0
3913 * offset + 60: write CRTC index for I2C pair 1
3914 * offset + 61: read CRTC index for I2C pair 1
3916 * offset + 67: maximum internal PLL frequency (single stage PLL)
3917 * offset + 71: minimum internal PLL frequency (single stage PLL)
3919 * offset + 75: script table pointers, as for parse_bit_init_tbl_entry
3921 * offset + 89: TMDS single link output A table pointer
3922 * offset + 91: TMDS single link output B table pointer
3923 * offset + 105: flat panel timings table pointer
3924 * offset + 107: flat panel strapping translation table pointer
3925 * offset + 117: LVDS manufacturer panel config table pointer
3926 * offset + 119: LVDS manufacturer strapping translation table pointer
3928 * offset + 142: PLL limits table pointer
3931 NVPtr pNv = NVPTR(pScrn);
3932 uint8_t bmp_version_major, bmp_version_minor;
3934 struct fppointers fpp;
3935 uint16_t legacy_scripts_offset, legacy_i2c_offset;
3937 memset(&fpp, 0, sizeof(struct fppointers));
3939 /* load needed defaults in case we can't parse this info */
3940 pNv->dcb_table.i2c_write[0] = 0x3f;
3941 pNv->dcb_table.i2c_read[0] = 0x3e;
3942 pNv->dcb_table.i2c_write[1] = 0x37;
3943 pNv->dcb_table.i2c_read[1] = 0x36;
3944 bios->fmaxvco = 256000;
3945 bios->fminvco = 128000;
3946 bios->fp.duallink_transition_clk = 90000;
3948 bmp_version_major = bios->data[offset + 5];
3949 bmp_version_minor = bios->data[offset + 6];
3951 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BMP version %d.%d\n",
3952 bmp_version_major, bmp_version_minor);
3954 /* Make sure that 0x36 is blank and can't be mistaken for a DCB pointer on early versions */
3955 if (bmp_version_major < 5)
3956 *(uint16_t *)&bios->data[0x36] = 0;
3958 /* Seems that the minor version was 1 for all major versions prior to 5 */
3959 /* Version 6 could theoretically exist, but I suspect BIT happened instead */
3960 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
3961 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "You have an unsupported BMP version. Please send in your bios\n");
3965 if (bmp_version_major == 0) /* nothing that's currently useful in this version */
3967 else if (bmp_version_major == 1)
3968 bmplength = 44; /* exact for 1.01 */
3969 else if (bmp_version_major == 2)
3970 bmplength = 48; /* exact for 2.01 */
3971 else if (bmp_version_major == 3)
3972 bmplength = 54; /* guessed - mem init tables added in this version */
3973 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) /* don't know if 5.0 exists... */
3974 bmplength = 62; /* guessed - BMP I2C indices added in version 4*/
3975 else if (bmp_version_minor < 0x6)
3976 bmplength = 67; /* exact for 5.01 */
3977 else if (bmp_version_minor < 0x10)
3978 bmplength = 75; /* exact for 5.06 */
3979 else if (bmp_version_minor == 0x10)
3980 bmplength = 89; /* exact for 5.10h */
3981 else if (bmp_version_minor < 0x14)
3982 bmplength = 118; /* exact for 5.11h */
3983 else if (bmp_version_minor < 0x24) /* not sure of version where pll limits came in;
3984 * certainly exist by 0x24 though */
3985 /* length not exact: this is long enough to get lvds members */
3987 else if (bmp_version_minor < 0x27)
3988 /* length not exact: this is long enough to get pll limit member */
3991 /* length not exact: this is long enough to get dual link transition clock */
3995 if (nv_cksum(bios->data + offset, 8)) {
3996 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Bad BMP checksum\n");
4000 /* bit 4 seems to indicate a mobile bios, bit 5 that the flat panel
4001 * tables are present, and bit 6 a tv bios */
4002 bios->feature_byte = bios->data[offset + 9];
4004 parse_bios_version(pScrn, bios, offset + 10);
4006 legacy_scripts_offset = offset + 18;
4007 if (bmp_version_major < 2)
4008 legacy_scripts_offset -= 4;
4009 bios->init_script_tbls_ptr = le16_to_cpu(*(uint16_t *)&bios->data[legacy_scripts_offset]);
4010 bios->extra_init_script_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[legacy_scripts_offset + 2]);
4012 if (bmp_version_major > 2) { /* appears in BMP 3 */
4013 bios->legacy.mem_init_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 24]);
4014 bios->legacy.sdr_seq_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 26]);
4015 bios->legacy.ddr_seq_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 28]);
4018 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
4020 legacy_i2c_offset = offset + 54;
4021 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
4022 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
4023 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
4024 pNv->dcb_table.i2c_write[0] = bios->data[legacy_i2c_offset + 4];
4025 pNv->dcb_table.i2c_read[0] = bios->data[legacy_i2c_offset + 5];
4026 pNv->dcb_table.i2c_write[1] = bios->data[legacy_i2c_offset + 6];
4027 pNv->dcb_table.i2c_read[1] = bios->data[legacy_i2c_offset + 7];
4029 if (bmplength > 74) {
4030 bios->fmaxvco = le32_to_cpu(*((uint32_t *)&bios->data[offset + 67]));
4031 bios->fminvco = le32_to_cpu(*((uint32_t *)&bios->data[offset + 71]));
4033 if (bmplength > 88) {
4034 bit_entry_t initbitentry;
4035 initbitentry.length = 14;
4036 initbitentry.offset = offset + 75;
4037 parse_bit_init_tbl_entry(pScrn, bios, &initbitentry);
4039 if (bmplength > 94) {
4040 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[offset + 89]));
4041 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[offset + 91]));
4042 /* it seems the old style lvds script pointer (which I've not observed in use) gets
4043 * reused as the 18/24 bit panel interface default for EDID equipped panels */
4044 bios->fp.if_is_24bit = bios->data[offset + 95] & 1;
4046 if (bmplength > 108) {
4047 fpp.fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 105])));
4048 fpp.fpxlatetableptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 107])));
4051 if (bmplength > 120) {
4052 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 117])));
4053 bios->fp.fpxlatemanufacturertableptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 119])));
4055 if (bmplength > 143)
4056 bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 142])));
4058 if (bmplength > 157)
4059 bios->fp.duallink_transition_clk = le16_to_cpu(*((uint16_t *)&bios->data[offset + 156])) * 10;
4061 /* want pll_limit_tbl_ptr set (if available) before init is run */
4062 if (bmp_version_major < 5 || bmp_version_minor < 0x10) {
4063 init_exec_t iexec = {true, false};
4064 if (bios->init_script_tbls_ptr)
4065 parse_init_table(pScrn, bios, bios->init_script_tbls_ptr, &iexec);
4066 if (bios->extra_init_script_tbl_ptr)
4067 parse_init_table(pScrn, bios, bios->extra_init_script_tbl_ptr, &iexec);
4069 parse_init_tables(pScrn, bios);
4071 /* If it's not a laptop, you probably don't care about fptables */
4072 if (!(bios->feature_byte & FEATURE_MOBILE))
4075 bios->fp.strapping = get_fp_strap(pScrn, bios);
4076 parse_lvds_manufacturer_table(pScrn, bios, 0);
4077 parse_fp_mode_table(pScrn, bios, &fpp);
4080 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
4084 for (i = 0; i <= (n - len); i++) {
4085 for (j = 0; j < len; j++)
4086 if (data[i + j] != str[j])
4096 read_dcb_i2c_entry(ScrnInfoPtr pScrn, uint8_t dcb_version, uint16_t i2ctabptr, int index)
4098 NVPtr pNv = NVPTR(pScrn);
4099 bios_t *bios = &pNv->VBIOS;
4100 uint8_t *i2ctable = &bios->data[i2ctabptr];
4101 uint8_t headerlen = 0;
4102 int i2c_entries = MAX_NUM_DCB_ENTRIES;
4103 int recordoffset = 0, rdofs = 1, wrofs = 0;
4108 if (dcb_version >= 0x30) {
4109 if (i2ctable[0] != dcb_version) /* necessary? */
4110 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4111 "DCB I2C table version mismatch (%02X vs %02X)\n",
4112 i2ctable[0], dcb_version);
4113 headerlen = i2ctable[1];
4114 i2c_entries = i2ctable[2];
4116 /* same address offset used for read and write for C51 and G80 */
4117 if (bios->chip_version == 0x51)
4119 if (i2ctable[0] >= 0x40)
4122 /* it's your own fault if you call this function on a DCB 1.1 BIOS --
4123 * the test below is for DCB 1.2
4125 if (dcb_version < 0x14) {
4133 if (index > i2c_entries) {
4134 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4135 "DCB I2C index too big (%d > %d)\n",
4136 index, i2ctable[2]);
4139 if (i2ctable[headerlen + 4 * index + 3] == 0xff) {
4140 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4141 "DCB I2C entry invalid\n");
4145 if (bios->chip_version == 0x51) {
4146 int port_type = i2ctable[headerlen + 4 * index + 3];
4149 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4150 "DCB I2C table has port type %d\n", port_type);
4152 if (i2ctable[0] >= 0x40) {
4153 int port_type = i2ctable[headerlen + 4 * index + 3];
4156 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4157 "DCB I2C table has port type %d\n", port_type);
4160 pNv->dcb_table.i2c_read[index] = i2ctable[headerlen + recordoffset + rdofs + 4 * index];
4161 pNv->dcb_table.i2c_write[index] = i2ctable[headerlen + recordoffset + wrofs + 4 * index];
4165 parse_dcb_entry(ScrnInfoPtr pScrn, int index, uint8_t dcb_version, uint16_t i2ctabptr, uint32_t conn, uint32_t conf)
4167 NVPtr pNv = NVPTR(pScrn);
4168 struct dcb_entry *entry = &pNv->dcb_table.entry[index];
4170 memset(entry, 0, sizeof (struct dcb_entry));
4172 entry->index = index;
4173 /* safe defaults for a crt */
4175 entry->i2c_index = 0;
4178 entry->location = LOC_ON_CHIP;
4180 entry->duallink_possible = false;
4182 if (dcb_version >= 0x20) {
4183 entry->type = conn & 0xf;
4184 entry->i2c_index = (conn >> 4) & 0xf;
4185 entry->heads = (conn >> 8) & 0xf;
4186 entry->bus = (conn >> 16) & 0xf;
4187 entry->location = (conn >> 20) & 0xf;
4188 entry->or = (conn >> 24) & 0xf;
4189 /* Normal entries consist of a single bit, but dual link has the
4190 * adjacent more significant bit set too
4192 if ((1 << (ffs(entry->or) - 1)) * 3 == entry->or)
4193 entry->duallink_possible = true;
4195 switch (entry->type) {
4200 entry->lvdsconf.use_straps_for_mode = true;
4201 if (dcb_version < 0x22) {
4203 /* both 0x4 and 0x8 show up in v2.0 tables; assume they mean
4204 * the same thing, which is probably wrong, but might work */
4205 if (conf & 0x4 || conf & 0x8)
4206 entry->lvdsconf.use_power_scripts = true;
4210 entry->lvdsconf.use_power_scripts = true;
4213 /* I'm bored of getting this reported; left as a reminder for someone to fix it */
4214 if (dcb_version >= 0x40) {
4215 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4216 "G80+ LVDS not initialized by driver; ignoring conf bits\n");
4219 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4220 "Unknown LVDS configuration bits, please report\n");
4221 /* cause output setting to fail, so message is seen */
4222 pNv->dcb_table.entries = 0;
4228 /* weird type that appears on g80 mobile bios; nv driver treats it as a terminator */
4231 read_dcb_i2c_entry(pScrn, dcb_version, i2ctabptr, entry->i2c_index);
4232 } else if (dcb_version >= 0x14 ) {
4233 if (conn != 0xf0003f00 && conn != 0xf2247f10 &&
4234 conn != 0xf2204001 && conn != 0xf2204301 && conn != 0xf2204311 && conn != 0xf2208001 && conn != 0xf2244001 && conn != 0xf2244311 && conn != 0xf4204011 && conn != 0xf4208011 && conn != 0xf4248011 &&
4235 conn != 0xf2045f14 && conn != 0xf2205004) {
4236 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4237 "Unknown DCB 1.4 / 1.5 entry, please report\n");
4238 /* cause output setting to fail, so message is seen */
4239 pNv->dcb_table.entries = 0;
4242 /* most of the below is a "best guess" atm */
4243 entry->type = conn & 0xf;
4244 if (entry->type == 4) { /* digital */
4246 entry->type = OUTPUT_LVDS;
4248 entry->type = OUTPUT_TMDS;
4250 /* what's in bits 5-13? could be some brooktree/chrontel/philips thing, in tv case */
4251 entry->i2c_index = (conn >> 14) & 0xf;
4252 /* raw heads field is in range 0-1, so move to 1-2 */
4253 entry->heads = ((conn >> 18) & 0x7) + 1;
4254 entry->location = (conn >> 21) & 0xf;
4255 entry->bus = (conn >> 25) & 0x7;
4256 /* set or to be same as heads -- hopefully safe enough */
4257 entry->or = entry->heads;
4259 switch (entry->type) {
4261 /* this is probably buried in conn's unknown bits */
4262 entry->lvdsconf.use_power_scripts = true;
4265 /* invent a DVI-A output, by copying the fields of the DVI-D output
4266 * reported to work by math_b on an NV20(!) */
4267 memcpy(&entry[1], &entry[0], sizeof(struct dcb_entry));
4268 entry[1].type = OUTPUT_ANALOG;
4269 pNv->dcb_table.entries++;
4271 read_dcb_i2c_entry(pScrn, dcb_version, i2ctabptr, entry->i2c_index);
4272 } else if (dcb_version >= 0x12) {
4273 /* v1.2 tables normally have the same 5 entries, which are not
4274 * specific to the card, so use the defaults for a crt */
4275 /* DCB v1.2 does have an I2C table that read_dcb_i2c_table can handle, but cards
4276 * exist (seen on nv11) where the pointer to the table points to the wrong
4277 * place, so for now, we rely on the indices parsed in parse_bmp_structure
4279 entry->i2c_index = pNv->VBIOS.legacy.i2c_indices.crt;
4280 } else { /* pre DCB / v1.1 - use the safe defaults for a crt */
4281 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4282 "No information in BIOS output table; assuming a CRT output exists\n");
4283 entry->i2c_index = pNv->VBIOS.legacy.i2c_indices.crt;
4286 if (entry->type == OUTPUT_LVDS && pNv->VBIOS.fp.strapping != 0xff)
4287 entry->lvdsconf.use_straps_for_mode = true;
4289 pNv->dcb_table.entries++;
4294 void merge_like_dcb_entries(ScrnInfoPtr pScrn)
4296 /* DCB v2.0 lists each output combination separately.
4297 * Here we merge compatible entries to have fewer outputs, with more options
4300 NVPtr pNv = NVPTR(pScrn);
4301 int i, newentries = 0;
4303 for (i = 0; i < pNv->dcb_table.entries; i++) {
4304 struct dcb_entry *ient = &pNv->dcb_table.entry[i];
4307 for (j = i + 1; j < pNv->dcb_table.entries; j++) {
4308 struct dcb_entry *jent = &pNv->dcb_table.entry[j];
4310 if (jent->type == 100) /* already merged entry */
4313 /* merge heads field when all other fields the same */
4314 if (jent->i2c_index == ient->i2c_index && jent->type == ient->type && jent->location == ient->location && jent->or == ient->or) {
4315 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4316 "Merging DCB entries %d and %d\n", i, j);
4317 ient->heads |= jent->heads;
4318 jent->type = 100; /* dummy value */
4323 /* Compact entries merged into others out of dcb_table */
4324 for (i = 0; i < pNv->dcb_table.entries; i++) {
4325 if ( pNv->dcb_table.entry[i].type == 100 )
4328 if (newentries != i)
4329 memcpy(&pNv->dcb_table.entry[newentries], &pNv->dcb_table.entry[i], sizeof(struct dcb_entry));
4333 pNv->dcb_table.entries = newentries;
4336 static unsigned int parse_dcb_table(ScrnInfoPtr pScrn, bios_t *bios)
4338 NVPtr pNv = NVPTR(pScrn);
4339 uint16_t dcbptr, i2ctabptr = 0;
4341 uint8_t dcb_version, headerlen = 0x4, entries = MAX_NUM_DCB_ENTRIES;
4342 bool configblock = true;
4343 int recordlength = 8, confofs = 4;
4346 pNv->dcb_table.entries = 0;
4348 /* get the offset from 0x36 */
4349 dcbptr = le16_to_cpu(*(uint16_t *)&bios->data[0x36]);
4351 if (dcbptr == 0x0) {
4352 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4353 "No Display Configuration Block pointer found\n");
4354 /* this situation likely means a really old card, pre DCB, so we'll add the safe CRT entry */
4355 parse_dcb_entry(pScrn, 0, 0, 0, 0, 0);
4359 dcbtable = &bios->data[dcbptr];
4361 /* get DCB version */
4362 dcb_version = dcbtable[0];
4363 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4364 "Display Configuration Block version %d.%d found\n",
4365 dcb_version >> 4, dcb_version & 0xf);
4367 if (dcb_version >= 0x20) { /* NV17+ */
4370 if (dcb_version >= 0x30) { /* NV40+ */
4371 headerlen = dcbtable[1];
4372 entries = dcbtable[2];
4373 recordlength = dcbtable[3];
4374 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[4]);
4375 sig = le32_to_cpu(*(uint32_t *)&dcbtable[6]);
4377 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4378 "DCB header length %d, with %d possible entries\n",
4379 headerlen, entries);
4381 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
4382 sig = le32_to_cpu(*(uint32_t *)&dcbtable[4]);
4386 if (sig != 0x4edcbdcb) {
4387 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4388 "Bad Display Configuration Block signature (%08X)\n", sig);
4391 } else if (dcb_version >= 0x14) { /* some NV15/16, and NV11+ */
4395 strncpy(sig, (char *)&dcbtable[-7], 7);
4396 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
4400 if (strcmp(sig, "DEV_REC")) {
4401 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4402 "Bad Display Configuration Block signature (%s)\n", sig);
4405 } else if (dcb_version >= 0x12) { /* some NV6/10, and NV15+ */
4406 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
4407 configblock = false;
4408 } else { /* NV5+, maybe NV4 */
4409 /* DCB 1.1 seems to be quite unhelpful - we'll just add the safe CRT entry */
4410 parse_dcb_entry(pScrn, 0, dcb_version, 0, 0, 0);
4414 if (entries >= MAX_NUM_DCB_ENTRIES)
4415 entries = MAX_NUM_DCB_ENTRIES;
4417 for (i = 0; i < entries; i++) {
4418 uint32_t connection, config = 0;
4420 connection = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + recordlength * i]);
4422 config = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + confofs + recordlength * i]);
4424 /* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
4425 if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
4427 if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */
4430 ErrorF("Raw DCB entry %d: %08x %08x\n", i, connection, config);
4431 if (!parse_dcb_entry(pScrn, pNv->dcb_table.entries, dcb_version, i2ctabptr, connection, config))
4435 merge_like_dcb_entries(pScrn);
4437 return pNv->dcb_table.entries;
4440 static void load_nv17_hw_sequencer_ucode(ScrnInfoPtr pScrn, bios_t *bios, uint16_t hwsq_offset, int entry)
4442 /* BMP based cards, from NV17, need a microcode loading to correctly
4443 * control the GPIO etc for LVDS panels
4445 * BIT based cards seem to do this directly in the init scripts
4447 * The microcode entries are found by the "HWSQ" signature.
4448 * The header following has the number of entries, and the entry size
4450 * An entry consists of a dword to write to the sequencer control reg
4451 * (0x00001304), followed by the ucode bytes, written sequentially,
4452 * starting at reg 0x00001400
4455 uint8_t bytes_to_write;
4456 uint16_t hwsq_entry_offset;
4459 if (bios->data[hwsq_offset] <= entry) {
4460 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4461 "Too few entries in HW sequencer table for requested entry\n");
4465 bytes_to_write = bios->data[hwsq_offset + 1];
4467 if (bytes_to_write != 36) {
4468 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unknown HW sequencer entry size\n");
4472 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Loading NV17 power sequencing microcode\n");
4474 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
4476 /* set sequencer control */
4477 nv32_wr(pScrn, 0x00001304, le32_to_cpu(*(uint32_t *)&bios->data[hwsq_entry_offset]));
4478 bytes_to_write -= 4;
4481 for (i = 0; i < bytes_to_write; i += 4)
4482 nv32_wr(pScrn, 0x00001400 + i, le32_to_cpu(*(uint32_t *)&bios->data[hwsq_entry_offset + i + 4]));
4484 /* twiddle NV_PBUS_DEBUG_4 */
4485 nv32_wr(pScrn, NV_PBUS_DEBUG_4, nv32_rd(pScrn, NV_PBUS_DEBUG_4) | 0x18);
4488 static void read_bios_edid(ScrnInfoPtr pScrn)
4490 bios_t *bios = &NVPTR(pScrn)->VBIOS;
4491 const uint8_t edid_sig[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
4492 uint16_t offset = 0, newoffset;
4493 int searchlen = NV_PROM_SIZE, i;
4496 if (!(newoffset = findstr(&bios->data[offset], searchlen, edid_sig, 8)))
4498 offset += newoffset;
4499 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
4502 searchlen -= offset;
4506 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found EDID in BIOS\n");
4508 bios->fp.edid = xalloc(EDID1_LEN);
4509 for (i = 0; i < EDID1_LEN; i++)
4510 bios->fp.edid[i] = bios->data[offset + i];
4513 bool NVInitVBIOS(ScrnInfoPtr pScrn)
4515 NVPtr pNv = NVPTR(pScrn);
4517 memset(&pNv->VBIOS, 0, sizeof(bios_t));
4518 pNv->VBIOS.data = xalloc(NV_PROM_SIZE);
4520 if (!NVShadowVBIOS(pScrn, pNv->VBIOS.data)) {
4521 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4522 "No valid BIOS image found\n");
4523 xfree(pNv->VBIOS.data);
4527 pNv->VBIOS.length = pNv->VBIOS.data[2] * 512;
4528 if (pNv->VBIOS.length > NV_PROM_SIZE)
4529 pNv->VBIOS.length = NV_PROM_SIZE;
4534 bool NVRunVBIOSInit(ScrnInfoPtr pScrn)
4536 NVPtr pNv = NVPTR(pScrn);
4537 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
4538 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
4539 int offset, ret = 0;
4541 crtc_access(pScrn, ACCESS_UNLOCK);
4543 if ((offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, bit_signature, sizeof(bit_signature)))) {
4544 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIT BIOS found\n");
4545 parse_bit_structure(pScrn, &pNv->VBIOS, offset + 6);
4546 } else if ((offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, bmp_signature, sizeof(bmp_signature)))) {
4547 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
4550 if ((hwsq_offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, hwsq_signature, sizeof(hwsq_signature))))
4551 /* always use entry 0? */
4552 load_nv17_hw_sequencer_ucode(pScrn, &pNv->VBIOS, hwsq_offset + sizeof(hwsq_signature), 0);
4554 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BMP BIOS found\n");
4555 parse_bmp_structure(pScrn, &pNv->VBIOS, offset);
4557 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4558 "No known BIOS signature found\n");
4562 crtc_access(pScrn, ACCESS_LOCK);
4570 unsigned int NVParseBios(ScrnInfoPtr pScrn)
4572 NVPtr pNv = NVPTR(pScrn);
4573 uint32_t saved_nv_pextdev_boot_0;
4576 if (!NVInitVBIOS(pScrn))
4579 /* these will need remembering across a suspend */
4580 saved_nv_pextdev_boot_0 = nv32_rd(pScrn, NV_PEXTDEV_BOOT_0);
4581 saved_nv_pfb_cfg0 = nv32_rd(pScrn, NV_PFB_CFG0);
4583 /* init script execution disabled */
4584 pNv->VBIOS.execute = false;
4586 nv32_wr(pScrn, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
4588 if (!NVRunVBIOSInit(pScrn))
4591 if (parse_dcb_table(pScrn, &pNv->VBIOS))
4592 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4593 "Found %d entries in DCB\n", pNv->dcb_table.entries);
4595 for (i = 0 ; i < pNv->dcb_table.entries; i++)
4596 if (pNv->dcb_table.entry[i].type == OUTPUT_LVDS)
4597 call_lvds_script(pScrn, &pNv->dcb_table.entry[i], nv_get_digital_bound_head(pNv, pNv->dcb_table.entry[i].or), LVDS_INIT, 0);
4599 if (pNv->VBIOS.feature_byte & FEATURE_MOBILE && !pNv->VBIOS.fp.native_mode)
4600 read_bios_edid(pScrn);
4602 /* allow subsequent scripts to execute */
4603 pNv->VBIOS.execute = true;