git.oblomov.eu Git - nouveau/blob - src/nv_output.c

   1 /*
   2  * Copyright 2003 NVIDIA, Corporation
   3  * Copyright 2006 Dave Airlie
   4  * Copyright 2007 Maarten Maathuis
   5  * Copyright 2007-2008 Stuart Bennett
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  23  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "xf86.h"
  32 #include "os.h"
  33 #include "mibank.h"
  34 #include "globals.h"
  35 #include "xf86.h"
  36 #include "xf86Priv.h"
  37 #include "xf86DDC.h"
  38 #include "mipointer.h"
  39 #include "windowstr.h"
  40 #include <randrstr.h>
  41 #include <X11/extensions/render.h>
  42 #include "X11/Xatom.h"
  43
  44 #include "xf86Crtc.h"
  45 #include "nv_include.h"
  46
  47 #define MULTIPLE_ENCODERS(e) (e & (e - 1))
  48 #define FOR_EACH_ENCODER_IN_CONNECTOR(i, c, e)  for (i = 0; i < pNv->dcb_table.entries; i++)    \
  49                                                         if (c->possible_encoders & (1 << i) &&  \
  50                                                             (e = &pNv->encoders[i]))
  51
  52 static Atom scaling_mode_atom;
  53 static Atom dithering_atom;
  54
  55 static int nv_output_ramdac_offset(struct nouveau_encoder *nv_encoder)
  56 {
  57         int offset = 0;
  58
  59         if (nv_encoder->dcb->or & (8 | OUTPUT_C))
  60                 offset += 0x68;
  61         if (nv_encoder->dcb->or & (8 | OUTPUT_B))
  62                 offset += 0x2000;
  63
  64         return offset;
  65 }
  66
  67 static void dpms_update_fp_control(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
  68 {
  69         NVPtr pNv = NVPTR(pScrn);
  70         struct nouveau_crtc *nv_crtc;
  71         NVCrtcRegPtr regp;
  72         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
  73         int i;
  74
  75         if (mode == DPMSModeOn) {
  76                 nv_crtc = to_nouveau_crtc(crtc);
  77                 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
  78
  79                 nv_crtc->fp_users |= 1 << nv_encoder->dcb->index;
  80                 NVWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control & ~0x20000022);
  81         } else
  82                 for (i = 0; i <= pNv->twoHeads; i++) {
  83                         nv_crtc = to_nouveau_crtc(xf86_config->crtc[i]);
  84                         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
  85
  86                         nv_crtc->fp_users &= ~(1 << nv_encoder->dcb->index);
  87                         if (!nv_crtc->fp_users) {
  88                                 /* cut the FP output */
  89                                 regp->fp_control |= 0x20000022;
  90                                 NVWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
  91                         }
  92                 }
  93 }
  94
  95 static void nv_digital_output_prepare_sel_clk(NVPtr pNv, struct nouveau_encoder *nv_encoder, int head);
  96
  97 static void
  98 lvds_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
  99 {
 100         NVPtr pNv = NVPTR(pScrn);
 101
 102         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "lvds_encoder_dpms is called with mode %d\n", mode);
 103
 104         if (nv_encoder->last_dpms == mode)
 105                 return;
 106         nv_encoder->last_dpms = mode;
 107
 108         if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
 109                 /* when removing an output, crtc may not be set, but PANEL_OFF must still be run */
 110                 int head = nv_get_digital_bound_head(pNv, nv_encoder->dcb->or);
 111                 int pclk = nv_encoder->native_mode->Clock;
 112
 113                 if (crtc)
 114                         head = to_nouveau_crtc(crtc)->head;
 115
 116                 if (mode == DPMSModeOn)
 117                         call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_ON, pclk);
 118                 else
 119                         call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_OFF, pclk);
 120         }
 121
 122         dpms_update_fp_control(pScrn, nv_encoder, crtc, mode);
 123
 124         if (mode == DPMSModeOn)
 125                 nv_digital_output_prepare_sel_clk(pNv, nv_encoder, to_nouveau_crtc(crtc)->head);
 126         else {
 127                 pNv->ModeReg.sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 128                 pNv->ModeReg.sel_clk &= ~0xf0;
 129         }
 130         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
 131 }
 132
 133 static void
 134 vga_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 135 {
 136         NVPtr pNv = NVPTR(pScrn);
 137
 138         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vga_encoder_dpms is called with mode %d\n", mode);
 139
 140         if (nv_encoder->last_dpms == mode)
 141                 return;
 142         nv_encoder->last_dpms = mode;
 143
 144         if (pNv->twoHeads) {
 145                 uint32_t outputval = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder));
 146
 147                 if (mode == DPMSModeOff)
 148                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 149                                       outputval & ~NV_RAMDAC_OUTPUT_DAC_ENABLE);
 150                 else if (mode == DPMSModeOn)
 151                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 152                                       outputval | NV_RAMDAC_OUTPUT_DAC_ENABLE);
 153         }
 154 }
 155
 156 static void
 157 tmds_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 158 {
 159         NVPtr pNv = NVPTR(pScrn);
 160
 161         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "tmds_encoder_dpms is called with mode %d\n", mode);
 162
 163         if (nv_encoder->last_dpms == mode)
 164                 return;
 165         nv_encoder->last_dpms = mode;
 166
 167         dpms_update_fp_control(pScrn, nv_encoder, crtc, mode);
 168
 169         if (nv_encoder->dcb->location != LOC_ON_CHIP) {
 170                 struct nouveau_crtc *nv_crtc;
 171                 int i;
 172
 173                 if (mode == DPMSModeOn) {
 174                         nv_crtc = to_nouveau_crtc(crtc);
 175                         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD,
 176                                        pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_VGA_CRTCX_LCD]);
 177                 } else
 178                         for (i = 0; i <= pNv->twoHeads; i++)
 179                                 NVWriteVgaCrtc(pNv, i, NV_VGA_CRTCX_LCD,
 180                                                NVReadVgaCrtc(pNv, i, NV_VGA_CRTCX_LCD) & ~((nv_encoder->dcb->or << 4) & 0x30));
 181         }
 182 }
 183
 184 static void nv_output_dpms(xf86OutputPtr output, int mode)
 185 {
 186         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 187         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 188         ScrnInfoPtr pScrn = output->scrn;
 189         xf86CrtcPtr crtc = output->crtc;
 190         NVPtr pNv = NVPTR(pScrn);
 191         int i;
 192         void (* const encoder_dpms[4])(ScrnInfoPtr, struct nouveau_encoder *, xf86CrtcPtr, int) =
 193                 /* index matches DCB type */
 194                 { vga_encoder_dpms, NULL, tmds_encoder_dpms, lvds_encoder_dpms };
 195
 196         struct nouveau_encoder *nv_encoder_i;
 197         FOR_EACH_ENCODER_IN_CONNECTOR(i, nv_connector, nv_encoder_i)
 198                 if (nv_encoder_i != nv_encoder)
 199                         encoder_dpms[nv_encoder_i->dcb->type](pScrn, nv_encoder_i, crtc, DPMSModeOff);
 200
 201         if (nv_encoder) /* may be called before encoder is picked, but iteration above solves it */
 202                 encoder_dpms[nv_encoder->dcb->type](pScrn, nv_encoder, crtc, mode);
 203 }
 204
 205 void nv_encoder_save(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
 206 {
 207         NVPtr pNv = NVPTR(pScrn);
 208
 209         if (!nv_encoder->dcb)   /* uninitialised encoder */
 210                 return;
 211
 212         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_encoder_save is called.\n");
 213
 214         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
 215                 nv_encoder->restore.output = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder));
 216         if (nv_encoder->dcb->type == OUTPUT_TMDS || nv_encoder->dcb->type == OUTPUT_LVDS)
 217                 nv_encoder->restore.head = nv_get_digital_bound_head(pNv, nv_encoder->dcb->or);
 218 }
 219
 220 static uint32_t nv_get_clock_from_crtc(ScrnInfoPtr pScrn, RIVA_HW_STATE *state, uint8_t crtc)
 221 {
 222         NVPtr pNv = NVPTR(pScrn);
 223         struct pll_lims pll_lim;
 224         uint32_t vplla = state->crtc_reg[crtc].vpll_a;
 225         uint32_t vpllb = state->crtc_reg[crtc].vpll_b;
 226         bool nv40_single = pNv->Architecture == 0x40 &&
 227                            ((!crtc && state->reg580 & NV_RAMDAC_580_VPLL1_ACTIVE) ||
 228                             (crtc && state->reg580 & NV_RAMDAC_580_VPLL2_ACTIVE));
 229
 230         if (!get_pll_limits(pScrn, crtc ? VPLL2 : VPLL1, &pll_lim))
 231                 return 0;
 232
 233         return nv_decode_pll_highregs(pNv, vplla, vpllb, nv40_single, pll_lim.refclk);
 234 }
 235
 236 void nv_encoder_restore(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
 237 {
 238         NVPtr pNv = NVPTR(pScrn);
 239         int head = nv_encoder->restore.head;
 240
 241         if (!nv_encoder->dcb)   /* uninitialised encoder */
 242                 return;
 243
 244         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_encoder_restore is called.\n");
 245
 246         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
 247                 NVWriteRAMDAC(pNv, 0,
 248                               NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 249                               nv_encoder->restore.output);
 250         if (nv_encoder->dcb->type == OUTPUT_LVDS)
 251                 call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_ON,
 252                                  nv_encoder->native_mode->Clock);
 253         if (nv_encoder->dcb->type == OUTPUT_TMDS) {
 254                 int clock = nv_get_clock_from_crtc(pScrn, &pNv->SavedReg, head);
 255
 256                 run_tmds_table(pScrn, nv_encoder->dcb, head, clock);
 257         }
 258
 259         nv_encoder->last_dpms = NV_DPMS_CLEARED;
 260 }
 261
 262 static int nv_output_mode_valid(xf86OutputPtr output, DisplayModePtr mode)
 263 {
 264         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 265         NVPtr pNv = NVPTR(output->scrn);
 266
 267         if (!output->doubleScanAllowed && mode->Flags & V_DBLSCAN)
 268                 return MODE_NO_DBLESCAN;
 269         if (!output->interlaceAllowed && mode->Flags & V_INTERLACE)
 270                 return MODE_NO_INTERLACE;
 271
 272         if (nv_encoder->dcb->type == OUTPUT_ANALOG) {
 273                 if (mode->Clock > (pNv->twoStagePLL ? 400000 : 350000))
 274                         return MODE_CLOCK_HIGH;
 275                 if (mode->Clock < 12000)
 276                         return MODE_CLOCK_LOW;
 277         }
 278         if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS)
 279                 /* No modes > panel's native res */
 280                 if (mode->HDisplay > nv_encoder->native_mode->HDisplay ||
 281                     mode->VDisplay > nv_encoder->native_mode->VDisplay)
 282                         return MODE_PANEL;
 283         if (nv_encoder->dcb->type == OUTPUT_TMDS) {
 284                 if (nv_encoder->dcb->duallink_possible) {
 285                         if (mode->Clock > 330000) /* 2x165 MHz */
 286                                 return MODE_CLOCK_HIGH;
 287                 } else {
 288                         if (mode->Clock > 165000) /* 165 MHz */
 289                                 return MODE_CLOCK_HIGH;
 290                 }
 291         }
 292
 293         return MODE_OK;
 294 }
 295
 296 static Bool
 297 nv_output_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
 298                      DisplayModePtr adjusted_mode)
 299 {
 300         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 301         ScrnInfoPtr pScrn = output->scrn;
 302
 303         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_mode_fixup is called.\n");
 304
 305         /* For internal panels and gpu scaling on DVI we need the native mode */
 306         if (nv_encoder->dcb->type == OUTPUT_LVDS ||
 307             (nv_encoder->dcb->type == OUTPUT_TMDS && nv_encoder->scaling_mode != SCALE_PANEL)) {
 308                 adjusted_mode->HDisplay = nv_encoder->native_mode->HDisplay;
 309                 adjusted_mode->HSkew = nv_encoder->native_mode->HSkew;
 310                 adjusted_mode->HSyncStart = nv_encoder->native_mode->HSyncStart;
 311                 adjusted_mode->HSyncEnd = nv_encoder->native_mode->HSyncEnd;
 312                 adjusted_mode->HTotal = nv_encoder->native_mode->HTotal;
 313                 adjusted_mode->VDisplay = nv_encoder->native_mode->VDisplay;
 314                 adjusted_mode->VScan = nv_encoder->native_mode->VScan;
 315                 adjusted_mode->VSyncStart = nv_encoder->native_mode->VSyncStart;
 316                 adjusted_mode->VSyncEnd = nv_encoder->native_mode->VSyncEnd;
 317                 adjusted_mode->VTotal = nv_encoder->native_mode->VTotal;
 318                 adjusted_mode->Clock = nv_encoder->native_mode->Clock;
 319                 adjusted_mode->Flags = nv_encoder->native_mode->Flags;
 320
 321                 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
 322         }
 323
 324         return TRUE;
 325 }
 326
 327 static void
 328 nv_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 329 {
 330         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 331         ScrnInfoPtr pScrn = output->scrn;
 332         NVPtr pNv = NVPTR(pScrn);
 333         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(output->crtc);
 334
 335         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_mode_set is called.\n");
 336
 337         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
 338                 /* bit 16-19 are bits that are set on some G70 cards,
 339                  * but don't seem to have much effect */
 340                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 341                               nv_crtc->head << 8 | NV_RAMDAC_OUTPUT_DAC_ENABLE);
 342         if (nv_encoder->dcb->type == OUTPUT_TMDS)
 343                 run_tmds_table(pScrn, nv_encoder->dcb, nv_crtc->head, adjusted_mode->Clock);
 344         else if (nv_encoder->dcb->type == OUTPUT_LVDS)
 345                 call_lvds_script(pScrn, nv_encoder->dcb, nv_crtc->head, LVDS_RESET, adjusted_mode->Clock);
 346
 347         /* This could use refinement for flatpanels, but it should work this way */
 348         if (pNv->NVArch < 0x44)
 349                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + nv_output_ramdac_offset(nv_encoder), 0xf0000000);
 350         else
 351                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + nv_output_ramdac_offset(nv_encoder), 0x00100000);
 352 }
 353
 354 static Bool
 355 nv_load_detect(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
 356 {
 357         NVPtr pNv = NVPTR(pScrn);
 358         uint32_t testval, regoffset = nv_output_ramdac_offset(nv_encoder);
 359         uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, saved_rtest_ctrl, temp;
 360         int present = 0;
 361
 362 #define RGB_TEST_DATA(r,g,b) (r << 0 | g << 10 | b << 20)
 363         testval = RGB_TEST_DATA(0x140, 0x140, 0x140); /* 0x94050140 */
 364         if (pNv->VBIOS.dactestval)
 365                 testval = pNv->VBIOS.dactestval;
 366
 367         saved_rtest_ctrl = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset);
 368         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl & ~0x00010000);
 369
 370         if (pNv->NVArch >= 0x17) {
 371                 saved_powerctrl_2 = nvReadMC(pNv, NV_PBUS_POWERCTRL_2);
 372
 373                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);
 374                 if (regoffset == 0x68) {
 375                         saved_powerctrl_4 = nvReadMC(pNv, NV_PBUS_POWERCTRL_4);
 376                         nvWriteMC(pNv, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);
 377                 }
 378         }
 379
 380         usleep(4000);
 381
 382         saved_routput = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset);
 383         /* nv driver and nv31 use 0xfffffeee
 384          * nv34 and 6600 use 0xfffffece */
 385         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, saved_routput & 0xfffffece);
 386         usleep(1000);
 387
 388         temp = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset);
 389         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, temp | 1);
 390
 391         /* no regoffset on purpose */
 392         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_DATA, 1 << 31 | testval);
 393         temp = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL);
 394         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL, temp | 0x1000);
 395         usleep(1000);
 396
 397         present = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset) & (1 << 28);
 398
 399         /* no regoffset on purpose */
 400         temp = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL);
 401         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL, temp & 0xffffefff);
 402         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_DATA, 0);
 403
 404         /* bios does something more complex for restoring, but I think this is good enough */
 405         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, saved_routput);
 406         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl);
 407         if (pNv->NVArch >= 0x17) {
 408                 if (regoffset == 0x68)
 409                         nvWriteMC(pNv, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);
 410                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);
 411         }
 412
 413         if (present) {
 414                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Load detected on output %c\n", '@' + ffs(nv_encoder->dcb->or));
 415                 return TRUE;
 416         }
 417
 418         return FALSE;
 419 }
 420
 421 static void
 422 update_output_fields(xf86OutputPtr output, struct nouveau_encoder *nv_encoder)
 423 {
 424         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 425         NVPtr pNv = NVPTR(output->scrn);
 426
 427         if (nv_connector->nv_encoder == nv_encoder)
 428                 return;
 429
 430         nv_connector->nv_encoder = nv_encoder;
 431         output->possible_crtcs = nv_encoder->dcb->heads;
 432         if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS) {
 433                 output->doubleScanAllowed = false;
 434                 output->interlaceAllowed = false;
 435         } else {
 436                 output->doubleScanAllowed = true;
 437                 if (pNv->Architecture == NV_ARCH_20 ||
 438                    (pNv->Architecture == NV_ARCH_10 &&
 439                     (pNv->Chipset & 0x0ff0) != CHIPSET_NV10 &&
 440                     (pNv->Chipset & 0x0ff0) != CHIPSET_NV15))
 441                         /* HW is broken */
 442                         output->interlaceAllowed = false;
 443                 else
 444                         output->interlaceAllowed = true;
 445         }
 446
 447         if (output->randr_output) {
 448                 RRDeleteOutputProperty(output->randr_output, dithering_atom);
 449                 RRDeleteOutputProperty(output->randr_output, scaling_mode_atom);
 450                 output->funcs->create_resources(output);
 451         }
 452 }
 453
 454 static xf86OutputStatus
 455 nv_output_detect(xf86OutputPtr output)
 456 {
 457         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 458         ScrnInfoPtr pScrn = output->scrn;
 459         NVPtr pNv = NVPTR(pScrn);
 460         struct nouveau_encoder *nv_encoder;
 461         xf86OutputStatus ret = XF86OutputStatusDisconnected;
 462
 463         struct nouveau_encoder *find_encoder_by_type(NVOutputType type)
 464         {
 465                 int i;
 466                 for (i = 0; i < pNv->dcb_table.entries; i++)
 467                         if (nv_connector->possible_encoders & (1 << i) &&
 468                             (type == OUTPUT_ANY || pNv->encoders[i].dcb->type == type))
 469                                 return &pNv->encoders[i];
 470                 return NULL;
 471         }
 472
 473         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_detect is called.\n");
 474
 475         if (nv_connector->pDDCBus &&
 476             (nv_connector->edid = xf86OutputGetEDID(output, nv_connector->pDDCBus),
 477              xf86OutputSetEDID(output, nv_connector->edid), nv_connector->edid)) {
 478                 if (MULTIPLE_ENCODERS(nv_connector->possible_encoders)) {
 479                         if (nv_connector->edid->features.input_type)
 480                                 nv_encoder = find_encoder_by_type(OUTPUT_TMDS);
 481                         else
 482                                 nv_encoder = find_encoder_by_type(OUTPUT_ANALOG);
 483                 } else
 484                         nv_encoder = find_encoder_by_type(OUTPUT_ANY);
 485                 ret = XF86OutputStatusConnected;
 486         } else if ((nv_encoder = find_encoder_by_type(OUTPUT_ANALOG))) {
 487                 /* we don't have a load det function for early cards */
 488                 if (!pNv->twoHeads || pNv->NVArch == 0x11)
 489                         ret = XF86OutputStatusUnknown;
 490                 else if (pNv->twoHeads && nv_load_detect(pScrn, nv_encoder))
 491                         ret = XF86OutputStatusConnected;
 492         } else if ((nv_encoder = find_encoder_by_type(OUTPUT_LVDS))) {
 493                 if (nv_encoder->dcb->lvdsconf.use_straps_for_mode &&
 494                     pNv->VBIOS.fp.native_mode)
 495                         ret = XF86OutputStatusConnected;
 496                 if (pNv->VBIOS.fp.edid) {
 497                         xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 498                                    "Will use hardcoded BIOS FP EDID\n");
 499                         nv_connector->edid = xf86InterpretEDID(pScrn->scrnIndex,
 500                                                            pNv->VBIOS.fp.edid);
 501                         xf86OutputSetEDID(output, nv_connector->edid);
 502                         ret = XF86OutputStatusConnected;
 503                 }
 504         }
 505
 506         if (ret != XF86OutputStatusDisconnected)
 507                 update_output_fields(output, nv_encoder);
 508
 509         return ret;
 510 }
 511
 512 static DisplayModePtr
 513 get_native_mode_from_edid(xf86OutputPtr output, DisplayModePtr edid_modes)
 514 {
 515         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 516         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 517         ScrnInfoPtr pScrn = output->scrn;
 518         int max_h_active = 0, max_v_active = 0;
 519         int i;
 520         DisplayModePtr mode;
 521
 522         for (i = 0; i < DET_TIMINGS; i++) {
 523                 /* We only look at detailed timings atm */
 524                 if (nv_connector->edid->det_mon[i].type != DT)
 525                         continue;
 526                 /* Selecting only based on width ok? */
 527                 if (nv_connector->edid->det_mon[i].section.d_timings.h_active > max_h_active) {
 528                         max_h_active = nv_connector->edid->det_mon[i].section.d_timings.h_active;
 529                         max_v_active = nv_connector->edid->det_mon[i].section.d_timings.v_active;
 530                 }
 531         }
 532         if (!(max_h_active && max_v_active)) {
 533                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No EDID detailed timings available, bailing out.\n");
 534                 return NULL;
 535         }
 536
 537         if (nv_encoder->native_mode) {
 538                 xfree(nv_encoder->native_mode);
 539                 nv_encoder->native_mode = NULL;
 540         }
 541
 542         for (mode = edid_modes; mode != NULL; mode = mode->next) {
 543                 if (mode->HDisplay == max_h_active &&
 544                         mode->VDisplay == max_v_active) {
 545                         /* Take the preferred mode when it exists. */
 546                         if (mode->type & M_T_PREFERRED) {
 547                                 nv_encoder->native_mode = xf86DuplicateMode(mode);
 548                                 break;
 549                         }
 550                         /* Find the highest refresh mode otherwise. */
 551                         if (!nv_encoder->native_mode || (mode->VRefresh > nv_encoder->native_mode->VRefresh)) {
 552                                 if (nv_encoder->native_mode)
 553                                         xfree(nv_encoder->native_mode);
 554                                 mode->type |= M_T_PREFERRED;
 555                                 nv_encoder->native_mode = xf86DuplicateMode(mode);
 556                         }
 557                 }
 558         }
 559
 560         return nv_encoder->native_mode;
 561 }
 562
 563 static DisplayModePtr
 564 nv_output_get_edid_modes(xf86OutputPtr output)
 565 {
 566         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 567         ScrnInfoPtr pScrn = output->scrn;
 568         DisplayModePtr edid_modes;
 569
 570         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_get_edid_modes is called.\n");
 571
 572         if (!(edid_modes = xf86OutputGetEDIDModes(output)))
 573                 return edid_modes;
 574
 575         if (nv_encoder->dcb->type == OUTPUT_TMDS || nv_encoder->dcb->type == OUTPUT_LVDS)
 576                 if (!get_native_mode_from_edid(output, edid_modes))
 577                         return NULL;
 578
 579         if (nv_encoder->dcb->type == OUTPUT_LVDS) {
 580                 static bool dual_link_correction_done = false;
 581
 582                 if (!dual_link_correction_done) {
 583                         parse_lvds_manufacturer_table(pScrn, &NVPTR(pScrn)->VBIOS, nv_encoder->native_mode->Clock);
 584                         dual_link_correction_done = true;
 585                 }
 586         }
 587
 588         return edid_modes;
 589 }
 590
 591 static void
 592 nv_output_destroy (xf86OutputPtr output)
 593 {
 594         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 595         struct nouveau_encoder *nv_encoder;
 596         ScrnInfoPtr pScrn = output->scrn;
 597         NVPtr pNv = NVPTR(output->scrn);
 598         int i;
 599
 600         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_destroy is called.\n");
 601
 602         if (!nv_connector)
 603                 return;
 604
 605         if (nv_connector->edid)
 606                 xfree(nv_connector->edid);
 607         FOR_EACH_ENCODER_IN_CONNECTOR(i, nv_connector, nv_encoder)
 608                 if (nv_encoder->native_mode)
 609                         xfree(nv_encoder->native_mode);
 610         xfree(nv_connector);
 611 }
 612
 613 static void nv_digital_output_prepare_sel_clk(NVPtr pNv, struct nouveau_encoder *nv_encoder, int head)
 614 {
 615         NVRegPtr state = &pNv->ModeReg;
 616         uint32_t bits1618 = nv_encoder->dcb->or & OUTPUT_A ? 0x10000 : 0x40000;
 617
 618         if (nv_encoder->dcb->location != LOC_ON_CHIP)
 619                 return;
 620
 621         /* SEL_CLK is only used on the primary ramdac
 622          * It toggles spread spectrum PLL output and sets the bindings of PLLs
 623          * to heads on digital outputs
 624          */
 625         if (head)
 626                 state->sel_clk |= bits1618;
 627         else
 628                 state->sel_clk &= ~bits1618;
 629
 630         /* nv30:
 631          *      bit 0           NVClk spread spectrum on/off
 632          *      bit 2           MemClk spread spectrum on/off
 633          *      bit 4           PixClk1 spread spectrum on/off toggle
 634          *      bit 6           PixClk2 spread spectrum on/off toggle
 635          *
 636          * nv40 (observations from bios behaviour and mmio traces):
 637          *      bits 4&6        as for nv30
 638          *      bits 5&7        head dependent as for bits 4&6, but do not appear with 4&6;
 639          *                      maybe a different spread mode
 640          *      bits 8&10       seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
 641          *      The logic behind turning spread spectrum on/off in the first place,
 642          *      and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
 643          *      entry has the necessary info)
 644          */
 645         if (nv_encoder->dcb->type == OUTPUT_LVDS && pNv->SavedReg.sel_clk & 0xf0) {
 646                 int shift = (pNv->SavedReg.sel_clk & 0x50) ? 0 : 1;
 647
 648                 state->sel_clk &= ~0xf0;
 649                 state->sel_clk |= (head ? 0x40 : 0x10) << shift;
 650         }
 651 }
 652
 653 static void
 654 nv_output_prepare(xf86OutputPtr output)
 655 {
 656         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 657         ScrnInfoPtr pScrn = output->scrn;
 658         NVPtr pNv = NVPTR(output->scrn);
 659         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(output->crtc);
 660         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 661
 662         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_prepare is called.\n");
 663
 664         output->funcs->dpms(output, DPMSModeOff);
 665
 666         /* calculate some output specific CRTC regs now, so that they can be written in nv_crtc_set_mode */
 667         if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS)
 668                 nv_digital_output_prepare_sel_clk(pNv, nv_encoder, nv_crtc->head);
 669
 670         /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f etc.) which we don't alter */
 671         if (!(regp->CRTC[NV_VGA_CRTCX_LCD] & 0x44)) {
 672                 if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS) {
 673                         regp->CRTC[NV_VGA_CRTCX_LCD] &= ~0x30;
 674                         regp->CRTC[NV_VGA_CRTCX_LCD] |= 0x3;
 675                         if (nv_crtc->head == 0)
 676                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= 0x8;
 677                         else
 678                                 regp->CRTC[NV_VGA_CRTCX_LCD] &= ~0x8;
 679                         if (nv_encoder->dcb->location != LOC_ON_CHIP)
 680                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (nv_encoder->dcb->or << 4) & 0x30;
 681                 } else
 682                         regp->CRTC[NV_VGA_CRTCX_LCD] = 0;
 683         }
 684 }
 685
 686 static void
 687 nv_output_commit(xf86OutputPtr output)
 688 {
 689         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 690         ScrnInfoPtr pScrn = output->scrn;
 691         xf86CrtcPtr crtc = output->crtc;
 692         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 693
 694         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_commit is called.\n");
 695
 696         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Output %s is running on CRTC %d using output %c\n", output->name, nv_crtc->head, '@' + ffs(nv_encoder->dcb->or));
 697
 698         output->funcs->dpms(output, DPMSModeOn);
 699 }
 700
 701 /*
 702  * Several scaling modes exist, let the user choose.
 703  */
 704 #define SCALING_MODE_NAME "SCALING_MODE"
 705 static const struct {
 706         char *name;
 707         enum scaling_modes mode;
 708 } scaling_mode[] = {
 709         { "panel", SCALE_PANEL },
 710         { "fullscreen", SCALE_FULLSCREEN },
 711         { "aspect", SCALE_ASPECT },
 712         { "noscale", SCALE_NOSCALE },
 713         { NULL, SCALE_INVALID}
 714 };
 715
 716 #define DITHERING_MODE_NAME "DITHERING"
 717
 718 static void
 719 nv_output_create_resources(xf86OutputPtr output)
 720 {
 721         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 722         ScrnInfoPtr pScrn = output->scrn;
 723         INT32 dithering_range[2] = { 0, 1 };
 724         int error, i;
 725
 726         /* may be called before encoder is picked, resources will be created
 727          * by update_output_fields()
 728          */
 729         if (!nv_encoder)
 730                 return;
 731
 732         /* no properties for vga */
 733         if (nv_encoder->dcb->type == OUTPUT_ANALOG)
 734                 return;
 735
 736         /*
 737          * Setup scaling mode property.
 738          */
 739         scaling_mode_atom = MakeAtom(SCALING_MODE_NAME, sizeof(SCALING_MODE_NAME) - 1, TRUE);
 740
 741         error = RRConfigureOutputProperty(output->randr_output,
 742                                         scaling_mode_atom, TRUE, FALSE, FALSE,
 743                                         0, NULL);
 744
 745         if (error != 0) {
 746                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 747                         "RRConfigureOutputProperty error, %d\n", error);
 748         }
 749
 750         char *existing_scale_name = NULL;
 751         for (i = 0; scaling_mode[i].name; i++)
 752                 if (scaling_mode[i].mode == nv_encoder->scaling_mode)
 753                         existing_scale_name = scaling_mode[i].name;
 754
 755         error = RRChangeOutputProperty(output->randr_output, scaling_mode_atom,
 756                                         XA_STRING, 8, PropModeReplace,
 757                                         strlen(existing_scale_name),
 758                                         existing_scale_name, FALSE, TRUE);
 759
 760         if (error != 0) {
 761                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 762                         "Failed to set scaling mode, %d\n", error);
 763         }
 764
 765         /*
 766          * Setup dithering property.
 767          */
 768         dithering_atom = MakeAtom(DITHERING_MODE_NAME, sizeof(DITHERING_MODE_NAME) - 1, TRUE);
 769
 770         error = RRConfigureOutputProperty(output->randr_output,
 771                                         dithering_atom, TRUE, TRUE, FALSE,
 772                                         2, dithering_range);
 773
 774         if (error != 0) {
 775                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 776                         "RRConfigureOutputProperty error, %d\n", error);
 777         }
 778
 779         /* promote bool into int32 to make RandR DIX and big endian happy */
 780         int32_t existing_dither = nv_encoder->dithering;
 781         error = RRChangeOutputProperty(output->randr_output, dithering_atom,
 782                                         XA_INTEGER, 32, PropModeReplace, 1,
 783                                         &existing_dither, FALSE, TRUE);
 784
 785         if (error != 0) {
 786                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 787                         "Failed to set dithering mode, %d\n", error);
 788         }
 789
 790         RRPostPendingProperties(output->randr_output);
 791 }
 792
 793 static Bool
 794 nv_output_set_property(xf86OutputPtr output, Atom property,
 795                                 RRPropertyValuePtr value)
 796 {
 797         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 798
 799         if (property == scaling_mode_atom) {
 800                 int32_t ret;
 801                 char *name = NULL;
 802
 803                 if (value->type != XA_STRING || value->format != 8)
 804                         return FALSE;
 805
 806                 name = (char *) value->data;
 807
 808                 /* Match a string to a scaling mode */
 809                 ret = nv_scaling_mode_lookup(name, value->size);
 810                 if (ret == SCALE_INVALID)
 811                         return FALSE;
 812
 813                 /* LVDS must always use gpu scaling. */
 814                 if (ret == SCALE_PANEL && nv_encoder->dcb->type == OUTPUT_LVDS)
 815                         return FALSE;
 816
 817                 nv_encoder->scaling_mode = ret;
 818         } else if (property == dithering_atom) {
 819                 if (value->type != XA_INTEGER || value->format != 32)
 820                         return FALSE;
 821
 822                 int32_t val = *(int32_t *) value->data;
 823
 824                 if (val < 0 || val > 1)
 825                         return FALSE;
 826
 827                 nv_encoder->dithering = val;
 828         }
 829
 830         return TRUE;
 831 }
 832
 833 static const xf86OutputFuncsRec nv_output_funcs = {
 834         .dpms = nv_output_dpms,
 835         .mode_valid = nv_output_mode_valid,
 836         .mode_fixup = nv_output_mode_fixup,
 837         .mode_set = nv_output_mode_set,
 838         .detect = nv_output_detect,
 839         .get_modes = nv_output_get_edid_modes,
 840         .destroy = nv_output_destroy,
 841         .prepare = nv_output_prepare,
 842         .commit = nv_output_commit,
 843         .create_resources = nv_output_create_resources,
 844         .set_property = nv_output_set_property,
 845 };
 846
 847 static DisplayModePtr
 848 nv_lvds_output_get_modes(xf86OutputPtr output)
 849 {
 850         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 851         ScrnInfoPtr pScrn = output->scrn;
 852         NVPtr pNv = NVPTR(pScrn);
 853         DisplayModePtr modes;
 854
 855         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_lvds_output_get_modes is called.\n");
 856
 857         if ((modes = nv_output_get_edid_modes(output)))
 858                 return modes;
 859
 860         if (!nv_encoder->dcb->lvdsconf.use_straps_for_mode || pNv->VBIOS.fp.native_mode == NULL)
 861                 return NULL;
 862
 863         if (nv_encoder->native_mode)
 864                 xfree(nv_encoder->native_mode);
 865         nv_encoder->native_mode = xf86DuplicateMode(pNv->VBIOS.fp.native_mode);
 866
 867         return xf86DuplicateMode(pNv->VBIOS.fp.native_mode);
 868 }
 869
 870 static const xf86OutputFuncsRec nv_lvds_output_funcs = {
 871         .dpms = nv_output_dpms,
 872         .mode_valid = nv_output_mode_valid,
 873         .mode_fixup = nv_output_mode_fixup,
 874         .mode_set = nv_output_mode_set,
 875         .detect = nv_output_detect,
 876         .get_modes = nv_lvds_output_get_modes,
 877         .destroy = nv_output_destroy,
 878         .prepare = nv_output_prepare,
 879         .commit = nv_output_commit,
 880         .create_resources = nv_output_create_resources,
 881         .set_property = nv_output_set_property,
 882 };
 883
 884 static void
 885 nv_add_encoder(ScrnInfoPtr pScrn, struct dcb_entry *dcbent)
 886 {
 887         NVPtr pNv = NVPTR(pScrn);
 888         struct nouveau_encoder *nv_encoder = &pNv->encoders[dcbent->index];
 889
 890         nv_encoder->dcb = dcbent;
 891         nv_encoder->last_dpms = NV_DPMS_CLEARED;
 892         nv_encoder->dithering = (pNv->FPDither || (nv_encoder->dcb->type == OUTPUT_LVDS && !pNv->VBIOS.fp.if_is_24bit));
 893         if (pNv->fpScaler) /* GPU Scaling */
 894                 nv_encoder->scaling_mode = SCALE_ASPECT;
 895         else if (nv_encoder->dcb->type == OUTPUT_LVDS)
 896                 nv_encoder->scaling_mode = SCALE_NOSCALE;
 897         else
 898                 nv_encoder->scaling_mode = SCALE_PANEL;
 899         if (xf86GetOptValString(pNv->Options, OPTION_SCALING_MODE)) {
 900                 nv_encoder->scaling_mode = nv_scaling_mode_lookup(xf86GetOptValString(pNv->Options, OPTION_SCALING_MODE), -1);
 901                 if (nv_encoder->scaling_mode == SCALE_INVALID)
 902                         nv_encoder->scaling_mode = SCALE_ASPECT; /* default */
 903         }
 904 }
 905
 906 static void
 907 nv_add_connector(ScrnInfoPtr pScrn, int i2c_index, int encoders, const xf86OutputFuncsRec *output_funcs, char *outputname)
 908 {
 909         NVPtr pNv = NVPTR(pScrn);
 910         xf86OutputPtr output;
 911         struct nouveau_connector *nv_connector;
 912
 913         if (!(output = xf86OutputCreate(pScrn, output_funcs, outputname)))
 914                 return;
 915         if (!(nv_connector = xnfcalloc(sizeof (struct nouveau_connector), 1)))
 916                 return;
 917
 918         output->driver_private = nv_connector;
 919
 920         if (i2c_index < 0xf)
 921                 NV_I2CInit(pScrn, &nv_connector->pDDCBus, pNv->dcb_table.i2c_read[i2c_index], xstrdup(outputname));
 922         nv_connector->possible_encoders = encoders;
 923 }
 924
 925 void NvSetupOutputs(ScrnInfoPtr pScrn)
 926 {
 927         NVPtr pNv = NVPTR(pScrn);
 928         uint16_t connectors[0x10];
 929         struct dcb_entry *dcbent;
 930         int i, vga_count = 0, dvid_count = 0, dvii_count = 0, lvds_count = 0;
 931
 932         if (!(pNv->encoders = xnfcalloc(pNv->dcb_table.entries, sizeof (struct nouveau_encoder))))
 933                 return;
 934
 935         memset(connectors, 0, sizeof (connectors));
 936
 937         for (i = 0; i < pNv->dcb_table.entries; i++) {
 938                 dcbent = &pNv->dcb_table.entry[i];
 939
 940                 if (dcbent->type == OUTPUT_TV)
 941                         continue;
 942                 if (dcbent->type > 3) {
 943                         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DCB type %d not known\n", dcbent->type);
 944                         continue;
 945                 }
 946
 947                 connectors[dcbent->i2c_index] |= 1 << i;
 948
 949                 nv_add_encoder(pScrn, dcbent);
 950         }
 951
 952         for (i = 0; i < pNv->dcb_table.entries; i++) {
 953                 int i2c_index = pNv->dcb_table.entry[i].i2c_index;
 954                 uint16_t encoders = connectors[i2c_index];
 955                 char outputname[20];
 956                 xf86OutputFuncsRec const *funcs = &nv_output_funcs;
 957
 958                 if (!encoders)
 959                         continue;
 960
 961                 switch (pNv->dcb_table.entry[i].type) {
 962                 case OUTPUT_ANALOG:
 963                         if (!MULTIPLE_ENCODERS(encoders))
 964                                 sprintf(outputname, "VGA-%d", vga_count++);
 965                         else
 966                                 sprintf(outputname, "DVI-I-%d", dvii_count++);
 967                         break;
 968                 case OUTPUT_TMDS:
 969                         if (!MULTIPLE_ENCODERS(encoders))
 970                                 sprintf(outputname, "DVI-D-%d", dvid_count++);
 971                         else
 972                                 sprintf(outputname, "DVI-I-%d", dvii_count++);
 973                         break;
 974                 case OUTPUT_LVDS:
 975                         sprintf(outputname, "LVDS-%d", lvds_count++);
 976                         funcs = &nv_lvds_output_funcs;
 977                         break;
 978                 default:
 979                         continue;
 980                 }
 981
 982                 nv_add_connector(pScrn, i2c_index, encoders, funcs, outputname);
 983                 connectors[i2c_index] = 0; /* avoid connectors being added multiply */
 984         }
 985 }