2 * Copyright 2006 Dave Airlie
3 * Copyright 2007 Maarten Maathuis
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
26 * decleration is at the bottom of this file as it is rather ugly
40 #include "mipointer.h"
41 #include "windowstr.h"
43 #include <X11/extensions/render.h>
46 #include "nv_include.h"
48 const char *OutputType[] = {
57 const char *MonTypeName[7] = {
68 * TMDS registers are indirect 8 bit registers.
69 * Reading is straightforward, writing a bit odd.
70 * Reading: Write adress (+write protect bit, do not forget this), then read value.
71 * Writing: Write adress (+write protect bit), write value, write adress again and write it again (+write protect bit).
74 void NVWriteTMDS(NVPtr pNv, int ramdac, CARD32 tmds_reg, CARD32 val)
76 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL,
77 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
79 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_DATA, val & 0xff);
81 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL, tmds_reg & 0xff);
82 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL,
83 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
86 CARD8 NVReadTMDS(NVPtr pNv, int ramdac, CARD32 tmds_reg)
88 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL,
89 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
91 return (nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_DATA) & 0xff);
94 void NVOutputWriteTMDS(xf86OutputPtr output, CARD32 tmds_reg, CARD32 val)
96 NVOutputPrivatePtr nv_output = output->driver_private;
97 ScrnInfoPtr pScrn = output->scrn;
98 NVPtr pNv = NVPTR(pScrn);
101 /* Is TMDS programmed on a different output? */
102 /* Always choose the prefered ramdac, since that one contains the tmds stuff */
103 /* Assumption: there is always once output that can only run of the primary ramdac */
104 if (nv_output->valid_ramdac & RAMDAC_1) {
110 NVWriteTMDS(pNv, ramdac, tmds_reg, val);
113 CARD8 NVOutputReadTMDS(xf86OutputPtr output, CARD32 tmds_reg)
115 NVOutputPrivatePtr nv_output = output->driver_private;
116 ScrnInfoPtr pScrn = output->scrn;
117 NVPtr pNv = NVPTR(pScrn);
120 /* Is TMDS programmed on a different output? */
121 /* Always choose the prefered ramdac, since that one contains the tmds stuff */
122 /* Assumption: there is always once output that can only run of the primary ramdac */
123 if (nv_output->valid_ramdac & RAMDAC_1) {
129 return NVReadTMDS(pNv, ramdac, tmds_reg);
132 void NVOutputWriteRAMDAC(xf86OutputPtr output, CARD32 ramdac_reg, CARD32 val)
134 NVOutputPrivatePtr nv_output = output->driver_private;
135 ScrnInfoPtr pScrn = output->scrn;
136 NVPtr pNv = NVPTR(pScrn);
138 nvWriteRAMDAC(pNv, nv_output->ramdac, ramdac_reg, val);
141 CARD32 NVOutputReadRAMDAC(xf86OutputPtr output, CARD32 ramdac_reg)
143 NVOutputPrivatePtr nv_output = output->driver_private;
144 ScrnInfoPtr pScrn = output->scrn;
145 NVPtr pNv = NVPTR(pScrn);
147 return nvReadRAMDAC(pNv, nv_output->ramdac, ramdac_reg);
150 static void nv_output_backlight_enable(xf86OutputPtr output, Bool on)
152 ScrnInfoPtr pScrn = output->scrn;
153 NVPtr pNv = NVPTR(pScrn);
155 ErrorF("nv_output_backlight_enable is called for output %s to turn %s\n", output->name, on ? "on" : "off");
157 /* This is done differently on each laptop. Here we
158 * define the ones we know for sure. */
160 #if defined(__powerpc__)
161 if ((pNv->Chipset == 0x10DE0179) ||
162 (pNv->Chipset == 0x10DE0189) ||
163 (pNv->Chipset == 0x10DE0329)) {
164 /* NV17,18,34 Apple iMac, iBook, PowerBook */
165 CARD32 tmp_pmc, tmp_pcrt;
166 tmp_pmc = nvReadMC(pNv, 0x10F0) & 0x7FFFFFFF;
167 tmp_pcrt = nvReadCRTC0(pNv, NV_CRTC_081C) & 0xFFFFFFFC;
169 tmp_pmc |= (1 << 31);
172 nvWriteMC(pNv, 0x10F0, tmp_pmc);
173 nvWriteCRTC0(pNv, NV_CRTC_081C, tmp_pcrt);
177 if(pNv->twoHeads && ((pNv->Chipset & 0x0ff0) != CHIPSET_NV11))
178 nvWriteMC(pNv, 0x130C, on ? 3 : 7);
182 nv_lvds_output_dpms(xf86OutputPtr output, int mode)
184 NVOutputPrivatePtr nv_output = output->driver_private;
185 NVPtr pNv = NVPTR(output->scrn);
187 if (nv_output->ramdac != -1 && mode != DPMSModeOff) {
188 /* This was not a modeset, but a normal dpms call */
189 pNv->ramdac_active[nv_output->ramdac] = TRUE;
190 ErrorF("Activating ramdac %d\n", nv_output->ramdac);
191 nv_output->ramdac_assigned = TRUE;
195 case DPMSModeStandby:
196 case DPMSModeSuspend:
198 nv_output_backlight_enable(output, 0);
201 nv_output_backlight_enable(output, 1);
206 /* We may be going for modesetting, so we must reset the ramdacs */
207 if (nv_output->ramdac != -1 && mode == DPMSModeOff) {
208 pNv->ramdac_active[nv_output->ramdac] = FALSE;
209 ErrorF("Deactivating ramdac %d\n", nv_output->ramdac);
210 nv_output->ramdac_assigned = FALSE;
215 nv_analog_output_dpms(xf86OutputPtr output, int mode)
217 xf86CrtcPtr crtc = output->crtc;
218 NVOutputPrivatePtr nv_output = output->driver_private;
219 NVPtr pNv = NVPTR(output->scrn);
221 ErrorF("nv_analog_output_dpms is called with mode %d\n", mode);
223 if (nv_output->ramdac != -1) {
224 /* We may be going for modesetting, so we must reset the ramdacs */
225 if (mode == DPMSModeOff) {
226 pNv->ramdac_active[nv_output->ramdac] = FALSE;
227 ErrorF("Deactivating ramdac %d\n", nv_output->ramdac);
228 nv_output->ramdac_assigned = FALSE;
229 /* This was not a modeset, but a normal dpms call */
231 pNv->ramdac_active[nv_output->ramdac] = TRUE;
232 ErrorF("Activating ramdac %d\n", nv_output->ramdac);
233 nv_output->ramdac_assigned = TRUE;
238 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
240 ErrorF("nv_analog_output_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
245 nv_tmds_output_dpms(xf86OutputPtr output, int mode)
247 xf86CrtcPtr crtc = output->crtc;
248 NVOutputPrivatePtr nv_output = output->driver_private;
249 NVPtr pNv = NVPTR(output->scrn);
251 ErrorF("nv_tmds_output_dpms is called with mode %d\n", mode);
253 /* We just woke up again from an actual monitor dpms and not a modeset prepare */
254 /* Put here since we actually need our ramdac to wake up again ;-) */
255 if (nv_output->ramdac != -1 && mode != DPMSModeOff) {
256 pNv->ramdac_active[nv_output->ramdac] = TRUE;
257 nv_output->ramdac_assigned = TRUE;
258 ErrorF("Activating ramdac %d\n", nv_output->ramdac);
261 /* Are we assigned a ramdac already?, else we will be activated during mode set */
262 if (crtc && nv_output->ramdac != -1) {
263 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
265 ErrorF("nv_tmds_output_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
267 CARD32 fpcontrol = nvReadRAMDAC(pNv, nv_output->ramdac, NV_RAMDAC_FP_CONTROL);
269 case DPMSModeStandby:
270 case DPMSModeSuspend:
272 /* cut the TMDS output */
273 fpcontrol |= 0x20000022;
276 /* disable cutting the TMDS output */
277 fpcontrol &= ~0x20000022;
280 nvWriteRAMDAC(pNv, nv_output->ramdac, NV_RAMDAC_FP_CONTROL, fpcontrol);
283 /* We may be going for modesetting, so we must reset the ramdacs */
284 if (nv_output->ramdac != -1 && mode == DPMSModeOff) {
285 pNv->ramdac_active[nv_output->ramdac] = FALSE;
286 nv_output->ramdac_assigned = FALSE;
287 ErrorF("Deactivating ramdac %d\n", nv_output->ramdac);
291 /* Some registers are not set, because they are zero. */
292 /* This sequence matters, this is how the blob does it */
293 int tmds_regs[] = { 0x2f, 0x2e, 0x33, 0x04, 0x05, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x00, 0x01, 0x02, 0x2e, 0x2f, 0x04, 0x3a, 0x33, 0x04 };
295 void nv_output_save_state_ext(xf86OutputPtr output, RIVA_HW_STATE *state, Bool override)
297 NVOutputPrivatePtr nv_output = output->driver_private;
298 ScrnInfoPtr pScrn = output->scrn;
299 NVPtr pNv = NVPTR(pScrn);
303 regp = &state->dac_reg[nv_output->ramdac];
304 regp->general = NVOutputReadRAMDAC(output, NV_RAMDAC_GENERAL_CONTROL);
305 regp->test_control = NVOutputReadRAMDAC(output, NV_RAMDAC_TEST_CONTROL);
306 regp->unk_670 = NVOutputReadRAMDAC(output, NV_RAMDAC_670);
307 regp->fp_control = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_CONTROL);
308 regp->debug_0 = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_DEBUG_0);
309 regp->debug_1 = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_DEBUG_1);
310 regp->debug_2 = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_DEBUG_2);
311 state->config = nvReadFB(pNv, NV_PFB_CFG0);
313 //regp->unk_900 = NVOutputReadRAMDAC(output, NV_RAMDAC_900);
315 regp->unk_a20 = NVOutputReadRAMDAC(output, NV_RAMDAC_A20);
316 regp->unk_a24 = NVOutputReadRAMDAC(output, NV_RAMDAC_A24);
317 regp->unk_a34 = NVOutputReadRAMDAC(output, NV_RAMDAC_A34);
319 regp->output = NVOutputReadRAMDAC(output, NV_RAMDAC_OUTPUT);
321 if ((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
322 regp->dither = NVOutputReadRAMDAC(output, NV_RAMDAC_DITHER_NV11);
323 } else if (pNv->twoHeads) {
324 regp->dither = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_DITHER);
326 regp->nv10_cursync = NVOutputReadRAMDAC(output, NV_RAMDAC_NV10_CURSYNC);
328 /* I want to be able reset TMDS registers for DVI-D/DVI-A pairs for example */
329 /* Also write on VT restore */
330 if (nv_output->type != OUTPUT_LVDS || override )
331 for (i = 0; i < sizeof(tmds_regs)/sizeof(tmds_regs[0]); i++) {
332 regp->TMDS[tmds_regs[i]] = NVOutputReadTMDS(output, tmds_regs[i]);
335 /* The regs below are 0 for non-flatpanels, so you can load and save them */
337 for (i = 0; i < 7; i++) {
338 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
339 regp->fp_horiz_regs[i] = NVOutputReadRAMDAC(output, ramdac_reg);
342 for (i = 0; i < 7; i++) {
343 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
344 regp->fp_vert_regs[i] = NVOutputReadRAMDAC(output, ramdac_reg);
347 regp->fp_hvalid_start = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_HVALID_START);
348 regp->fp_hvalid_end = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_HVALID_END);
349 regp->fp_vvalid_start = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_VVALID_START);
350 regp->fp_vvalid_end = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_VVALID_END);
353 void nv_output_load_state_ext(xf86OutputPtr output, RIVA_HW_STATE *state, Bool override)
355 NVOutputPrivatePtr nv_output = output->driver_private;
356 ScrnInfoPtr pScrn = output->scrn;
357 NVPtr pNv = NVPTR(pScrn);
361 regp = &state->dac_reg[nv_output->ramdac];
363 if (nv_output->type == OUTPUT_LVDS) {
364 ErrorF("Writing %08X to RAMDAC_FP_DEBUG_0\n", regp->debug_0);
365 ErrorF("Writing %08X to RAMDAC_FP_DEBUG_1\n", regp->debug_1);
366 ErrorF("Writing %08X to RAMDAC_FP_DEBUG_2\n", regp->debug_2);
367 ErrorF("Writing %08X to RAMDAC_OUTPUT\n", regp->output);
368 ErrorF("Writing %08X to RAMDAC_FP_CONTROL\n", regp->fp_control);
370 NVOutputWriteRAMDAC(output, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
371 NVOutputWriteRAMDAC(output, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
372 NVOutputWriteRAMDAC(output, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
373 NVOutputWriteRAMDAC(output, NV_RAMDAC_OUTPUT, regp->output);
374 NVOutputWriteRAMDAC(output, NV_RAMDAC_FP_CONTROL, regp->fp_control);
376 NVOutputWriteRAMDAC(output, NV_RAMDAC_A20, regp->unk_a20);
377 NVOutputWriteRAMDAC(output, NV_RAMDAC_A24, regp->unk_a24);
378 NVOutputWriteRAMDAC(output, NV_RAMDAC_A34, regp->unk_a34);
380 //NVOutputWriteRAMDAC(output, NV_RAMDAC_900, regp->unk_900);
382 if ((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
383 NVOutputWriteRAMDAC(output, NV_RAMDAC_DITHER_NV11, regp->dither);
384 } else if (pNv->twoHeads) {
385 NVOutputWriteRAMDAC(output, NV_RAMDAC_FP_DITHER, regp->dither);
388 NVOutputWriteRAMDAC(output, NV_RAMDAC_GENERAL_CONTROL, regp->general);
389 NVOutputWriteRAMDAC(output, NV_RAMDAC_TEST_CONTROL, regp->test_control);
390 NVOutputWriteRAMDAC(output, NV_RAMDAC_670, regp->unk_670);
391 NVOutputWriteRAMDAC(output, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
393 /* I want to be able reset TMDS registers for DVI-D/DVI-A pairs for example */
394 /* Also write on VT restore */
395 if (nv_output->type != OUTPUT_LVDS || override )
396 for (i = 0; i < sizeof(tmds_regs)/sizeof(tmds_regs[0]); i++) {
397 NVOutputWriteTMDS(output, tmds_regs[i], regp->TMDS[tmds_regs[i]]);
400 /* The regs below are 0 for non-flatpanels, so you can load and save them */
402 for (i = 0; i < 7; i++) {
403 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
404 NVOutputWriteRAMDAC(output, ramdac_reg, regp->fp_horiz_regs[i]);
407 for (i = 0; i < 7; i++) {
408 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
409 NVOutputWriteRAMDAC(output, ramdac_reg, regp->fp_vert_regs[i]);
412 NVOutputWriteRAMDAC(output, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
413 NVOutputWriteRAMDAC(output, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
414 NVOutputWriteRAMDAC(output, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
415 NVOutputWriteRAMDAC(output, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
418 /* NOTE: Don't rely on this data for anything other than restoring VT's */
421 nv_output_save (xf86OutputPtr output)
423 ScrnInfoPtr pScrn = output->scrn;
424 NVPtr pNv = NVPTR(pScrn);
425 RIVA_HW_STATE *state;
426 NVOutputPrivatePtr nv_output = output->driver_private;
427 int ramdac_backup = nv_output->ramdac;
429 ErrorF("nv_output_save is called\n");
431 /* This is early init and we have not yet been assigned a ramdac */
432 /* Always choose the prefered ramdac, for consistentcy */
433 /* Assumption: there is always once output that can only run of the primary ramdac */
434 if (nv_output->valid_ramdac & RAMDAC_1) {
435 nv_output->ramdac = 1;
437 nv_output->ramdac = 0;
440 state = &pNv->SavedReg;
442 /* Due to strange mapping of outputs we could have swapped analog and digital */
443 /* So we force save all the registers */
444 nv_output_save_state_ext(output, state, TRUE);
446 /* restore previous state */
447 nv_output->ramdac = ramdac_backup;
451 nv_output_restore (xf86OutputPtr output)
453 ScrnInfoPtr pScrn = output->scrn;
454 NVPtr pNv = NVPTR(pScrn);
455 RIVA_HW_STATE *state;
456 NVOutputPrivatePtr nv_output = output->driver_private;
457 int ramdac_backup = nv_output->ramdac;
459 ErrorF("nv_output_restore is called\n");
461 /* We want consistent mode restoring and the ramdac entry is variable */
462 /* Always choose the prefered ramdac, for consistentcy */
463 /* Assumption: there is always once output that can only run of the primary ramdac */
464 if (nv_output->valid_ramdac & RAMDAC_1) {
465 nv_output->ramdac = 1;
467 nv_output->ramdac = 0;
470 state = &pNv->SavedReg;
472 /* Due to strange mapping of outputs we could have swapped analog and digital */
473 /* So we force load all the registers */
474 nv_output_load_state_ext(output, state, TRUE);
476 /* restore previous state */
477 nv_output->ramdac = ramdac_backup;
481 nv_output_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
483 if (pMode->Flags & V_DBLSCAN)
484 return MODE_NO_DBLESCAN;
486 if (pMode->Clock > 400000 || pMode->Clock < 25000)
487 return MODE_CLOCK_RANGE;
494 nv_output_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
495 DisplayModePtr adjusted_mode)
497 ScrnInfoPtr pScrn = output->scrn;
498 NVPtr pNv = NVPTR(pScrn);
499 NVOutputPrivatePtr nv_output = output->driver_private;
501 ErrorF("nv_output_mode_fixup is called\n");
503 /* For internal panels and gpu scaling on DVI we need the native mode */
504 if ((nv_output->type == OUTPUT_LVDS) || (pNv->fpScaler && (nv_output->type == OUTPUT_TMDS))) {
505 adjusted_mode->HDisplay = nv_output->native_mode->HDisplay;
506 adjusted_mode->HSkew = nv_output->native_mode->HSkew;
507 adjusted_mode->HSyncStart = nv_output->native_mode->HSyncStart;
508 adjusted_mode->HSyncEnd = nv_output->native_mode->HSyncEnd;
509 adjusted_mode->HTotal = nv_output->native_mode->HTotal;
510 adjusted_mode->VDisplay = nv_output->native_mode->VDisplay;
511 adjusted_mode->VScan = nv_output->native_mode->VScan;
512 adjusted_mode->VSyncStart = nv_output->native_mode->VSyncStart;
513 adjusted_mode->VSyncEnd = nv_output->native_mode->VSyncEnd;
514 adjusted_mode->VTotal = nv_output->native_mode->VTotal;
515 adjusted_mode->Clock = nv_output->native_mode->Clock;
517 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
524 nv_output_tweak_panel(xf86OutputPtr output, NVRegPtr state)
526 NVOutputPrivatePtr nv_output = output->driver_private;
527 ScrnInfoPtr pScrn = output->scrn;
528 NVPtr pNv = NVPTR(pScrn);
532 regp = &state->dac_reg[nv_output->ramdac];
533 if (pNv->usePanelTweak) {
534 tweak = pNv->PanelTweak;
536 /* begin flat panel hacks */
537 /* This is unfortunate, but some chips need this register
538 tweaked or else you get artifacts where adjacent pixels are
539 swapped. There are no hard rules for what to set here so all
540 we can do is experiment and apply hacks. */
542 if(((pNv->Chipset & 0xffff) == 0x0328) && (regp->bpp == 32)) {
543 /* At least one NV34 laptop needs this workaround. */
547 if((pNv->Chipset & 0xfff0) == CHIPSET_NV31) {
550 /* end flat panel hacks */
556 nv_output_mode_set_regs(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode)
558 NVOutputPrivatePtr nv_output = output->driver_private;
559 ScrnInfoPtr pScrn = output->scrn;
561 NVPtr pNv = NVPTR(pScrn);
562 NVFBLayout *pLayout = &pNv->CurrentLayout;
563 RIVA_HW_STATE *state, *sv_state;
565 NVOutputRegPtr regp, regp2, savep;
566 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
567 float aspect_ratio, panel_ratio;
568 uint32_t h_scale, v_scale;
571 state = &pNv->ModeReg;
572 regp = &state->dac_reg[nv_output->ramdac];
573 /* The other ramdac */
574 regp2 = &state->dac_reg[(~(nv_output->ramdac)) & 1];
576 sv_state = &pNv->SavedReg;
577 savep = &sv_state->dac_reg[nv_output->ramdac];
579 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS)) {
582 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
583 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
584 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
585 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
586 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
587 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
588 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
590 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
591 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
592 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VDisplay;
593 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
594 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
595 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
596 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
598 ErrorF("Horizontal:\n");
599 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
600 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
601 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
602 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
603 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
604 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
605 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
607 ErrorF("Vertical:\n");
608 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
609 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
610 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
611 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
612 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
613 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
614 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
618 * bit0: positive vsync
619 * bit4: positive hsync
620 * bit8: enable panel scaling
621 * bit26: a bit sometimes seen on some g70 cards
622 * bit31: sometimes seen on LVDS panels
623 * This must also be set for non-flatpanels
624 * Some bits seem shifted for vga monitors
628 regp->fp_control = 0x11100000;
630 regp->fp_control = 0x21100000;
632 if (nv_output->type == OUTPUT_LVDS) {
633 /* Let's assume LVDS to be on ramdac0, remember that in the ramdac routing is somewhat random (compared to bios setup), so don't trust it */
634 regp->fp_control = nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & 0xfff00000;
636 /* If the special bit exists, it exists on both ramdac's */
637 regp->fp_control |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
640 /* Deal with vsync/hsync polarity */
641 /* These analog monitor offsets are guesswork */
642 if (adjusted_mode->Flags & V_PVSYNC) {
643 regp->fp_control |= (1 << (0 + !is_fp));
646 if (adjusted_mode->Flags & V_PHSYNC) {
647 regp->fp_control |= (1 << (4 + !is_fp));
651 ErrorF("Pre-panel scaling\n");
652 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
653 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
654 ErrorF("panel_ratio=%f\n", panel_ratio);
655 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
656 ErrorF("aspect_ratio=%f\n", aspect_ratio);
657 /* Scale factors is the so called 20.12 format, taken from Haiku */
658 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
659 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
660 ErrorF("h_scale=%d\n", h_scale);
661 ErrorF("v_scale=%d\n", v_scale);
663 /* Don't limit last fetched line */
666 /* We want automatic scaling */
669 regp->fp_hvalid_start = 0;
670 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
672 regp->fp_vvalid_start = 0;
673 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
675 if (!pNv->fpScaler) {
676 ErrorF("Flat panel is doing the scaling.\n");
677 regp->fp_control |= (1 << 8);
679 ErrorF("GPU is doing the scaling.\n");
680 /* GPU scaling happens automaticly at a ratio of 1.33 */
681 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
682 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
685 ErrorF("Scaling resolution on a widescreen panel\n");
687 /* Scaling in both directions needs to the same */
690 /* Set a new horizontal scale factor and enable testmode (bit12) */
691 regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
693 diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
694 regp->fp_hvalid_start = diff/2;
695 regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
698 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
699 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
702 ErrorF("Scaling resolution on a portrait panel\n");
704 /* Scaling in both directions needs to the same */
707 /* Set a new vertical scale factor and enable testmode (bit28) */
708 regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
710 diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
711 regp->fp_vvalid_start = diff/2;
712 regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
716 ErrorF("Post-panel scaling\n");
719 if (pNv->Architecture >= NV_ARCH_10) {
720 /* Bios and blob don't seem to do anything (else) */
721 regp->nv10_cursync = (1<<25);
724 /* These are the common blob values, minus a few fp specific bit's */
725 /* Let's keep the TMDS pll and fpclock running in all situations */
726 regp->debug_0 = 0x1101111;
729 /* I am not completely certain, but seems to be set only for dfp's */
730 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
733 ErrorF("output %d debug_0 %08X\n", nv_output->ramdac, regp->debug_0);
735 /* This is just a guess, there are probably more registers which need setting */
736 /* But we must start somewhere ;-) */
738 regp->TMDS[0x4] = 0x80;
739 /* Enable crosswired mode */
740 /* As far as i know, this may never be set on ramdac 0 tmds registers (ramdac 1 -> crosswired -> ramdac 0 tmds regs) */
741 /* This will upset the monitor, trust me, i know it :-( */
742 /* Now allowed for non-bios inited systems */
743 if ((nv_output->ramdac == 0) && (nv_output->valid_ramdac & RAMDAC_1)) {
744 regp->TMDS[0x4] |= (1 << 3);
748 /* The TMDS game begins */
749 /* A few registers are also programmed on non-tmds monitors */
750 /* At the moment i can't give rationale for these values */
752 regp->TMDS[0x2e] = 0x80;
753 regp->TMDS[0x2f] = 0xff;
754 regp->TMDS[0x33] = 0xfe;
756 NVCrtcPrivatePtr nv_crtc = output->crtc->driver_private;
757 uint32_t pll_setup_control = nvReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SETUP_CONTROL);
758 regp->TMDS[0x2b] = 0x7d;
759 regp->TMDS[0x2c] = 0x0;
760 if (nv_crtc->head == 1) {
761 regp->TMDS[0x2e] = 0x81;
763 regp->TMDS[0x2e] = 0x85;
765 regp->TMDS[0x2f] = 0x21;
766 regp->TMDS[0x30] = 0x0;
767 regp->TMDS[0x31] = 0x0;
768 regp->TMDS[0x32] = 0x0;
769 regp->TMDS[0x33] = 0xf0;
770 regp->TMDS[0x3a] = 0x80;
772 /* Here starts the registers that may cause problems for some */
773 /* This an educated guess */
774 if (pNv->misc_info.reg_c040 & (1 << 10)) {
775 regp->TMDS[0x5] = 0x68;
777 regp->TMDS[0x5] = 0x6e;
780 /* This seems to be related to PLL_SETUP_CONTROL */
781 /* When PLL_SETUP_CONTROL ends with 0x1c, then this value is 0xc1 */
783 if ((pll_setup_control & 0xff) == 0x1c) {
784 regp->TMDS[0x0] = 0xc1;
786 regp->TMDS[0x0] = 0xf1;
789 /* This is also related to PLL_SETUP_CONTROL, exactly how is unknown */
790 if (pll_setup_control == 0) {
791 regp->TMDS[0x1] = 0x0;
793 if (nvReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK) & (1<<12)) {
794 regp->TMDS[0x1] = 0x41;
796 regp->TMDS[0x1] = 0x42;
800 if (pll_setup_control == 0x0) {
801 regp->TMDS[0x2] = 0x90;
803 regp->TMDS[0x2] = 0x89;
805 /* This test is not needed for me although the blob sets this value */
806 /* It may be wrong, but i'm leaving it for historical reference */
807 /*if (pNv->misc_info.reg_c040 == 0x3c0bc003 || pNv->misc_info.reg_c040 == 0x3c0bc333) {
808 regp->TMDS[0x2] = 0xa9;
812 /* Flatpanel support needs at least a NV10 */
814 /* Instead of 1, several other values are also used: 2, 7, 9 */
815 /* The purpose is unknown */
817 regp->dither = 0x00010000;
821 if(pLayout->depth < 24) {
822 bpp = pLayout->depth;
827 /* Kindly borrowed from haiku driver */
828 /* bit4 and bit5 activate indirect mode trough color palette */
829 switch (pLayout->depth) {
832 regp->general = 0x00101130;
836 regp->general = 0x00100130;
840 regp->general = 0x00101100;
844 if (pNv->alphaCursor) {
845 regp->general |= (1<<29);
848 regp->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
850 /* Some values the blob sets */
851 /* This may apply to the real ramdac that is being used (for crosswired situations) */
852 /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
854 regp->unk_a24 = 0xfffff;
857 /* Put test control into what seems to be the neutral position */
858 if (pNv->NVArch < 0x44) {
859 regp->test_control = 0xf0000000;
861 /* Bit 16 i got from nv_hw.c */
862 regp->test_control = 0xf0110000;
865 /* This is a similar register to test control */
866 /* Common values are 0xf0000000, 0xf0100000 and 0xf0010000, also without the f */
867 /* This is an educated guess */
868 /* The blob doesn't set this on ramdac 1, so maybe the primary one counts for both? */
869 if (pNv->NVArch < 0x44) {
870 regp->unk_670 = 0xf0010000;
872 regp->unk_670 = 0xf0100000;
875 /* This may be causing problems */
876 //regp->unk_900 = 0x10000;
879 NVCrtcPrivatePtr nv_crtc = output->crtc->driver_private;
883 for (i = 0; i < config->num_output; i++) {
884 NVOutputPrivatePtr nv_output2 = config->output[i]->driver_private;
886 /* is it this output ?? */
887 if (config->output[i] == output)
890 /* it the output connected */
891 if (config->output[i]->crtc == NULL)
895 if ((nv_output2->type == OUTPUT_ANALOG) && (nv_output->type == OUTPUT_ANALOG)) {
903 regp->output = NV_RAMDAC_OUTPUT_DAC_ENABLE;
906 if (nv_crtc->head == 1) {
907 regp->output |= NV_RAMDAC_OUTPUT_SELECT_VPLL2;
909 regp->output &= ~NV_RAMDAC_OUTPUT_SELECT_VPLL2;
912 ErrorF("%d: crtc %d output%d: %04X: twocrt %d twomon %d\n", is_fp, nv_crtc->crtc, nv_output->ramdac, regp->output, two_crt, two_mon);
917 nv_output_mode_set(xf86OutputPtr output, DisplayModePtr mode,
918 DisplayModePtr adjusted_mode)
920 ScrnInfoPtr pScrn = output->scrn;
921 NVPtr pNv = NVPTR(pScrn);
922 RIVA_HW_STATE *state;
924 ErrorF("nv_output_mode_set is called\n");
926 state = &pNv->ModeReg;
928 nv_output_mode_set_regs(output, mode, adjusted_mode);
929 nv_output_load_state_ext(output, state, FALSE);
933 nv_get_edid(xf86OutputPtr output)
935 /* no use for shared DDC output */
936 NVOutputPrivatePtr nv_output = output->driver_private;
939 if (nv_output->pDDCBus == NULL)
942 ddc_mon = xf86OutputGetEDID(output, nv_output->pDDCBus);
946 if (ddc_mon->features.input_type && (nv_output->type == OUTPUT_ANALOG))
949 if ((!ddc_mon->features.input_type) && (nv_output->type == OUTPUT_TMDS ||
950 nv_output->type == OUTPUT_LVDS))
961 nv_ddc_detect(xf86OutputPtr output)
963 xf86MonPtr m = nv_get_edid(output);
973 nv_crt_load_detect(xf86OutputPtr output)
975 ScrnInfoPtr pScrn = output->scrn;
976 NVOutputPrivatePtr nv_output = output->driver_private;
977 NVPtr pNv = NVPTR(pScrn);
978 CARD32 reg_output, reg_test_ctrl, temp;
984 /* Restrict to primary ramdac for now, because i get false positives on the secondary */
985 for (ramdac = 0; ramdac < 1; ramdac++) {
986 reg_output = nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_OUTPUT);
987 reg_test_ctrl = nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL);
989 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL, (reg_test_ctrl & ~0x00010000));
991 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_OUTPUT, (reg_output & 0x0000FEEE));
994 temp = nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_OUTPUT);
995 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_OUTPUT, temp | 1);
997 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_DATA, 0x94050140);
998 temp = nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL);
999 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL, temp | 0x1000);
1003 present[ramdac] = (nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL) & (1 << 28)) ? TRUE : FALSE;
1005 temp = NVOutputReadRAMDAC(output, NV_RAMDAC_TEST_CONTROL);
1006 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL, temp & 0x000EFFF);
1008 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_OUTPUT, reg_output);
1009 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL, reg_test_ctrl);
1012 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "CRT detect returned %d for ramdac0\n", present[0]);
1013 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "CRT detect returned %d for ramdac1\n", present[1]);
1015 /* Can we only be ramdac0 ?*/
1016 if (!(nv_output->valid_ramdac & RAMDAC_1)) {
1022 /* What do with a secondary output running of the primary ramdac? */
1028 static xf86OutputStatus
1029 nv_tmds_output_detect(xf86OutputPtr output)
1031 ErrorF("nv_tmds_output_detect is called\n");
1033 if (nv_ddc_detect(output))
1034 return XF86OutputStatusConnected;
1036 return XF86OutputStatusDisconnected;
1040 static xf86OutputStatus
1041 nv_analog_output_detect(xf86OutputPtr output)
1043 ErrorF("nv_analog_output_detect is called\n");
1045 if (nv_ddc_detect(output))
1046 return XF86OutputStatusConnected;
1048 /* This may not work in all cases, but it's the best that can be done */
1049 /* Example: Secondary output running of primary ramdac, what to do? */
1050 //if (nv_crt_load_detect(output))
1051 // return XF86OutputStatusConnected;
1053 return XF86OutputStatusDisconnected;
1056 static DisplayModePtr
1057 nv_output_get_modes(xf86OutputPtr output)
1059 NVOutputPrivatePtr nv_output = output->driver_private;
1061 DisplayModePtr ddc_modes;
1063 ErrorF("nv_output_get_modes is called\n");
1065 ddc_mon = nv_get_edid(output);
1067 xf86OutputSetEDID(output, ddc_mon);
1069 if (ddc_mon == NULL)
1072 ddc_modes = xf86OutputGetEDIDModes (output);
1074 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
1076 DisplayModePtr mode;
1078 for (i = 0; i < 4; i++) {
1079 /* We only look at detailed timings atm */
1080 if (ddc_mon->det_mon[i].type != DT)
1082 /* Selecting only based on width ok? */
1083 if (ddc_mon->det_mon[i].section.d_timings.h_active > nv_output->fpWidth) {
1084 nv_output->fpWidth = ddc_mon->det_mon[i].section.d_timings.h_active;
1085 nv_output->fpHeight = ddc_mon->det_mon[i].section.d_timings.v_active;
1089 /* Add a native resolution mode that is preferred */
1090 /* Reduced blanking should be fine on DVI monitor */
1091 nv_output->native_mode = xf86CVTMode(nv_output->fpWidth, nv_output->fpHeight, 60.0, TRUE, FALSE);
1092 nv_output->native_mode->type = M_T_DRIVER | M_T_PREFERRED;
1093 /* We want the new mode to be preferred */
1094 for (mode = ddc_modes; mode != NULL; mode = mode->next) {
1095 if (mode->type & M_T_PREFERRED) {
1096 mode->type &= ~M_T_PREFERRED;
1099 ddc_modes = xf86ModesAdd(ddc_modes, nv_output->native_mode);
1106 nv_output_destroy (xf86OutputPtr output)
1108 ErrorF("nv_output_destroy is called\n");
1109 if (output->driver_private)
1110 xfree (output->driver_private);
1114 nv_clear_ramdac_from_outputs(xf86OutputPtr output, int ramdac)
1117 ScrnInfoPtr pScrn = output->scrn;
1118 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1119 xf86OutputPtr output2;
1120 NVOutputPrivatePtr nv_output2;
1121 for (i = 0; i < xf86_config->num_output; i++) {
1122 output2 = xf86_config->output[i];
1123 nv_output2 = output2->driver_private;
1124 if (nv_output2->ramdac == ramdac && output != output2) {
1125 nv_output2->ramdac = -1;
1126 nv_output2->ramdac_assigned = FALSE;
1133 nv_output_prepare(xf86OutputPtr output)
1135 ErrorF("nv_output_prepare is called\n");
1136 NVOutputPrivatePtr nv_output = output->driver_private;
1137 ScrnInfoPtr pScrn = output->scrn;
1138 NVPtr pNv = NVPTR(pScrn);
1139 xf86CrtcPtr crtc = output->crtc;
1140 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1142 output->funcs->dpms(output, DPMSModeOff);
1144 if (nv_output->ramdac_assigned) {
1145 ErrorF("We already have a ramdac.\n");
1149 /* We need this ramdac, so let's steal it */
1150 if (!(nv_output->valid_ramdac & RAMDAC_1) && pNv->ramdac_active[0]) {
1151 ErrorF("Stealing ramdac0 ;-)\n");
1153 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1154 xf86OutputPtr output2;
1155 NVOutputPrivatePtr nv_output2;
1156 for (i = 0; i < xf86_config->num_output; i++) {
1157 output2 = xf86_config->output[i];
1158 nv_output2 = output2->driver_private;
1159 if (nv_output2->ramdac == 0 && output != output2) {
1160 nv_output2->ramdac = -1;
1161 nv_output2->ramdac_assigned = FALSE;
1165 pNv->ramdac_active[0] = FALSE;
1168 /* I sometimes get the strange feeling that ramdac's like to be paired with their matching crtc */
1169 if ((nv_output->valid_ramdac & RAMDAC_0) && !(pNv->ramdac_active[0]) && nv_crtc->head == 0) {
1170 ErrorF("Activating ramdac %d\n", 0);
1171 pNv->ramdac_active[0] = TRUE;
1172 nv_output->ramdac = 0;
1173 } else if ((nv_output->valid_ramdac & RAMDAC_1) && !(pNv->ramdac_active[1]) && nv_crtc->head == 1) {
1174 ErrorF("Activating ramdac %d\n", 1);
1175 pNv->ramdac_active[1] = TRUE;
1176 nv_output->ramdac = 1;
1179 if (nv_output->ramdac != -1) {
1180 nv_output->ramdac_assigned = TRUE;
1181 nv_clear_ramdac_from_outputs(output, nv_output->ramdac);
1186 nv_output_commit(xf86OutputPtr output)
1188 ErrorF("nv_output_commit is called\n");
1190 output->funcs->dpms(output, DPMSModeOn);
1193 static const xf86OutputFuncsRec nv_analog_output_funcs = {
1194 .dpms = nv_analog_output_dpms,
1195 .save = nv_output_save,
1196 .restore = nv_output_restore,
1197 .mode_valid = nv_output_mode_valid,
1198 .mode_fixup = nv_output_mode_fixup,
1199 .mode_set = nv_output_mode_set,
1200 .detect = nv_analog_output_detect,
1201 .get_modes = nv_output_get_modes,
1202 .destroy = nv_output_destroy,
1203 .prepare = nv_output_prepare,
1204 .commit = nv_output_commit,
1207 static const xf86OutputFuncsRec nv_tmds_output_funcs = {
1208 .dpms = nv_tmds_output_dpms,
1209 .save = nv_output_save,
1210 .restore = nv_output_restore,
1211 .mode_valid = nv_output_mode_valid,
1212 .mode_fixup = nv_output_mode_fixup,
1213 .mode_set = nv_output_mode_set,
1214 .detect = nv_tmds_output_detect,
1215 .get_modes = nv_output_get_modes,
1216 .destroy = nv_output_destroy,
1217 .prepare = nv_output_prepare,
1218 .commit = nv_output_commit,
1221 static int nv_lvds_output_mode_valid
1222 (xf86OutputPtr output, DisplayModePtr pMode)
1224 NVOutputPrivatePtr nv_output = output->driver_private;
1226 /* No modes > panel's native res */
1227 if (pMode->HDisplay > nv_output->fpWidth || pMode->VDisplay > nv_output->fpHeight)
1230 return nv_output_mode_valid(output, pMode);
1233 static xf86OutputStatus
1234 nv_lvds_output_detect(xf86OutputPtr output)
1236 ScrnInfoPtr pScrn = output->scrn;
1237 NVPtr pNv = NVPTR(pScrn);
1239 if (pNv->fp_native_mode || nv_ddc_detect(output))
1240 return XF86OutputStatusConnected;
1242 return XF86OutputStatusDisconnected;
1245 static DisplayModePtr
1246 nv_lvds_output_get_modes(xf86OutputPtr output)
1248 ScrnInfoPtr pScrn = output->scrn;
1249 NVPtr pNv = NVPTR(pScrn);
1250 NVOutputPrivatePtr nv_output = output->driver_private;
1251 DisplayModePtr modes;
1253 if ((modes = nv_output_get_modes(output)))
1256 /* it is possible to set up a mode from what we can read from the
1257 * RAMDAC registers, but if we can't read the BIOS table correctly
1258 * we might as well give up */
1259 if (pNv->fp_native_mode == NULL)
1262 nv_output->fpWidth = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_HDISP_END) + 1;
1263 nv_output->fpHeight = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_VDISP_END) + 1;
1264 nv_output->fpSyncs = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_CONTROL) & 0x30000033;
1266 if (pNv->fp_native_mode->HDisplay != nv_output->fpWidth ||
1267 pNv->fp_native_mode->VDisplay != nv_output->fpHeight) {
1268 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1269 "Panel size mismatch; ignoring RAMDAC\n");
1270 nv_output->fpWidth = pNv->fp_native_mode->HDisplay;
1271 nv_output->fpHeight = pNv->fp_native_mode->VDisplay;
1274 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Panel size is %u x %u\n",
1275 nv_output->fpWidth, nv_output->fpHeight);
1277 nv_output->native_mode = xf86DuplicateMode(pNv->fp_native_mode);
1279 return xf86DuplicateMode(pNv->fp_native_mode);
1282 static const xf86OutputFuncsRec nv_lvds_output_funcs = {
1283 .dpms = nv_lvds_output_dpms,
1284 .save = nv_output_save,
1285 .restore = nv_output_restore,
1286 .mode_valid = nv_lvds_output_mode_valid,
1287 .mode_fixup = nv_output_mode_fixup,
1288 .mode_set = nv_output_mode_set,
1289 .detect = nv_lvds_output_detect,
1290 .get_modes = nv_lvds_output_get_modes,
1291 .destroy = nv_output_destroy,
1292 .prepare = nv_output_prepare,
1293 .commit = nv_output_commit,
1296 static void nv_add_analog_output(ScrnInfoPtr pScrn, int order, int i2c_index, Bool dvi_pair)
1298 NVPtr pNv = NVPTR(pScrn);
1299 xf86OutputPtr output;
1300 NVOutputPrivatePtr nv_output;
1301 char outputname[20];
1303 Bool create_output = TRUE;
1305 /* DVI have an analog connector and a digital one, differentiate between that and a normal vga */
1307 sprintf(outputname, "DVI-A-%d", pNv->dvi_a_count);
1310 sprintf(outputname, "VGA-%d", pNv->vga_count);
1314 nv_output = xnfcalloc (sizeof (NVOutputPrivateRec), 1);
1319 if (pNv->dcb_table.i2c_read[i2c_index] && pNv->pI2CBus[i2c_index] == NULL)
1320 NV_I2CInit(pScrn, &pNv->pI2CBus[i2c_index], pNv->dcb_table.i2c_read[i2c_index], xstrdup(outputname));
1322 nv_output->type = OUTPUT_ANALOG;
1325 * bit0: RAMDAC_0 valid
1326 * bit1: RAMDAC_1 valid
1327 * So lowest order has highest priority.
1329 nv_output->valid_ramdac = order;
1331 /* Some early nvidia cards have outputs only valid on secondary */
1332 if (nv_output->valid_ramdac & RAMDAC_0)
1333 crtc_mask |= (1<<0);
1335 /* Restricting this will cause a full mode set when trying to squeeze in the primary mode */
1336 if (nv_output->valid_ramdac & RAMDAC_1)
1337 crtc_mask |= (1<<1);
1339 if (!create_output) {
1344 /* Delay creation of output until we actually know we want it */
1345 output = xf86OutputCreate (pScrn, &nv_analog_output_funcs, outputname);
1349 output->driver_private = nv_output;
1351 nv_output->pDDCBus = pNv->pI2CBus[i2c_index];
1353 nv_output->ramdac = -1;
1355 output->possible_crtcs = crtc_mask;
1356 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Adding output %s\n", outputname);
1359 static void nv_add_digital_output(ScrnInfoPtr pScrn, int order, int i2c_index, int lvds)
1361 NVPtr pNv = NVPTR(pScrn);
1362 xf86OutputPtr output;
1363 NVOutputPrivatePtr nv_output;
1364 char outputname[20];
1366 Bool create_output = TRUE;
1369 sprintf(outputname, "LVDS-%d", pNv->lvds_count);
1372 sprintf(outputname, "DVI-D-%d", pNv->dvi_d_count);
1376 nv_output = xnfcalloc (sizeof (NVOutputPrivateRec), 1);
1382 if (pNv->dcb_table.i2c_read[i2c_index] && pNv->pI2CBus[i2c_index] == NULL)
1383 NV_I2CInit(pScrn, &pNv->pI2CBus[i2c_index], pNv->dcb_table.i2c_read[i2c_index], xstrdup(outputname));
1385 nv_output->pDDCBus = pNv->pI2CBus[i2c_index];
1388 * bit0: RAMDAC_0 valid
1389 * bit1: RAMDAC_1 valid
1390 * So lowest order has highest priority.
1392 nv_output->valid_ramdac = order;
1394 /* Some early nvidia cards have outputs only valid on secondary */
1395 if (nv_output->valid_ramdac & RAMDAC_0)
1396 crtc_mask |= (1<<0);
1398 /* Restricting this will cause a full mode set when trying to squeeze in the primary mode */
1399 if (nv_output->valid_ramdac & RAMDAC_1)
1400 crtc_mask |= (1<<1);
1403 nv_output->type = OUTPUT_LVDS;
1404 /* comment below two lines to test LVDS under RandR12.
1405 * If your screen "blooms" or "bleeds" (i.e. has a developing
1406 * white / psychedelic pattern) then KILL X IMMEDIATELY
1407 * (ctrl+alt+backspace) & if the effect continues reset power */
1408 ErrorF("Output refused because we don't accept LVDS at the moment.\n");
1409 create_output = FALSE;
1411 nv_output->type = OUTPUT_TMDS;
1414 if (!create_output) {
1419 /* Delay creation of output until we are certain is desirable */
1421 output = xf86OutputCreate (pScrn, &nv_lvds_output_funcs, outputname);
1423 output = xf86OutputCreate (pScrn, &nv_tmds_output_funcs, outputname);
1427 output->driver_private = nv_output;
1429 nv_output->ramdac = -1;
1431 output->possible_crtcs = crtc_mask;
1432 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Adding output %s\n", outputname);
1435 void NvDCBSetupOutputs(ScrnInfoPtr pScrn)
1437 unsigned char type, i2c_index = 0xf, old_i2c_index, or;
1438 NVPtr pNv = NVPTR(pScrn);
1440 Bool dvi_pair[MAX_NUM_DCB_ENTRIES];
1442 /* check how many TMDS ports there are */
1443 if (pNv->dcb_table.entries) {
1444 for (i = 0 ; i < pNv->dcb_table.entries; i++) {
1445 type = pNv->dcb_table.entry[i].type;
1446 old_i2c_index = i2c_index;
1447 i2c_index = pNv->dcb_table.entry[i].i2c_index;
1449 dvi_pair[i] = FALSE;
1451 /* Are we on the same i2c index? */
1452 if (i2c_index != 0xf && i2c_index == old_i2c_index) {
1453 /* Have we passed the analog connector or not? */
1454 if (type == OUTPUT_TMDS) {
1455 dvi_pair[i - 1] = TRUE;
1456 } else if (type == OUTPUT_ANALOG) {
1457 dvi_pair[i ] = TRUE;
1463 /* It's time to gather some information */
1465 /* Being slaved indicates we're a flatpanel (or tv-out) */
1466 if (NVReadVGA0(pNv, NV_VGA_CRTCX_PIXEL) & 0x80) {
1467 pNv->output_info |= OUTPUT_0_SLAVED;
1469 if (NVReadVGA1(pNv, NV_VGA_CRTCX_PIXEL) & 0x80) {
1470 pNv->output_info |= OUTPUT_1_SLAVED;
1472 /* This is an educated guess */
1473 if (NVReadTMDS(pNv, 0, 0x4) & (1 << 3)) {
1474 pNv->output_info |= OUTPUT_0_CROSSWIRED_TMDS;
1476 if (NVReadTMDS(pNv, 1, 0x4) & (1 << 3)) {
1477 pNv->output_info |= OUTPUT_1_CROSSWIRED_TMDS;
1480 if (NVReadTMDS(pNv, 0, 0x4) & (1 << 0)) {
1481 pNv->output_info |= OUTPUT_0_LVDS;
1483 if (NVReadTMDS(pNv, 1, 0x4) & (1 << 0)) {
1484 pNv->output_info |= OUTPUT_1_LVDS;
1487 /* we setup the outputs up from the BIOS table */
1488 for (i = 0 ; i < pNv->dcb_table.entries; i++) {
1489 type = pNv->dcb_table.entry[i].type;
1490 i2c_index = pNv->dcb_table.entry[i].i2c_index;
1491 or = ffs(pNv->dcb_table.entry[i].or);
1494 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "DCB entry %d: type: %d, i2c_index: %d, or: %d\n", i, type, i2c_index, or);
1498 nv_add_analog_output(pScrn, or, i2c_index, dvi_pair[i]);
1501 nv_add_digital_output(pScrn, or, i2c_index, 0);
1504 nv_add_digital_output(pScrn, or, i2c_index, 1);
1513 void NvSetupOutputs(ScrnInfoPtr pScrn)
1515 NVPtr pNv = NVPTR(pScrn);
1517 pNv->Television = FALSE;
1519 memset(pNv->pI2CBus, 0, sizeof(pNv->pI2CBus));
1520 NvDCBSetupOutputs(pScrn);
1523 /*************************************************************************** \
1525 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
1527 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
1528 |* international laws. Users and possessors of this source code are *|
1529 |* hereby granted a nonexclusive, royalty-free copyright license to *|
1530 |* use this code in individual and commercial software. *|
1532 |* Any use of this source code must include, in the user documenta- *|
1533 |* tion and internal comments to the code, notices to the end user *|
1536 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
1538 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
1539 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
1540 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
1541 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
1542 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
1543 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
1544 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
1545 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
1546 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
1547 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
1548 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
1550 |* U.S. Government End Users. This source code is a "commercial *|
1551 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
1552 |* consisting of "commercial computer software" and "commercial *|
1553 |* computer software documentation," as such terms are used in *|
1554 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
1555 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
1556 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
1557 |* all U.S. Government End Users acquire the source code with only *|
1558 |* those rights set forth herein. *|
1560 \***************************************************************************/