2 * Copyright 2006 Dave Airlie
3 * Copyright 2007 Maarten Maathuis
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
26 * decleration is at the bottom of this file as it is rather ugly
40 #include "mipointer.h"
41 #include "windowstr.h"
43 #include <X11/extensions/render.h>
46 #include "nv_include.h"
48 const char *OutputType[] = {
57 const char *MonTypeName[7] = {
68 * TMDS registers are indirect 8 bit registers.
69 * Reading is straightforward, writing a bit odd.
70 * Reading: Write adress (+write protect bit, do not forget this), then read value.
71 * Writing: Write adress (+write protect bit), write value, write adress again and write it again (+write protect bit).
74 void NVWriteTMDS(NVPtr pNv, int ramdac, CARD32 tmds_reg, CARD32 val)
76 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL,
77 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
79 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_DATA, val & 0xff);
81 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL, tmds_reg & 0xff);
82 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL,
83 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
86 CARD8 NVReadTMDS(NVPtr pNv, int ramdac, CARD32 tmds_reg)
88 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL,
89 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
91 return (nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_DATA) & 0xff);
94 void NVOutputWriteTMDS(xf86OutputPtr output, CARD32 tmds_reg, CARD32 val)
96 NVOutputPrivatePtr nv_output = output->driver_private;
97 ScrnInfoPtr pScrn = output->scrn;
98 NVPtr pNv = NVPTR(pScrn);
101 /* Is TMDS programmed on a different output? */
102 /* Always choose the prefered ramdac, since that one contains the tmds stuff */
103 /* Assumption: there is always once output that can only run of the primary ramdac */
104 if (nv_output->valid_ramdac & RAMDAC_1) {
110 NVWriteTMDS(pNv, ramdac, tmds_reg, val);
113 CARD8 NVOutputReadTMDS(xf86OutputPtr output, CARD32 tmds_reg)
115 NVOutputPrivatePtr nv_output = output->driver_private;
116 ScrnInfoPtr pScrn = output->scrn;
117 NVPtr pNv = NVPTR(pScrn);
120 /* Is TMDS programmed on a different output? */
121 /* Always choose the prefered ramdac, since that one contains the tmds stuff */
122 /* Assumption: there is always once output that can only run of the primary ramdac */
123 if (nv_output->valid_ramdac & RAMDAC_1) {
129 return NVReadTMDS(pNv, ramdac, tmds_reg);
132 void NVOutputWriteRAMDAC(xf86OutputPtr output, CARD32 ramdac_reg, CARD32 val)
134 NVOutputPrivatePtr nv_output = output->driver_private;
135 ScrnInfoPtr pScrn = output->scrn;
136 NVPtr pNv = NVPTR(pScrn);
138 nvWriteRAMDAC(pNv, nv_output->ramdac, ramdac_reg, val);
141 CARD32 NVOutputReadRAMDAC(xf86OutputPtr output, CARD32 ramdac_reg)
143 NVOutputPrivatePtr nv_output = output->driver_private;
144 ScrnInfoPtr pScrn = output->scrn;
145 NVPtr pNv = NVPTR(pScrn);
147 return nvReadRAMDAC(pNv, nv_output->ramdac, ramdac_reg);
150 static void nv_output_backlight_enable(xf86OutputPtr output, Bool on)
152 ScrnInfoPtr pScrn = output->scrn;
153 NVPtr pNv = NVPTR(pScrn);
155 ErrorF("nv_output_backlight_enable is called for output %s to turn %s\n", output->name, on ? "on" : "off");
157 /* This is done differently on each laptop. Here we
158 * define the ones we know for sure. */
160 #if defined(__powerpc__)
161 if ((pNv->Chipset == 0x10DE0179) ||
162 (pNv->Chipset == 0x10DE0189) ||
163 (pNv->Chipset == 0x10DE0329)) {
164 /* NV17,18,34 Apple iMac, iBook, PowerBook */
165 CARD32 tmp_pmc, tmp_pcrt;
166 tmp_pmc = nvReadMC(pNv, 0x10F0) & 0x7FFFFFFF;
167 tmp_pcrt = nvReadCRTC0(pNv, NV_CRTC_081C) & 0xFFFFFFFC;
169 tmp_pmc |= (1 << 31);
172 nvWriteMC(pNv, 0x10F0, tmp_pmc);
173 nvWriteCRTC0(pNv, NV_CRTC_081C, tmp_pcrt);
177 if(pNv->twoHeads && ((pNv->Chipset & 0x0ff0) != CHIPSET_NV11))
178 nvWriteMC(pNv, 0x130C, on ? 3 : 7);
182 nv_lvds_output_dpms(xf86OutputPtr output, int mode)
184 NVOutputPrivatePtr nv_output = output->driver_private;
185 NVPtr pNv = NVPTR(output->scrn);
187 if (nv_output->ramdac != -1 && mode != DPMSModeOff) {
188 /* This was not a modeset, but a normal dpms call */
189 pNv->ramdac_active[nv_output->ramdac] = TRUE;
190 ErrorF("Activating ramdac %d\n", nv_output->ramdac);
191 nv_output->ramdac_assigned = TRUE;
195 case DPMSModeStandby:
196 case DPMSModeSuspend:
198 nv_output_backlight_enable(output, 0);
201 nv_output_backlight_enable(output, 1);
206 /* We may be going for modesetting, so we must reset the ramdacs */
207 if (nv_output->ramdac != -1 && mode == DPMSModeOff) {
208 pNv->ramdac_active[nv_output->ramdac] = FALSE;
209 ErrorF("Deactivating ramdac %d\n", nv_output->ramdac);
210 nv_output->ramdac_assigned = FALSE;
215 nv_analog_output_dpms(xf86OutputPtr output, int mode)
217 xf86CrtcPtr crtc = output->crtc;
218 NVOutputPrivatePtr nv_output = output->driver_private;
219 NVPtr pNv = NVPTR(output->scrn);
221 ErrorF("nv_analog_output_dpms is called with mode %d\n", mode);
223 if (nv_output->ramdac != -1) {
224 /* We may be going for modesetting, so we must reset the ramdacs */
225 if (mode == DPMSModeOff) {
226 pNv->ramdac_active[nv_output->ramdac] = FALSE;
227 ErrorF("Deactivating ramdac %d\n", nv_output->ramdac);
228 nv_output->ramdac_assigned = FALSE;
229 /* This was not a modeset, but a normal dpms call */
231 pNv->ramdac_active[nv_output->ramdac] = TRUE;
232 ErrorF("Activating ramdac %d\n", nv_output->ramdac);
233 nv_output->ramdac_assigned = TRUE;
238 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
240 ErrorF("nv_analog_output_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
245 nv_tmds_output_dpms(xf86OutputPtr output, int mode)
247 xf86CrtcPtr crtc = output->crtc;
248 NVOutputPrivatePtr nv_output = output->driver_private;
249 NVPtr pNv = NVPTR(output->scrn);
251 ErrorF("nv_tmds_output_dpms is called with mode %d\n", mode);
253 /* We just woke up again from an actual monitor dpms and not a modeset prepare */
254 /* Put here since we actually need our ramdac to wake up again ;-) */
255 if (nv_output->ramdac != -1 && mode != DPMSModeOff) {
256 pNv->ramdac_active[nv_output->ramdac] = TRUE;
257 nv_output->ramdac_assigned = TRUE;
258 ErrorF("Activating ramdac %d\n", nv_output->ramdac);
261 /* Are we assigned a ramdac already?, else we will be activated during mode set */
262 if (crtc && nv_output->ramdac != -1) {
263 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
265 ErrorF("nv_tmds_output_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
267 CARD32 fpcontrol = nvReadRAMDAC(pNv, nv_output->ramdac, NV_RAMDAC_FP_CONTROL);
269 case DPMSModeStandby:
270 case DPMSModeSuspend:
272 /* cut the TMDS output */
273 fpcontrol |= 0x20000022;
276 /* disable cutting the TMDS output */
277 fpcontrol &= ~0x20000022;
280 nvWriteRAMDAC(pNv, nv_output->ramdac, NV_RAMDAC_FP_CONTROL, fpcontrol);
283 /* We may be going for modesetting, so we must reset the ramdacs */
284 if (nv_output->ramdac != -1 && mode == DPMSModeOff) {
285 pNv->ramdac_active[nv_output->ramdac] = FALSE;
286 nv_output->ramdac_assigned = FALSE;
287 ErrorF("Deactivating ramdac %d\n", nv_output->ramdac);
291 /* This sequence is an optimized/shortened version of what the blob does */
292 uint32_t tmds_regs_nv40[] = { 0x04, 0x05, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x40, 0x43, 0x00, 0x01, 0x02, 0x2e, 0x2f, 0x3a };
293 uint32_t tmds_regs_nv30[] = { 0x04, 0x05, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x29, 0x2a, 0x00, 0x01, 0x02, 0x2e, 0x2f, 0x3a };
295 #define TMDS_REGS(index) ( tmds_regs(pNv, index) )
297 uint32_t tmds_regs(NVPtr pNv, int i)
299 if (pNv->Architecture == NV_ARCH_40) {
300 return tmds_regs_nv40[i];
302 return tmds_regs_nv30[i];
306 #define TMDS_SIZE ( tmds_size(pNv) )
308 uint32_t tmds_size(NVPtr pNv)
310 if (pNv->Architecture == NV_ARCH_40) {
311 return(sizeof(tmds_regs_nv40)/sizeof(tmds_regs_nv40[0]));
313 return(sizeof(tmds_regs_nv30)/sizeof(tmds_regs_nv30[0]));
317 void nv_output_save_state_ext(xf86OutputPtr output, RIVA_HW_STATE *state, Bool override)
319 NVOutputPrivatePtr nv_output = output->driver_private;
320 ScrnInfoPtr pScrn = output->scrn;
321 NVPtr pNv = NVPTR(pScrn);
325 regp = &state->dac_reg[nv_output->ramdac];
326 regp->test_control = NVOutputReadRAMDAC(output, NV_RAMDAC_TEST_CONTROL);
327 regp->unk_670 = NVOutputReadRAMDAC(output, NV_RAMDAC_670);
328 state->config = nvReadFB(pNv, NV_PFB_CFG0);
330 //regp->unk_900 = NVOutputReadRAMDAC(output, NV_RAMDAC_900);
332 /* This exists purely for proper text mode restore */
333 if (override) regp->output = NVOutputReadRAMDAC(output, NV_RAMDAC_OUTPUT);
335 for (i = 0; i < TMDS_SIZE; i++) {
336 regp->TMDS[TMDS_REGS(i)] = NVOutputReadTMDS(output, TMDS_REGS(i));
340 void nv_output_load_state_ext(xf86OutputPtr output, RIVA_HW_STATE *state, Bool override)
342 NVOutputPrivatePtr nv_output = output->driver_private;
344 ScrnInfoPtr pScrn = output->scrn;
345 NVPtr pNv = NVPTR(pScrn);
348 regp = &state->dac_reg[nv_output->ramdac];
350 /* This exists purely for proper text mode restore */
351 if (override) NVOutputWriteRAMDAC(output, NV_RAMDAC_OUTPUT, regp->output);
353 //NVOutputWriteRAMDAC(output, NV_RAMDAC_900, regp->unk_900);
355 NVOutputWriteRAMDAC(output, NV_RAMDAC_TEST_CONTROL, regp->test_control);
356 NVOutputWriteRAMDAC(output, NV_RAMDAC_670, regp->unk_670);
358 for (i = 0; i < TMDS_SIZE; i++) {
359 NVOutputWriteTMDS(output, TMDS_REGS(i), regp->TMDS[TMDS_REGS(i)]);
363 /* NOTE: Don't rely on this data for anything other than restoring VT's */
366 nv_output_save (xf86OutputPtr output)
368 ScrnInfoPtr pScrn = output->scrn;
369 NVPtr pNv = NVPTR(pScrn);
370 RIVA_HW_STATE *state;
371 NVOutputPrivatePtr nv_output = output->driver_private;
372 int ramdac_backup = nv_output->ramdac;
374 ErrorF("nv_output_save is called\n");
376 /* This is early init and we have not yet been assigned a ramdac */
377 /* Always choose the prefered ramdac, for consistentcy */
378 /* Assumption: there is always once output that can only run of the primary ramdac */
379 if (nv_output->valid_ramdac & RAMDAC_1) {
380 nv_output->ramdac = 1;
382 nv_output->ramdac = 0;
385 state = &pNv->SavedReg;
387 /* Due to strange mapping of outputs we could have swapped analog and digital */
388 /* So we force save all the registers */
389 nv_output_save_state_ext(output, state, TRUE);
391 /* restore previous state */
392 nv_output->ramdac = ramdac_backup;
396 nv_output_restore (xf86OutputPtr output)
398 ScrnInfoPtr pScrn = output->scrn;
399 NVPtr pNv = NVPTR(pScrn);
400 RIVA_HW_STATE *state;
401 NVOutputPrivatePtr nv_output = output->driver_private;
402 int ramdac_backup = nv_output->ramdac;
404 ErrorF("nv_output_restore is called\n");
406 /* We want consistent mode restoring and the ramdac entry is variable */
407 /* Always choose the prefered ramdac, for consistentcy */
408 /* Assumption: there is always once output that can only run of the primary ramdac */
409 if (nv_output->valid_ramdac & RAMDAC_1) {
410 nv_output->ramdac = 1;
412 nv_output->ramdac = 0;
415 state = &pNv->SavedReg;
417 /* Due to strange mapping of outputs we could have swapped analog and digital */
418 /* So we force load all the registers */
419 nv_output_load_state_ext(output, state, TRUE);
421 /* restore previous state */
422 nv_output->ramdac = ramdac_backup;
426 nv_output_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
428 if (pMode->Flags & V_DBLSCAN)
429 return MODE_NO_DBLESCAN;
431 if (pMode->Clock > 400000 || pMode->Clock < 25000)
432 return MODE_CLOCK_RANGE;
439 nv_output_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
440 DisplayModePtr adjusted_mode)
442 ErrorF("nv_output_mode_fixup is called\n");
448 nv_output_mode_set_regs(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode)
450 NVOutputPrivatePtr nv_output = output->driver_private;
451 ScrnInfoPtr pScrn = output->scrn;
452 NVPtr pNv = NVPTR(pScrn);
453 RIVA_HW_STATE *state, *sv_state;
455 Bool is_lvds = FALSE;
456 NVOutputRegPtr regp, regp2, savep;
457 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
460 xf86CrtcPtr crtc = output->crtc;
461 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
463 state = &pNv->ModeReg;
464 regp = &state->dac_reg[nv_output->ramdac];
465 /* The other ramdac */
466 regp2 = &state->dac_reg[(~(nv_output->ramdac)) & 1];
468 sv_state = &pNv->SavedReg;
469 savep = &sv_state->dac_reg[nv_output->ramdac];
471 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS)) {
473 if (nv_output->type == OUTPUT_LVDS) {
478 /* This is just a guess, there are probably more registers which need setting */
479 /* But we must start somewhere ;-) */
481 regp->TMDS[0x4] = 0x80;
482 /* Enable crosswired mode */
483 /* This will upset the monitor, trust me, i know it :-( */
484 /* Now allowed for non-bios inited systems */
485 if (nv_crtc->head != nv_output->preferred_crtc) {
486 regp->TMDS[0x4] |= (1 << 3);
490 regp->TMDS[0x4] |= (1 << 0);
494 /* The TMDS game begins */
495 /* A few registers are also programmed on non-tmds monitors */
496 /* At the moment i can't give rationale for these values */
498 regp->TMDS[0x2e] = 0x80;
499 regp->TMDS[0x2f] = 0xff;
500 regp->TMDS[0x33] = 0xfe;
502 NVCrtcPrivatePtr nv_crtc = output->crtc->driver_private;
503 uint32_t pll_setup_control = nvReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SETUP_CONTROL);
504 regp->TMDS[0x2b] = 0x7d;
505 regp->TMDS[0x2c] = 0x0;
506 /* Various combinations exist for lvds, 0x08, 0x48, 0xc8, 0x88 */
507 /* 0x88 seems most popular and (maybe) the end setting */
509 if (pNv->Architecture == NV_ARCH_40) {
510 regp->TMDS[0x2e] = 0x88;
512 /* observed on nv31m */
513 regp->TMDS[0x2e] = 0x0;
516 if (nv_crtc->head == 1) {
517 regp->TMDS[0x2e] = 0x81;
519 regp->TMDS[0x2e] = 0x85;
522 /* 0x08 is also seen for lvds */
523 regp->TMDS[0x2f] = 0x21;
524 regp->TMDS[0x30] = 0x0;
525 regp->TMDS[0x31] = 0x0;
526 regp->TMDS[0x32] = 0x0;
527 regp->TMDS[0x33] = 0xf0;
528 /* 0x00 is also seen for lvds */
529 regp->TMDS[0x3a] = 0x80;
531 /* Here starts the registers that may cause problems for some */
532 /* This an educated guess */
533 if (pNv->Architecture == NV_ARCH_40 && pNv->misc_info.reg_c040 & (1 << 10)) {
534 regp->TMDS[0x5] = 0x68;
536 regp->TMDS[0x5] = 0x6e;
540 if (pNv->Architecture == NV_ARCH_40) {
541 regp->TMDS[0x0] = 0x61;
543 /* observed on a nv31m */
544 regp->TMDS[0x0] = 0x71;
547 /* This seems to be related to PLL_SETUP_CONTROL */
548 /* When PLL_SETUP_CONTROL ends with 0x1c, then this value is 0xc1 */
550 if ((pll_setup_control & 0xff) == 0x1c) {
551 regp->TMDS[0x0] = 0xc1;
553 regp->TMDS[0x0] = 0xf1;
557 /* This is also related to PLL_SETUP_CONTROL, exactly how is unknown */
558 if (pll_setup_control == 0) {
559 regp->TMDS[0x1] = 0x0;
561 if (nvReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK) & (1<<12)) {
562 regp->TMDS[0x1] = 0x41;
564 regp->TMDS[0x1] = 0x42;
569 regp->TMDS[0x2] = 0x0;
571 if (pll_setup_control == 0x0) {
572 regp->TMDS[0x2] = 0x90;
574 regp->TMDS[0x2] = 0x89;
578 /* I assume they are zero for !is_lvds */
579 if (is_lvds && pNv->Architecture == NV_ARCH_40) {
580 /* Observed values are 0x11 and 0x14, TODO: this needs refinement */
581 regp->TMDS[0x40] = 0x14;
582 regp->TMDS[0x43] = 0xb0;
586 /* Put test control into what seems to be the neutral position */
587 if (pNv->NVArch < 0x44) {
588 regp->test_control = 0x00000000;
590 regp->test_control = 0x00100000;
593 /* This is a similar register to test control */
594 regp->unk_670 = regp->test_control;
596 /* This may be causing problems */
597 //regp->unk_900 = 0x10000;
600 NVCrtcPrivatePtr nv_crtc = output->crtc->driver_private;
604 for (i = 0; i < config->num_output; i++) {
605 NVOutputPrivatePtr nv_output2 = config->output[i]->driver_private;
607 /* is it this output ?? */
608 if (config->output[i] == output)
611 /* it the output connected */
612 if (config->output[i]->crtc == NULL)
616 if ((nv_output2->type == OUTPUT_ANALOG) && (nv_output->type == OUTPUT_ANALOG)) {
621 ErrorF("%d: crtc %d ramdac %d twocrt %d twomon %d\n", is_fp, nv_crtc->crtc, nv_output->ramdac, two_crt, two_mon);
626 nv_output_mode_set_routing(xf86OutputPtr output)
628 NVOutputPrivatePtr nv_output = output->driver_private;
629 xf86CrtcPtr crtc = output->crtc;
630 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
631 ScrnInfoPtr pScrn = output->scrn;
632 NVPtr pNv = NVPTR(pScrn);
634 int other_ramdac = 0;
636 uint32_t output_reg = nvReadRAMDAC(pNv, nv_output->ramdac, NV_RAMDAC_OUTPUT);
638 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS)) {
645 output_reg = NV_RAMDAC_OUTPUT_DAC_ENABLE;
648 if (nv_crtc->head == 1) {
649 output_reg |= NV_RAMDAC_OUTPUT_SELECT_VPLL2;
651 output_reg &= ~NV_RAMDAC_OUTPUT_SELECT_VPLL2;
654 if (nv_output->ramdac == 1) {
660 uint32_t output2_reg = nvReadRAMDAC(pNv, other_ramdac, NV_RAMDAC_OUTPUT);
662 if (nv_crtc->head == 1) {
663 output2_reg &= ~NV_RAMDAC_OUTPUT_SELECT_VPLL2;
665 output2_reg |= NV_RAMDAC_OUTPUT_SELECT_VPLL2;
668 nvWriteRAMDAC(pNv, nv_output->ramdac, NV_RAMDAC_OUTPUT, output_reg);
669 nvWriteRAMDAC(pNv, other_ramdac, NV_RAMDAC_OUTPUT, output2_reg);
673 nv_output_mode_set(xf86OutputPtr output, DisplayModePtr mode,
674 DisplayModePtr adjusted_mode)
676 ScrnInfoPtr pScrn = output->scrn;
677 NVPtr pNv = NVPTR(pScrn);
678 RIVA_HW_STATE *state;
680 ErrorF("nv_output_mode_set is called\n");
682 state = &pNv->ModeReg;
684 nv_output_mode_set_regs(output, mode, adjusted_mode);
685 nv_output_load_state_ext(output, state, FALSE);
686 nv_output_mode_set_routing(output);
690 nv_get_edid(xf86OutputPtr output)
692 /* no use for shared DDC output */
693 NVOutputPrivatePtr nv_output = output->driver_private;
696 if (nv_output->pDDCBus == NULL)
699 ddc_mon = xf86OutputGetEDID(output, nv_output->pDDCBus);
703 if (ddc_mon->features.input_type && (nv_output->type == OUTPUT_ANALOG))
706 if ((!ddc_mon->features.input_type) && (nv_output->type == OUTPUT_TMDS ||
707 nv_output->type == OUTPUT_LVDS))
718 nv_ddc_detect(xf86OutputPtr output)
720 xf86MonPtr m = nv_get_edid(output);
730 nv_crt_load_detect(xf86OutputPtr output)
732 ScrnInfoPtr pScrn = output->scrn;
733 NVOutputPrivatePtr nv_output = output->driver_private;
734 NVPtr pNv = NVPTR(pScrn);
735 CARD32 reg_output, reg_test_ctrl, temp;
736 Bool present = FALSE;
739 /* Usually these outputs are native to ramdac 1 */
740 if (nv_output->valid_ramdac & RAMDAC_0 && nv_output->valid_ramdac & RAMDAC_1) {
742 } else if (nv_output->valid_ramdac & RAMDAC_1) {
744 } else if (nv_output->valid_ramdac & RAMDAC_0) {
750 /* For some reason we get false positives on ramdac 1, maybe due tv-out? */
755 if (nv_output->pDDCBus != NULL) {
756 xf86MonPtr ddc_mon = xf86OutputGetEDID(output, nv_output->pDDCBus);
757 /* Is there a digital flatpanel on this channel? */
758 if (ddc_mon && ddc_mon->features.input_type) {
763 reg_output = nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_OUTPUT);
764 reg_test_ctrl = nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL);
766 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL, (reg_test_ctrl & ~0x00010000));
768 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_OUTPUT, (reg_output & 0x0000FEEE));
771 temp = nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_OUTPUT);
772 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_OUTPUT, temp | 1);
774 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_DATA, 0x94050140);
775 temp = nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL);
776 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL, temp | 0x1000);
780 present = (nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL) & (1 << 28)) ? TRUE : FALSE;
782 temp = NVOutputReadRAMDAC(output, NV_RAMDAC_TEST_CONTROL);
783 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL, temp & 0x000EFFF);
785 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_OUTPUT, reg_output);
786 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_TEST_CONTROL, reg_test_ctrl);
789 ErrorF("A crt was detected on ramdac %d with no ddc support\n", ramdac);
796 static xf86OutputStatus
797 nv_tmds_output_detect(xf86OutputPtr output)
799 ErrorF("nv_tmds_output_detect is called\n");
801 if (nv_ddc_detect(output))
802 return XF86OutputStatusConnected;
804 return XF86OutputStatusDisconnected;
808 static xf86OutputStatus
809 nv_analog_output_detect(xf86OutputPtr output)
811 ErrorF("nv_analog_output_detect is called\n");
813 if (nv_ddc_detect(output))
814 return XF86OutputStatusConnected;
816 if (nv_crt_load_detect(output))
817 return XF86OutputStatusConnected;
819 return XF86OutputStatusDisconnected;
822 static DisplayModePtr
823 nv_output_get_modes(xf86OutputPtr output)
825 NVOutputPrivatePtr nv_output = output->driver_private;
827 DisplayModePtr ddc_modes;
829 ErrorF("nv_output_get_modes is called\n");
831 ddc_mon = nv_get_edid(output);
833 xf86OutputSetEDID(output, ddc_mon);
838 ddc_modes = xf86OutputGetEDIDModes (output);
840 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
844 for (i = 0; i < 4; i++) {
845 /* We only look at detailed timings atm */
846 if (ddc_mon->det_mon[i].type != DT)
848 /* Selecting only based on width ok? */
849 if (ddc_mon->det_mon[i].section.d_timings.h_active > nv_output->fpWidth) {
850 nv_output->fpWidth = ddc_mon->det_mon[i].section.d_timings.h_active;
851 nv_output->fpHeight = ddc_mon->det_mon[i].section.d_timings.v_active;
855 /* Add a native resolution mode that is preferred */
856 /* Reduced blanking should be fine on DVI monitor */
857 nv_output->native_mode = xf86CVTMode(nv_output->fpWidth, nv_output->fpHeight, 60.0, TRUE, FALSE);
858 nv_output->native_mode->type = M_T_DRIVER | M_T_PREFERRED;
859 /* We want the new mode to be preferred */
860 for (mode = ddc_modes; mode != NULL; mode = mode->next) {
861 if (mode->type & M_T_PREFERRED) {
862 mode->type &= ~M_T_PREFERRED;
865 ddc_modes = xf86ModesAdd(ddc_modes, nv_output->native_mode);
872 nv_output_destroy (xf86OutputPtr output)
874 ErrorF("nv_output_destroy is called\n");
875 if (output->driver_private)
876 xfree (output->driver_private);
880 nv_clear_ramdac_from_outputs(xf86OutputPtr output, int ramdac)
883 ScrnInfoPtr pScrn = output->scrn;
884 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
885 xf86OutputPtr output2;
886 NVOutputPrivatePtr nv_output2;
887 for (i = 0; i < xf86_config->num_output; i++) {
888 output2 = xf86_config->output[i];
889 nv_output2 = output2->driver_private;
890 if (nv_output2->ramdac == ramdac && output != output2) {
891 nv_output2->ramdac = -1;
892 nv_output2->ramdac_assigned = FALSE;
899 nv_output_prepare(xf86OutputPtr output)
901 ErrorF("nv_output_prepare is called\n");
902 NVOutputPrivatePtr nv_output = output->driver_private;
903 ScrnInfoPtr pScrn = output->scrn;
904 NVPtr pNv = NVPTR(pScrn);
905 Bool stole_ramdac = FALSE;
906 xf86OutputPtr output2 = NULL;
908 output->funcs->dpms(output, DPMSModeOff);
910 if (nv_output->ramdac_assigned) {
911 ErrorF("We already have a ramdac.\n");
915 /* We need ramdac 0, so let's steal it */
916 if (!(nv_output->valid_ramdac & RAMDAC_1) && pNv->ramdac_active[0]) {
917 ErrorF("Stealing ramdac0 ;-)\n");
919 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
920 NVOutputPrivatePtr nv_output2;
921 for (i = 0; i < xf86_config->num_output; i++) {
922 output2 = xf86_config->output[i];
923 nv_output2 = output2->driver_private;
924 if (nv_output2->ramdac == 0 && output != output2) {
925 nv_output2->ramdac = -1;
926 nv_output2->ramdac_assigned = FALSE;
930 pNv->ramdac_active[0] = FALSE;
934 /* We need ramdac 1, so let's steal it */
935 if (!(nv_output->valid_ramdac & RAMDAC_0) && pNv->ramdac_active[1]) {
936 ErrorF("Stealing ramdac1 ;-)\n");
938 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
939 NVOutputPrivatePtr nv_output2;
940 for (i = 0; i < xf86_config->num_output; i++) {
941 output2 = xf86_config->output[i];
942 nv_output2 = output2->driver_private;
943 if (nv_output2->ramdac == 1 && output != output2) {
944 nv_output2->ramdac = -1;
945 nv_output2->ramdac_assigned = FALSE;
949 pNv->ramdac_active[1] = FALSE;
953 /* TODO: figure out what ramdac 2 is and how it is identified */
955 /* At this point we already stole ramdac 0 or 1 if we need it */
956 if (!pNv->ramdac_active[0] && (nv_output->valid_ramdac & RAMDAC_0)) {
957 ErrorF("Activating ramdac %d\n", 0);
958 pNv->ramdac_active[0] = TRUE;
959 nv_output->ramdac = 0;
961 ErrorF("Activating ramdac %d\n", 1);
962 pNv->ramdac_active[1] = TRUE;
963 nv_output->ramdac = 1;
966 if (nv_output->ramdac != -1) {
967 nv_output->ramdac_assigned = TRUE;
968 nv_clear_ramdac_from_outputs(output, nv_output->ramdac);
972 ErrorF("Resetting the stolen ramdac\n");
973 output2->funcs->prepare(output2);
974 output2->funcs->mode_set(output2, &(output2->crtc->desiredMode), &(output2->crtc->desiredMode));
979 nv_output_commit(xf86OutputPtr output)
981 ErrorF("nv_output_commit is called\n");
983 output->funcs->dpms(output, DPMSModeOn);
986 static const xf86OutputFuncsRec nv_analog_output_funcs = {
987 .dpms = nv_analog_output_dpms,
988 .save = nv_output_save,
989 .restore = nv_output_restore,
990 .mode_valid = nv_output_mode_valid,
991 .mode_fixup = nv_output_mode_fixup,
992 .mode_set = nv_output_mode_set,
993 .detect = nv_analog_output_detect,
994 .get_modes = nv_output_get_modes,
995 .destroy = nv_output_destroy,
996 .prepare = nv_output_prepare,
997 .commit = nv_output_commit,
1000 static const xf86OutputFuncsRec nv_tmds_output_funcs = {
1001 .dpms = nv_tmds_output_dpms,
1002 .save = nv_output_save,
1003 .restore = nv_output_restore,
1004 .mode_valid = nv_output_mode_valid,
1005 .mode_fixup = nv_output_mode_fixup,
1006 .mode_set = nv_output_mode_set,
1007 .detect = nv_tmds_output_detect,
1008 .get_modes = nv_output_get_modes,
1009 .destroy = nv_output_destroy,
1010 .prepare = nv_output_prepare,
1011 .commit = nv_output_commit,
1014 static int nv_lvds_output_mode_valid
1015 (xf86OutputPtr output, DisplayModePtr pMode)
1017 NVOutputPrivatePtr nv_output = output->driver_private;
1019 /* No modes > panel's native res */
1020 if (pMode->HDisplay > nv_output->fpWidth || pMode->VDisplay > nv_output->fpHeight)
1023 return nv_output_mode_valid(output, pMode);
1026 static xf86OutputStatus
1027 nv_lvds_output_detect(xf86OutputPtr output)
1029 ScrnInfoPtr pScrn = output->scrn;
1030 NVPtr pNv = NVPTR(pScrn);
1032 if (pNv->fp_native_mode || nv_ddc_detect(output))
1033 return XF86OutputStatusConnected;
1035 return XF86OutputStatusDisconnected;
1038 static DisplayModePtr
1039 nv_lvds_output_get_modes(xf86OutputPtr output)
1041 ScrnInfoPtr pScrn = output->scrn;
1042 NVPtr pNv = NVPTR(pScrn);
1043 NVOutputPrivatePtr nv_output = output->driver_private;
1044 DisplayModePtr modes;
1046 if ((modes = nv_output_get_modes(output)))
1049 /* it is possible to set up a mode from what we can read from the
1050 * RAMDAC registers, but if we can't read the BIOS table correctly
1051 * we might as well give up */
1052 if (pNv->fp_native_mode == NULL)
1055 nv_output->fpWidth = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_HDISP_END) + 1;
1056 nv_output->fpHeight = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_VDISP_END) + 1;
1057 nv_output->fpSyncs = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_CONTROL) & 0x30000033;
1059 if (pNv->fp_native_mode->HDisplay != nv_output->fpWidth ||
1060 pNv->fp_native_mode->VDisplay != nv_output->fpHeight) {
1061 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1062 "Panel size mismatch; ignoring RAMDAC\n");
1063 nv_output->fpWidth = pNv->fp_native_mode->HDisplay;
1064 nv_output->fpHeight = pNv->fp_native_mode->VDisplay;
1067 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Panel size is %u x %u\n",
1068 nv_output->fpWidth, nv_output->fpHeight);
1070 nv_output->native_mode = xf86DuplicateMode(pNv->fp_native_mode);
1072 return xf86DuplicateMode(pNv->fp_native_mode);
1075 static const xf86OutputFuncsRec nv_lvds_output_funcs = {
1076 .dpms = nv_lvds_output_dpms,
1077 .save = nv_output_save,
1078 .restore = nv_output_restore,
1079 .mode_valid = nv_lvds_output_mode_valid,
1080 .mode_fixup = nv_output_mode_fixup,
1081 .mode_set = nv_output_mode_set,
1082 .detect = nv_lvds_output_detect,
1083 .get_modes = nv_lvds_output_get_modes,
1084 .destroy = nv_output_destroy,
1085 .prepare = nv_output_prepare,
1086 .commit = nv_output_commit,
1089 static void nv_add_analog_output(ScrnInfoPtr pScrn, int heads, int order, int i2c_index, Bool dvi_pair)
1091 NVPtr pNv = NVPTR(pScrn);
1092 xf86OutputPtr output;
1093 NVOutputPrivatePtr nv_output;
1094 char outputname[20];
1095 Bool create_output = TRUE;
1097 /* DVI have an analog connector and a digital one, differentiate between that and a normal vga */
1099 sprintf(outputname, "DVI-A-%d", pNv->dvi_a_count);
1102 sprintf(outputname, "VGA-%d", pNv->vga_count);
1106 nv_output = xnfcalloc (sizeof (NVOutputPrivateRec), 1);
1111 if (pNv->dcb_table.i2c_read[i2c_index] && pNv->pI2CBus[i2c_index] == NULL)
1112 NV_I2CInit(pScrn, &pNv->pI2CBus[i2c_index], pNv->dcb_table.i2c_read[i2c_index], xstrdup(outputname));
1114 nv_output->type = OUTPUT_ANALOG;
1117 * bit0: RAMDAC_0 valid
1118 * bit1: RAMDAC_1 valid
1119 * So lowest order has highest priority.
1120 * Below is guesswork:
1121 * bit2: All ramdac's valid?
1122 * FIXME: this probably wrong
1124 nv_output->valid_ramdac = order;
1126 if (!create_output) {
1131 /* Delay creation of output until we actually know we want it */
1132 output = xf86OutputCreate (pScrn, &nv_analog_output_funcs, outputname);
1136 output->driver_private = nv_output;
1138 nv_output->pDDCBus = pNv->pI2CBus[i2c_index];
1140 nv_output->ramdac = -1;
1142 /* This is only to facilitate proper output routing for dvi */
1143 /* See sel_clk assignment in nv_crtc.c */
1144 if (order & RAMDAC_1) {
1145 nv_output->preferred_crtc = 1;
1147 nv_output->preferred_crtc = 0;
1150 output->possible_crtcs = heads;
1151 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Adding output %s\n", outputname);
1154 static void nv_add_digital_output(ScrnInfoPtr pScrn, int heads, int order, int i2c_index, int lvds)
1156 NVPtr pNv = NVPTR(pScrn);
1157 xf86OutputPtr output;
1158 NVOutputPrivatePtr nv_output;
1159 char outputname[20];
1160 Bool create_output = TRUE;
1163 sprintf(outputname, "LVDS-%d", pNv->lvds_count);
1166 sprintf(outputname, "DVI-D-%d", pNv->dvi_d_count);
1170 nv_output = xnfcalloc (sizeof (NVOutputPrivateRec), 1);
1176 if (pNv->dcb_table.i2c_read[i2c_index] && pNv->pI2CBus[i2c_index] == NULL)
1177 NV_I2CInit(pScrn, &pNv->pI2CBus[i2c_index], pNv->dcb_table.i2c_read[i2c_index], xstrdup(outputname));
1179 nv_output->pDDCBus = pNv->pI2CBus[i2c_index];
1182 * bit0: RAMDAC_0 valid
1183 * bit1: RAMDAC_1 valid
1184 * So lowest order has highest priority.
1185 * Below is guesswork:
1186 * bit2: All ramdac's valid?
1187 * FIXME: this probably wrong
1189 nv_output->valid_ramdac = order;
1192 nv_output->type = OUTPUT_LVDS;
1193 /* comment below two lines to test LVDS under RandR12.
1194 * If your screen "blooms" or "bleeds" (i.e. has a developing
1195 * white / psychedelic pattern) then KILL X IMMEDIATELY
1196 * (ctrl+alt+backspace) & if the effect continues reset power */
1197 ErrorF("Output refused because we don't accept LVDS at the moment.\n");
1198 create_output = FALSE;
1200 nv_output->type = OUTPUT_TMDS;
1203 if (!create_output) {
1208 /* Delay creation of output until we are certain is desirable */
1210 output = xf86OutputCreate (pScrn, &nv_lvds_output_funcs, outputname);
1212 output = xf86OutputCreate (pScrn, &nv_tmds_output_funcs, outputname);
1216 output->driver_private = nv_output;
1218 nv_output->ramdac = -1;
1220 /* This is a theory: */
1221 /* DVI outputs are in no way bound to ramdac's, but exist purely on a crtc level */
1222 /* Don't ask why this relation seems valid, ask those weirdos at nvidia */
1223 if (order & RAMDAC_1) {
1224 nv_output->preferred_crtc = 1;
1226 nv_output->preferred_crtc = 0;
1229 output->possible_crtcs = heads;
1230 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Adding output %s\n", outputname);
1233 void NvDCBSetupOutputs(ScrnInfoPtr pScrn)
1235 unsigned char type, i2c_index, or, heads, bus;
1236 NVPtr pNv = NVPTR(pScrn);
1237 int i, bus_count[0xf];
1239 memset(bus_count, 0, sizeof(bus_count));
1240 for (i = 0 ; i < pNv->dcb_table.entries; i++)
1241 bus_count[pNv->dcb_table.entry[i].bus]++;
1243 /* we setup the outputs up from the BIOS table */
1244 for (i = 0 ; i < pNv->dcb_table.entries; i++) {
1245 type = pNv->dcb_table.entry[i].type;
1246 i2c_index = pNv->dcb_table.entry[i].i2c_index;
1247 or = ffs(pNv->dcb_table.entry[i].or);
1248 heads = pNv->dcb_table.entry[i].head;
1249 bus = pNv->dcb_table.entry[i].bus;
1252 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DCB type %d not known\n", type);
1256 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "DCB entry %d: type: %d, i2c_index: %d, head: %d, bus: %d, or: %d\n", i, type, i2c_index, heads, bus, or);
1260 nv_add_analog_output(pScrn, heads, or, i2c_index, (bus_count[bus] > 1));
1263 nv_add_digital_output(pScrn, heads, or, i2c_index, 0);
1266 nv_add_digital_output(pScrn, heads, or, i2c_index, 1);
1274 void NvSetupOutputs(ScrnInfoPtr pScrn)
1276 NVPtr pNv = NVPTR(pScrn);
1278 pNv->Television = FALSE;
1280 memset(pNv->pI2CBus, 0, sizeof(pNv->pI2CBus));
1281 NvDCBSetupOutputs(pScrn);
1284 /*************************************************************************** \
1286 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
1288 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
1289 |* international laws. Users and possessors of this source code are *|
1290 |* hereby granted a nonexclusive, royalty-free copyright license to *|
1291 |* use this code in individual and commercial software. *|
1293 |* Any use of this source code must include, in the user documenta- *|
1294 |* tion and internal comments to the code, notices to the end user *|
1297 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
1299 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
1300 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
1301 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
1302 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
1303 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
1304 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
1305 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
1306 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
1307 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
1308 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
1309 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
1311 |* U.S. Government End Users. This source code is a "commercial *|
1312 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
1313 |* consisting of "commercial computer software" and "commercial *|
1314 |* computer software documentation," as such terms are used in *|
1315 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
1316 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
1317 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
1318 |* all U.S. Government End Users acquire the source code with only *|
1319 |* those rights set forth herein. *|
1321 \***************************************************************************/