2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2008 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "nv_include.h"
28 #if defined(__FreeBSD__) || defined(__NetBSD__)
29 #define bswap_16 bswap16
30 #define bswap_32 bswap32
36 /* FIXME: put these somewhere */
37 #define SEQ_INDEX VGA_SEQ_INDEX
38 #define NV_CIO_CRE_44_HEADA 0x0
39 #define NV_CIO_CRE_44_HEADB 0x3
40 #define FEATURE_MOBILE 0x10
42 //#define BIOSLOG(sip, fmt, arg...) xf86DrvMsg(sip->scrnIndex, X_INFO, fmt, ##arg)
43 //#define LOG_OLD_VALUE(x) x
44 #define BIOSLOG(sip, fmt, arg...)
45 #define LOG_OLD_VALUE(x)
47 #define BIOS_USLEEP(n) usleep(n)
49 static int crtchead = 0;
51 /* this will need remembering across a suspend */
52 static uint32_t saved_nv_pfb_cfg0;
59 static uint16_t le16_to_cpu(const uint16_t x)
61 #if X_BYTE_ORDER == X_BIG_ENDIAN
68 static uint32_t le32_to_cpu(const uint32_t x)
70 #if X_BYTE_ORDER == X_BIG_ENDIAN
77 static bool nv_cksum(const uint8_t *data, unsigned int length)
79 /* there's a few checksums in the BIOS, so here's a generic checking function */
83 for (i = 0; i < length; i++)
92 static int score_vbios(ScrnInfoPtr pScrn, const uint8_t *data)
94 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
95 xf86DrvMsg(pScrn->scrnIndex, X_NOTICE, "... BIOS signature not found\n");
99 if (nv_cksum(data, data[2] * 512)) {
100 xf86DrvMsg(pScrn->scrnIndex, X_NOTICE, "... BIOS checksum invalid\n");
103 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "... appears to be valid\n");
108 static void load_vbios_prom(NVPtr pNv, uint8_t *data)
112 /* enable ROM access */
113 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED);
114 for (i = 0; i < NV_PROM_SIZE; i++) {
115 /* according to nvclock, we need that to work around a 6600GT/6800LE bug */
116 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
117 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
118 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
119 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
120 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
122 /* disable ROM access */
123 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
126 static void load_vbios_pramin(NVPtr pNv, uint8_t *data)
128 uint32_t old_bar0_pramin = 0;
131 if (pNv->Architecture >= NV_ARCH_50) {
132 uint32_t vbios_vram = (NV_RD32(pNv->REGS, 0x619f04) & ~0xff) << 8;
135 vbios_vram = (NV_RD32(pNv->REGS, 0x1700) << 16) + 0xf0000;
137 old_bar0_pramin = NV_RD32(pNv->REGS, 0x1700);
138 NV_WR32(pNv->REGS, 0x1700, vbios_vram >> 16);
141 for (i = 0; i < NV_PROM_SIZE; i++)
142 data[i] = NV_RD08(pNv->REGS, NV_PRAMIN_OFFSET + i);
144 if (pNv->Architecture >= NV_ARCH_50)
145 NV_WR32(pNv->REGS, 0x1700, old_bar0_pramin);
148 static void load_vbios_pci(NVPtr pNv, uint8_t *data)
150 #if XSERVER_LIBPCIACCESS
151 pci_device_read_rom(pNv->PciInfo, data);
153 xf86ReadPciBIOS(0, pNv->PciTag, 0, data, NV_PROM_SIZE);
157 static bool NVShadowVBIOS(ScrnInfoPtr pScrn, uint8_t *data)
159 NVPtr pNv = NVPTR(pScrn);
162 void (*loadbios)(NVPtr, uint8_t *);
166 { "PROM", load_vbios_prom },
168 { "PRAMIN", load_vbios_pramin },
170 { "PCI ROM", load_vbios_pci }
175 for (i = 0; i < sizeof(method) / sizeof(struct methods); i++) {
176 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
177 "Attempting to load BIOS image from %s\n", method[i].desc);
178 method[i].loadbios(pNv, data);
179 if ((method[i].score = score_vbios(pScrn, data)) == 2)
183 for (i = 0; i < sizeof(method) / sizeof(struct methods); i++)
184 if (method[i].score == 1) {
185 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
186 "Using BIOS image from %s\n", method[i].desc);
187 method[i].loadbios(pNv, data);
191 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid BIOS image found\n");
201 int length_multiplier;
202 bool (*handler)(ScrnInfoPtr pScrn, bios_t *, uint16_t, init_exec_t *);
211 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec);
213 #define MACRO_INDEX_SIZE 2
215 #define CONDITION_SIZE 12
216 #define IO_FLAG_CONDITION_SIZE 9
217 #define MEM_INIT_SIZE 66
219 static void still_alive(void)
222 // BIOS_USLEEP(2000);
225 static int nv_valid_reg(ScrnInfoPtr pScrn, uint32_t reg)
227 NVPtr pNv = NVPTR(pScrn);
229 /* C51 has misaligned regs on purpose. Marvellous */
230 if ((reg & 0x3 && pNv->VBIOS.chip_version != 0x51) ||
231 (reg & 0x2 && pNv->VBIOS.chip_version == 0x51)) {
232 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
233 "========== misaligned reg 0x%08X ==========\n", reg);
237 #define WITHIN(x,y,z) ((x>=y)&&(x<=y+z))
238 if (WITHIN(reg,NV_PMC_OFFSET,NV_PMC_SIZE))
240 if (WITHIN(reg,NV_PBUS_OFFSET,NV_PBUS_SIZE))
242 if (WITHIN(reg,NV_PFIFO_OFFSET,NV_PFIFO_SIZE))
244 /* maybe a little large, but it will do for the moment. */
245 if (pNv->VBIOS.chip_version >= 0x80 && WITHIN(reg, 0x1000, 0xEFFF))
247 if (pNv->VBIOS.chip_version >= 0x30 && WITHIN(reg,0x4000,0x600))
249 if (pNv->VBIOS.chip_version >= 0x40 && WITHIN(reg,0xc000,0x48))
251 if (pNv->VBIOS.chip_version >= 0x17 && reg == 0x0000d204)
253 if (pNv->VBIOS.chip_version >= 0x40) {
254 if (reg == 0x00011014 || reg == 0x00020328)
256 if (WITHIN(reg,0x88000,NV_PBUS_SIZE)) /* new PBUS */
259 if (WITHIN(reg,NV_PFB_OFFSET,NV_PFB_SIZE))
261 if (WITHIN(reg,NV_PEXTDEV_OFFSET,NV_PEXTDEV_SIZE))
263 if (WITHIN(reg,NV_PCRTC0_OFFSET,NV_PCRTC0_SIZE * 2))
265 if (pNv->VBIOS.chip_version >= 0x80 && WITHIN(reg, NV50_DISPLAY_OFFSET, NV50_DISPLAY_SIZE))
267 if (WITHIN(reg,NV_PRAMDAC0_OFFSET,NV_PRAMDAC0_SIZE * 2))
269 if (pNv->VBIOS.chip_version >= 0x17 && reg == 0x0070fff0)
271 if (pNv->VBIOS.chip_version == 0x51 && WITHIN(reg,NV_PRAMIN_OFFSET,NV_PRAMIN_SIZE))
275 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
276 "========== unknown reg 0x%08X ==========\n", reg);
281 static bool nv_valid_idx_port(ScrnInfoPtr pScrn, uint16_t port)
283 /* if adding more ports here, the read/write functions below will need
284 * updating so that the correct mmio range (PCIO, PDIO, PVIO) is used
285 * for the port in question
287 if (port == CRTC_INDEX_COLOR)
289 if (port == SEQ_INDEX)
292 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
293 "========== unknown indexed io port 0x%04X ==========\n", port);
298 static bool nv_valid_port(ScrnInfoPtr pScrn, uint16_t port)
300 /* if adding more ports here, the read/write functions below will need
301 * updating so that the correct mmio range (PCIO, PDIO, PVIO) is used
302 * for the port in question
304 if (port == VGA_ENABLE)
307 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
308 "========== unknown io port 0x%04X ==========\n", port);
313 static uint32_t nv32_rd(ScrnInfoPtr pScrn, uint32_t reg)
315 NVPtr pNv = NVPTR(pScrn);
318 if (!nv_valid_reg(pScrn, reg))
321 /* C51 sometimes uses regs with bit0 set in the address. For these
322 * cases there should exist a translation in a BIOS table to an IO
323 * port address which the BIOS uses for accessing the reg
325 * These only seem to appear for the power control regs to a flat panel
326 * and in C51 mmio traces the normal regs for 0x1308 and 0x1310 are
327 * used - hence the mask below. An S3 suspend-resume mmio trace from a
328 * C51 will be required to see if this is true for the power microcode
329 * in 0x14.., or whether the direct IO port access method is needed
334 data = NV_RD32(pNv->REGS, reg);
336 BIOSLOG(pScrn, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
341 static void nv32_wr(ScrnInfoPtr pScrn, uint32_t reg, uint32_t data)
343 NVPtr pNv = NVPTR(pScrn);
345 if (!nv_valid_reg(pScrn, reg))
348 /* see note in nv32_rd */
352 LOG_OLD_VALUE(nv32_rd(pScrn, reg));
353 BIOSLOG(pScrn, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
355 if (pNv->VBIOS.execute) {
357 NV_WR32(pNv->REGS, reg, data);
361 static uint8_t nv_idx_port_rd(ScrnInfoPtr pScrn, uint16_t port, uint8_t index)
363 NVPtr pNv = NVPTR(pScrn);
366 if (!nv_valid_idx_port(pScrn, port))
369 if (port == SEQ_INDEX)
370 data = NVReadVgaSeq(pNv, crtchead, index);
371 else /* assume CRTC_INDEX_COLOR */
372 data = NVReadVgaCrtc(pNv, crtchead, index);
374 BIOSLOG(pScrn, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
375 port, index, crtchead, data);
380 static void nv_idx_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t index, uint8_t data)
382 NVPtr pNv = NVPTR(pScrn);
384 if (!nv_valid_idx_port(pScrn, port))
387 /* The current head is maintained in a file scope variable crtchead.
388 * We trap changes to CR44 and update the head variable and hence the
389 * register set written.
390 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
391 * of the write, and to head1 after the write
393 if (port == CRTC_INDEX_COLOR && index == NV_CIO_CRE_44 && data != NV_CIO_CRE_44_HEADB)
396 LOG_OLD_VALUE(nv_idx_port_rd(pScrn, port, index));
397 BIOSLOG(pScrn, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
398 port, index, crtchead, data);
400 if (pNv->VBIOS.execute) {
402 if (port == SEQ_INDEX)
403 NVWriteVgaSeq(pNv, crtchead, index, data);
404 else /* assume CRTC_INDEX_COLOR */
405 NVWriteVgaCrtc(pNv, crtchead, index, data);
408 if (port == CRTC_INDEX_COLOR && index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
412 static uint8_t nv_port_rd(ScrnInfoPtr pScrn, uint16_t port)
414 NVPtr pNv = NVPTR(pScrn);
417 if (!nv_valid_port(pScrn, port))
420 data = NVReadPVIO(pNv, crtchead, port);
422 BIOSLOG(pScrn, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
423 port, crtchead, data);
428 static void nv_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t data)
430 NVPtr pNv = NVPTR(pScrn);
432 if (!nv_valid_port(pScrn, port))
435 LOG_OLD_VALUE(nv_port_rd(pScrn, port));
436 BIOSLOG(pScrn, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
437 port, crtchead, data);
439 if (pNv->VBIOS.execute) {
441 NVWritePVIO(pNv, crtchead, port, data);
445 #define ACCESS_UNLOCK 0
446 #define ACCESS_LOCK 1
447 static void crtc_access(NVPtr pNv, bool lock)
451 NVLockVgaCrtc(pNv, 0, lock);
454 NVLockVgaCrtc(pNv, 1, lock);
455 NVSetOwner(pNv, crtchead);
459 static bool io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, uint8_t cond)
461 /* The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
462 * for the CRTC index; 1 byte for the mask to apply to the value
463 * retrieved from the CRTC; 1 byte for the shift right to apply to the
464 * masked CRTC value; 2 bytes for the offset to the flag array, to
465 * which the shifted value is added; 1 byte for the mask applied to the
466 * value read from the flag array; and 1 byte for the value to compare
467 * against the masked byte from the flag table.
470 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
471 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[condptr])));
472 uint8_t crtcindex = bios->data[condptr + 2];
473 uint8_t mask = bios->data[condptr + 3];
474 uint8_t shift = bios->data[condptr + 4];
475 uint16_t flagarray = le16_to_cpu(*((uint16_t *)(&bios->data[condptr + 5])));
476 uint8_t flagarraymask = bios->data[condptr + 7];
477 uint8_t cmpval = bios->data[condptr + 8];
480 BIOSLOG(pScrn, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, Cmpval: 0x%02X\n",
481 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
483 data = nv_idx_port_rd(pScrn, crtcport, crtcindex);
485 data = bios->data[flagarray + ((data & mask) >> shift)];
486 data &= flagarraymask;
488 BIOSLOG(pScrn, "0x%04X: Checking if 0x%02X equals 0x%02X\n", offset, data, cmpval);
496 int getMNP_single(ScrnInfoPtr pScrn, struct pll_lims *pll_lim, int clk, int *bestNM, int *bestlog2P)
498 /* Find M, N and P for a single stage PLL
500 * Note that some bioses (NV3x) have lookup tables of precomputed MNP
501 * values, but we're too lazy to use those atm
503 * "clk" parameter in kHz
504 * returns calculated clock
507 bios_t *bios = &NVPTR(pScrn)->VBIOS;
508 int minvco = pll_lim->vco1.minfreq, maxvco = pll_lim->vco1.maxfreq;
509 int minM = pll_lim->vco1.min_m, maxM = pll_lim->vco1.max_m;
510 int minN = pll_lim->vco1.min_n, maxN = pll_lim->vco1.max_n;
511 int minU = pll_lim->vco1.min_inputfreq, maxU = pll_lim->vco1.max_inputfreq;
513 int crystal = pll_lim->refclk;
516 int delta, bestdelta = INT_MAX;
519 /* this division verified for nv20, nv18, nv28 (Haiku), and nv34 */
520 /* possibly correlated with introduction of 27MHz crystal */
521 if (bios->chip_version <= 0x16 || bios->chip_version == 0x20) {
527 } else if (bios->chip_version < 0x40) {
535 } else /* nv4x may be subject to the nv17+ limits, but assume not for now */
538 if ((clk << maxlog2P) < minvco) {
539 minvco = clk << maxlog2P;
542 if (clk + clk/200 > maxvco) /* +0.5% */
543 maxvco = clk + clk/200;
545 /* NV34 goes maxlog2P->0, NV20 goes 0->maxlog2P */
546 for (log2P = 0; log2P <= maxlog2P; log2P++) {
555 for (M = minM; M <= maxM; M++) {
556 if (crystal/M < minU)
558 if (crystal/M > maxU)
561 /* add crystal/2 to round better */
562 N = (clkP * M + crystal/2) / crystal;
569 /* more rounding additions */
570 calcclk = ((N * crystal + P/2) / P + M/2) / M;
571 delta = abs(calcclk - clk);
572 /* we do an exhaustive search rather than terminating
573 * on an optimality condition...
575 if (delta < bestdelta) {
578 *bestNM = N << 8 | M;
580 if (delta == 0) /* except this one */
589 int getMNP_double(ScrnInfoPtr pScrn, struct pll_lims *pll_lim, int clk, int *bestNM1, int *bestNM2, int *bestlog2P)
591 /* Find M, N and P for a two stage PLL
593 * Note that some bioses (NV30+) have lookup tables of precomputed MNP
594 * values, but we're too lazy to use those atm
596 * "clk" parameter in kHz
597 * returns calculated clock
600 int minvco1 = pll_lim->vco1.minfreq, maxvco1 = pll_lim->vco1.maxfreq;
601 int minvco2 = pll_lim->vco2.minfreq, maxvco2 = pll_lim->vco2.maxfreq;
602 int minU1 = pll_lim->vco1.min_inputfreq, minU2 = pll_lim->vco2.min_inputfreq;
603 int maxU1 = pll_lim->vco1.max_inputfreq, maxU2 = pll_lim->vco2.max_inputfreq;
604 int minM1 = pll_lim->vco1.min_m, maxM1 = pll_lim->vco1.max_m;
605 int minN1 = pll_lim->vco1.min_n, maxN1 = pll_lim->vco1.max_n;
606 int minM2 = pll_lim->vco2.min_m, maxM2 = pll_lim->vco2.max_m;
607 int minN2 = pll_lim->vco2.min_n, maxN2 = pll_lim->vco2.max_n;
608 int crystal = pll_lim->refclk;
609 bool fixedgain2 = (minM2 == maxM2 && minN2 == maxN2);
610 int M1, N1, M2, N2, log2P;
611 int clkP, calcclk1, calcclk2, calcclkout;
612 int delta, bestdelta = INT_MAX;
615 int vco2 = (maxvco2 - maxvco2/200) / 2;
616 for (log2P = 0; clk && log2P < 6 && clk <= (vco2 >> log2P); log2P++) /* log2P is maximum of 6 */
620 if (maxvco2 < clk + clk/200) /* +0.5% */
621 maxvco2 = clk + clk/200;
623 for (M1 = minM1; M1 <= maxM1; M1++) {
624 if (crystal/M1 < minU1)
626 if (crystal/M1 > maxU1)
629 for (N1 = minN1; N1 <= maxN1; N1++) {
630 calcclk1 = crystal * N1 / M1;
631 if (calcclk1 < minvco1)
633 if (calcclk1 > maxvco1)
636 for (M2 = minM2; M2 <= maxM2; M2++) {
637 if (calcclk1/M2 < minU2)
639 if (calcclk1/M2 > maxU2)
642 /* add calcclk1/2 to round better */
643 N2 = (clkP * M2 + calcclk1/2) / calcclk1;
650 if (NVPTR(pScrn)->VBIOS.chip_version < 0x60)
651 if (N2/M2 < 4 || N2/M2 > 10)
654 calcclk2 = calcclk1 * N2 / M2;
655 if (calcclk2 < minvco2)
657 if (calcclk2 > maxvco2)
662 calcclkout = calcclk2 >> log2P;
663 delta = abs(calcclkout - clk);
664 /* we do an exhaustive search rather than terminating
665 * on an optimality condition...
667 if (delta < bestdelta) {
669 bestclk = calcclkout;
670 *bestNM1 = N1 << 8 | M1;
671 *bestNM2 = N2 << 8 | M2;
673 if (delta == 0) /* except this one */
683 static void setPLL_single(ScrnInfoPtr pScrn, uint32_t reg, int NM, int log2P)
685 bios_t *bios = &NVPTR(pScrn)->VBIOS;
686 uint32_t oldpll = nv32_rd(pScrn, reg);
687 uint32_t pll = (oldpll & 0xfff80000) | log2P << 16 | NM;
688 uint32_t saved_powerctrl_1 = 0;
689 int shift_powerctrl_1 = -4;
692 return; /* already set */
694 /* nv18 doesn't change POWERCTRL_1 for VPLL*; does gf4 need special-casing? */
695 if (bios->chip_version >= 0x17 && bios->chip_version != 0x20) {
697 case NV_RAMDAC_VPLL2:
698 shift_powerctrl_1 += 4;
700 shift_powerctrl_1 += 4;
702 shift_powerctrl_1 += 4;
703 case NV_RAMDAC_NVPLL:
704 shift_powerctrl_1 += 4;
707 if (shift_powerctrl_1 >= 0) {
708 saved_powerctrl_1 = nv32_rd(pScrn, NV_PBUS_POWERCTRL_1);
709 nv32_wr(pScrn, NV_PBUS_POWERCTRL_1, (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 1 << shift_powerctrl_1);
714 nv32_wr(pScrn, reg, (oldpll & 0xffff0000) | NM);
720 /* then write P as well */
721 nv32_wr(pScrn, reg, pll);
723 if (shift_powerctrl_1 >= 0)
724 nv32_wr(pScrn, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
727 static void setPLL_double_highregs(ScrnInfoPtr pScrn, uint32_t reg1, int NM1, int NM2, int log2P)
729 bios_t *bios = &NVPTR(pScrn)->VBIOS;
730 bool nv3035 = bios->chip_version == 0x30 || bios->chip_version == 0x35;
731 uint32_t reg2 = reg1 + ((reg1 == NV_RAMDAC_VPLL2) ? 0x5c : 0x70);
732 uint32_t oldpll1 = nv32_rd(pScrn, reg1), oldpll2 = !nv3035 ? nv32_rd(pScrn, reg2) : 0;
733 uint32_t pll1 = (oldpll1 & 0xfff80000) | log2P << 16 | NM1;
734 uint32_t pll2 = !nv3035 ? (oldpll2 & 0x7fff0000) | 1 << 31 | NM2 : 0;
735 uint32_t saved_powerctrl_1 = 0, savedc040 = 0, maskc040 = ~0;
736 int shift_powerctrl_1 = -1;
737 bool single_stage = !NM2 || (((NM2 >> 8) & 0xff) == (NM2 & 0xff));
740 pll1 = (pll1 & 0xfcc7ffff) | (NM2 & (0x18 << 8)) << 13 | (NM2 & (0x7 << 8)) << 11 | 8 << 4 | (NM2 & 7) << 4;
742 if (oldpll1 == pll1 && oldpll2 == pll2)
743 return; /* already set */
745 if (reg1 == NV_RAMDAC_NVPLL) {
746 shift_powerctrl_1 = 0;
747 maskc040 = ~(3 << 20);
749 if (reg1 == NV_RAMDAC_MPLL) {
750 shift_powerctrl_1 = 4;
751 maskc040 = ~(3 << 22);
753 if (shift_powerctrl_1 >= 0) {
754 saved_powerctrl_1 = nv32_rd(pScrn, NV_PBUS_POWERCTRL_1);
755 nv32_wr(pScrn, NV_PBUS_POWERCTRL_1, (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 1 << shift_powerctrl_1);
758 if (bios->chip_version >= 0x40) {
759 savedc040 = nv32_rd(pScrn, 0xc040);
760 nv32_wr(pScrn, 0xc040, savedc040 & maskc040);
763 if (reg1 == NV_RAMDAC_VPLL)
764 nv32_wr(pScrn, NV_RAMDAC_580, nv32_rd(pScrn, NV_RAMDAC_580) & ~NV_RAMDAC_580_VPLL1_ACTIVE);
765 if (reg1 == NV_RAMDAC_VPLL2)
766 nv32_wr(pScrn, NV_RAMDAC_580, nv32_rd(pScrn, NV_RAMDAC_580) & ~NV_RAMDAC_580_VPLL2_ACTIVE);
768 if (reg1 == NV_RAMDAC_VPLL)
769 nv32_wr(pScrn, NV_RAMDAC_580, nv32_rd(pScrn, NV_RAMDAC_580) | NV_RAMDAC_580_VPLL1_ACTIVE);
770 if (reg1 == NV_RAMDAC_VPLL2)
771 nv32_wr(pScrn, NV_RAMDAC_580, nv32_rd(pScrn, NV_RAMDAC_580) | NV_RAMDAC_580_VPLL2_ACTIVE);
777 nv32_wr(pScrn, reg2, pll2);
778 nv32_wr(pScrn, reg1, pll1);
780 if (shift_powerctrl_1 >= 0) {
781 nv32_wr(pScrn, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
782 if (bios->chip_version >= 0x40)
783 nv32_wr(pScrn, 0xc040, savedc040);
787 static void setPLL_double_lowregs(ScrnInfoPtr pScrn, uint32_t NMNMreg, int NM1, int NM2, int log2P)
789 /* When setting PLLs, there is a merry game of disabling and enabling
790 * various bits of hardware during the process. This function is a
791 * synthesis of six nv40 traces, nearly each card doing a subtly
792 * different thing. With luck all the necessary bits for each card are
793 * combined herein. Without luck it deviates from each card's formula
794 * so as to not work on any :)
797 uint32_t Preg = NMNMreg - 4;
798 uint32_t oldPval = nv32_rd(pScrn, Preg);
799 uint32_t NMNM = NM2 << 16 | NM1;
800 uint32_t Pval = (oldPval & ((Preg == 0x4020) ? ~(0x11 << 16) : ~(1 << 16))) | 0xc << 28 | log2P << 16;
801 uint32_t saved4600 = 0;
802 /* some cards have different maskc040s */
803 uint32_t maskc040 = ~(3 << 14), savedc040;
804 bool single_stage = !NM2 || (((NM2 >> 8) & 0xff) == (NM2 & 0xff));
806 if (nv32_rd(pScrn, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
812 maskc040 = ~(0xc << 24);
814 if (Preg == 0x4020) {
815 struct pll_lims pll_lim;
818 if (!get_pll_limits(pScrn, Preg, &pll_lim))
821 Pval2 = log2P + pll_lim.log2p_bias;
822 if (Pval2 > pll_lim.max_log2p_bias)
823 Pval2 = pll_lim.max_log2p_bias;
824 Pval |= 1 << 28 | Pval2 << 20;
826 saved4600 = nv32_rd(pScrn, 0x4600);
827 nv32_wr(pScrn, 0x4600, saved4600 | 8 << 28);
830 Pval |= (Preg == 0x4020) ? 1 << 12 : 1 << 8;
832 nv32_wr(pScrn, Preg, oldPval | 1 << 28);
833 nv32_wr(pScrn, Preg, Pval & ~(4 << 28));
834 if (Preg == 0x4020) {
836 nv32_wr(pScrn, 0x4020, Pval & ~(0xc << 28));
837 nv32_wr(pScrn, 0x4038, Pval & ~(0xc << 28));
840 savedc040 = nv32_rd(pScrn, 0xc040);
841 nv32_wr(pScrn, 0xc040, savedc040 & maskc040);
843 nv32_wr(pScrn, NMNMreg, NMNM);
844 if (NMNMreg == 0x4024)
845 nv32_wr(pScrn, 0x403c, NMNM);
847 nv32_wr(pScrn, Preg, Pval);
848 if (Preg == 0x4020) {
850 nv32_wr(pScrn, 0x4020, Pval);
851 nv32_wr(pScrn, 0x4038, Pval);
852 nv32_wr(pScrn, 0x4600, saved4600);
855 nv32_wr(pScrn, 0xc040, savedc040);
857 if (Preg == 0x4020) {
858 nv32_wr(pScrn, 0x4020, Pval & ~(1 << 28));
859 nv32_wr(pScrn, 0x4038, Pval & ~(1 << 28));
863 static void setPLL(ScrnInfoPtr pScrn, bios_t *bios, uint32_t reg, uint32_t clk)
866 struct pll_lims pll_lim;
867 int NM1 = 0xbeef, NM2 = 0xdead, log2P;
869 /* high regs (such as in the mac g5 table) are not -= 4 */
870 if (!get_pll_limits(pScrn, reg > 0x405c ? reg : reg - 4, &pll_lim))
873 if (bios->chip_version >= 0x40 || bios->chip_version == 0x30 ||
874 bios->chip_version == 0x31 || bios->chip_version == 0x35 ||
875 bios->chip_version == 0x36) {
876 getMNP_double(pScrn, &pll_lim, clk, &NM1, &NM2, &log2P);
878 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
879 "Could not find a suitable set of PLL coefficients, giving up\n");
883 setPLL_double_highregs(pScrn, reg, NM1, NM2, log2P);
885 setPLL_double_lowregs(pScrn, reg, NM1, NM2, log2P);
887 getMNP_single(pScrn, &pll_lim, clk, &NM1, &log2P);
888 setPLL_single(pScrn, reg, NM1, log2P);
893 static bool init_prog(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
895 /* INIT_PROG opcode: 0x31
897 * offset (8 bit): opcode
898 * offset + 1 (32 bit): reg
899 * offset + 5 (32 bit): and mask
900 * offset + 9 (8 bit): shift right
901 * offset + 10 (8 bit): number of configurations
902 * offset + 11 (32 bit): register
903 * offset + 15 (32 bit): configuration 1
906 * Starting at offset + 15 there are "number of configurations"
907 * 32 bit values. To find out which configuration value to use
908 * read "CRTC reg" on the CRTC controller with index "CRTC index"
909 * and bitwise AND this value with "and mask" and then bit shift the
910 * result "shift right" bits to the right.
911 * Assign "register" with appropriate configuration value.
914 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
915 CARD32 and = *((CARD32 *) (&bios->data[offset + 5]));
916 CARD8 shiftr = *((CARD8 *) (&bios->data[offset + 9]));
917 CARD8 nr = *((CARD8 *) (&bios->data[offset + 10]));
918 CARD32 reg2 = *((CARD32 *) (&bios->data[offset + 11]));
920 CARD32 configval, tmp;
922 if (iexec->execute) {
923 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%04X\n", offset,
926 tmp = nv32_rd(pScrn, reg);
927 configuration = (tmp & and) >> shiftr;
929 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONFIGURATION TO USE: 0x%02X\n",
930 offset, configuration);
932 if (configuration <= nr) {
935 *((CARD32 *) (&bios->data[offset + 15 + configuration * 4]));
937 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%08X, VALUE: 0x%08X\n", offset,
940 tmp = nv32_rd(pScrn, reg2);
941 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n",
943 nv32_wr(pScrn, reg2, configval);
950 static bool init_io_restrict_prog(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
952 /* INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
954 * offset (8 bit): opcode
955 * offset + 1 (16 bit): CRTC port
956 * offset + 3 (8 bit): CRTC index
957 * offset + 4 (8 bit): mask
958 * offset + 5 (8 bit): shift
959 * offset + 6 (8 bit): count
960 * offset + 7 (32 bit): register
961 * offset + 11 (32 bit): configuration 1
964 * Starting at offset + 11 there are "count" 32 bit values.
965 * To find out which value to use read index "CRTC index" on "CRTC port",
966 * AND this value with "mask" and then bit shift right "shift" bits.
967 * Read the appropriate value using this index and write to "register"
970 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
971 uint8_t crtcindex = bios->data[offset + 3];
972 uint8_t mask = bios->data[offset + 4];
973 uint8_t shift = bios->data[offset + 5];
974 uint8_t count = bios->data[offset + 6];
975 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
982 BIOSLOG(pScrn, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
983 offset, crtcport, crtcindex, mask, shift, count, reg);
985 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
986 if (config > count) {
987 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
988 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
989 offset, config, count);
993 configval = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
995 BIOSLOG(pScrn, "0x%04X: Writing config %02X\n", offset, config);
997 nv32_wr(pScrn, reg, configval);
1002 static bool init_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1004 /* INIT_REPEAT opcode: 0x33 ('3')
1006 * offset (8 bit): opcode
1007 * offset + 1 (8 bit): count
1009 * Execute script following this opcode up to INIT_REPEAT_END
1013 uint8_t count = bios->data[offset + 1];
1016 /* no iexec->execute check by design */
1018 BIOSLOG(pScrn, "0x%04X: Repeating following segment %d times\n", offset, count);
1020 iexec->repeat = true;
1022 /* count - 1, as the script block will execute once when we leave this
1023 * opcode -- this is compatible with bios behaviour as:
1024 * a) the block is always executed at least once, even if count == 0
1025 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
1028 for (i = 0; i < count - 1; i++)
1029 parse_init_table(pScrn, bios, offset + 2, iexec);
1031 iexec->repeat = false;
1036 static bool init_io_restrict_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1038 /* INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
1040 * offset (8 bit): opcode
1041 * offset + 1 (16 bit): CRTC port
1042 * offset + 3 (8 bit): CRTC index
1043 * offset + 4 (8 bit): mask
1044 * offset + 5 (8 bit): shift
1045 * offset + 6 (8 bit): IO flag condition index
1046 * offset + 7 (8 bit): count
1047 * offset + 8 (32 bit): register
1048 * offset + 12 (16 bit): frequency 1
1051 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
1052 * Set PLL register "register" to coefficients for frequency n,
1053 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1054 * "mask" and shifted right by "shift". If "IO flag condition index" > 0,
1055 * and condition met, double frequency before setting it.
1058 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1059 uint8_t crtcindex = bios->data[offset + 3];
1060 uint8_t mask = bios->data[offset + 4];
1061 uint8_t shift = bios->data[offset + 5];
1062 int8_t io_flag_condition_idx = bios->data[offset + 6];
1063 uint8_t count = bios->data[offset + 7];
1064 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 8])));
1068 if (!iexec->execute)
1071 BIOSLOG(pScrn, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, IO Flag Condition: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1072 offset, crtcport, crtcindex, mask, shift, io_flag_condition_idx, count, reg);
1074 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1075 if (config > count) {
1076 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1077 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1078 offset, config, count);
1082 freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 12 + config * 2])));
1084 if (io_flag_condition_idx > 0) {
1085 if (io_flag_condition(pScrn, bios, offset, io_flag_condition_idx)) {
1086 BIOSLOG(pScrn, "0x%04X: Condition fulfilled -- frequency doubled\n", offset);
1089 BIOSLOG(pScrn, "0x%04X: Condition not fulfilled -- frequency unchanged\n", offset);
1092 BIOSLOG(pScrn, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1093 offset, reg, config, freq);
1095 setPLL(pScrn, bios, reg, freq * 10);
1100 static bool init_end_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1102 /* INIT_END_REPEAT opcode: 0x36 ('6')
1104 * offset (8 bit): opcode
1106 * Marks the end of the block for INIT_REPEAT to repeat
1109 /* no iexec->execute check by design */
1111 /* iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1112 * we're not in repeat mode
1120 static bool init_copy(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1122 /* INIT_COPY opcode: 0x37 ('7')
1124 * offset (8 bit): opcode
1125 * offset + 1 (32 bit): register
1126 * offset + 5 (8 bit): shift
1127 * offset + 6 (8 bit): srcmask
1128 * offset + 7 (16 bit): CRTC port
1129 * offset + 9 (8 bit): CRTC index
1130 * offset + 10 (8 bit): mask
1132 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1133 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC port
1136 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1137 uint8_t shift = bios->data[offset + 5];
1138 uint8_t srcmask = bios->data[offset + 6];
1139 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 7])));
1140 uint8_t crtcindex = bios->data[offset + 9];
1141 uint8_t mask = bios->data[offset + 10];
1145 if (!iexec->execute)
1148 BIOSLOG(pScrn, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1149 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1151 data = nv32_rd(pScrn, reg);
1156 data <<= (0x100 - shift);
1160 crtcdata = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) | (uint8_t)data;
1161 nv_idx_port_wr(pScrn, crtcport, crtcindex, crtcdata);
1166 static bool init_not(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1168 /* INIT_NOT opcode: 0x38 ('8')
1170 * offset (8 bit): opcode
1172 * Invert the current execute / no-execute condition (i.e. "else")
1175 BIOSLOG(pScrn, "0x%04X: ------ Skipping following commands ------\n", offset);
1177 BIOSLOG(pScrn, "0x%04X: ------ Executing following commands ------\n", offset);
1179 iexec->execute = !iexec->execute;
1183 static bool init_io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1185 /* INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1187 * offset (8 bit): opcode
1188 * offset + 1 (8 bit): condition number
1190 * Check condition "condition number" in the IO flag condition table.
1191 * If condition not met skip subsequent opcodes until condition is
1192 * inverted (INIT_NOT), or we hit INIT_RESUME
1195 uint8_t cond = bios->data[offset + 1];
1197 if (!iexec->execute)
1200 if (io_flag_condition(pScrn, bios, offset, cond))
1201 BIOSLOG(pScrn, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1203 BIOSLOG(pScrn, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1204 iexec->execute = false;
1210 static bool init_idx_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1212 /* INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1214 * offset (8 bit): opcode
1215 * offset + 1 (32 bit): control register
1216 * offset + 5 (32 bit): data register
1217 * offset + 9 (32 bit): mask
1218 * offset + 13 (32 bit): data
1219 * offset + 17 (8 bit): count
1220 * offset + 18 (8 bit): address 1
1221 * offset + 19 (8 bit): data 1
1224 * For each of "count" address and data pairs, write "data n" to "data register",
1225 * read the current value of "control register", and write it back once ANDed
1226 * with "mask", ORed with "data", and ORed with "address n"
1229 uint32_t controlreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1230 uint32_t datareg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1231 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1232 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 13])));
1233 uint8_t count = bios->data[offset + 17];
1237 if (!iexec->execute)
1240 BIOSLOG(pScrn, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1241 offset, controlreg, datareg, mask, data, count);
1243 for (i = 0; i < count; i++) {
1244 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1245 uint8_t instdata = bios->data[offset + 19 + i * 2];
1247 BIOSLOG(pScrn, "0x%04X: Address: 0x%02X, Data: 0x%02X\n", offset, instaddress, instdata);
1249 nv32_wr(pScrn, datareg, instdata);
1250 value = (nv32_rd(pScrn, controlreg) & mask) | data | instaddress;
1251 nv32_wr(pScrn, controlreg, value);
1257 static bool init_io_restrict_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1259 /* INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1261 * offset (8 bit): opcode
1262 * offset + 1 (16 bit): CRTC port
1263 * offset + 3 (8 bit): CRTC index
1264 * offset + 4 (8 bit): mask
1265 * offset + 5 (8 bit): shift
1266 * offset + 6 (8 bit): count
1267 * offset + 7 (32 bit): register
1268 * offset + 11 (32 bit): frequency 1
1271 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1272 * Set PLL register "register" to coefficients for frequency n,
1273 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1274 * "mask" and shifted right by "shift".
1277 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1278 uint8_t crtcindex = bios->data[offset + 3];
1279 uint8_t mask = bios->data[offset + 4];
1280 uint8_t shift = bios->data[offset + 5];
1281 uint8_t count = bios->data[offset + 6];
1282 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
1286 if (!iexec->execute)
1289 BIOSLOG(pScrn, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1290 offset, crtcport, crtcindex, mask, shift, count, reg);
1295 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1296 if (config > count) {
1297 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1298 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1299 offset, config, count);
1303 freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
1305 BIOSLOG(pScrn, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1306 offset, reg, config, freq);
1308 setPLL(pScrn, bios, reg, freq);
1313 static bool init_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1315 /* INIT_PLL2 opcode: 0x4B ('K')
1317 * offset (8 bit): opcode
1318 * offset + 1 (32 bit): register
1319 * offset + 5 (32 bit): freq
1321 * Set PLL register "register" to coefficients for frequency "freq"
1324 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1325 uint32_t freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1327 if (!iexec->execute)
1330 BIOSLOG(pScrn, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1333 setPLL(pScrn, bios, reg, freq);
1338 static uint32_t get_tmds_index_reg(ScrnInfoPtr pScrn, uint8_t mlv)
1340 /* For mlv < 0x80, it is an index into a table of TMDS base addresses
1341 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
1342 * to index a table of offsets to the basic 0x6808b0 address
1343 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
1344 * to index a table of offsets to the basic 0x6808b0 address, and then flip the offset by 8
1347 NVPtr pNv = NVPTR(pScrn);
1348 const int pramdac_offset[13] = {0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000};
1349 const uint32_t pramdac_table[4] = {0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8};
1352 /* here we assume that the DCB table has already been parsed */
1353 uint8_t dcb_entry = NVReadVgaCrtc5758(NVPTR(pScrn), crtchead, 0);
1356 if (dcb_entry > pNv->dcb_table.entries) {
1357 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1358 "CR58 doesn't have a valid DCB entry currently (%02X)\n", dcb_entry);
1361 dacoffset = pramdac_offset[pNv->dcb_table.entry[dcb_entry].or];
1364 return (0x6808b0 + dacoffset);
1366 if (mlv > (sizeof(pramdac_table) / sizeof(uint32_t))) {
1367 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1368 "Magic Lookup Value too big (%02X)\n", mlv);
1371 return pramdac_table[mlv];
1375 static bool init_tmds(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1377 /* INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1379 * offset (8 bit): opcode
1380 * offset + 1 (8 bit): magic lookup value
1381 * offset + 2 (8 bit): TMDS address
1382 * offset + 3 (8 bit): mask
1383 * offset + 4 (8 bit): data
1385 * Read the data reg for TMDS address "TMDS address", AND it with mask
1386 * and OR it with data, then write it back
1387 * "magic lookup value" determines which TMDS base address register is used --
1388 * see get_tmds_index_reg()
1391 uint8_t mlv = bios->data[offset + 1];
1392 uint32_t tmdsaddr = bios->data[offset + 2];
1393 uint8_t mask = bios->data[offset + 3];
1394 uint8_t data = bios->data[offset + 4];
1395 uint32_t reg, value;
1397 if (!iexec->execute)
1400 BIOSLOG(pScrn, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1401 offset, mlv, tmdsaddr, mask, data);
1403 if (!(reg = get_tmds_index_reg(pScrn, mlv)))
1406 nv32_wr(pScrn, reg, tmdsaddr | 0x10000);
1407 value = (nv32_rd(pScrn, reg + 4) & mask) | data;
1408 nv32_wr(pScrn, reg + 4, value);
1409 nv32_wr(pScrn, reg, tmdsaddr);
1414 static bool init_zm_tmds_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1416 /* INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1418 * offset (8 bit): opcode
1419 * offset + 1 (8 bit): magic lookup value
1420 * offset + 2 (8 bit): count
1421 * offset + 3 (8 bit): addr 1
1422 * offset + 4 (8 bit): data 1
1425 * For each of "count" TMDS address and data pairs write "data n" to "addr n"
1426 * "magic lookup value" determines which TMDS base address register is used --
1427 * see get_tmds_index_reg()
1430 uint8_t mlv = bios->data[offset + 1];
1431 uint8_t count = bios->data[offset + 2];
1435 if (!iexec->execute)
1438 BIOSLOG(pScrn, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1439 offset, mlv, count);
1441 if (!(reg = get_tmds_index_reg(pScrn, mlv)))
1444 for (i = 0; i < count; i++) {
1445 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1446 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1448 nv32_wr(pScrn, reg + 4, tmdsdata);
1449 nv32_wr(pScrn, reg, tmdsaddr);
1455 static bool init_cr_idx_adr_latch(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1457 /* INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1459 * offset (8 bit): opcode
1460 * offset + 1 (8 bit): CRTC index1
1461 * offset + 2 (8 bit): CRTC index2
1462 * offset + 3 (8 bit): baseaddr
1463 * offset + 4 (8 bit): count
1464 * offset + 5 (8 bit): data 1
1467 * For each of "count" address and data pairs, write "baseaddr + n" to
1468 * "CRTC index1" and "data n" to "CRTC index2"
1469 * Once complete, restore initial value read from "CRTC index1"
1471 uint8_t crtcindex1 = bios->data[offset + 1];
1472 uint8_t crtcindex2 = bios->data[offset + 2];
1473 uint8_t baseaddr = bios->data[offset + 3];
1474 uint8_t count = bios->data[offset + 4];
1475 uint8_t oldaddr, data;
1478 if (!iexec->execute)
1481 BIOSLOG(pScrn, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, BaseAddr: 0x%02X, Count: 0x%02X\n",
1482 offset, crtcindex1, crtcindex2, baseaddr, count);
1484 oldaddr = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex1);
1486 for (i = 0; i < count; i++) {
1487 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, baseaddr + i);
1489 data = bios->data[offset + 5 + i];
1490 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex2, data);
1493 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, oldaddr);
1498 static bool init_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1500 /* INIT_CR opcode: 0x52 ('R')
1502 * offset (8 bit): opcode
1503 * offset + 1 (8 bit): CRTC index
1504 * offset + 2 (8 bit): mask
1505 * offset + 3 (8 bit): data
1507 * Assign the value of at "CRTC index" ANDed with mask and ORed with data
1508 * back to "CRTC index"
1511 uint8_t crtcindex = bios->data[offset + 1];
1512 uint8_t mask = bios->data[offset + 2];
1513 uint8_t data = bios->data[offset + 3];
1516 if (!iexec->execute)
1519 BIOSLOG(pScrn, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1520 offset, crtcindex, mask, data);
1522 value = (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex) & mask) | data;
1523 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, value);
1528 static bool init_zm_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1530 /* INIT_ZM_CR opcode: 0x53 ('S')
1532 * offset (8 bit): opcode
1533 * offset + 1 (8 bit): CRTC index
1534 * offset + 2 (8 bit): value
1536 * Assign "value" to CRTC register with index "CRTC index".
1539 uint8_t crtcindex = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1540 uint8_t data = bios->data[offset + 2];
1542 if (!iexec->execute)
1545 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, data);
1550 static bool init_zm_cr_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1552 /* INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1554 * offset (8 bit): opcode
1555 * offset + 1 (8 bit): count
1556 * offset + 2 (8 bit): CRTC index 1
1557 * offset + 3 (8 bit): value 1
1560 * For "count", assign "value n" to CRTC register with index "CRTC index n".
1563 uint8_t count = bios->data[offset + 1];
1566 if (!iexec->execute)
1569 for (i = 0; i < count; i++)
1570 init_zm_cr(pScrn, bios, offset + 2 + 2 * i - 1, iexec);
1575 static bool init_condition_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1577 /* INIT_CONDITION_TIME opcode: 0x56 ('V')
1579 * offset (8 bit): opcode
1580 * offset + 1 (8 bit): condition number
1581 * offset + 2 (8 bit): retries / 50
1583 * Check condition "condition number" in the condition table.
1584 * The condition table entry has 4 bytes for the address of the
1585 * register to check, 4 bytes for a mask and 4 for a test value.
1586 * If condition not met sleep for 2ms, and repeat upto "retries" times.
1587 * If still not met after retries, clear execution flag for this table.
1590 uint8_t cond = bios->data[offset + 1];
1591 uint16_t retries = bios->data[offset + 2];
1592 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
1593 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
1594 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
1595 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
1598 if (!iexec->execute)
1603 BIOSLOG(pScrn, "0x%04X: Cond: 0x%02X, Retries: 0x%02X\n", offset, cond, retries);
1605 for (; retries > 0; retries--) {
1606 data = nv32_rd(pScrn, reg) & mask;
1608 BIOSLOG(pScrn, "0x%04X: Checking if 0x%08X equals 0x%08X\n", offset, data, cmpval);
1610 if (data != cmpval) {
1611 BIOSLOG(pScrn, "0x%04X: Condition not met, sleeping for 2ms\n", offset);
1614 BIOSLOG(pScrn, "0x%04X: Condition met, continuing\n", offset);
1619 if (data != cmpval) {
1620 BIOSLOG(pScrn, "0x%04X: Condition still not met, skiping following opcodes\n", offset);
1621 iexec->execute = false;
1627 static bool init_zm_reg_sequence(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1629 /* INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1631 * offset (8 bit): opcode
1632 * offset + 1 (32 bit): base register
1633 * offset + 5 (8 bit): count
1634 * offset + 6 (32 bit): value 1
1637 * Starting at offset + 6 there are "count" 32 bit values.
1638 * For "count" iterations set "base register" + 4 * current_iteration
1639 * to "value current_iteration"
1642 uint32_t basereg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1643 uint32_t count = bios->data[offset + 5];
1646 if (!iexec->execute)
1649 BIOSLOG(pScrn, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n", offset, basereg, count);
1651 for (i = 0; i < count; i++) {
1652 uint32_t reg = basereg + i * 4;
1653 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + i * 4])));
1655 nv32_wr(pScrn, reg, data);
1662 static bool init_indirect_reg(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1664 /* INIT_INDIRECT_REG opcode: 0x5A
1666 * offset (8 bit): opcode
1667 * offset + 1 (32 bit): register
1668 * offset + 5 (16 bit): adress offset (in bios)
1670 * Lookup value at offset data in the bios and write it to reg
1672 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
1673 CARD16 data = le16_to_cpu(*((CARD16 *) (&bios->data[offset + 5])));
1674 CARD32 data2 = bios->data[data];
1676 if (iexec->execute) {
1677 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1678 "0x%04X: REG: 0x%04X, DATA AT: 0x%04X, VALUE IS: 0x%08X\n",
1679 offset, reg, data, data2);
1681 if (DEBUGLEVEL >= 6) {
1683 tmpval = nv32_rd(pScrn, reg);
1684 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n", offset, tmpval);
1687 nv32_wr(pScrn, reg, data2);
1693 static bool init_sub_direct(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1695 /* INIT_SUB_DIRECT opcode: 0x5B ('[')
1697 * offset (8 bit): opcode
1698 * offset + 1 (16 bit): subroutine offset (in bios)
1700 * Calls a subroutine that will execute commands until INIT_DONE
1704 uint16_t sub_offset = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1706 if (!iexec->execute)
1709 BIOSLOG(pScrn, "0x%04X: Executing subroutine at 0x%04X\n", offset, sub_offset);
1711 parse_init_table(pScrn, bios, sub_offset, iexec);
1713 BIOSLOG(pScrn, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1718 static bool init_copy_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1720 /* INIT_COPY_NV_REG opcode: 0x5F ('_')
1722 * offset (8 bit): opcode
1723 * offset + 1 (32 bit): src reg
1724 * offset + 5 (8 bit): shift
1725 * offset + 6 (32 bit): src mask
1726 * offset + 10 (32 bit): xor
1727 * offset + 14 (32 bit): dst reg
1728 * offset + 18 (32 bit): dst mask
1730 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1731 * "src mask", then XOR with "xor". Write this OR'd with
1732 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1735 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1736 uint8_t shift = bios->data[offset + 5];
1737 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1738 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1739 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1740 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1741 uint32_t srcvalue, dstvalue;
1743 if (!iexec->execute)
1746 BIOSLOG(pScrn, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1747 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1749 srcvalue = nv32_rd(pScrn, srcreg);
1754 srcvalue <<= (0x100 - shift);
1756 srcvalue = (srcvalue & srcmask) ^ xor;
1758 dstvalue = nv32_rd(pScrn, dstreg) & dstmask;
1760 nv32_wr(pScrn, dstreg, dstvalue | srcvalue);
1765 static bool init_zm_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1767 /* INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1769 * offset (8 bit): opcode
1770 * offset + 1 (16 bit): CRTC port
1771 * offset + 3 (8 bit): CRTC index
1772 * offset + 4 (8 bit): data
1774 * Write "data" to index "CRTC index" of "CRTC port"
1776 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1777 uint8_t crtcindex = bios->data[offset + 3];
1778 uint8_t data = bios->data[offset + 4];
1780 if (!iexec->execute)
1783 nv_idx_port_wr(pScrn, crtcport, crtcindex, data);
1788 static bool init_compute_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1790 /* INIT_COMPUTE_MEM opcode: 0x63 ('c')
1792 * offset (8 bit): opcode
1794 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
1795 * that the hardware can correctly calculate how much VRAM it has
1796 * (and subsequently report that value in 0x10020C)
1798 * The implementation of this opcode in general consists of two parts:
1799 * 1) determination of the memory bus width
1800 * 2) determination of how many of the card's RAM pads have ICs attached
1802 * 1) is done by a cunning combination of writes to offsets 0x1c and
1803 * 0x3c in the framebuffer, and seeing whether the written values are
1804 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
1806 * 2) is done by a cunning combination of writes to an offset slightly
1807 * less than the maximum memory reported by 0x10020C, then seeing if
1808 * the test pattern can be read back. This then affects bits 12-15 of
1811 * In this context a "cunning combination" may include multiple reads
1812 * and writes to varying locations, often alternating the test pattern
1813 * and 0, doubtless to make sure buffers are filled, residual charges
1814 * on tracks are removed etc.
1816 * Unfortunately, the "cunning combination"s mentioned above, and the
1817 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
1820 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
1821 * we started was correct, and use that instead
1824 /* no iexec->execute check by design */
1826 /* on every card I've seen, this step gets done for us earlier in the init scripts
1827 uint8_t crdata = nv_idx_port_rd(pScrn, SEQ_INDEX, 0x01);
1828 nv_idx_port_wr(pScrn, SEQ_INDEX, 0x01, crdata | 0x20);
1831 /* this also has probably been done in the scripts, but an mmio trace of
1832 * s3 resume shows nvidia doing it anyway (unlike the SEQ_INDEX write)
1834 nv32_wr(pScrn, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
1836 /* write back the saved configuration value */
1837 nv32_wr(pScrn, NV_PFB_CFG0, saved_nv_pfb_cfg0);
1842 static bool init_reset(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1844 /* INIT_RESET opcode: 0x65 ('e')
1846 * offset (8 bit): opcode
1847 * offset + 1 (32 bit): register
1848 * offset + 5 (32 bit): value1
1849 * offset + 9 (32 bit): value2
1851 * Assign "value1" to "register", then assign "value2" to "register"
1854 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1855 uint32_t value1 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1856 uint32_t value2 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1857 uint32_t pci_nv_19, pci_nv_20;
1859 /* no iexec->execute check by design */
1861 pci_nv_19 = nv32_rd(pScrn, NV_PBUS_PCI_NV_19);
1862 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, 0);
1863 nv32_wr(pScrn, reg, value1);
1867 nv32_wr(pScrn, reg, value2);
1868 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, pci_nv_19);
1870 pci_nv_20 = nv32_rd(pScrn, NV_PBUS_PCI_NV_20);
1871 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
1872 nv32_wr(pScrn, NV_PBUS_PCI_NV_20, pci_nv_20);
1877 static bool init_configure_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1879 /* INIT_CONFIGURE_MEM opcode: 0x66 ('f')
1881 * offset (8 bit): opcode
1883 * Equivalent to INIT_DONE on bios version 3 or greater.
1884 * For early bios versions, sets up the memory registers, using values
1885 * taken from the memory init table
1888 /* no iexec->execute check by design */
1890 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
1891 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
1894 if (bios->major_version > 2)
1897 nv_idx_port_wr(pScrn, SEQ_INDEX, 0x01, nv_idx_port_rd(pScrn, SEQ_INDEX, 0x01) | 0x20);
1899 if (bios->data[meminitoffs] & 1)
1900 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
1902 for (reg = le32_to_cpu(*(uint32_t *)&bios->data[seqtbloffs]);
1904 reg = le32_to_cpu(*(uint32_t *)&bios->data[seqtbloffs += 4])) {
1908 data = NV_PFB_PRE_CMD_PRECHARGE;
1911 data = NV_PFB_PAD_CKE_NORMAL;
1914 data = NV_PFB_REF_CMD_REFRESH;
1917 data = le32_to_cpu(*(uint32_t *)&bios->data[meminitdata]);
1919 if (data == 0xffffffff)
1923 nv32_wr(pScrn, reg, data);
1929 static bool init_configure_clk(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1931 /* INIT_CONFIGURE_CLK opcode: 0x67 ('g')
1933 * offset (8 bit): opcode
1935 * Equivalent to INIT_DONE on bios version 3 or greater.
1936 * For early bios versions, sets up the NVClk and MClk PLLs, using
1937 * values taken from the memory init table
1940 /* no iexec->execute check by design */
1942 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
1945 if (bios->major_version > 2)
1948 clock = le16_to_cpu(*(uint16_t *)&bios->data[meminitoffs + 4]) * 10;
1949 setPLL(pScrn, bios, NV_RAMDAC_NVPLL, clock);
1951 clock = le16_to_cpu(*(uint16_t *)&bios->data[meminitoffs + 2]) * 10;
1952 if (bios->data[meminitoffs] & 1) /* DDR */
1954 setPLL(pScrn, bios, NV_RAMDAC_MPLL, clock);
1959 static bool init_configure_preinit(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1961 /* INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
1963 * offset (8 bit): opcode
1965 * Equivalent to INIT_DONE on bios version 3 or greater.
1966 * For early bios versions, does early init, loading ram and crystal
1967 * configuration from straps into CR3C
1970 /* no iexec->execute check by design */
1972 uint32_t straps = nv32_rd(pScrn, NV_PEXTDEV_BOOT_0);
1973 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6));
1975 if (bios->major_version > 2)
1978 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
1983 static bool init_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1985 /* INIT_IO opcode: 0x69 ('i')
1987 * offset (8 bit): opcode
1988 * offset + 1 (16 bit): CRTC port
1989 * offset + 3 (8 bit): mask
1990 * offset + 4 (8 bit): data
1992 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
1995 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1996 uint8_t mask = bios->data[offset + 3];
1997 uint8_t data = bios->data[offset + 4];
1999 if (!iexec->execute)
2002 BIOSLOG(pScrn, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2003 offset, crtcport, mask, data);
2005 nv_port_wr(pScrn, crtcport, (nv_port_rd(pScrn, crtcport) & mask) | data);
2010 static bool init_sub(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2012 /* INIT_SUB opcode: 0x6B ('k')
2014 * offset (8 bit): opcode
2015 * offset + 1 (8 bit): script number
2017 * Execute script number "script number", as a subroutine
2020 uint8_t sub = bios->data[offset + 1];
2022 if (!iexec->execute)
2025 BIOSLOG(pScrn, "0x%04X: Calling script %d\n", offset, sub);
2027 parse_init_table(pScrn, bios,
2028 le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + sub * 2]))),
2031 BIOSLOG(pScrn, "0x%04X: End of script %d\n", offset, sub);
2036 static bool init_ram_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2038 /* INIT_RAM_CONDITION opcode: 0x6D ('m')
2040 * offset (8 bit): opcode
2041 * offset + 1 (8 bit): mask
2042 * offset + 2 (8 bit): cmpval
2044 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval".
2045 * If condition not met skip subsequent opcodes until condition is
2046 * inverted (INIT_NOT), or we hit INIT_RESUME
2049 uint8_t mask = bios->data[offset + 1];
2050 uint8_t cmpval = bios->data[offset + 2];
2053 if (!iexec->execute)
2056 data = nv32_rd(pScrn, NV_PFB_BOOT_0) & mask;
2058 BIOSLOG(pScrn, "0x%04X: Checking if 0x%08X equals 0x%08X\n", offset, data, cmpval);
2061 BIOSLOG(pScrn, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2063 BIOSLOG(pScrn, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2064 iexec->execute = false;
2070 static bool init_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2072 /* INIT_NV_REG opcode: 0x6E ('n')
2074 * offset (8 bit): opcode
2075 * offset + 1 (32 bit): register
2076 * offset + 5 (32 bit): mask
2077 * offset + 9 (32 bit): data
2079 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2082 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2083 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2084 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
2086 if (!iexec->execute)
2089 BIOSLOG(pScrn, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n", offset, reg, mask, data);
2091 nv32_wr(pScrn, reg, (nv32_rd(pScrn, reg) & mask) | data);
2096 static bool init_macro(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2098 /* INIT_MACRO opcode: 0x6F ('o')
2100 * offset (8 bit): opcode
2101 * offset + 1 (8 bit): macro number
2103 * Look up macro index "macro number" in the macro index table.
2104 * The macro index table entry has 1 byte for the index in the macro table,
2105 * and 1 byte for the number of times to repeat the macro.
2106 * The macro table entry has 4 bytes for the register address and
2107 * 4 bytes for the value to write to that register
2110 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2111 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2112 uint8_t macro_tbl_idx = bios->data[tmp];
2113 uint8_t count = bios->data[tmp + 1];
2117 if (!iexec->execute)
2120 BIOSLOG(pScrn, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, Count: 0x%02X\n",
2121 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2123 for (i = 0; i < count; i++) {
2124 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2126 reg = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr])));
2127 data = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr + 4])));
2129 nv32_wr(pScrn, reg, data);
2135 static bool init_done(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2137 /* INIT_DONE opcode: 0x71 ('q')
2139 * offset (8 bit): opcode
2141 * End the current script
2144 /* mild retval abuse to stop parsing this table */
2148 static bool init_resume(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2150 /* INIT_RESUME opcode: 0x72 ('r')
2152 * offset (8 bit): opcode
2154 * End the current execute / no-execute condition
2160 iexec->execute = true;
2161 BIOSLOG(pScrn, "0x%04X: ---- Executing following commands ----\n", offset);
2167 static bool init_ram_condition2(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
2169 /* INIT_RAM_CONDITION2 opcode: 0x73
2171 * offset (8 bit): opcode
2172 * offset + 1 (8 bit): and mask
2173 * offset + 2 (8 bit): cmpval
2175 * Test if (NV_EXTDEV_BOOT & and mask) matches cmpval
2177 NVPtr pNv = NVPTR(pScrn);
2178 CARD32 and = *((CARD32 *) (&bios->data[offset + 1]));
2179 CARD32 cmpval = *((CARD32 *) (&bios->data[offset + 5]));
2182 if (iexec->execute) {
2183 data=(nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT))∧
2185 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2186 "0x%04X: CHECKING IF REGVAL: 0x%08X equals COND: 0x%08X\n",
2187 offset, data, cmpval);
2189 if (data == cmpval) {
2190 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2191 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n",
2194 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2195 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2196 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2197 iexec->execute = false;
2204 static bool init_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2206 /* INIT_TIME opcode: 0x74 ('t')
2208 * offset (8 bit): opcode
2209 * offset + 1 (16 bit): time
2211 * Sleep for "time" microseconds.
2214 uint16_t time = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2216 if (!iexec->execute)
2219 BIOSLOG(pScrn, "0x%04X: Sleeping for 0x%04X microseconds\n", offset, time);
2226 static bool init_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2228 /* INIT_CONDITION opcode: 0x75 ('u')
2230 * offset (8 bit): opcode
2231 * offset + 1 (8 bit): condition number
2233 * Check condition "condition number" in the condition table.
2234 * The condition table entry has 4 bytes for the address of the
2235 * register to check, 4 bytes for a mask and 4 for a test value.
2236 * If condition not met skip subsequent opcodes until condition is
2237 * inverted (INIT_NOT), or we hit INIT_RESUME
2240 uint8_t cond = bios->data[offset + 1];
2241 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
2242 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
2243 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
2244 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
2247 if (!iexec->execute)
2250 BIOSLOG(pScrn, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X, Cmpval: 0x%08X\n",
2251 offset, cond, reg, mask, cmpval);
2253 data = nv32_rd(pScrn, reg) & mask;
2255 BIOSLOG(pScrn, "0x%04X: Checking if 0x%08X equals 0x%08X\n", offset, data, cmpval);
2258 BIOSLOG(pScrn, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2260 BIOSLOG(pScrn, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2261 iexec->execute = false;
2267 static bool init_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2269 /* INIT_INDEX_IO opcode: 0x78 ('x')
2271 * offset (8 bit): opcode
2272 * offset + 1 (16 bit): CRTC port
2273 * offset + 3 (8 bit): CRTC index
2274 * offset + 4 (8 bit): mask
2275 * offset + 5 (8 bit): data
2277 * Read value at index "CRTC index" on "CRTC port", AND with "mask", OR with "data", write-back
2280 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2281 uint8_t crtcindex = bios->data[offset + 3];
2282 uint8_t mask = bios->data[offset + 4];
2283 uint8_t data = bios->data[offset + 5];
2286 if (!iexec->execute)
2289 BIOSLOG(pScrn, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
2290 offset, crtcport, crtcindex, mask, data);
2292 value = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) | data;
2293 nv_idx_port_wr(pScrn, crtcport, crtcindex, value);
2298 static bool init_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2300 /* INIT_PLL opcode: 0x79 ('y')
2302 * offset (8 bit): opcode
2303 * offset + 1 (32 bit): register
2304 * offset + 5 (16 bit): freq
2306 * Set PLL register "register" to coefficients for frequency (10kHz) "freq"
2309 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2310 uint16_t freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 5])));
2312 if (!iexec->execute)
2315 BIOSLOG(pScrn, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
2317 setPLL(pScrn, bios, reg, freq * 10);
2322 static bool init_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2324 /* INIT_ZM_REG opcode: 0x7A ('z')
2326 * offset (8 bit): opcode
2327 * offset + 1 (32 bit): register
2328 * offset + 5 (32 bit): value
2330 * Assign "value" to "register"
2333 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2334 uint32_t value = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2336 if (!iexec->execute)
2339 nv32_wr(pScrn, reg, value);
2344 static bool init_8e(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2346 /* INIT_8E opcode: 0x8E ('')
2348 * offset (8 bit): opcode
2350 * The purpose of this opcode is unclear (being for nv50 cards), and
2351 * the literal functionality can be seen in the code below.
2353 * A brief synopsis is that for each entry in a table pointed to by the
2354 * DCB table header, depending on the settings of various bits, various
2355 * other bits in registers 0xe100, 0xe104, and 0xe108, are set or
2359 uint16_t dcbptr = le16_to_cpu(*(uint16_t *)&bios->data[0x36]);
2360 uint16_t init8etblptr = le16_to_cpu(*(uint16_t *)&bios->data[dcbptr + 10]);
2361 uint8_t headerlen = bios->data[init8etblptr + 1];
2362 uint8_t entries = bios->data[init8etblptr + 2];
2363 uint8_t recordlen = bios->data[init8etblptr + 3];
2367 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2368 "No Display Configuration Block pointer found\n");
2371 if (bios->data[dcbptr] != 0x40) {
2372 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2373 "DCB table not version 4.0\n");
2376 if (!init8etblptr) {
2377 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
2378 "Invalid pointer to INIT_8E table\n");
2382 for (i = 0; i < entries; i++) {
2383 uint32_t entry = le32_to_cpu(*(uint32_t *)&bios->data[init8etblptr + headerlen + recordlen * i]);
2384 int shift = (entry & 0x1f) * 4;
2386 uint32_t reg = 0xe104;
2389 if ((entry & 0xff00) == 0xff00)
2398 mask = ~(3 << shift);
2399 if (entry & (1 << 24))
2400 data = (entry >> 21);
2402 data = (entry >> 19);
2403 data = ((data & 3) ^ 2) << shift;
2405 BIOSLOG(pScrn, "0x%04X: Entry: 0x%08X, Reg: 0x%08X, Shift: 0x%02X, Mask: 0x%08X, Data: 0x%08X\n",
2406 offset, entry, reg, shift, mask, data);
2408 nv32_wr(pScrn, reg, (nv32_rd(pScrn, reg) & mask) | data);
2411 shift = entry & 0x1f;
2413 mask = ~(1 << 16 | 1);
2414 mask = mask << shift | mask >> (32 - shift);
2416 if ((entry & (3 << 25)) == (1 << 25))
2418 if ((entry & (3 << 25)) == (2 << 25))
2422 BIOSLOG(pScrn, "0x%04X: Entry: 0x%08X, Reg: 0x%08X, Shift: 0x%02X, Mask: 0x%08X, Data: 0x%08X\n",
2423 offset, entry, reg, shift, mask, data);
2425 nv32_wr(pScrn, reg, (nv32_rd(pScrn, reg) & mask) | data);
2431 /* hack to avoid moving the itbl_entry array before this function */
2432 int init_ram_restrict_zm_reg_group_blocklen = 0;
2434 static bool init_ram_restrict_zm_reg_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2436 /* INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2438 * offset (8 bit): opcode
2439 * offset + 1 (32 bit): reg
2440 * offset + 5 (8 bit): regincrement
2441 * offset + 6 (8 bit): count
2442 * offset + 7 (32 bit): value 1,1
2445 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2446 * ram_restrict_table_ptr. The value read from here is 'n', and
2447 * "value 1,n" gets written to "reg". This repeats "count" times and on
2448 * each iteration 'm', "reg" increases by "regincrement" and
2449 * "value m,n" is used. The extent of n is limited by a number read
2450 * from the 'M' BIT table, herein called "blocklen"
2453 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2454 uint8_t regincrement = bios->data[offset + 5];
2455 uint8_t count = bios->data[offset + 6];
2456 uint32_t strap_ramcfg, data;
2461 /* previously set by 'M' BIT table */
2462 blocklen = init_ram_restrict_zm_reg_group_blocklen;
2464 if (!iexec->execute)
2468 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2469 "0x%04X: Zero block length - has the M table been parsed?\n", offset);
2473 strap_ramcfg = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2474 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2476 BIOSLOG(pScrn, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2477 offset, reg, regincrement, count, strap_ramcfg, index);
2479 for (i = 0; i < count; i++) {
2480 data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7 + index * 4 + blocklen * i])));
2482 nv32_wr(pScrn, reg, data);
2484 reg += regincrement;
2490 static bool init_copy_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2492 /* INIT_COPY_ZM_REG opcode: 0x90 ('')
2494 * offset (8 bit): opcode
2495 * offset + 1 (32 bit): src reg
2496 * offset + 5 (32 bit): dst reg
2498 * Put contents of "src reg" into "dst reg"
2501 uint32_t srcreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2502 uint32_t dstreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2504 if (!iexec->execute)
2507 nv32_wr(pScrn, dstreg, nv32_rd(pScrn, srcreg));
2512 static bool init_zm_reg_group_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2514 /* INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2516 * offset (8 bit): opcode
2517 * offset + 1 (32 bit): dst reg
2518 * offset + 5 (8 bit): count
2519 * offset + 6 (32 bit): data 1
2522 * For each of "count" values write "data n" to "dst reg"
2525 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2526 uint8_t count = bios->data[offset + 5];
2529 if (!iexec->execute)
2532 for (i = 0; i < count; i++) {
2533 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + 4 * i])));
2534 nv32_wr(pScrn, reg, data);
2540 static bool init_reserved(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2542 /* INIT_RESERVED opcode: 0x92 ('')
2544 * offset (8 bit): opcode
2546 * Seemingly does nothing
2552 static init_tbl_entry_t itbl_entry[] = {
2553 /* command name , id , length , offset , mult , command handler */
2554 // { "INIT_PROG" , 0x31, 15 , 10 , 4 , init_prog },
2555 { "INIT_IO_RESTRICT_PROG" , 0x32, 11 , 6 , 4 , init_io_restrict_prog },
2556 { "INIT_REPEAT" , 0x33, 2 , 0 , 0 , init_repeat },
2557 { "INIT_IO_RESTRICT_PLL" , 0x34, 12 , 7 , 2 , init_io_restrict_pll },
2558 { "INIT_END_REPEAT" , 0x36, 1 , 0 , 0 , init_end_repeat },
2559 { "INIT_COPY" , 0x37, 11 , 0 , 0 , init_copy },
2560 { "INIT_NOT" , 0x38, 1 , 0 , 0 , init_not },
2561 { "INIT_IO_FLAG_CONDITION" , 0x39, 2 , 0 , 0 , init_io_flag_condition },
2562 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, 18 , 17 , 2 , init_idx_addr_latched },
2563 { "INIT_IO_RESTRICT_PLL2" , 0x4A, 11 , 6 , 4 , init_io_restrict_pll2 },
2564 { "INIT_PLL2" , 0x4B, 9 , 0 , 0 , init_pll2 },
2565 /* { "INIT_I2C_BYTE" , 0x4C, x , x , x , init_i2c_byte }, */
2566 /* { "INIT_ZM_I2C_BYTE" , 0x4D, x , x , x , init_zm_i2c_byte }, */
2567 /* { "INIT_ZM_I2C" , 0x4E, x , x , x , init_zm_i2c }, */
2568 { "INIT_TMDS" , 0x4F, 5 , 0 , 0 , init_tmds },
2569 { "INIT_ZM_TMDS_GROUP" , 0x50, 3 , 2 , 2 , init_zm_tmds_group },
2570 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, 5 , 4 , 1 , init_cr_idx_adr_latch },
2571 { "INIT_CR" , 0x52, 4 , 0 , 0 , init_cr },
2572 { "INIT_ZM_CR" , 0x53, 3 , 0 , 0 , init_zm_cr },
2573 { "INIT_ZM_CR_GROUP" , 0x54, 2 , 1 , 2 , init_zm_cr_group },
2574 { "INIT_CONDITION_TIME" , 0x56, 3 , 0 , 0 , init_condition_time },
2575 { "INIT_ZM_REG_SEQUENCE" , 0x58, 6 , 5 , 4 , init_zm_reg_sequence },
2576 // { "INIT_INDIRECT_REG" , 0x5A, 7 , 0 , 0 , init_indirect_reg },
2577 { "INIT_SUB_DIRECT" , 0x5B, 3 , 0 , 0 , init_sub_direct },
2578 { "INIT_COPY_NV_REG" , 0x5F, 22 , 0 , 0 , init_copy_nv_reg },
2579 { "INIT_ZM_INDEX_IO" , 0x62, 5 , 0 , 0 , init_zm_index_io },
2580 { "INIT_COMPUTE_MEM" , 0x63, 1 , 0 , 0 , init_compute_mem },
2581 { "INIT_RESET" , 0x65, 13 , 0 , 0 , init_reset },
2582 { "INIT_CONFIGURE_MEM" , 0x66, 1 , 0 , 0 , init_configure_mem },
2583 { "INIT_CONFIGURE_CLK" , 0x67, 1 , 0 , 0 , init_configure_clk },
2584 { "INIT_CONFIGURE_PREINIT" , 0x68, 1 , 0 , 0 , init_configure_preinit },
2585 { "INIT_IO" , 0x69, 5 , 0 , 0 , init_io },
2586 { "INIT_SUB" , 0x6B, 2 , 0 , 0 , init_sub },
2587 { "INIT_RAM_CONDITION" , 0x6D, 3 , 0 , 0 , init_ram_condition },
2588 { "INIT_NV_REG" , 0x6E, 13 , 0 , 0 , init_nv_reg },
2589 { "INIT_MACRO" , 0x6F, 2 , 0 , 0 , init_macro },
2590 { "INIT_DONE" , 0x71, 1 , 0 , 0 , init_done },
2591 { "INIT_RESUME" , 0x72, 1 , 0 , 0 , init_resume },
2592 // { "INIT_RAM_CONDITION2" , 0x73, 9 , 0 , 0 , init_ram_condition2 },
2593 { "INIT_TIME" , 0x74, 3 , 0 , 0 , init_time },
2594 { "INIT_CONDITION" , 0x75, 2 , 0 , 0 , init_condition },
2595 /* { "INIT_IO_CONDITION" , 0x76, x , x , x , init_io_condition }, */
2596 { "INIT_INDEX_IO" , 0x78, 6 , 0 , 0 , init_index_io },
2597 { "INIT_PLL" , 0x79, 7 , 0 , 0 , init_pll },
2598 { "INIT_ZM_REG" , 0x7A, 9 , 0 , 0 , init_zm_reg },
2599 { "INIT_8E" , 0x8E, 1 , 0 , 0 , init_8e },
2600 /* INIT_RAM_RESTRICT_ZM_REG_GROUP's mult is loaded by M table in BIT */
2601 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, 7 , 6 , 0 , init_ram_restrict_zm_reg_group },
2602 { "INIT_COPY_ZM_REG" , 0x90, 9 , 0 , 0 , init_copy_zm_reg },
2603 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, 6 , 5 , 4 , init_zm_reg_group_addr_latched },
2604 { "INIT_RESERVED" , 0x92, 1 , 0 , 0 , init_reserved },
2605 { 0 , 0 , 0 , 0 , 0 , 0 }
2608 static unsigned int get_init_table_entry_length(bios_t *bios, unsigned int offset, int i)
2610 /* Calculates the length of a given init table entry. */
2611 return itbl_entry[i].length + bios->data[offset + itbl_entry[i].length_offset]*itbl_entry[i].length_multiplier;
2614 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec)
2616 /* Parses all commands in a init table. */
2618 /* We start out executing all commands found in the
2619 * init table. Some op codes may change the status
2620 * of this variable to SKIP, which will cause
2621 * the following op codes to perform no operation until
2622 * the value is changed back to EXECUTE.
2628 /* Loop until INIT_DONE causes us to break out of the loop
2629 * (or until offset > bios length just in case... )
2630 * (and no more than 10000 iterations just in case... ) */
2631 while ((offset < bios->length) && (count++ < 10000)) {
2632 id = bios->data[offset];
2634 /* Find matching id in itbl_entry */
2635 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
2638 if (itbl_entry[i].name) {
2639 BIOSLOG(pScrn, "0x%04X: [ (0x%02X) - %s ]\n",
2640 offset, itbl_entry[i].id, itbl_entry[i].name);
2642 /* execute eventual command handler */
2643 if (itbl_entry[i].handler)
2644 if (!(*itbl_entry[i].handler)(pScrn, bios, offset, iexec))
2647 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2648 "0x%04X: Init table command not found: 0x%02X\n", offset, id);
2652 /* Add the offset of the current command including all data
2653 * of that command. The offset will then be pointing on the
2656 offset += get_init_table_entry_length(bios, offset, i);
2660 static void parse_init_tables(ScrnInfoPtr pScrn, bios_t *bios)
2662 /* Loops and calls parse_init_table() for each present table. */
2666 init_exec_t iexec = {true, false};
2668 while ((table = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + i]))))) {
2669 xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
2670 "Parsing VBIOS init table %d at offset 0x%04X\n", i / 2, table);
2671 BIOSLOG(pScrn, "0x%04X: ------ Executing following commands ------\n", table);
2673 parse_init_table(pScrn, bios, table, &iexec);
2678 static void link_head_and_output(ScrnInfoPtr pScrn, struct dcb_entry *dcbent, int head)
2680 /* The BIOS scripts don't do this for us, sadly
2681 * Luckily we do know the values ;-)
2683 * head < 0 indicates we wish to force a setting with the overrideval
2684 * (for VT restore etc.)
2687 NVPtr pNv = NVPTR(pScrn);
2688 int ramdac = (dcbent->or & OUTPUT_C) >> 2;
2689 uint8_t tmds04 = 0x80;
2694 if (dcbent->type == OUTPUT_LVDS)
2697 nv_write_tmds(pNv, dcbent->or, 0, 0x04, tmds04);
2699 if (dcbent->type == OUTPUT_LVDS && pNv->VBIOS.fp.dual_link)
2700 nv_write_tmds(pNv, dcbent->or, 1, 0x04, tmds04 ^ 0x08);
2703 static uint16_t clkcmptable(bios_t *bios, uint16_t clktable, int pxclk)
2705 int compare_record_len, i = 0;
2706 uint16_t compareclk, scriptptr = 0;
2708 if (bios->major_version < 5) /* pre BIT */
2709 compare_record_len = 3;
2711 compare_record_len = 4;
2714 compareclk = le16_to_cpu(*((uint16_t *)&bios->data[clktable + compare_record_len * i]));
2715 if (pxclk >= compareclk * 10) {
2716 if (bios->major_version < 5) {
2717 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
2718 scriptptr = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + tmdssub * 2])));
2720 scriptptr = le16_to_cpu(*((uint16_t *)&bios->data[clktable + 2 + compare_record_len * i]));
2724 } while (compareclk);
2729 static void rundigitaloutscript(ScrnInfoPtr pScrn, uint16_t scriptptr, struct dcb_entry *dcbent, int head)
2731 bios_t *bios = &NVPTR(pScrn)->VBIOS;
2732 init_exec_t iexec = {true, false};
2734 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing digital output script table\n", scriptptr);
2735 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_CIO_CRE_44,
2736 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
2737 NVWriteVgaCrtc5758(NVPTR(pScrn), head, 0, dcbent->index);
2738 parse_init_table(pScrn, bios, scriptptr, &iexec);
2740 link_head_and_output(pScrn, dcbent, head);
2743 static void call_lvds_manufacturer_script(ScrnInfoPtr pScrn, struct dcb_entry *dcbent, int head, enum LVDS_script script)
2745 NVPtr pNv = NVPTR(pScrn);
2746 bios_t *bios = &pNv->VBIOS;
2747 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
2748 uint16_t scriptofs = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + sub * 2])));
2750 if (!bios->fp.xlated_entry || !sub || !scriptofs)
2753 rundigitaloutscript(pScrn, scriptofs, dcbent, head);
2755 if (script == LVDS_PANEL_OFF)
2756 /* off-on delay in ms */
2757 BIOS_USLEEP(le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.xlated_entry + 7]));
2759 /* Powerbook specific quirks */
2760 if (script == LVDS_RESET && ((pNv->Chipset & 0xffff) == 0x0179 || (pNv->Chipset & 0xffff) == 0x0329))
2761 nv_write_tmds(pNv, dcbent->or, 0, 0x02, 0x72);
2762 if ((pNv->Chipset & 0xffff) == 0x0179 || (pNv->Chipset & 0xffff) == 0x0189 || (pNv->Chipset & 0xffff) == 0x0329) {
2763 if (script == LVDS_PANEL_ON) {
2764 nv32_wr(pScrn, NV_PBUS_DEBUG_DUALHEAD_CTL, nv32_rd(pScrn, NV_PBUS_DEBUG_DUALHEAD_CTL) | (1 << 31));
2765 nv32_wr(pScrn, NV_CRTC_GPIO_EXT, nv32_rd(pScrn, NV_CRTC_GPIO_EXT) | 1);
2767 if (script == LVDS_PANEL_OFF) {
2768 nv32_wr(pScrn, NV_PBUS_DEBUG_DUALHEAD_CTL, nv32_rd(pScrn, NV_PBUS_DEBUG_DUALHEAD_CTL) & ~(1 << 31));
2769 nv32_wr(pScrn, NV_CRTC_GPIO_EXT, nv32_rd(pScrn, NV_CRTC_GPIO_EXT) & ~3);
2775 static void run_lvds_table(ScrnInfoPtr pScrn, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
2777 /* The BIT LVDS table's header has the information to setup the
2778 * necessary registers. Following the standard 4 byte header are:
2779 * A bitmask byte and a dual-link transition pxclk value for use in
2780 * selecting the init script when not using straps; 4 script pointers
2781 * for panel power, selected by output and on/off; and 8 table pointers
2782 * for panel init, the needed one determined by output, and bits in the
2783 * conf byte. These tables are similar to the TMDS tables, consisting
2784 * of a list of pxclks and script pointers.
2787 NVPtr pNv = NVPTR(pScrn);
2788 bios_t *bios = &pNv->VBIOS;
2789 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
2790 uint16_t scriptptr = 0, clktable;
2791 uint8_t clktableptr = 0;
2793 /* for now we assume version 3.0 table - g80 support will need some changes */
2798 case LVDS_BACKLIGHT_ON:
2800 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
2802 case LVDS_BACKLIGHT_OFF:
2803 case LVDS_PANEL_OFF:
2804 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
2807 if (dcbent->lvdsconf.use_straps_for_mode) {
2808 if (bios->fp.dual_link)
2810 if (bios->fp.BITbit1)
2813 uint8_t fallback = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
2814 int fallbackcmpval = (dcbent->or == 4) ? 4 : 1;
2816 if (bios->fp.dual_link) {
2818 fallbackcmpval *= 2;
2820 if (fallbackcmpval & fallback)
2824 /* adding outputset * 8 may not be correct */
2825 clktable = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 15 + clktableptr * 2 + outputset * 8]);
2827 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Pixel clock comparison table not found\n");
2830 scriptptr = clkcmptable(bios, clktable, pxclk);
2834 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "LVDS output init script not found\n");
2837 rundigitaloutscript(pScrn, scriptptr, dcbent, head);
2840 void call_lvds_script(ScrnInfoPtr pScrn, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
2842 /* LVDS operations are multiplexed in an effort to present a single API
2843 * which works with two vastly differing underlying structures.
2844 * This acts as the demux
2847 bios_t *bios = &NVPTR(pScrn)->VBIOS;
2848 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
2849 uint32_t sel_clk_binding;
2850 static int last_invoc = 0;
2852 if (last_invoc == (script << 1 | head) || !lvds_ver)
2855 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
2856 call_lvds_script(pScrn, dcbent, head, LVDS_RESET, pxclk);
2857 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
2858 call_lvds_script(pScrn, dcbent, head, LVDS_PANEL_OFF, pxclk);
2860 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Calling LVDS script %d:\n", script);
2862 /* don't let script change pll->head binding */
2863 sel_clk_binding = nv32_rd(pScrn, NV_RAMDAC_SEL_CLK) & 0x50000;
2865 if (lvds_ver < 0x30)
2866 call_lvds_manufacturer_script(pScrn, dcbent, head, script);
2868 run_lvds_table(pScrn, dcbent, head, script, pxclk);
2870 last_invoc = (script << 1 | head);
2872 nv32_wr(pScrn, NV_RAMDAC_SEL_CLK, (nv32_rd(pScrn, NV_RAMDAC_SEL_CLK) & ~0x50000) | sel_clk_binding);
2873 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
2874 nv32_wr(pScrn, NV_PBUS_POWERCTRL_2, 0);
2878 uint16_t fptablepointer;
2879 uint16_t fpxlatetableptr;
2883 struct lvdstableheader {
2884 uint8_t lvds_ver, headerlen, recordlen;
2887 static void parse_lvds_manufacturer_table_header(ScrnInfoPtr pScrn, bios_t *bios, struct lvdstableheader *lth)
2889 /* BMP version (0xa) LVDS table has a simple header of version and
2890 * record length. The BIT LVDS table has the typical BIT table header:
2891 * version byte, header length byte, record length byte, and a byte for
2892 * the maximum number of records that can be held in the table */
2894 uint8_t lvds_ver, headerlen, recordlen;
2896 memset(lth, 0, sizeof(struct lvdstableheader));
2898 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
2899 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2900 "Pointer to LVDS manufacturer table invalid\n");
2904 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
2907 case 0x0a: /* pre NV40 */
2909 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
2911 case 0x30: /* NV4x */
2912 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
2913 if (headerlen < 0x1f) {
2914 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2915 "LVDS table header not understood\n");
2918 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
2920 case 0x40: /* G80/G90 */
2921 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
2922 if (headerlen < 0x7) {
2923 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2924 "LVDS table header not understood\n");
2927 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
2930 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2931 "LVDS table revision %d.%d not currently supported\n",
2932 lvds_ver >> 4, lvds_ver & 0xf);
2936 lth->lvds_ver = lvds_ver;
2937 lth->headerlen = headerlen;
2938 lth->recordlen = recordlen;
2941 static void parse_fp_mode_table(ScrnInfoPtr pScrn, bios_t *bios, struct fppointers *fpp)
2944 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
2946 struct lvdstableheader lth;
2948 DisplayModePtr mode;
2950 if (fpp->fptablepointer == 0x0) {
2951 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2952 "Pointer to flat panel table invalid\n");
2956 fptable = &bios->data[fpp->fptablepointer];
2957 fptable_ver = fptable[0];
2959 switch (fptable_ver) {
2960 /* BMP version 0x5.0x11 BIOSen have version 1 like tables, but no version field,
2961 * and miss one of the spread spectrum/PWM bytes.
2962 * This could affect early GF2Go parts (not seen any appropriate ROMs though).
2963 * Here we assume that a version of 0x05 matches this case (combining with a
2964 * BMP version check would be better), as the common case for the panel type
2965 * field is 0x0005, and that is in fact what we are reading the first byte of. */
2966 case 0x05: /* some NV10, 11, 15, 16 */
2970 case 0x10: /* some NV15/16, and NV11+ */
2974 case 0x20: /* NV40+ */
2975 headerlen = fptable[1];
2976 recordlen = fptable[2];
2977 fpentries = fptable[3];
2978 /* fptable[4] is the minimum RAMDAC_FP_HCRTC->RAMDAC_FP_HSYNC_START gap */
2979 bios->digital_min_front_porch = fptable[4];
2983 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2984 "FP table revision %d.%d not currently supported\n",
2985 fptable_ver >> 4, fptable_ver & 0xf);
2989 /* non mobile only needs to set digital_min_front_porch */
2990 if (!(bios->feature_byte & FEATURE_MOBILE))
2993 parse_lvds_manufacturer_table_header(pScrn, bios, <h);
2995 switch (lth.lvds_ver) {
2997 /* make sure to match the 0xff strapping check below */
2998 if ((bios->fp.strapping & 0xf) == 0xf)
2999 bios->data[fpp->fpxlatetableptr + 0xf] = 0xf;
3003 fpp->fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + lth.headerlen + 1;
3004 fpp->xlatwidth = lth.recordlen;
3006 if (fpp->fpxlatetableptr == 0x0) {
3007 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3008 "Pointer to flat panel xlat table invalid\n");
3012 /* Query all modes and find one with a matching clock. */
3013 /* Note that this only serves as a backup solution if ddc fails. */
3014 if (lth.lvds_ver == 0x40) {
3015 uint32_t clock, needed_clock;
3016 int i, index = 0xF, matches = 0;
3017 needed_clock = nv32_rd(pScrn, 0x00616404) & 0xFFFFF;
3018 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "LVDS clock seems to be %d KHz.\n", needed_clock);
3020 for (i = 0; i < fpentries; i++) {
3021 modeofs = headerlen + recordlen * i;
3022 clock = le16_to_cpu(*(uint16_t *)&fptable[modeofs]) * 10;
3023 if (clock == needed_clock) {
3030 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found a mode with matching clock\n");
3032 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found %d modes, this is not useful\n", matches);
3037 fpindex = bios->data[fpp->fpxlatetableptr + index * fpp->xlatwidth];
3038 bios->fp.strapping = ((fpindex & 0xF) << 4) | (fpindex & 0xF);
3040 fpindex = bios->data[fpp->fpxlatetableptr + bios->fp.strapping * fpp->xlatwidth];
3041 bios->fp.strapping |= fpindex << 4;
3044 if (fpindex > fpentries) {
3045 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3046 "Bad flat panel table index\n");
3050 /* reserved values - means that ddc or hard coded edid should be used */
3051 if (bios->fp.strapping == 0xff) {
3052 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Ignoring FP table\n");
3056 if (!(mode = xcalloc(1, sizeof(DisplayModeRec))))
3059 modeofs = headerlen + recordlen * fpindex + ofs;
3060 mode->Clock = le16_to_cpu(*(uint16_t *)&fptable[modeofs]) * 10;
3061 mode->HDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 4] + 1);
3062 mode->HSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 10] + 1);
3063 mode->HSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 12] + 1);
3064 mode->HTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 14] + 1);
3065 mode->VDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 18] + 1);
3066 mode->VSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 24] + 1);
3067 mode->VSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 26] + 1);
3068 mode->VTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 28] + 1);
3069 mode->Flags |= (fptable[modeofs + 30] & 0x10) ? V_PHSYNC : V_NHSYNC;
3070 mode->Flags |= (fptable[modeofs + 30] & 0x1) ? V_PVSYNC : V_NVSYNC;
3073 * bytes 1-2 are "panel type", including bits on whether Colour/mono, single/dual link, and type (TFT etc.)
3074 * bytes 3-6 are bits per colour in RGBX
3077 * 13-14 is HValid Start
3078 * 15-16 is HValid End
3079 * bytes 38-39 relate to spread spectrum settings
3080 * bytes 40-43 are something to do with PWM */
3082 mode->status = MODE_OK;
3083 mode->type = M_T_DRIVER | M_T_PREFERRED;
3084 xf86SetModeDefaultName(mode);
3086 // if (XF86_CRTC_CONFIG_PTR(pScrn)->debug_modes) {
3087 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3088 "Found flat panel mode in BIOS tables:\n");
3089 xf86PrintModeline(pScrn->scrnIndex, mode);
3092 bios->fp.native_mode = mode;
3095 void parse_lvds_manufacturer_table(ScrnInfoPtr pScrn, bios_t *bios, int pxclk)
3097 /* The LVDS table header is (mostly) described in
3098 * parse_lvds_manufacturer_table_header(): the BIT header additionally
3099 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
3100 * straps are not being used for the panel, this specifies the frequency
3101 * at which modes should be set up in the dual link style.
3103 * Following the header, the BMP (ver 0xa) table has several records,
3104 * indexed by a seperate xlat table, indexed in turn by the fp strap in
3105 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
3106 * numbers for use by INIT_SUB which controlled panel init and power,
3107 * and finally a dword of ms to sleep between power off and on
3110 * In the BIT versions, the table following the header serves as an
3111 * integrated config and xlat table: the records in the table are
3112 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
3113 * two bytes - the first as a config byte, the second for indexing the
3114 * fp mode table pointed to by the BIT 'D' table
3116 * Due to the stage at which DDC is used in X's DDX design, the EDID res
3117 * for a panel isn't known at init, so the tests against the pixel clock
3118 * in the EDID case for selection of the correct table entry and setting
3119 * of the dual link flag cannot be done until later - this function may
3120 * be called at runtime with a non-zero pxclk argument to perform these
3124 unsigned int lvdsmanufacturerindex = 0;
3125 struct lvdstableheader lth;
3128 parse_lvds_manufacturer_table_header(pScrn, bios, <h);
3130 switch (lth.lvds_ver) {
3131 case 0: /* header parsing failed */
3133 case 0x0a: /* pre NV40 */
3134 lvdsmanufacturerindex = bios->data[bios->fp.fpxlatemanufacturertableptr + (bios->fp.strapping & 0xf)];
3136 /* we're done if this isn't the EDID panel case */
3137 if (pxclk == 0 || (bios->fp.strapping & 0xf) != 0xf)
3140 /* change in behaviour guessed at nv30; see datapoints below */
3141 if (bios->chip_version < 0x30) {
3142 /* nv17 behaviour */
3143 lvdsmanufacturerindex = bios->fp.if_is_24bit ? 2 : 0;
3144 if (pxclk >= bios->fp.duallink_transition_clk)
3145 lvdsmanufacturerindex++;
3147 /* nv31, nv34 behaviour */
3148 lvdsmanufacturerindex = 0;
3149 if (pxclk >= bios->fp.duallink_transition_clk)
3150 lvdsmanufacturerindex = 2;
3151 if (pxclk >= 140000)
3152 lvdsmanufacturerindex = 3;
3155 /* nvidia set the high nibble of (cr57=f, cr58) to
3156 * lvdsmanufacturerindex in this case; we don't */
3158 case 0x30: /* NV4x */
3159 lvdsmanufacturerindex = bios->fp.strapping & 0xf;
3161 case 0x40: /* G80/G90 */
3162 lvdsmanufacturerindex = bios->fp.strapping & 0xf;
3165 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3166 "LVDS table revision not currently supported\n");
3170 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
3171 switch (lth.lvds_ver) {
3173 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
3174 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
3175 bios->fp.dual_link = bios->data[lvdsofs] & 4;
3176 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
3177 bios->fp.if_is_24bit = bios->data[lvdsofs] & 16;
3180 /* My money would be on there being a 24 bit interface bit in this table,
3181 * but I have no example of a laptop bios with a 24 bit panel to confirm that.
3182 * Hence we shout loudly if any bit other than bit 0 is set (I've not even
3185 if (bios->data[lvdsofs] > 1)
3186 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3187 "You have a very unusual laptop display; please report it\n");
3188 /* no sign of the "power off for reset" or "reset for panel on" bits, but it's safer to assume we should */
3189 bios->fp.power_off_for_reset = true;
3190 bios->fp.reset_after_pclk_change = true;
3191 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3192 bios->fp.BITbit1 = bios->data[lvdsofs] & 2;
3193 bios->fp.duallink_transition_clk = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3196 /* fairly sure, but not 100% */
3197 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3198 bios->fp.duallink_transition_clk = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3202 /* set dual_link flag for EDID case */
3203 if ((bios->fp.strapping & 0xf) == 0xf && pxclk) {
3204 if (pxclk >= bios->fp.duallink_transition_clk)
3205 bios->fp.dual_link = true;
3207 bios->fp.dual_link = false;
3211 void run_tmds_table(ScrnInfoPtr pScrn, struct dcb_entry *dcbent, int head, int pxclk)
3213 /* the pxclk parameter is in kHz
3215 * This runs the TMDS regs setting code found on BIT bios cards
3217 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
3218 * ffs(or) == 3, use the second.
3221 NVPtr pNv = NVPTR(pScrn);
3222 bios_t *bios = &pNv->VBIOS;
3223 uint16_t clktable = 0, scriptptr;
3224 uint32_t sel_clk_binding;
3226 if (dcbent->location != LOC_ON_CHIP)
3229 switch (ffs(dcbent->or)) {
3231 clktable = bios->tmds.output0_script_ptr;
3235 clktable = bios->tmds.output1_script_ptr;
3240 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Pixel clock comparison table not found\n");
3244 scriptptr = clkcmptable(bios, clktable, pxclk);
3247 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "TMDS output init script not found\n");
3251 /* don't let script change pll->head binding */
3252 sel_clk_binding = nv32_rd(pScrn, NV_RAMDAC_SEL_CLK) & 0x50000;
3253 rundigitaloutscript(pScrn, scriptptr, dcbent, head);
3254 nv32_wr(pScrn, NV_RAMDAC_SEL_CLK, (nv32_rd(pScrn, NV_RAMDAC_SEL_CLK) & ~0x50000) | sel_clk_binding);
3257 static int get_fp_strap(ScrnInfoPtr pScrn, bios_t *bios)
3259 /* the fp strap is normally dictated by the "User Strap" in
3260 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3261 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3262 * by the PCI subsystem ID during POST, but not before the previous user
3263 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3264 * read and used instead
3267 /* Now comes the G80/G90 story, i've only got one hint.
3268 * I can read back the clock freq from register 0x00616404.
3269 * So for the moment just write 0xF here.
3272 if (bios->chip_version >= 0x80)
3275 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
3276 return (NVReadVgaCrtc5758(NVPTR(pScrn), 0, 0xf) & 0xf);
3278 return ((nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 16) & 0xf);
3281 static void parse_bios_version(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset)
3283 /* offset + 0 (8 bits): Micro version
3284 * offset + 1 (8 bits): Minor version
3285 * offset + 2 (8 bits): Chip version
3286 * offset + 3 (8 bits): Major version
3289 bios->major_version = bios->data[offset + 3];
3290 bios->chip_version = bios->data[offset + 2];
3291 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios version %02x.%02x.%02x.%02x\n",
3292 bios->data[offset + 3], bios->data[offset + 2],
3293 bios->data[offset + 1], bios->data[offset]);
3296 bool get_pll_limits(ScrnInfoPtr pScrn, uint32_t limit_match, struct pll_lims *pll_lim)
3300 * Version 0x10: NV31
3301 * One byte header (version), one record of 24 bytes
3302 * Version 0x11: NV36 - Not implemented
3303 * Seems to have same record style as 0x10, but 3 records rather than 1
3304 * Version 0x20: Found on Geforce 6 cards
3305 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
3306 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
3307 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
3308 * length in general, some (integrated) have an extra configuration byte
3311 NVPtr pNv = NVPTR(pScrn);
3312 bios_t *bios = &pNv->VBIOS;
3313 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
3315 uint32_t crystal_strap_mask, crystal_straps;
3317 if (!bios->pll_limit_tbl_ptr) {
3318 if (bios->chip_version >= 0x40 || bios->chip_version == 0x31 || bios->chip_version == 0x36) {
3319 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Pointer to PLL limits table invalid\n");
3323 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
3325 crystal_strap_mask = 1 << 6;
3326 /* open coded pNv->twoHeads test */
3327 if (bios->chip_version > 0x10 && bios->chip_version != 0x15 &&
3328 bios->chip_version != 0x1a && bios->chip_version != 0x20)
3329 crystal_strap_mask |= 1 << 22;
3330 crystal_straps = nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & crystal_strap_mask;
3332 switch (pll_lim_ver) {
3333 /* we use version 0 to indicate a pre limit table bios (single stage pll)
3334 * and load the hard coded limits instead */
3338 case 0x11: /* strictly v0x11 has 3 entries, but the last two don't seem to get used */
3346 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
3347 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
3348 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
3351 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3352 "PLL limits table revision 0x%X not currently supported\n", pll_lim_ver);
3356 /* initialize all members to zero */
3357 memset(pll_lim, 0, sizeof(struct pll_lims));
3359 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
3360 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex;
3362 pll_lim->vco1.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs])));
3363 pll_lim->vco1.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 4])));
3364 pll_lim->vco2.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 8])));
3365 pll_lim->vco2.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 12])));
3366 pll_lim->vco1.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 16])));
3367 pll_lim->vco2.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 20])));
3368 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
3370 /* these values taken from nv30/31/36 */
3371 pll_lim->vco1.min_n = 0x1;
3372 if (bios->chip_version == 0x36)
3373 pll_lim->vco1.min_n = 0x5;
3374 pll_lim->vco1.max_n = 0xff;
3375 pll_lim->vco1.min_m = 0x1;
3376 pll_lim->vco1.max_m = 0xd;
3377 pll_lim->vco2.min_n = 0x4;
3378 /* on nv30, 31, 36 (i.e. all cards with two stage PLLs with this
3379 * table version (apart from nv35)), N2 is compared to
3380 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
3383 pll_lim->vco2.max_n = 0x28;
3384 if (bios->chip_version == 0x30 || bios->chip_version == 0x35)
3385 /* only 5 bits available for N2 on nv30/35 */
3386 pll_lim->vco2.max_n = 0x1f;
3387 pll_lim->vco2.min_m = 0x1;
3388 pll_lim->vco2.max_m = 0x4;
3389 } else if (pll_lim_ver) { /* ver 0x20, 0x21 */
3390 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
3391 uint32_t reg = 0; /* default match */
3394 /* first entry is default match, if nothing better. warn if reg field nonzero */
3395 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs])))
3396 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3397 "Default PLL limit entry has non-zero register field\n");
3399 if (limit_match > MAX_PLL_TYPES)
3400 /* we've been passed a reg as the match */
3402 else /* limit match is a pll type */
3403 for (i = 1; i < entries && !reg; i++) {
3404 uint32_t cmpreg = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + recordlen * i])));
3406 if (limit_match == NVPLL && (cmpreg == NV_RAMDAC_NVPLL || cmpreg == 0x4000))
3408 if (limit_match == MPLL && (cmpreg == NV_RAMDAC_MPLL || cmpreg == 0x4020))
3410 if (limit_match == VPLL1 && (cmpreg == NV_RAMDAC_VPLL || cmpreg == 0x4010))
3412 if (limit_match == VPLL2 && (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018))
3416 for (i = 1; i < entries; i++)
3417 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs + recordlen * i])) == reg) {
3422 plloffs += recordlen * pllindex;
3424 BIOSLOG(pScrn, "Loading PLL limits for reg 0x%08x\n", pllindex ? reg : 0);
3426 /* frequencies are stored in tables in MHz, kHz are more useful, so we convert */
3428 /* What output frequencies can each VCO generate? */
3429 pll_lim->vco1.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 4]))) * 1000;
3430 pll_lim->vco1.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 6]))) * 1000;
3431 pll_lim->vco2.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 8]))) * 1000;
3432 pll_lim->vco2.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 10]))) * 1000;
3434 /* What input frequencies do they accept (past the m-divider)? */
3435 pll_lim->vco1.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 12]))) * 1000;
3436 pll_lim->vco2.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 14]))) * 1000;
3437 pll_lim->vco1.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 16]))) * 1000;
3438 pll_lim->vco2.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 18]))) * 1000;
3440 /* What values are accepted as multiplier and divider? */
3441 pll_lim->vco1.min_n = bios->data[plloffs + 20];
3442 pll_lim->vco1.max_n = bios->data[plloffs + 21];
3443 pll_lim->vco1.min_m = bios->data[plloffs + 22];
3444 pll_lim->vco1.max_m = bios->data[plloffs + 23];
3445 pll_lim->vco2.min_n = bios->data[plloffs + 24];
3446 pll_lim->vco2.max_n = bios->data[plloffs + 25];
3447 pll_lim->vco2.min_m = bios->data[plloffs + 26];
3448 pll_lim->vco2.max_m = bios->data[plloffs + 27];
3450 pll_lim->unk1c = bios->data[plloffs + 28];
3451 pll_lim->max_log2p_bias = bios->data[plloffs + 29];
3452 pll_lim->log2p_bias = bios->data[plloffs + 30];
3454 if (recordlen > 0x22)
3455 pll_lim->refclk = le32_to_cpu(*((uint32_t *)&bios->data[plloffs + 31]));
3457 if (recordlen > 0x23)
3458 if (bios->data[plloffs + 35])
3459 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3460 "Bits set in PLL configuration byte (%x)\n", bios->data[plloffs + 35]);
3462 /* C51 special not seen elsewhere */
3463 if (bios->chip_version == 0x51 && !pll_lim->refclk) {
3464 uint32_t sel_clk = nv32_rd(pScrn, NV_RAMDAC_SEL_CLK);
3466 if (((limit_match == NV_RAMDAC_VPLL || limit_match == VPLL1) && sel_clk & 0x20) ||
3467 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) {
3468 if (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
3469 pll_lim->refclk = 200000;
3471 pll_lim->refclk = 25000;
3476 /* By now any valid limit table ought to have set a max frequency for
3477 * vco1, so if it's zero it's either a pre limit table bios, or one
3478 * with an empty limit table (seen on nv18)
3480 if (!pll_lim->vco1.maxfreq) {
3481 pll_lim->vco1.minfreq = bios->fminvco;
3482 pll_lim->vco1.maxfreq = bios->fmaxvco;
3483 pll_lim->vco1.min_inputfreq = 0;
3484 pll_lim->vco1.max_inputfreq = INT_MAX;
3485 pll_lim->vco1.min_n = 0x1;
3486 pll_lim->vco1.max_n = 0xff;
3487 pll_lim->vco1.min_m = 0x1;
3488 if (crystal_straps == 0) {
3489 /* nv05 does this, nv11 doesn't, nv10 unknown */
3490 if (bios->chip_version < 0x11)
3491 pll_lim->vco1.min_m = 0x7;
3492 pll_lim->vco1.max_m = 0xd;
3494 if (bios->chip_version < 0x11)
3495 pll_lim->vco1.min_m = 0x8;
3496 pll_lim->vco1.max_m = 0xe;
3500 if (!pll_lim->refclk)
3501 switch (crystal_straps) {
3503 pll_lim->refclk = 13500;
3506 pll_lim->refclk = 14318;
3509 pll_lim->refclk = 27000;
3511 case (1 << 22 | 1 << 6):
3512 pll_lim->refclk = 25000;
3516 #if 0 /* for easy debugging */
3517 ErrorF("pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
3518 ErrorF("pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
3519 ErrorF("pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
3520 ErrorF("pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
3522 ErrorF("pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
3523 ErrorF("pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
3524 ErrorF("pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
3525 ErrorF("pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
3527 ErrorF("pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
3528 ErrorF("pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
3529 ErrorF("pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
3530 ErrorF("pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
3531 ErrorF("pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
3532 ErrorF("pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
3533 ErrorF("pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
3534 ErrorF("pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
3536 ErrorF("pll.unk1c: %d\n", pll_lim->unk1c);
3537 ErrorF("pll.max_log2p_bias: %d\n", pll_lim->max_log2p_bias);
3538 ErrorF("pll.log2p_bias: %d\n", pll_lim->log2p_bias);
3540 ErrorF("pll.refclk: %d\n", pll_lim->refclk);
3546 static int parse_bit_C_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3548 /* offset + 8 (16 bits): PLL limits table pointer
3550 * There's more in here, but that's unknown.
3553 if (bitentry->length < 10) {
3554 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand BIT C table\n");
3558 bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
3563 static int parse_bit_display_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3565 /* Parses the flat panel table segment that the bit entry points to.
3566 * Starting at bitentry->offset:
3568 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte records beginning with a freq
3569 * offset + 2 (16 bits): mode table pointer
3572 struct fppointers fpp = { 0 };
3574 if (bitentry->length != 4) {
3575 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand BIT display table\n");
3579 fpp.fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
3581 parse_fp_mode_table(pScrn, bios, &fpp);
3586 static unsigned int parse_bit_init_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3588 /* Parses the init table segment that the bit entry points to.
3589 * Starting at bitentry->offset:
3591 * offset + 0 (16 bits): init script tables pointer
3592 * offset + 2 (16 bits): macro index table pointer
3593 * offset + 4 (16 bits): macro table pointer
3594 * offset + 6 (16 bits): condition table pointer
3595 * offset + 8 (16 bits): io condition table pointer
3596 * offset + 10 (16 bits): io flag condition table pointer
3597 * offset + 12 (16 bits): init function table pointer
3601 if (bitentry->length < 14) {
3602 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand init table\n");
3606 bios->init_script_tbls_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3607 bios->macro_index_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
3608 bios->macro_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 4])));
3609 bios->condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 6])));
3610 bios->io_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
3611 bios->io_flag_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 10])));
3612 bios->init_function_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 12])));
3617 static int parse_bit_i_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3619 /* BIT 'i' (info?) table
3621 * offset + 0 (32 bits): BIOS version dword (as in B table)
3622 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
3623 * offset + 13 (16 bits): pointer to table containing DAC load detection comparison values
3625 * There's other things in the table, purpose unknown
3628 uint16_t daccmpoffset;
3629 uint8_t dacversion, dacheaderlen;
3631 if (bitentry->length < 6) {
3632 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3633 "BIT i table not long enough for BIOS version and feature byte\n");
3637 parse_bios_version(pScrn, bios, bitentry->offset);
3639 /* bit 4 seems to indicate a mobile bios, other bits possibly as for BMP feature byte */
3640 bios->feature_byte = bios->data[bitentry->offset + 5];
3642 if (bitentry->length < 15) {
3643 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3644 "BIT i table not long enough for DAC load detection comparison table\n");
3648 daccmpoffset = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 13])));
3650 /* doesn't exist on g80 */
3654 /* The first value in the table, following the header, is the comparison value
3655 * Purpose of subsequent values unknown -- TV load detection?
3658 dacversion = bios->data[daccmpoffset];
3659 dacheaderlen = bios->data[daccmpoffset + 1];
3661 if (dacversion != 0x00 && dacversion != 0x10) {
3662 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3663 "DAC load detection comparison table version %d.%d not known\n",
3664 dacversion >> 4, dacversion & 0xf);
3668 bios->dactestval = le32_to_cpu(*((uint32_t *)(&bios->data[daccmpoffset + dacheaderlen])));
3673 static int parse_bit_lvds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3675 /* Parses the LVDS table segment that the bit entry points to.
3676 * Starting at bitentry->offset:
3678 * offset + 0 (16 bits): LVDS strap xlate table pointer
3681 if (bitentry->length != 2) {
3682 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand BIT LVDS table\n");
3686 /* no idea if it's still called the LVDS manufacturer table, but the concept's close enough */
3687 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3688 bios->fp.strapping = get_fp_strap(pScrn, bios);
3690 parse_lvds_manufacturer_table(pScrn, bios, 0);
3695 static int parse_bit_M_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3697 /* offset + 2 (8 bits): number of options in an INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
3698 * offset + 3 (16 bits): pointer to strap xlate table for RAM restrict option selection
3700 * There's a bunch of bits in this table other than the RAM restrict
3701 * stuff that we don't use - their use currently unknown
3706 /* Older bios versions don't have a sufficiently long table for what we want */
3707 if (bitentry->length < 0x5)
3710 /* set up multiplier for INIT_RAM_RESTRICT_ZM_REG_GROUP */
3711 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != 0x8f); i++)
3713 itbl_entry[i].length_multiplier = bios->data[bitentry->offset + 2] * 4;
3714 init_ram_restrict_zm_reg_group_blocklen = itbl_entry[i].length_multiplier;
3716 bios->ram_restrict_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 3])));
3721 static int parse_bit_tmds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3723 /* Parses the pointer to the TMDS table
3725 * Starting at bitentry->offset:
3727 * offset + 0 (16 bits): TMDS table pointer
3729 * The TMDS table is typically found just before the DCB table, with a
3730 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
3733 * At offset +7 is a pointer to a script, which I don't know how to run yet
3734 * At offset +9 is a pointer to another script, likewise
3735 * Offset +11 has a pointer to a table where the first word is a pxclk
3736 * frequency and the second word a pointer to a script, which should be
3737 * run if the comparison pxclk frequency is less than the pxclk desired.
3738 * This repeats for decreasing comparison frequencies
3739 * Offset +13 has a pointer to a similar table
3740 * The selection of table (and possibly +7/+9 script) is dictated by
3741 * "or" from the DCB.
3744 uint16_t tmdstableptr, script1, script2;
3746 if (bitentry->length != 2) {
3747 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand BIT TMDS table\n");
3751 tmdstableptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3753 if (tmdstableptr == 0x0) {
3754 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Pointer to TMDS table invalid\n");
3758 /* nv50+ has v2.0, but we don't parse it atm */
3759 if (bios->data[tmdstableptr] != 0x11) {
3760 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "TMDS table revision %d.%d not currently supported\n",
3761 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
3765 /* These two scripts are odd: they don't seem to get run even when they are not stubbed */
3766 script1 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 7]));
3767 script2 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 9]));
3768 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
3769 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "TMDS table script pointers not stubbed\n");
3771 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 11]));
3772 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 13]));
3777 static void parse_bit_structure(ScrnInfoPtr pScrn, bios_t *bios, const uint16_t bitoffset)
3779 int entries = bios->data[bitoffset + 4];
3780 /* parse i first, I next (which needs C & M before it), and L before D */
3781 char parseorder[] = "iCMILDT";
3782 bit_entry_t bitentry;
3785 for (i = 0; i < sizeof(parseorder); i++) {
3786 for (j = 0, offset = bitoffset + 6; j < entries; j++, offset += 6) {
3787 bitentry.id[0] = bios->data[offset];
3788 bitentry.id[1] = bios->data[offset + 1];
3789 bitentry.length = le16_to_cpu(*((uint16_t *)&bios->data[offset + 2]));
3790 bitentry.offset = le16_to_cpu(*((uint16_t *)&bios->data[offset + 4]));
3792 if (bitentry.id[0] != parseorder[i])
3795 switch (bitentry.id[0]) {
3797 parse_bit_C_tbl_entry(pScrn, bios, &bitentry);
3800 parse_bit_display_tbl_entry(pScrn, bios, &bitentry);
3803 parse_bit_init_tbl_entry(pScrn, bios, &bitentry);
3804 parse_init_tables(pScrn, bios);
3806 case 'i': /* info? */
3807 parse_bit_i_tbl_entry(pScrn, bios, &bitentry);
3810 if (bios->feature_byte & FEATURE_MOBILE)
3811 parse_bit_lvds_tbl_entry(pScrn, bios, &bitentry);
3813 case 'M': /* memory? */
3814 parse_bit_M_tbl_entry(pScrn, bios, &bitentry);
3817 parse_bit_tmds_tbl_entry(pScrn, bios, &bitentry);
3824 static void parse_bmp_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset)
3826 /* Parse the BMP structure for useful things
3828 * offset + 5: BMP major version
3829 * offset + 6: BMP minor version
3830 * offset + 10: BCD encoded BIOS version
3832 * offset + 18: init script table pointer (for bios versions < 5.10h)
3833 * offset + 20: extra init script table pointer (for bios versions < 5.10h)
3835 * offset + 24: memory init table pointer (used on early bios versions)
3836 * offset + 26: SDR memory sequencing setup data table
3837 * offset + 28: DDR memory sequencing setup data table
3839 * offset + 54: index of I2C CRTC pair to use for CRT output
3840 * offset + 55: index of I2C CRTC pair to use for TV output
3841 * offset + 56: index of I2C CRTC pair to use for flat panel output
3842 * offset + 58: write CRTC index for I2C pair 0
3843 * offset + 59: read CRTC index for I2C pair 0
3844 * offset + 60: write CRTC index for I2C pair 1
3845 * offset + 61: read CRTC index for I2C pair 1
3847 * offset + 67: maximum internal PLL frequency (single stage PLL)
3848 * offset + 71: minimum internal PLL frequency (single stage PLL)
3850 * offset + 75: script table pointers, as for parse_bit_init_tbl_entry
3852 * offset + 89: TMDS single link output A table pointer
3853 * offset + 91: TMDS single link output B table pointer
3854 * offset + 105: flat panel timings table pointer
3855 * offset + 107: flat panel strapping translation table pointer
3856 * offset + 117: LVDS manufacturer panel config table pointer
3857 * offset + 119: LVDS manufacturer strapping translation table pointer
3859 * offset + 142: PLL limits table pointer
3862 NVPtr pNv = NVPTR(pScrn);
3863 uint8_t bmp_version_major, bmp_version_minor;
3865 struct fppointers fpp = { 0 };
3866 uint16_t legacy_scripts_offset, legacy_i2c_offset;
3868 /* load needed defaults in case we can't parse this info */
3869 pNv->dcb_table.i2c_write[0] = 0x3f;
3870 pNv->dcb_table.i2c_read[0] = 0x3e;
3871 pNv->dcb_table.i2c_write[1] = 0x37;
3872 pNv->dcb_table.i2c_read[1] = 0x36;
3873 bios->digital_min_front_porch = 0x4b;
3874 bios->fmaxvco = 256000;
3875 bios->fminvco = 128000;
3876 bios->fp.duallink_transition_clk = 90000;
3878 bmp_version_major = bios->data[offset + 5];
3879 bmp_version_minor = bios->data[offset + 6];
3881 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BMP version %d.%d\n",
3882 bmp_version_major, bmp_version_minor);
3884 /* Make sure that 0x36 is blank and can't be mistaken for a DCB pointer on early versions */
3885 if (bmp_version_major < 5)
3886 *(uint16_t *)&bios->data[0x36] = 0;
3888 /* Seems that the minor version was 1 for all major versions prior to 5 */
3889 /* Version 6 could theoretically exist, but I suspect BIT happened instead */
3890 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
3891 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "You have an unsupported BMP version. Please send in your bios\n");
3895 if (bmp_version_major == 0) /* nothing that's currently useful in this version */
3897 else if (bmp_version_major == 1)
3898 bmplength = 44; /* exact for 1.01 */
3899 else if (bmp_version_major == 2)
3900 bmplength = 48; /* exact for 2.01 */
3901 else if (bmp_version_major == 3)
3902 bmplength = 54; /* guessed - mem init tables added in this version */
3903 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) /* don't know if 5.0 exists... */
3904 bmplength = 62; /* guessed - BMP I2C indices added in version 4*/
3905 else if (bmp_version_minor < 0x6)
3906 bmplength = 67; /* exact for 5.01 */
3907 else if (bmp_version_minor < 0x10)
3908 bmplength = 75; /* exact for 5.06 */
3909 else if (bmp_version_minor == 0x10)
3910 bmplength = 89; /* exact for 5.10h */
3911 else if (bmp_version_minor < 0x14)
3912 bmplength = 118; /* exact for 5.11h */
3913 else if (bmp_version_minor < 0x24) /* not sure of version where pll limits came in;
3914 * certainly exist by 0x24 though */
3915 /* length not exact: this is long enough to get lvds members */
3917 else if (bmp_version_minor < 0x27)
3918 /* length not exact: this is long enough to get pll limit member */
3921 /* length not exact: this is long enough to get dual link transition clock */
3925 if (nv_cksum(bios->data + offset, 8)) {
3926 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Bad BMP checksum\n");
3930 /* bit 4 seems to indicate a mobile bios, bit 5 that the flat panel
3931 * tables are present, and bit 6 a tv bios */
3932 bios->feature_byte = bios->data[offset + 9];
3934 parse_bios_version(pScrn, bios, offset + 10);
3936 legacy_scripts_offset = offset + 18;
3937 if (bmp_version_major < 2)
3938 legacy_scripts_offset -= 4;
3939 bios->init_script_tbls_ptr = le16_to_cpu(*(uint16_t *)&bios->data[legacy_scripts_offset]);
3940 bios->extra_init_script_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[legacy_scripts_offset + 2]);
3942 if (bmp_version_major > 2) { /* appears in BMP 3 */
3943 bios->legacy.mem_init_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 24]);
3944 bios->legacy.sdr_seq_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 26]);
3945 bios->legacy.ddr_seq_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 28]);
3948 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
3950 legacy_i2c_offset = offset + 54;
3951 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
3952 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
3953 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
3954 pNv->dcb_table.i2c_write[0] = bios->data[legacy_i2c_offset + 4];
3955 pNv->dcb_table.i2c_read[0] = bios->data[legacy_i2c_offset + 5];
3956 pNv->dcb_table.i2c_write[1] = bios->data[legacy_i2c_offset + 6];
3957 pNv->dcb_table.i2c_read[1] = bios->data[legacy_i2c_offset + 7];
3959 if (bmplength > 74) {
3960 bios->fmaxvco = le32_to_cpu(*((uint32_t *)&bios->data[offset + 67]));
3961 bios->fminvco = le32_to_cpu(*((uint32_t *)&bios->data[offset + 71]));
3963 if (bmplength > 88) {
3964 bit_entry_t initbitentry;
3965 initbitentry.length = 14;
3966 initbitentry.offset = offset + 75;
3967 parse_bit_init_tbl_entry(pScrn, bios, &initbitentry);
3969 if (bmplength > 94) {
3970 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[offset + 89]));
3971 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[offset + 91]));
3972 /* it seems the old style lvds script pointer (which I've not observed in use) gets
3973 * reused as the 18/24 bit panel interface default for EDID equipped panels */
3974 bios->fp.if_is_24bit = bios->data[offset + 95] & 1;
3976 if (bmplength > 108) {
3977 fpp.fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 105])));
3978 fpp.fpxlatetableptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 107])));
3981 if (bmplength > 120) {
3982 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 117])));
3983 bios->fp.fpxlatemanufacturertableptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 119])));
3985 if (bmplength > 143)
3986 bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 142])));
3988 if (bmplength > 157)
3989 bios->fp.duallink_transition_clk = le16_to_cpu(*((uint16_t *)&bios->data[offset + 156])) * 10;
3991 /* want pll_limit_tbl_ptr set (if available) before init is run */
3992 if (bmp_version_major < 5 || bmp_version_minor < 0x10) {
3993 init_exec_t iexec = {true, false};
3994 if (bios->init_script_tbls_ptr)
3995 parse_init_table(pScrn, bios, bios->init_script_tbls_ptr, &iexec);
3996 if (bios->extra_init_script_tbl_ptr)
3997 parse_init_table(pScrn, bios, bios->extra_init_script_tbl_ptr, &iexec);
3999 parse_init_tables(pScrn, bios);
4001 /* If it's not a laptop, you probably don't care about fptables */
4002 if (!(bios->feature_byte & FEATURE_MOBILE))
4005 bios->fp.strapping = get_fp_strap(pScrn, bios);
4006 parse_lvds_manufacturer_table(pScrn, bios, 0);
4007 parse_fp_mode_table(pScrn, bios, &fpp);
4010 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
4014 for (i = 0; i <= (n - len); i++) {
4015 for (j = 0; j < len; j++)
4016 if (data[i + j] != str[j])
4026 read_dcb_i2c_entry(ScrnInfoPtr pScrn, uint8_t dcb_version, uint16_t i2ctabptr, int index)
4028 NVPtr pNv = NVPTR(pScrn);
4029 bios_t *bios = &pNv->VBIOS;
4030 uint8_t *i2ctable = &bios->data[i2ctabptr];
4031 uint8_t headerlen = 0;
4032 int i2c_entries = MAX_NUM_DCB_ENTRIES;
4033 int recordoffset = 0, rdofs = 1, wrofs = 0;
4038 if (dcb_version >= 0x30) {
4039 if (i2ctable[0] != dcb_version) /* necessary? */
4040 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4041 "DCB I2C table version mismatch (%02X vs %02X)\n",
4042 i2ctable[0], dcb_version);
4043 headerlen = i2ctable[1];
4044 i2c_entries = i2ctable[2];
4046 /* same address offset used for read and write for C51 and G80 */
4047 if (bios->chip_version == 0x51)
4049 if (i2ctable[0] >= 0x40)
4052 /* it's your own fault if you call this function on a DCB 1.1 BIOS --
4053 * the test below is for DCB 1.2
4055 if (dcb_version < 0x14) {
4063 if (index > i2c_entries) {
4064 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4065 "DCB I2C index too big (%d > %d)\n",
4066 index, i2ctable[2]);
4069 if (i2ctable[headerlen + 4 * index + 3] == 0xff) {
4070 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4071 "DCB I2C entry invalid\n");
4075 if (bios->chip_version == 0x51) {
4076 int port_type = i2ctable[headerlen + 4 * index + 3];
4079 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4080 "DCB I2C table has port type %d\n", port_type);
4082 if (i2ctable[0] >= 0x40) {
4083 int port_type = i2ctable[headerlen + 4 * index + 3];
4086 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4087 "DCB I2C table has port type %d\n", port_type);
4090 pNv->dcb_table.i2c_read[index] = i2ctable[headerlen + recordoffset + rdofs + 4 * index];
4091 pNv->dcb_table.i2c_write[index] = i2ctable[headerlen + recordoffset + wrofs + 4 * index];
4095 parse_dcb_entry(ScrnInfoPtr pScrn, int index, uint8_t dcb_version, uint16_t i2ctabptr, uint32_t conn, uint32_t conf)
4097 NVPtr pNv = NVPTR(pScrn);
4098 struct dcb_entry *entry = &pNv->dcb_table.entry[index];
4100 memset(entry, 0, sizeof (struct dcb_entry));
4102 entry->index = index;
4103 /* safe defaults for a crt */
4105 entry->i2c_index = 0;
4108 entry->location = LOC_ON_CHIP;
4110 entry->duallink_possible = false;
4112 if (dcb_version >= 0x20) {
4113 entry->type = conn & 0xf;
4114 entry->i2c_index = (conn >> 4) & 0xf;
4115 entry->heads = (conn >> 8) & 0xf;
4116 entry->bus = (conn >> 16) & 0xf;
4117 entry->location = (conn >> 20) & 0xf;
4118 entry->or = (conn >> 24) & 0xf;
4119 /* Normal entries consist of a single bit, but dual link has the
4120 * adjacent more significant bit set too
4122 if ((1 << (ffs(entry->or) - 1)) * 3 == entry->or)
4123 entry->duallink_possible = true;
4125 switch (entry->type) {
4130 entry->lvdsconf.use_straps_for_mode = true;
4131 if (dcb_version < 0x22) {
4133 /* both 0x4 and 0x8 show up in v2.0 tables; assume they mean
4134 * the same thing, which is probably wrong, but might work */
4135 if (conf & 0x4 || conf & 0x8)
4136 entry->lvdsconf.use_power_scripts = true;
4140 entry->lvdsconf.use_power_scripts = true;
4143 /* I'm bored of getting this reported; left as a reminder for someone to fix it */
4144 if (dcb_version >= 0x40) {
4145 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4146 "G80+ LVDS not initialized by driver; ignoring conf bits\n");
4149 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4150 "Unknown LVDS configuration bits, please report\n");
4151 /* cause output setting to fail, so message is seen */
4152 pNv->dcb_table.entries = 0;
4158 /* weird type that appears on g80 mobile bios; nv driver treats it as a terminator */
4161 read_dcb_i2c_entry(pScrn, dcb_version, i2ctabptr, entry->i2c_index);
4162 } else if (dcb_version >= 0x14 ) {
4163 if (conn != 0xf0003f00 && conn != 0xf2247f10 &&
4164 conn != 0xf2204001 && conn != 0xf2204301 && conn != 0xf2204311 && conn != 0xf2208001 && conn != 0xf2244001 && conn != 0xf2244301 && conn != 0xf2244311 && conn != 0xf4204011 && conn != 0xf4208011 && conn != 0xf4248011 &&
4165 conn != 0xf2045f14 && conn != 0xf2205004) {
4166 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4167 "Unknown DCB 1.4 / 1.5 entry, please report\n");
4169 /* cause output setting to fail for non-TVs, so message is seen */
4170 if ((conn & 0xf) != 0x1)
4171 pNv->dcb_table.entries = 0;
4175 /* most of the below is a "best guess" atm */
4176 entry->type = conn & 0xf;
4177 if (entry->type == 4) { /* digital */
4179 entry->type = OUTPUT_LVDS;
4181 entry->type = OUTPUT_TMDS;
4183 /* what's in bits 5-13? could be some brooktree/chrontel/philips thing, in tv case */
4184 entry->i2c_index = (conn >> 14) & 0xf;
4185 /* raw heads field is in range 0-1, so move to 1-2 */
4186 entry->heads = ((conn >> 18) & 0x7) + 1;
4187 entry->location = (conn >> 21) & 0xf;
4188 entry->bus = (conn >> 25) & 0x7;
4189 /* set or to be same as heads -- hopefully safe enough */
4190 entry->or = entry->heads;
4192 switch (entry->type) {
4194 /* this is probably buried in conn's unknown bits */
4195 entry->lvdsconf.use_power_scripts = true;
4198 /* invent a DVI-A output, by copying the fields of the DVI-D output
4199 * reported to work by math_b on an NV20(!) */
4200 memcpy(&entry[1], &entry[0], sizeof(struct dcb_entry));
4201 entry[1].index = ++index;
4202 entry[1].type = OUTPUT_ANALOG;
4203 xf86DrvMsg(pScrn->scrnIndex, X_NOTICE,
4204 "Concocting additional DCB entry for analogue encoder on DVI output\n");
4205 pNv->dcb_table.entries++;
4207 read_dcb_i2c_entry(pScrn, dcb_version, i2ctabptr, entry->i2c_index);
4208 } else if (dcb_version >= 0x12) {
4209 /* v1.2 tables normally have the same 5 entries, which are not
4210 * specific to the card, so use the defaults for a crt */
4211 /* DCB v1.2 does have an I2C table that read_dcb_i2c_table can handle, but cards
4212 * exist (seen on nv11) where the pointer to the table points to the wrong
4213 * place, so for now, we rely on the indices parsed in parse_bmp_structure
4215 entry->i2c_index = pNv->VBIOS.legacy.i2c_indices.crt;
4216 } else { /* pre DCB / v1.1 - use the safe defaults for a crt */
4217 xf86DrvMsg(pScrn->scrnIndex, X_NOTICE,
4218 "No information in BIOS output table; assuming a CRT output exists\n");
4219 entry->i2c_index = pNv->VBIOS.legacy.i2c_indices.crt;
4222 if (entry->type == OUTPUT_LVDS && pNv->VBIOS.fp.strapping != 0xff)
4223 entry->lvdsconf.use_straps_for_mode = true;
4225 pNv->dcb_table.entries++;
4230 void merge_like_dcb_entries(ScrnInfoPtr pScrn)
4232 /* DCB v2.0 lists each output combination separately.
4233 * Here we merge compatible entries to have fewer outputs, with more options
4236 NVPtr pNv = NVPTR(pScrn);
4237 int i, newentries = 0;
4239 for (i = 0; i < pNv->dcb_table.entries; i++) {
4240 struct dcb_entry *ient = &pNv->dcb_table.entry[i];
4243 for (j = i + 1; j < pNv->dcb_table.entries; j++) {
4244 struct dcb_entry *jent = &pNv->dcb_table.entry[j];
4246 if (jent->type == 100) /* already merged entry */
4249 /* merge heads field when all other fields the same */
4250 if (jent->i2c_index == ient->i2c_index && jent->type == ient->type && jent->location == ient->location && jent->or == ient->or) {
4251 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4252 "Merging DCB entries %d and %d\n", i, j);
4253 ient->heads |= jent->heads;
4254 jent->type = 100; /* dummy value */
4259 /* Compact entries merged into others out of dcb_table */
4260 for (i = 0; i < pNv->dcb_table.entries; i++) {
4261 if ( pNv->dcb_table.entry[i].type == 100 )
4264 if (newentries != i)
4265 memcpy(&pNv->dcb_table.entry[newentries], &pNv->dcb_table.entry[i], sizeof(struct dcb_entry));
4269 pNv->dcb_table.entries = newentries;
4272 static unsigned int parse_dcb_table(ScrnInfoPtr pScrn, bios_t *bios)
4274 NVPtr pNv = NVPTR(pScrn);
4275 uint16_t dcbptr, i2ctabptr = 0;
4277 uint8_t dcb_version, headerlen = 0x4, entries = MAX_NUM_DCB_ENTRIES;
4278 bool configblock = true;
4279 int recordlength = 8, confofs = 4;
4282 pNv->dcb_table.entries = 0;
4284 /* get the offset from 0x36 */
4285 dcbptr = le16_to_cpu(*(uint16_t *)&bios->data[0x36]);
4287 if (dcbptr == 0x0) {
4288 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4289 "No Display Configuration Block pointer found\n");
4290 /* this situation likely means a really old card, pre DCB, so we'll add the safe CRT entry */
4291 parse_dcb_entry(pScrn, 0, 0, 0, 0, 0);
4295 dcbtable = &bios->data[dcbptr];
4297 /* get DCB version */
4298 dcb_version = dcbtable[0];
4299 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4300 "Found Display Configuration Block version %d.%d\n",
4301 dcb_version >> 4, dcb_version & 0xf);
4303 if (dcb_version >= 0x20) { /* NV17+ */
4306 if (dcb_version >= 0x30) { /* NV40+ */
4307 headerlen = dcbtable[1];
4308 entries = dcbtable[2];
4309 recordlength = dcbtable[3];
4310 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[4]);
4311 sig = le32_to_cpu(*(uint32_t *)&dcbtable[6]);
4313 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
4314 sig = le32_to_cpu(*(uint32_t *)&dcbtable[4]);
4318 if (sig != 0x4edcbdcb) {
4319 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4320 "Bad Display Configuration Block signature (%08X)\n", sig);
4323 } else if (dcb_version >= 0x14) { /* some NV15/16, and NV11+ */
4324 char sig[8] = { 0 };
4326 strncpy(sig, (char *)&dcbtable[-7], 7);
4327 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
4331 if (strcmp(sig, "DEV_REC")) {
4332 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4333 "Bad Display Configuration Block signature (%s)\n", sig);
4336 } else if (dcb_version >= 0x12) { /* some NV6/10, and NV15+ */
4337 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
4338 configblock = false;
4339 } else { /* NV5+, maybe NV4 */
4340 /* DCB 1.1 seems to be quite unhelpful - we'll just add the safe CRT entry */
4341 parse_dcb_entry(pScrn, 0, dcb_version, 0, 0, 0);
4345 if (entries >= MAX_NUM_DCB_ENTRIES)
4346 entries = MAX_NUM_DCB_ENTRIES;
4348 for (i = 0; i < entries; i++) {
4349 uint32_t connection, config = 0;
4351 connection = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + recordlength * i]);
4353 config = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + confofs + recordlength * i]);
4355 /* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
4356 if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
4358 if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */
4361 xf86DrvMsg(pScrn->scrnIndex, X_NOTICE, "Raw DCB entry %d: %08x %08x\n",
4362 pNv->dcb_table.entries, connection, config);
4364 if (!parse_dcb_entry(pScrn, pNv->dcb_table.entries, dcb_version, i2ctabptr, connection, config))
4368 merge_like_dcb_entries(pScrn);
4370 return pNv->dcb_table.entries;
4373 static void load_nv17_hw_sequencer_ucode(ScrnInfoPtr pScrn, bios_t *bios, uint16_t hwsq_offset, int entry)
4375 /* BMP based cards, from NV17, need a microcode loading to correctly
4376 * control the GPIO etc for LVDS panels
4378 * BIT based cards seem to do this directly in the init scripts
4380 * The microcode entries are found by the "HWSQ" signature.
4381 * The header following has the number of entries, and the entry size
4383 * An entry consists of a dword to write to the sequencer control reg
4384 * (0x00001304), followed by the ucode bytes, written sequentially,
4385 * starting at reg 0x00001400
4388 uint8_t bytes_to_write;
4389 uint16_t hwsq_entry_offset;
4392 if (bios->data[hwsq_offset] <= entry) {
4393 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4394 "Too few entries in HW sequencer table for requested entry\n");
4398 bytes_to_write = bios->data[hwsq_offset + 1];
4400 if (bytes_to_write != 36) {
4401 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unknown HW sequencer entry size\n");
4405 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Loading NV17 power sequencing microcode\n");
4407 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
4409 /* set sequencer control */
4410 nv32_wr(pScrn, 0x00001304, le32_to_cpu(*(uint32_t *)&bios->data[hwsq_entry_offset]));
4411 bytes_to_write -= 4;
4414 for (i = 0; i < bytes_to_write; i += 4)
4415 nv32_wr(pScrn, 0x00001400 + i, le32_to_cpu(*(uint32_t *)&bios->data[hwsq_entry_offset + i + 4]));
4417 /* twiddle NV_PBUS_DEBUG_4 */
4418 nv32_wr(pScrn, NV_PBUS_DEBUG_4, nv32_rd(pScrn, NV_PBUS_DEBUG_4) | 0x18);
4421 static void read_bios_edid(ScrnInfoPtr pScrn)
4423 bios_t *bios = &NVPTR(pScrn)->VBIOS;
4424 const uint8_t edid_sig[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
4425 uint16_t offset = 0, newoffset;
4426 int searchlen = NV_PROM_SIZE, i;
4429 if (!(newoffset = findstr(&bios->data[offset], searchlen, edid_sig, 8)))
4431 offset += newoffset;
4432 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
4435 searchlen -= offset;
4439 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found EDID in BIOS\n");
4441 if (!(bios->fp.edid = xalloc(EDID1_LEN)))
4443 for (i = 0; i < EDID1_LEN; i++)
4444 bios->fp.edid[i] = bios->data[offset + i];
4447 bool NVInitVBIOS(ScrnInfoPtr pScrn)
4449 NVPtr pNv = NVPTR(pScrn);
4451 memset(&pNv->VBIOS, 0, sizeof(bios_t));
4452 if (!(pNv->VBIOS.data = xalloc(NV_PROM_SIZE)))
4455 if (!NVShadowVBIOS(pScrn, pNv->VBIOS.data)) {
4456 xfree(pNv->VBIOS.data);
4460 pNv->VBIOS.length = pNv->VBIOS.data[2] * 512;
4461 if (pNv->VBIOS.length > NV_PROM_SIZE)
4462 pNv->VBIOS.length = NV_PROM_SIZE;
4467 bool NVRunVBIOSInit(ScrnInfoPtr pScrn)
4469 NVPtr pNv = NVPTR(pScrn);
4470 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
4471 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
4472 int offset, ret = 0;
4474 crtc_access(pNv, ACCESS_UNLOCK);
4476 if ((offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, bit_signature, sizeof(bit_signature)))) {
4477 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIT BIOS found\n");
4478 parse_bit_structure(pScrn, &pNv->VBIOS, offset + 6);
4479 } else if ((offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, bmp_signature, sizeof(bmp_signature)))) {
4480 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
4483 if ((hwsq_offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, hwsq_signature, sizeof(hwsq_signature))))
4484 /* always use entry 0? */
4485 load_nv17_hw_sequencer_ucode(pScrn, &pNv->VBIOS, hwsq_offset + sizeof(hwsq_signature), 0);
4487 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BMP BIOS found\n");
4488 parse_bmp_structure(pScrn, &pNv->VBIOS, offset);
4490 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4491 "No known BIOS signature found\n");
4495 crtc_access(pNv, ACCESS_LOCK);
4503 unsigned int NVParseBios(ScrnInfoPtr pScrn)
4505 NVPtr pNv = NVPTR(pScrn);
4506 uint32_t saved_nv_pextdev_boot_0;
4509 if (!NVInitVBIOS(pScrn))
4512 /* these will need remembering across a suspend */
4513 saved_nv_pextdev_boot_0 = nv32_rd(pScrn, NV_PEXTDEV_BOOT_0);
4514 saved_nv_pfb_cfg0 = nv32_rd(pScrn, NV_PFB_CFG0);
4516 /* init script execution disabled */
4517 pNv->VBIOS.execute = false;
4519 nv32_wr(pScrn, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
4521 if (!NVRunVBIOSInit(pScrn))
4524 parse_dcb_table(pScrn, &pNv->VBIOS);
4526 for (i = 0 ; i < pNv->dcb_table.entries; i++)
4527 if (pNv->dcb_table.entry[i].type == OUTPUT_LVDS)
4528 call_lvds_script(pScrn, &pNv->dcb_table.entry[i], nv_get_digital_bound_head(pNv, pNv->dcb_table.entry[i].or), LVDS_INIT, 0);
4530 if (pNv->VBIOS.feature_byte & FEATURE_MOBILE && !pNv->VBIOS.fp.native_mode)
4531 read_bios_edid(pScrn);
4533 /* allow subsequent scripts to execute */
4534 pNv->VBIOS.execute = true;