2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 #include "nv_include.h"
28 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
29 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
30 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
31 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
32 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
33 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
34 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
35 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
37 static uint32_t NVCrtcReadCRTC(xf86CrtcPtr crtc, uint32_t reg)
39 ScrnInfoPtr pScrn = crtc->scrn;
40 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
41 NVPtr pNv = NVPTR(pScrn);
43 return NVReadCRTC(pNv, nv_crtc->head, reg);
46 static void NVCrtcWriteCRTC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
48 ScrnInfoPtr pScrn = crtc->scrn;
49 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
50 NVPtr pNv = NVPTR(pScrn);
52 NVWriteCRTC(pNv, nv_crtc->head, reg, val);
55 static uint32_t NVCrtcReadRAMDAC(xf86CrtcPtr crtc, uint32_t reg)
57 ScrnInfoPtr pScrn = crtc->scrn;
58 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
59 NVPtr pNv = NVPTR(pScrn);
61 return NVReadRAMDAC(pNv, nv_crtc->head, reg);
64 static void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
66 ScrnInfoPtr pScrn = crtc->scrn;
67 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
68 NVPtr pNv = NVPTR(pScrn);
70 NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
73 void NVCrtcLockUnlock(xf86CrtcPtr crtc, bool lock)
75 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
76 NVPtr pNv = NVPTR(crtc->scrn);
79 NVSetOwner(pNv, nv_crtc->head);
80 NVLockVgaCrtc(pNv, nv_crtc->head, lock);
83 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
84 /* They are only valid for NV4x, appearantly reordered for NV5x */
85 /* gpu pll: 0x4000 + 0x4004
86 * unknown pll: 0x4008 + 0x400c
87 * vpll1: 0x4010 + 0x4014
88 * vpll2: 0x4018 + 0x401c
89 * unknown pll: 0x4020 + 0x4024
90 * unknown pll: 0x4038 + 0x403c
91 * Some of the unknown's are probably memory pll's.
92 * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
93 * 1 and 2 refer to the registers of each pair. There is only one post divider.
94 * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
95 * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
96 * bit8: A switch that turns of the second divider and multiplier off.
97 * bit12: Also a switch, i haven't seen it yet.
99 * but 28-31: Something related to the mode that is used (see bit8).
100 * 2) bit0-7: m-divider (a)
101 * bit8-15: n-multiplier (a)
102 * bit16-23: m-divider (b)
103 * bit24-31: n-multiplier (b)
106 /* Modifying the gpu pll for example requires:
107 * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
108 * This is not needed for the vpll's which have their own bits.
111 static void nv_crtc_save_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
113 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
114 NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
115 NVPtr pNv = NVPTR(crtc->scrn);
118 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
119 if (pNv->twoStagePLL)
120 regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
122 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
123 if (pNv->twoStagePLL)
124 regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
127 state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
128 state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
129 if (pNv->Architecture == NV_ARCH_40)
130 state->reg580 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_580);
133 static void nv_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
135 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
136 NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
137 ScrnInfoPtr pScrn = crtc->scrn;
138 NVPtr pNv = NVPTR(pScrn);
139 uint32_t savedc040 = 0;
141 /* This sequence is important, the NV28 is very sensitive in this area. */
142 /* Keep pllsel last and sel_clk first. */
144 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
146 if (pNv->Architecture == NV_ARCH_40) {
147 savedc040 = nvReadMC(pNv, 0xc040);
149 /* for vpll1 change bits 16 and 17 are disabled */
150 /* for vpll2 change bits 18 and 19 are disabled */
151 nvWriteMC(pNv, 0xc040, savedc040 & ~(3 << (16 + nv_crtc->head * 2)));
155 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, regp->vpll_a);
156 if (pNv->twoStagePLL)
157 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, regp->vpll_b);
159 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, regp->vpll_a);
160 if (pNv->twoStagePLL)
161 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, regp->vpll_b);
164 if (pNv->Architecture == NV_ARCH_40) {
165 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
167 /* We need to wait a while */
169 nvWriteMC(pNv, 0xc040, savedc040);
172 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_PLL_SELECT %08X\n", state->pllsel);
173 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
176 static void nv_crtc_cursor_set(xf86CrtcPtr crtc)
178 NVPtr pNv = NVPTR(crtc->scrn);
179 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
180 uint32_t cursor_start;
181 uint8_t *CRTC = pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC;
183 if (pNv->Architecture == NV_ARCH_04)
184 cursor_start = 0x5E00 << 2;
186 cursor_start = nv_crtc->head ? pNv->Cursor2->offset : pNv->Cursor->offset;
188 CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = cursor_start >> 17;
189 if (pNv->Architecture != NV_ARCH_04)
190 CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] |= 0x80;
191 CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = (cursor_start >> 11) << 2;
192 if (crtc->mode.Flags & V_DBLSCAN)
193 CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= 2;
194 CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = cursor_start >> 24;
196 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX, CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX]);
197 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX, CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]);
198 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX, CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX]);
199 if (pNv->Architecture == NV_ARCH_40)
200 nv_fix_nv40_hw_cursor(pNv, nv_crtc->head);
203 static void nv_crtc_calc_state_ext(xf86CrtcPtr crtc, DisplayModePtr mode, int dot_clock)
205 ScrnInfoPtr pScrn = crtc->scrn;
206 NVPtr pNv = NVPTR(pScrn);
207 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
208 RIVA_HW_STATE *state = &pNv->ModeReg;
209 NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
210 struct pll_lims pll_lim;
211 int NM1 = 0xbeef, NM2 = 0, log2P = 0, VClk = 0;
212 uint32_t g70_pll_special_bits = 0;
213 bool nv4x_single_stage_pll_mode = false;
214 uint8_t arbitration0;
215 uint16_t arbitration1;
217 if (!get_pll_limits(pScrn, nv_crtc->head ? VPLL2 : VPLL1, &pll_lim))
220 if (pNv->twoStagePLL || pNv->NVArch == 0x30 || pNv->NVArch == 0x35) {
221 if (dot_clock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* use a single VCO */
222 nv4x_single_stage_pll_mode = true;
223 /* Turn the second set of divider and multiplier off */
224 /* Bogus data, the same nvidia uses */
226 VClk = getMNP_single(pScrn, &pll_lim, dot_clock, &NM1, &log2P);
228 VClk = getMNP_double(pScrn, &pll_lim, dot_clock, &NM1, &NM2, &log2P);
230 VClk = getMNP_single(pScrn, &pll_lim, dot_clock, &NM1, &log2P);
232 /* Are these all the (relevant) G70 cards? */
233 if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
234 /* This is a big guess, but should be reasonable until we can narrow it down. */
235 /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
236 if (nv4x_single_stage_pll_mode)
237 g70_pll_special_bits = 0x1;
239 g70_pll_special_bits = 0x3;
242 if (pNv->NVArch == 0x30 || pNv->NVArch == 0x35)
243 /* See nvregisters.xml for details. */
244 regp->vpll_a = (NM2 & (0x18 << 8)) << 13 | (NM2 & (0x7 << 8)) << 11 | log2P << 16 | NV30_RAMDAC_ENABLE_VCO2 | (NM2 & 7) << 4 | NM1;
246 regp->vpll_a = g70_pll_special_bits << 30 | log2P << 16 | NM1;
247 regp->vpll_b = NV31_RAMDAC_ENABLE_VCO2 | NM2;
249 if (nv4x_single_stage_pll_mode) {
250 if (nv_crtc->head == 0)
251 state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
253 state->reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
255 if (nv_crtc->head == 0)
256 state->reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
258 state->reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
261 /* The NV40 seems to have more similarities to NV3x than other NV4x */
262 if (pNv->NVArch < 0x41)
263 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL |
264 NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
265 /* The blob uses this always, so let's do the same */
266 if (pNv->Architecture == NV_ARCH_40)
267 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
269 if (nv_crtc->head == 1) {
270 if (!nv4x_single_stage_pll_mode)
271 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
273 state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
274 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
276 if (!nv4x_single_stage_pll_mode)
277 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
279 state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
280 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
283 if ((!pNv->twoStagePLL && pNv->NVArch != 0x30 && pNv->NVArch != 0x35) || nv4x_single_stage_pll_mode)
284 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n %d m %d log2p %d\n", NM1 >> 8, NM1 & 0xff, log2P);
286 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P);
288 if (pNv->Architecture < NV_ARCH_30)
289 nv4_10UpdateArbitrationSettings(pScrn, VClk, pScrn->bitsPerPixel, &arbitration0, &arbitration1);
290 else if ((pNv->Chipset & 0xfff0) == CHIPSET_C51 ||
291 (pNv->Chipset & 0xfff0) == CHIPSET_C512) {
293 arbitration1 = 0x0480;
295 nv30UpdateArbitrationSettings(&arbitration0, &arbitration1);
297 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arbitration0;
298 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arbitration1 & 0xff;
299 if (pNv->Architecture >= NV_ARCH_30)
300 regp->CRTC[NV_CIO_CRE_47] = arbitration1 >> 8;
302 nv_crtc_cursor_set(crtc);
306 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
308 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
309 ScrnInfoPtr pScrn = crtc->scrn;
310 NVPtr pNv = NVPTR(pScrn);
311 unsigned char seq1 = 0, crtc17 = 0;
312 unsigned char crtc1A;
314 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting dpms mode %d on CRTC %d\n", mode, nv_crtc->head);
316 if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
319 nv_crtc->last_dpms = mode;
322 NVSetOwner(pNv, nv_crtc->head);
324 crtc1A = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX) & ~0xC0;
326 case DPMSModeStandby:
327 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
332 case DPMSModeSuspend:
333 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
339 /* Screen: Off; HSync: Off, VSync: Off */
346 /* Screen: On; HSync: On, VSync: On */
352 NVVgaSeqReset(pNv, nv_crtc->head, true);
353 /* Each head has it's own sequencer, so we can turn it off when we want */
354 seq1 |= (NVReadVgaSeq(pNv, nv_crtc->head, 0x01) & ~0x20);
355 NVWriteVgaSeq(pNv, nv_crtc->head, 0x1, seq1);
356 crtc17 |= (NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_MODE_INDEX) & ~0x80);
358 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_MODE_INDEX, crtc17);
359 NVVgaSeqReset(pNv, nv_crtc->head, false);
361 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX, crtc1A);
365 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
366 DisplayModePtr adjusted_mode)
372 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
374 ScrnInfoPtr pScrn = crtc->scrn;
375 NVPtr pNv = NVPTR(pScrn);
376 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
377 NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
379 /* Calculate our timings */
380 int horizDisplay = (mode->CrtcHDisplay >> 3) - 1;
381 int horizStart = (mode->CrtcHSyncStart >> 3) - 1;
382 int horizEnd = (mode->CrtcHSyncEnd >> 3) - 1;
383 int horizTotal = (mode->CrtcHTotal >> 3) - 5;
384 int horizBlankStart = (mode->CrtcHDisplay >> 3) - 1;
385 int horizBlankEnd = (mode->CrtcHTotal >> 3) - 1;
386 int vertDisplay = mode->CrtcVDisplay - 1;
387 int vertStart = mode->CrtcVSyncStart - 1;
388 int vertEnd = mode->CrtcVSyncEnd - 1;
389 int vertTotal = mode->CrtcVTotal - 2;
390 int vertBlankStart = mode->CrtcVDisplay - 1;
391 int vertBlankEnd = mode->CrtcVTotal - 1;
393 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
394 bool fp_output = false;
397 for (i = 0; i < xf86_config->num_output; i++) {
398 xf86OutputPtr output = xf86_config->output[i];
399 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
401 if (output->crtc == crtc && (nv_encoder->dcb->type == OUTPUT_LVDS ||
402 nv_encoder->dcb->type == OUTPUT_TMDS))
407 vertStart = vertTotal - 3;
408 vertEnd = vertTotal - 2;
409 vertBlankStart = vertStart;
410 horizStart = horizTotal - 5;
411 horizEnd = horizTotal - 2;
412 horizBlankEnd = horizTotal + 4;
413 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10)
414 /* This reportedly works around some video overlay bandwidth problems */
418 if (mode->Flags & V_INTERLACE)
422 ErrorF("horizDisplay: 0x%X \n", horizDisplay);
423 ErrorF("horizStart: 0x%X \n", horizStart);
424 ErrorF("horizEnd: 0x%X \n", horizEnd);
425 ErrorF("horizTotal: 0x%X \n", horizTotal);
426 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
427 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
428 ErrorF("vertDisplay: 0x%X \n", vertDisplay);
429 ErrorF("vertStart: 0x%X \n", vertStart);
430 ErrorF("vertEnd: 0x%X \n", vertEnd);
431 ErrorF("vertTotal: 0x%X \n", vertTotal);
432 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
433 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
437 * compute correct Hsync & Vsync polarity
439 if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
440 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
442 regp->MiscOutReg = 0x23;
443 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
444 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
446 int VDisplay = mode->VDisplay;
447 if (mode->Flags & V_DBLSCAN)
450 VDisplay *= mode->VScan;
452 regp->MiscOutReg = 0xA3; /* +hsync -vsync */
453 else if (VDisplay < 480)
454 regp->MiscOutReg = 0x63; /* -hsync +vsync */
455 else if (VDisplay < 768)
456 regp->MiscOutReg = 0xE3; /* -hsync -vsync */
458 regp->MiscOutReg = 0x23; /* +hsync +vsync */
461 regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
466 regp->Sequencer[0] = 0x00;
467 /* 0x20 disables the sequencer */
468 if (mode->Flags & V_CLKDIV2)
469 regp->Sequencer[1] = 0x29;
471 regp->Sequencer[1] = 0x21;
472 regp->Sequencer[2] = 0x0F;
473 regp->Sequencer[3] = 0x00; /* Font select */
474 regp->Sequencer[4] = 0x0E; /* Misc */
479 regp->CRTC[NV_CIO_CR_HDT_INDEX] = Set8Bits(horizTotal);
480 regp->CRTC[NV_CIO_CR_HDE_INDEX] = Set8Bits(horizDisplay);
481 regp->CRTC[NV_CIO_CR_HBS_INDEX] = Set8Bits(horizBlankStart);
482 regp->CRTC[NV_CIO_CR_HBE_INDEX] = SetBitField(horizBlankEnd,4:0,4:0)
484 regp->CRTC[NV_CIO_CR_HRS_INDEX] = Set8Bits(horizStart);
485 regp->CRTC[NV_CIO_CR_HRE_INDEX] = SetBitField(horizBlankEnd,5:5,7:7)
486 | SetBitField(horizEnd,4:0,4:0);
487 regp->CRTC[NV_CIO_CR_VDT_INDEX] = SetBitField(vertTotal,7:0,7:0);
488 regp->CRTC[NV_CIO_CR_OVL_INDEX] = SetBitField(vertTotal,8:8,0:0)
489 | SetBitField(vertDisplay,8:8,1:1)
490 | SetBitField(vertStart,8:8,2:2)
491 | SetBitField(vertBlankStart,8:8,3:3)
493 | SetBitField(vertTotal,9:9,5:5)
494 | SetBitField(vertDisplay,9:9,6:6)
495 | SetBitField(vertStart,9:9,7:7);
496 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00;
497 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = SetBitField(vertBlankStart,9:9,5:5)
499 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
500 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
501 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
502 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
503 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
504 regp->CRTC[0xe] = 0x00;
505 regp->CRTC[0xf] = 0x00;
506 regp->CRTC[NV_CIO_CR_VRS_INDEX] = Set8Bits(vertStart);
507 /* What is the meaning of bit5, it is empty in the vga spec. */
508 regp->CRTC[NV_CIO_CR_VRE_INDEX] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
509 regp->CRTC[NV_CIO_CR_VDE_INDEX] = Set8Bits(vertDisplay);
510 /* framebuffer can be larger than crtc scanout area. */
511 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8;
512 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
513 regp->CRTC[NV_CIO_CR_VBS_INDEX] = Set8Bits(vertBlankStart);
514 regp->CRTC[NV_CIO_CR_VBE_INDEX] = Set8Bits(vertBlankEnd);
515 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
516 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
519 * Some extended CRTC registers (they are not saved with the rest of the vga regs).
522 /* framebuffer can be larger than crtc scanout area. */
523 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = ((pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8) & 0x700) >> 3;
524 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->CrtcHDisplay < 1280 ? 0x04 : 0x00;
525 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = SetBitField(horizBlankEnd,6:6,4:4)
526 | SetBitField(vertBlankStart,10:10,3:3)
527 | SetBitField(vertStart,10:10,2:2)
528 | SetBitField(vertDisplay,10:10,1:1)
529 | SetBitField(vertTotal,10:10,0:0);
531 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = SetBitField(horizTotal,8:8,0:0)
532 | SetBitField(horizDisplay,8:8,1:1)
533 | SetBitField(horizBlankStart,8:8,2:2)
534 | SetBitField(horizStart,8:8,3:3);
536 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = SetBitField(vertTotal,11:11,0:0)
537 | SetBitField(vertDisplay,11:11,2:2)
538 | SetBitField(vertStart,11:11,4:4)
539 | SetBitField(vertBlankStart,11:11,6:6);
541 if(mode->Flags & V_INTERLACE) {
542 horizTotal = (horizTotal >> 1) & ~1;
543 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = Set8Bits(horizTotal);
544 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= SetBitField(horizTotal,8:8,4:4);
546 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */
549 * Graphics Display Controller
551 regp->Graphics[0] = 0x00;
552 regp->Graphics[1] = 0x00;
553 regp->Graphics[2] = 0x00;
554 regp->Graphics[3] = 0x00;
555 regp->Graphics[4] = 0x00;
556 regp->Graphics[5] = 0x40; /* 256 color mode */
557 regp->Graphics[6] = 0x05; /* map 64k mem + graphic mode */
558 regp->Graphics[7] = 0x0F;
559 regp->Graphics[8] = 0xFF;
561 regp->Attribute[0] = 0x00; /* standard colormap translation */
562 regp->Attribute[1] = 0x01;
563 regp->Attribute[2] = 0x02;
564 regp->Attribute[3] = 0x03;
565 regp->Attribute[4] = 0x04;
566 regp->Attribute[5] = 0x05;
567 regp->Attribute[6] = 0x06;
568 regp->Attribute[7] = 0x07;
569 regp->Attribute[8] = 0x08;
570 regp->Attribute[9] = 0x09;
571 regp->Attribute[10] = 0x0A;
572 regp->Attribute[11] = 0x0B;
573 regp->Attribute[12] = 0x0C;
574 regp->Attribute[13] = 0x0D;
575 regp->Attribute[14] = 0x0E;
576 regp->Attribute[15] = 0x0F;
577 regp->Attribute[16] = 0x01; /* Enable graphic mode */
579 regp->Attribute[17] = 0x00;
580 regp->Attribute[18] = 0x0F; /* enable all color planes */
581 regp->Attribute[19] = 0x00;
582 regp->Attribute[20] = 0x00;
586 * Sets up registers for the given mode/adjusted_mode pair.
588 * The clocks, CRTCs and outputs attached to this CRTC must be off.
590 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
591 * be easily turned on/off after this.
594 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode)
596 ScrnInfoPtr pScrn = crtc->scrn;
597 NVPtr pNv = NVPTR(pScrn);
598 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
599 NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
600 NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
601 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
602 bool lvds_output = false, tmds_output = false;
605 for (i = 0; i < xf86_config->num_output; i++) {
606 xf86OutputPtr output = xf86_config->output[i];
607 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
609 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_LVDS)
611 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_TMDS)
615 /* Registers not directly related to the (s)vga mode */
617 /* bit2 = 0 -> fine pitched crtc granularity */
618 /* The rest disables double buffering on CRTC access */
619 regp->CRTC[NV_CIO_CRE_21] = 0xfa;
621 /* the blob sometimes sets |= 0x10 (which is the same as setting |=
622 * 1 << 30 on 0x60.830), for no apparent reason */
623 regp->CRTC[NV_CIO_CRE_59] = 0x0;
624 if (tmds_output && pNv->Architecture < NV_ARCH_40)
625 regp->CRTC[NV_CIO_CRE_59] |= 0x1;
627 /* What is the meaning of this register? */
628 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
629 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
632 /* Except for rare conditions I2C is enabled on the primary crtc */
633 if (nv_crtc->head == 0)
634 regp->head |= NV_CRTC_FSEL_I2C;
635 /* Set overlay to desired crtc. */
636 if (pNv->overlayAdaptor) {
637 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
638 if (pPriv->overlayCRTC == nv_crtc->head)
639 regp->head |= NV_CRTC_FSEL_OVERLAY;
642 /* This is not what nv does, but it is what the blob does (for nv4x at least) */
643 /* This fixes my cursor corruption issue */
644 regp->cursorConfig = 0x0;
645 if(mode->Flags & V_DBLSCAN)
646 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
647 if (pNv->alphaCursor) {
648 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32BPP |
649 NV_CRTC_CURSOR_CONFIG_64PIXELS |
650 NV_CRTC_CURSOR_CONFIG_64LINES |
651 NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND;
653 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES;
655 /* Unblock some timings */
656 regp->CRTC[NV_CIO_CRE_53] = 0;
657 regp->CRTC[NV_CIO_CRE_54] = 0;
659 /* What is the purpose of this register? */
660 /* 0x14 may be disabled? */
661 regp->CRTC[NV_CIO_CR_ARX_INDEX] = 0x20;
663 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
665 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
666 else if (tmds_output)
667 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
669 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
671 /* These values seem to vary */
672 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
673 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
675 regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
677 /* What does this do?:
682 if (nv_crtc->head == 0)
683 regp->CRTC[NV_CIO_CRE_4B] = 0x81;
685 regp->CRTC[NV_CIO_CRE_4B] = 0x80;
688 regp->CRTC[NV_CIO_CRE_4B] |= 0x40;
690 /* The blob seems to take the current value from crtc 0, add 4 to that
691 * and reuse the old value for crtc 1 */
692 regp->CRTC[NV_CIO_CRE_52] = pNv->SavedReg.crtc_reg[0].CRTC[NV_CIO_CRE_52];
694 regp->CRTC[NV_CIO_CRE_52] += 4;
696 regp->unk830 = mode->CrtcVDisplay - 3;
697 regp->unk834 = mode->CrtcVDisplay - 1;
700 /* This is what the blob does */
701 regp->unk850 = NVReadCRTC(pNv, 0, NV_CRTC_0850);
703 /* Never ever modify gpio, unless you know very well what you're doing */
704 regp->gpio = NVReadCRTC(pNv, 0, NV_CRTC_GPIO);
707 regp->gpio_ext = NVReadCRTC(pNv, 0, NV_CRTC_GPIO_EXT);
709 regp->config = 0x2; /* HSYNC mode */
712 if (pNv->Architecture == NV_ARCH_40) {
713 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
714 regp->CRTC[NV_CIO_CRE_86] = 0x1;
717 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (pScrn->depth + 1) / 8;
718 /* Enable slaved mode */
719 if (lvds_output || tmds_output)
720 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
722 /* Generic PRAMDAC regs */
724 if (pNv->Architecture >= NV_ARCH_10)
725 /* Only bit that bios and blob set. */
726 regp->nv10_cursync = (1 << 25);
728 switch (pScrn->depth) {
731 regp->general = 0x00100130;
735 regp->general = 0x00101130;
738 if (pNv->alphaCursor)
739 /* PIPE_LONG mode, something to do with the size of the cursor? */
740 regp->general |= 1 << 29;
742 regp->unk_630 = 0; /* turn off green mode (tv test pattern?) */
744 /* Some values the blob sets */
746 regp->unk_a24 = 0xfffff;
750 /* this could be set in nv_output, but would require some rework of load/save */
752 nv_crtc_mode_set_fp_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
754 ScrnInfoPtr pScrn = crtc->scrn;
755 NVPtr pNv = NVPTR(pScrn);
756 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
757 NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
758 NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
759 struct nouveau_encoder *nv_encoder = NULL;
760 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
762 bool is_lvds = false;
763 uint32_t mode_ratio, panel_ratio;
766 for (i = 0; i < xf86_config->num_output; i++) {
767 xf86OutputPtr output = xf86_config->output[i];
768 /* assuming one fp output per crtc seems ok */
769 nv_encoder = to_nouveau_encoder(output);
771 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_LVDS)
773 if (is_lvds || (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_TMDS)) {
781 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
782 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
783 if ((adjusted_mode->HSyncStart - adjusted_mode->HDisplay) >= pNv->VBIOS.digital_min_front_porch)
784 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
786 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - pNv->VBIOS.digital_min_front_porch - 1;
787 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
788 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
789 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
790 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
792 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
793 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
794 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
795 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
796 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
797 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
798 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
801 * bit0: positive vsync
802 * bit4: positive hsync
803 * bit8: enable center mode
804 * bit9: enable native mode
805 * bit24: 12/24 bit interface (12bit=on, 24bit=off)
806 * bit26: a bit sometimes seen on some g70 cards
807 * bit28: fp display enable bit
808 * bit31: set for dual link LVDS
811 regp->fp_control = (savep->fp_control & 0x04100000) |
812 NV_RAMDAC_FP_CONTROL_DISPEN_POS;
814 /* Deal with vsync/hsync polarity */
815 /* LVDS screens do set this, but modes with +ve syncs are very rare */
816 if (adjusted_mode->Flags & V_PVSYNC)
817 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
818 if (adjusted_mode->Flags & V_PHSYNC)
819 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
821 if (nv_encoder->scaling_mode == SCALE_PANEL ||
822 nv_encoder->scaling_mode == SCALE_NOSCALE) /* panel needs to scale */
823 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
824 /* This is also true for panel scaling, so we must put the panel scale check first */
825 else if (mode->HDisplay == adjusted_mode->HDisplay &&
826 mode->VDisplay == adjusted_mode->VDisplay) /* native mode */
827 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
828 else /* gpu needs to scale */
829 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
831 if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
832 regp->fp_control |= NV_RAMDAC_FP_CONTROL_WIDTH_12;
834 if (is_lvds && pNv->VBIOS.fp.dual_link)
835 regp->fp_control |= (8 << 28);
837 /* Use the generic value, and enable x-scaling, y-scaling, and the TMDS enable bit */
838 regp->debug_0 = 0x01101191;
839 /* We want automatic scaling */
841 /* This can override HTOTAL and VTOTAL */
844 /* Use 20.12 fixed point format to avoid floats */
845 mode_ratio = (1 << 12) * mode->HDisplay / mode->VDisplay;
846 panel_ratio = (1 << 12) * adjusted_mode->HDisplay / adjusted_mode->VDisplay;
847 /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
848 * get treated the same as SCALE_FULLSCREEN */
849 if (nv_encoder->scaling_mode == SCALE_ASPECT && mode_ratio != panel_ratio) {
850 uint32_t diff, scale;
852 if (mode_ratio < panel_ratio) {
853 /* vertical needs to expand to glass size (automatic)
854 * horizontal needs to be scaled at vertical scale factor
855 * to maintain aspect */
857 scale = (1 << 12) * mode->VDisplay / adjusted_mode->VDisplay;
858 regp->debug_1 = 1 << 12 | ((scale >> 1) & 0xfff);
860 /* restrict area of screen used, horizontally */
861 diff = adjusted_mode->HDisplay -
862 adjusted_mode->VDisplay * mode_ratio / (1 << 12);
863 regp->fp_horiz_regs[REG_DISP_VALID_START] += diff / 2;
864 regp->fp_horiz_regs[REG_DISP_VALID_END] -= diff / 2;
867 if (mode_ratio > panel_ratio) {
868 /* horizontal needs to expand to glass size (automatic)
869 * vertical needs to be scaled at horizontal scale factor
870 * to maintain aspect */
872 scale = (1 << 12) * mode->HDisplay / adjusted_mode->HDisplay;
873 regp->debug_1 = 1 << 28 | ((scale >> 1) & 0xfff) << 16;
875 /* restrict area of screen used, vertically */
876 diff = adjusted_mode->VDisplay -
877 (1 << 12) * adjusted_mode->HDisplay / mode_ratio;
878 regp->fp_vert_regs[REG_DISP_VALID_START] += diff / 2;
879 regp->fp_vert_regs[REG_DISP_VALID_END] -= diff / 2;
883 /* Flatpanel support needs at least a NV10 */
885 /* Output property. */
886 if (nv_encoder && nv_encoder->dithering) {
887 if (pNv->NVArch == 0x11)
888 regp->dither = savep->dither | 0x00010000;
891 regp->dither = savep->dither | 0x00000001;
892 for (i = 0; i < 3; i++) {
893 regp->dither_regs[i] = 0xe4e4e4e4;
894 regp->dither_regs[i + 3] = 0x44444444;
898 if (pNv->NVArch != 0x11) {
901 for (i = 0; i < 3; i++) {
902 regp->dither_regs[i] = savep->dither_regs[i];
903 regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
906 regp->dither = savep->dither;
909 regp->dither = savep->dither;
913 * Sets up registers for the given mode/adjusted_mode pair.
915 * The clocks, CRTCs and outputs attached to this CRTC must be off.
917 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
918 * be easily turned on/off after this.
921 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
922 DisplayModePtr adjusted_mode,
925 ScrnInfoPtr pScrn = crtc->scrn;
926 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
927 NVPtr pNv = NVPTR(pScrn);
929 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CTRC mode on CRTC %d:\n", nv_crtc->head);
930 xf86PrintModeline(pScrn->scrnIndex, mode);
931 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Output mode on CRTC %d:\n", nv_crtc->head);
932 xf86PrintModeline(pScrn->scrnIndex, adjusted_mode);
935 NVSetOwner(pNv, nv_crtc->head);
937 nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
939 /* calculated in output_prepare, nv40 needs it written before calculating PLLs */
940 if (pNv->Architecture == NV_ARCH_40)
941 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
942 nv_crtc_mode_set_regs(crtc, mode);
943 nv_crtc_mode_set_fp_regs(crtc, mode, adjusted_mode);
944 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->Clock);
946 NVVgaProtect(pNv, nv_crtc->head, true);
947 nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
948 nv_crtc_load_state_ext(crtc, &pNv->ModeReg);
949 nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
950 nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
951 nv_crtc_load_state_pll(crtc, &pNv->ModeReg);
953 NVVgaProtect(pNv, nv_crtc->head, false);
955 NVCrtcSetBase(crtc, x, y);
957 #if X_BYTE_ORDER == X_BIG_ENDIAN
958 /* turn on LFB swapping */
962 tmp = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RCR);
964 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RCR, tmp);
969 static void nv_crtc_save(xf86CrtcPtr crtc)
971 ScrnInfoPtr pScrn = crtc->scrn;
972 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
973 NVPtr pNv = NVPTR(pScrn);
975 /* We just came back from terminal, so unlock */
976 NVCrtcLockUnlock(crtc, false);
978 nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
979 nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
980 nv_crtc_save_state_palette(crtc, &pNv->SavedReg);
981 nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
982 nv_crtc_save_state_pll(crtc, &pNv->SavedReg);
984 /* init some state to saved value */
985 pNv->ModeReg.reg580 = pNv->SavedReg.reg580;
986 pNv->ModeReg.sel_clk = pNv->SavedReg.sel_clk & ~(0x5 << 16);
987 pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_CIO_CRE_LCD__INDEX] = pNv->SavedReg.crtc_reg[nv_crtc->head].CRTC[NV_CIO_CRE_LCD__INDEX];
990 static void nv_crtc_restore(xf86CrtcPtr crtc)
992 ScrnInfoPtr pScrn = crtc->scrn;
993 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
994 NVPtr pNv = NVPTR(pScrn);
995 RIVA_HW_STATE *state;
998 state = &pNv->SavedReg;
999 savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1001 /* Just to be safe */
1002 NVCrtcLockUnlock(crtc, false);
1004 NVVgaProtect(pNv, nv_crtc->head, true);
1005 nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
1006 nv_crtc_load_state_ext(crtc, &pNv->SavedReg);
1007 nv_crtc_load_state_palette(crtc, &pNv->SavedReg);
1008 nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1009 nv_crtc_load_state_pll(crtc, &pNv->SavedReg);
1010 NVVgaProtect(pNv, nv_crtc->head, false);
1012 nv_crtc->last_dpms = NV_DPMS_CLEARED;
1015 static void nv_crtc_prepare(xf86CrtcPtr crtc)
1017 ScrnInfoPtr pScrn = crtc->scrn;
1018 NVPtr pNv = NVPTR(pScrn);
1019 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1022 NVCrtcLockUnlock(crtc, 0);
1024 crtc->funcs->dpms(crtc, DPMSModeOff);
1026 /* Sync the engine before adjust mode */
1027 if (pNv->EXADriverPtr) {
1028 exaMarkSync(pScrn->pScreen);
1029 exaWaitSync(pScrn->pScreen);
1032 NVBlankScreen(pNv, nv_crtc->head, true);
1034 /* Some more preperation. */
1035 NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
1036 if (pNv->Architecture == NV_ARCH_40) {
1037 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1038 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1042 static void nv_crtc_commit(xf86CrtcPtr crtc)
1044 crtc->funcs->dpms (crtc, DPMSModeOn);
1046 if (crtc->scrn->pScreen != NULL) {
1047 NVPtr pNv = NVPTR(crtc->scrn);
1049 xf86_reload_cursors (crtc->scrn->pScreen);
1050 if (!pNv->alphaCursor) {
1051 /* this works round the fact that xf86_reload_cursors
1052 * will quite happily show the hw cursor when it knows
1053 * the hardware can't do alpha, and the current cursor
1054 * has an alpha channel
1056 xf86ForceHWCursor(crtc->scrn->pScreen, 1);
1057 xf86ForceHWCursor(crtc->scrn->pScreen, 0);
1062 static void nv_crtc_destroy(xf86CrtcPtr crtc)
1064 xfree(to_nouveau_crtc(crtc));
1067 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1072 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1077 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
1080 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1081 ScrnInfoPtr pScrn = crtc->scrn;
1082 NVPtr pNv = NVPTR(pScrn);
1083 NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1086 switch (pScrn->depth) {
1089 /* We've got 5 bit (32 values) colors and 256 registers for each color */
1090 for (i = 0; i < 32; i++)
1091 for (j = 0; j < 8; j++) {
1092 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1093 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
1094 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1099 /* First deal with the 5 bit colors */
1100 for (i = 0; i < 32; i++)
1101 for (j = 0; j < 8; j++) {
1102 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1103 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1105 /* Now deal with the 6 bit color */
1106 for (i = 0; i < 64; i++)
1107 for (j = 0; j < 4; j++)
1108 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
1112 for (i = 0; i < 256; i++) {
1113 regp->DAC[i * 3] = red[i] >> 8;
1114 regp->DAC[(i * 3) + 1] = green[i] >> 8;
1115 regp->DAC[(i * 3) + 2] = blue[i] >> 8;
1120 nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
1124 * Allocates memory for a locked-in-framebuffer shadow of the given
1125 * width and height for this CRTC's rotated shadow framebuffer.
1129 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
1131 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1132 ScrnInfoPtr pScrn = crtc->scrn;
1133 #if !NOUVEAU_EXA_PIXMAPS
1134 ScreenPtr pScreen = pScrn->pScreen;
1135 #endif /* !NOUVEAU_EXA_PIXMAPS */
1136 NVPtr pNv = NVPTR(pScrn);
1139 unsigned long rotate_pitch;
1140 int size, align = 64;
1142 rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1143 size = rotate_pitch * height;
1145 assert(nv_crtc->shadow == NULL);
1146 #if NOUVEAU_EXA_PIXMAPS
1147 if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
1148 align, size, &nv_crtc->shadow)) {
1149 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to allocate memory for shadow buffer!\n");
1153 if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
1154 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1155 "Failed to map shadow buffer.\n");
1159 offset = nv_crtc->shadow->map;
1161 nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
1162 if (nv_crtc->shadow == NULL) {
1163 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1164 "Couldn't allocate shadow memory for rotated CRTC.\n");
1167 offset = pNv->FB->map + nv_crtc->shadow->offset;
1168 #endif /* NOUVEAU_EXA_PIXMAPS */
1174 * Creates a pixmap for this CRTC's rotated shadow framebuffer.
1177 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
1179 ScrnInfoPtr pScrn = crtc->scrn;
1180 #if NOUVEAU_EXA_PIXMAPS
1181 ScreenPtr pScreen = pScrn->pScreen;
1182 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1183 #endif /* NOUVEAU_EXA_PIXMAPS */
1184 unsigned long rotate_pitch;
1185 PixmapPtr rotate_pixmap;
1186 #if NOUVEAU_EXA_PIXMAPS
1187 struct nouveau_pixmap *nvpix;
1188 #endif /* NOUVEAU_EXA_PIXMAPS */
1191 data = crtc->funcs->shadow_allocate (crtc, width, height);
1193 rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1195 #if NOUVEAU_EXA_PIXMAPS
1196 /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
1197 rotate_pixmap = pScreen->CreatePixmap(pScreen,
1200 #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
1205 #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
1207 rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
1210 pScrn->bitsPerPixel,
1213 #endif /* NOUVEAU_EXA_PIXMAPS */
1215 if (rotate_pixmap == NULL) {
1216 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1217 "Couldn't allocate shadow pixmap for rotated CRTC\n");
1220 #if NOUVEAU_EXA_PIXMAPS
1221 nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1223 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No initial shadow private available for rotation.\n");
1225 nvpix->bo = nv_crtc->shadow;
1226 nvpix->mapped = TRUE;
1229 /* Modify the pixmap to actually be the one we need. */
1230 pScreen->ModifyPixmapHeader(rotate_pixmap,
1234 pScrn->bitsPerPixel,
1238 nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1239 if (!nvpix || !nvpix->bo)
1240 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No final shadow private available for rotation.\n");
1241 #endif /* NOUVEAU_EXA_PIXMAPS */
1243 return rotate_pixmap;
1247 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
1249 ScrnInfoPtr pScrn = crtc->scrn;
1250 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1251 ScreenPtr pScreen = pScrn->pScreen;
1253 if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
1254 pScreen->DestroyPixmap(rotate_pixmap);
1257 #if !NOUVEAU_EXA_PIXMAPS
1258 if (data && nv_crtc->shadow) {
1259 exaOffscreenFree(pScreen, nv_crtc->shadow);
1261 #endif /* !NOUVEAU_EXA_PIXMAPS */
1263 nv_crtc->shadow = NULL;
1266 static const xf86CrtcFuncsRec nv_crtc_funcs = {
1267 .dpms = nv_crtc_dpms,
1268 .save = nv_crtc_save,
1269 .restore = nv_crtc_restore,
1270 .mode_fixup = nv_crtc_mode_fixup,
1271 .mode_set = nv_crtc_mode_set,
1272 .prepare = nv_crtc_prepare,
1273 .commit = nv_crtc_commit,
1274 .destroy = nv_crtc_destroy,
1275 .lock = nv_crtc_lock,
1276 .unlock = nv_crtc_unlock,
1277 .set_cursor_colors = NULL, /* Alpha cursors do not need this */
1278 .set_cursor_position = nv_crtc_set_cursor_position,
1279 .show_cursor = nv_crtc_show_cursor,
1280 .hide_cursor = nv_crtc_hide_cursor,
1281 .load_cursor_argb = nv_crtc_load_cursor_argb,
1282 .gamma_set = nv_crtc_gamma_set,
1283 .shadow_create = nv_crtc_shadow_create,
1284 .shadow_allocate = nv_crtc_shadow_allocate,
1285 .shadow_destroy = nv_crtc_shadow_destroy,
1289 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
1291 NVPtr pNv = NVPTR(pScrn);
1292 static xf86CrtcFuncsRec crtcfuncs;
1294 struct nouveau_crtc *nv_crtc;
1295 NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[crtc_num];
1298 crtcfuncs = nv_crtc_funcs;
1300 /* NV04-NV10 doesn't support alpha cursors */
1301 if (pNv->NVArch < 0x11) {
1302 crtcfuncs.set_cursor_colors = nv_crtc_set_cursor_colors;
1303 crtcfuncs.load_cursor_image = nv_crtc_load_cursor_image;
1304 crtcfuncs.load_cursor_argb = NULL;
1307 crtcfuncs.shadow_create = NULL;
1308 crtcfuncs.shadow_allocate = NULL;
1309 crtcfuncs.shadow_destroy = NULL;
1312 if (!(crtc = xf86CrtcCreate(pScrn, &crtcfuncs)))
1315 if (!(nv_crtc = xcalloc(1, sizeof (struct nouveau_crtc)))) {
1316 xf86CrtcDestroy(crtc);
1320 nv_crtc->head = crtc_num;
1321 nv_crtc->last_dpms = NV_DPMS_CLEARED;
1323 crtc->driver_private = nv_crtc;
1325 /* Initialise the default LUT table. */
1326 for (i = 0; i < 256; i++) {
1328 regp->DAC[(i*3)+1] = i;
1329 regp->DAC[(i*3)+2] = i;
1332 NVCrtcLockUnlock(crtc, false);
1335 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1337 ScrnInfoPtr pScrn = crtc->scrn;
1338 NVPtr pNv = NVPTR(pScrn);
1339 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1341 NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1343 NVWritePVIO(pNv, nv_crtc->head, VGA_MISC_OUT_W, regp->MiscOutReg);
1345 for (i = 0; i < 5; i++)
1346 NVWriteVgaSeq(pNv, nv_crtc->head, i, regp->Sequencer[i]);
1348 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
1349 NVWriteVgaCrtc(pNv, nv_crtc->head, 17, regp->CRTC[17] & ~0x80);
1351 for (i = 0; i < 25; i++)
1352 NVWriteVgaCrtc(pNv, nv_crtc->head, i, regp->CRTC[i]);
1354 for (i = 0; i < 9; i++)
1355 NVWriteVgaGr(pNv, nv_crtc->head, i, regp->Graphics[i]);
1357 NVSetEnablePalette(pNv, nv_crtc->head, true);
1358 for (i = 0; i < 21; i++)
1359 NVWriteVgaAttr(pNv, nv_crtc->head, i, regp->Attribute[i]);
1361 NVSetEnablePalette(pNv, nv_crtc->head, false);
1364 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1366 ScrnInfoPtr pScrn = crtc->scrn;
1367 NVPtr pNv = NVPTR(pScrn);
1368 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1372 regp = &state->crtc_reg[nv_crtc->head];
1374 if (pNv->Architecture >= NV_ARCH_10) {
1376 /* setting FSEL *must* come before CIO_CRE_LCD, as writing CIO_CRE_LCD sets some
1377 * bits (16 & 17) in FSEL that should not be overwritten by writing FSEL */
1378 NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, regp->head);
1380 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
1381 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
1382 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
1383 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
1384 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1385 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1386 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1387 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1388 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
1390 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_21, regp->CRTC[NV_CIO_CRE_21]);
1391 NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
1392 NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
1393 NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
1394 if (pNv->Architecture == NV_ARCH_40) {
1395 NVCrtcWriteCRTC(crtc, NV_CRTC_0850, regp->unk850);
1396 NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO_EXT, regp->gpio_ext);
1399 if (pNv->Architecture == NV_ARCH_40) {
1400 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1401 if (regp->config == 0x2) /* enhanced "horizontal only" non-vga mode */
1402 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 | 0x10000);
1404 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1408 NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
1409 NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio);
1411 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC0_INDEX, regp->CRTC[NV_CIO_CRE_RPC0_INDEX]);
1412 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX, regp->CRTC[NV_CIO_CRE_RPC1_INDEX]);
1413 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LSR_INDEX, regp->CRTC[NV_CIO_CRE_LSR_INDEX]);
1414 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_PIXEL_INDEX, regp->CRTC[NV_CIO_CRE_PIXEL_INDEX]);
1415 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LCD__INDEX, regp->CRTC[NV_CIO_CRE_LCD__INDEX]);
1416 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HEB__INDEX, regp->CRTC[NV_CIO_CRE_HEB__INDEX]);
1417 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ENH_INDEX, regp->CRTC[NV_CIO_CRE_ENH_INDEX]);
1418 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FF_INDEX, regp->CRTC[NV_CIO_CRE_FF_INDEX]);
1419 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FFLWM__INDEX, regp->CRTC[NV_CIO_CRE_FFLWM__INDEX]);
1420 if (pNv->Architecture >= NV_ARCH_30)
1421 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_47, regp->CRTC[NV_CIO_CRE_47]);
1423 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX, regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX]);
1424 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX, regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]);
1425 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX, regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX]);
1426 if (pNv->Architecture == NV_ARCH_40)
1427 nv_fix_nv40_hw_cursor(pNv, nv_crtc->head);
1428 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ILACE__INDEX, regp->CRTC[NV_CIO_CRE_ILACE__INDEX]);
1430 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_ARX_INDEX, regp->CRTC[NV_CIO_CR_ARX_INDEX]);
1431 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH3__INDEX, regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX]);
1432 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH4__INDEX, regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]);
1433 if (pNv->Architecture >= NV_ARCH_10) {
1434 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_EBR_INDEX, regp->CRTC[NV_CIO_CRE_EBR_INDEX]);
1435 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_CSB, regp->CRTC[NV_CIO_CRE_CSB]);
1436 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_4B, regp->CRTC[NV_CIO_CRE_4B]);
1437 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_52, regp->CRTC[NV_CIO_CRE_52]);
1439 /* NV11 and NV20 stop at 0x52. */
1440 if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1441 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_53, regp->CRTC[NV_CIO_CRE_53]);
1442 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_54, regp->CRTC[NV_CIO_CRE_54]);
1444 for (i = 0; i < 0x10; i++)
1445 NVWriteVgaCrtc5758(pNv, nv_crtc->head, i, regp->CR58[i]);
1446 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_59, regp->CRTC[NV_CIO_CRE_59]);
1448 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_85, regp->CRTC[NV_CIO_CRE_85]);
1449 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_86, regp->CRTC[NV_CIO_CRE_86]);
1452 NVCrtcWriteCRTC(crtc, NV_CRTC_START, regp->fb_start);
1454 /* Setting 1 on this value gives you interrupts for every vblank period. */
1455 NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_EN_0, 0);
1456 NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
1459 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1461 ScrnInfoPtr pScrn = crtc->scrn;
1462 NVPtr pNv = NVPTR(pScrn);
1463 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1465 NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1467 regp->MiscOutReg = NVReadPVIO(pNv, nv_crtc->head, VGA_MISC_OUT_R);
1469 for (i = 0; i < 25; i++)
1470 regp->CRTC[i] = NVReadVgaCrtc(pNv, nv_crtc->head, i);
1472 NVSetEnablePalette(pNv, nv_crtc->head, true);
1473 for (i = 0; i < 21; i++)
1474 regp->Attribute[i] = NVReadVgaAttr(pNv, nv_crtc->head, i);
1475 NVSetEnablePalette(pNv, nv_crtc->head, false);
1477 for (i = 0; i < 9; i++)
1478 regp->Graphics[i] = NVReadVgaGr(pNv, nv_crtc->head, i);
1480 for (i = 0; i < 5; i++)
1481 regp->Sequencer[i] = NVReadVgaSeq(pNv, nv_crtc->head, i);
1484 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1486 ScrnInfoPtr pScrn = crtc->scrn;
1487 NVPtr pNv = NVPTR(pScrn);
1488 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1492 regp = &state->crtc_reg[nv_crtc->head];
1494 regp->CRTC[NV_CIO_CRE_LCD__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LCD__INDEX);
1495 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC0_INDEX);
1496 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX);
1497 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LSR_INDEX);
1498 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_PIXEL_INDEX);
1499 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HEB__INDEX);
1500 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ENH_INDEX);
1502 regp->CRTC[NV_CIO_CRE_FF_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FF_INDEX);
1503 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FFLWM__INDEX);
1504 regp->CRTC[NV_CIO_CRE_21] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_21);
1505 if (pNv->Architecture >= NV_ARCH_30)
1506 regp->CRTC[NV_CIO_CRE_47] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_47);
1507 regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX);
1508 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX);
1509 regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX);
1510 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ILACE__INDEX);
1512 if (pNv->Architecture >= NV_ARCH_10) {
1513 regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
1514 regp->unk834 = NVCrtcReadCRTC(crtc, NV_CRTC_0834);
1515 if (pNv->Architecture == NV_ARCH_40) {
1516 regp->unk850 = NVCrtcReadCRTC(crtc, NV_CRTC_0850);
1517 regp->gpio_ext = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO_EXT);
1519 if (pNv->twoHeads) {
1520 regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL);
1521 regp->crtcOwner = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_44);
1523 regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG);
1526 regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO);
1527 regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
1529 regp->CRTC[NV_CIO_CR_ARX_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_ARX_INDEX);
1530 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH3__INDEX);
1531 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH4__INDEX);
1532 if (pNv->Architecture >= NV_ARCH_10) {
1533 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_EBR_INDEX);
1534 regp->CRTC[NV_CIO_CRE_CSB] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_CSB);
1535 regp->CRTC[NV_CIO_CRE_4B] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_4B);
1536 regp->CRTC[NV_CIO_CRE_52] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_52);
1538 /* NV11 and NV20 don't have this, they stop at 0x52. */
1539 if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1540 for (i = 0; i < 0x10; i++)
1541 regp->CR58[i] = NVReadVgaCrtc5758(pNv, nv_crtc->head, i);
1543 regp->CRTC[NV_CIO_CRE_59] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_59);
1544 regp->CRTC[NV_CIO_CRE_53] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_53);
1545 regp->CRTC[NV_CIO_CRE_54] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_54);
1547 regp->CRTC[NV_CIO_CRE_85] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_85);
1548 regp->CRTC[NV_CIO_CRE_86] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_86);
1551 regp->fb_start = NVCrtcReadCRTC(crtc, NV_CRTC_START);
1554 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1556 ScrnInfoPtr pScrn = crtc->scrn;
1557 NVPtr pNv = NVPTR(pScrn);
1558 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1562 regp = &state->crtc_reg[nv_crtc->head];
1564 regp->general = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL);
1566 if (pNv->twoHeads) {
1567 if (pNv->NVArch >= 0x17)
1568 regp->unk_630 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_630);
1569 regp->fp_control = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_CONTROL);
1570 regp->debug_0 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0);
1571 regp->debug_1 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1);
1572 regp->debug_2 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2);
1574 regp->unk_a20 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A20);
1575 regp->unk_a24 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A24);
1576 regp->unk_a34 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A34);
1579 if (pNv->NVArch == 0x11) {
1580 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_DITHER_NV11);
1581 } else if (pNv->twoHeads) {
1582 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DITHER);
1583 for (i = 0; i < 3; i++) {
1584 regp->dither_regs[i] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4);
1585 regp->dither_regs[i + 3] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4);
1588 if (pNv->Architecture >= NV_ARCH_10)
1589 regp->nv10_cursync = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC);
1591 /* The regs below are 0 for non-flatpanels, so you can load and save them */
1593 for (i = 0; i < 7; i++) {
1594 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
1595 regp->fp_horiz_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1598 for (i = 0; i < 7; i++) {
1599 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
1600 regp->fp_vert_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1604 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1606 ScrnInfoPtr pScrn = crtc->scrn;
1607 NVPtr pNv = NVPTR(pScrn);
1608 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1612 regp = &state->crtc_reg[nv_crtc->head];
1614 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL, regp->general);
1616 if (pNv->twoHeads) {
1617 if (pNv->NVArch >= 0x17)
1618 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_630, regp->unk_630);
1619 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_CONTROL, regp->fp_control);
1620 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
1621 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
1622 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
1623 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
1624 uint32_t reg890 = NVCrtcReadRAMDAC(crtc, NV30_RAMDAC_890);
1625 NVCrtcWriteRAMDAC(crtc, NV30_RAMDAC_89C, reg890);
1628 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A20, regp->unk_a20);
1629 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A24, regp->unk_a24);
1630 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A34, regp->unk_a34);
1633 if (pNv->NVArch == 0x11)
1634 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_DITHER_NV11, regp->dither);
1635 else if (pNv->twoHeads) {
1636 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DITHER, regp->dither);
1637 for (i = 0; i < 3; i++) {
1638 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4, regp->dither_regs[i]);
1639 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4, regp->dither_regs[i + 3]);
1642 if (pNv->Architecture >= NV_ARCH_10)
1643 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
1645 /* The regs below are 0 for non-flatpanels, so you can load and save them */
1647 for (i = 0; i < 7; i++) {
1648 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
1649 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_horiz_regs[i]);
1652 for (i = 0; i < 7; i++) {
1653 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
1654 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_vert_regs[i]);
1658 void NVCrtcSetBase(xf86CrtcPtr crtc, int x, int y)
1660 ScrnInfoPtr pScrn = crtc->scrn;
1661 NVPtr pNv = NVPTR(pScrn);
1662 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1663 uint32_t start = (y * pScrn->displayWidth + x) * pScrn->bitsPerPixel / 8;
1665 if (crtc->rotatedData != NULL) /* we do not exist on the real framebuffer */
1666 #if NOUVEAU_EXA_PIXMAPS
1667 start = nv_crtc->shadow->offset;
1669 start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
1672 start += pNv->FB->offset;
1674 /* 30 bits addresses in 32 bits according to haiku */
1676 pNv->ModeReg.crtc_reg[nv_crtc->head].fb_start = start;
1677 NVCrtcWriteCRTC(crtc, NV_CRTC_START, start);
1683 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1685 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1686 NVPtr pNv = NVPTR(crtc->scrn);
1687 uint32_t mmiobase = nv_crtc->head ? NV_PDIO1_OFFSET : NV_PDIO0_OFFSET;
1690 VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff);
1691 VGA_WR08(pNv->REGS, VGA_DAC_READ_ADDR + mmiobase, 0x0);
1693 for (i = 0; i < 768; i++) {
1694 state->crtc_reg[nv_crtc->head].DAC[i] = NV_RD08(pNv->REGS, VGA_DAC_DATA + mmiobase);
1695 DDXMMIOH("nv_crtc_save_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
1698 NVSetEnablePalette(pNv, nv_crtc->head, false);
1700 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1702 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1703 NVPtr pNv = NVPTR(crtc->scrn);
1704 uint32_t mmiobase = nv_crtc->head ? NV_PDIO1_OFFSET : NV_PDIO0_OFFSET;
1707 VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff);
1708 VGA_WR08(pNv->REGS, VGA_DAC_WRITE_ADDR + mmiobase, 0x0);
1710 for (i = 0; i < 768; i++) {
1711 DDXMMIOH("nv_crtc_load_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
1712 NV_WR08(pNv->REGS, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
1715 NVSetEnablePalette(pNv, nv_crtc->head, false);