git.oblomov.eu Git - nouveau/blob - src/nv_output.c

   1 /*
   2  * Copyright 2003 NVIDIA, Corporation
   3  * Copyright 2006 Dave Airlie
   4  * Copyright 2007 Maarten Maathuis
   5  * Copyright 2007-2008 Stuart Bennett
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  23  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #include <X11/Xatom.h>
  28 #include "nv_include.h"
  29
  30 #define MULTIPLE_ENCODERS(e) (e & (e - 1))
  31 #define FOR_EACH_ENCODER_IN_CONNECTOR(i, c, e)  for (i = 0; i < pNv->dcb_table.entries; i++)    \
  32                                                         if (c->possible_encoders & (1 << i) &&  \
  33                                                             (e = &pNv->encoders[i]))
  34
  35 static int nv_output_ramdac_offset(struct nouveau_encoder *nv_encoder)
  36 {
  37         int offset = 0;
  38
  39         if (nv_encoder->dcb->or & (8 | OUTPUT_C))
  40                 offset += 0x68;
  41         if (nv_encoder->dcb->or & (8 | OUTPUT_B))
  42                 offset += 0x2000;
  43
  44         return offset;
  45 }
  46
  47 static bool
  48 nv_load_detect(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
  49 {
  50         NVPtr pNv = NVPTR(pScrn);
  51         uint32_t testval, regoffset = nv_output_ramdac_offset(nv_encoder);
  52         uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, saved_rtest_ctrl, temp;
  53         int head, present = 0;
  54         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
  55
  56 #define RGB_TEST_DATA(r,g,b) (r << 0 | g << 10 | b << 20)
  57         testval = RGB_TEST_DATA(0x140, 0x140, 0x140); /* 0x94050140 */
  58         if (pNv->VBIOS.dactestval)
  59                 testval = pNv->VBIOS.dactestval;
  60
  61         saved_rtest_ctrl = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset);
  62         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl & ~0x00010000);
  63
  64         if (pNv->NVArch >= 0x17) {
  65                 saved_powerctrl_2 = nvReadMC(pNv, NV_PBUS_POWERCTRL_2);
  66
  67                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);
  68                 if (regoffset == 0x68) {
  69                         saved_powerctrl_4 = nvReadMC(pNv, NV_PBUS_POWERCTRL_4);
  70                         nvWriteMC(pNv, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);
  71                 }
  72         }
  73
  74         usleep(4000);
  75
  76         saved_routput = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset);
  77         head = (saved_routput & 0x100) >> 8;
  78         /* if there's a spare crtc, using it will minimise flicker for the case
  79          * where the in-use crtc is in use by an off-chip tmds encoder */
  80         if (xf86_config->crtc[head]->enabled && !xf86_config->crtc[head ^ 1]->enabled)
  81                 head ^= 1;
  82         /* nv driver and nv31 use 0xfffffeee, nv34 and 6600 use 0xfffffece */
  83         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset,
  84                       (saved_routput & 0xfffffece) | head << 8);
  85         usleep(1000);
  86
  87         temp = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset);
  88         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, temp | 1);
  89
  90         NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_DATA, 1 << 31 | testval);
  91         temp = NVReadRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL);
  92         NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL, temp | 0x1000);
  93         usleep(1000);
  94
  95         present = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset) & (1 << 28);
  96
  97         temp = NVReadRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL);
  98         NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL, temp & 0xffffefff);
  99         NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_DATA, 0);
 100
 101         /* bios does something more complex for restoring, but I think this is good enough */
 102         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, saved_routput);
 103         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl);
 104         if (pNv->NVArch >= 0x17) {
 105                 if (regoffset == 0x68)
 106                         nvWriteMC(pNv, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);
 107                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);
 108         }
 109
 110         if (present) {
 111                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Load detected on output %c\n", '@' + ffs(nv_encoder->dcb->or));
 112                 return true;
 113         }
 114
 115         return false;
 116 }
 117
 118 static void
 119 update_output_fields(xf86OutputPtr output, struct nouveau_encoder *det_encoder)
 120 {
 121         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 122         NVPtr pNv = NVPTR(output->scrn);
 123
 124         if (nv_connector->detected_encoder == det_encoder)
 125                 return;
 126
 127         nv_connector->detected_encoder = det_encoder;
 128         output->possible_crtcs = det_encoder->dcb->heads;
 129         if (det_encoder->dcb->type == OUTPUT_LVDS || det_encoder->dcb->type == OUTPUT_TMDS) {
 130                 output->doubleScanAllowed = false;
 131                 output->interlaceAllowed = false;
 132         } else {
 133                 output->doubleScanAllowed = true;
 134                 if (pNv->Architecture == NV_ARCH_20 ||
 135                    (pNv->Architecture == NV_ARCH_10 &&
 136                     (pNv->Chipset & 0x0ff0) != CHIPSET_NV10 &&
 137                     (pNv->Chipset & 0x0ff0) != CHIPSET_NV15))
 138                         /* HW is broken */
 139                         output->interlaceAllowed = false;
 140                 else
 141                         output->interlaceAllowed = true;
 142         }
 143 }
 144
 145 static xf86OutputStatus
 146 nv_output_detect(xf86OutputPtr output)
 147 {
 148         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 149         ScrnInfoPtr pScrn = output->scrn;
 150         NVPtr pNv = NVPTR(pScrn);
 151         struct nouveau_encoder *det_encoder;
 152         xf86OutputStatus ret = XF86OutputStatusDisconnected;
 153
 154         struct nouveau_encoder *find_encoder_by_type(NVOutputType type)
 155         {
 156                 int i;
 157                 for (i = 0; i < pNv->dcb_table.entries; i++)
 158                         if (nv_connector->possible_encoders & (1 << i) &&
 159                             (type == OUTPUT_ANY || pNv->encoders[i].dcb->type == type))
 160                                 return &pNv->encoders[i];
 161                 return NULL;
 162         }
 163
 164         if (nv_connector->pDDCBus &&
 165             (nv_connector->edid = xf86OutputGetEDID(output, nv_connector->pDDCBus),
 166              xf86OutputSetEDID(output, nv_connector->edid), nv_connector->edid)) {
 167                 if (MULTIPLE_ENCODERS(nv_connector->possible_encoders)) {
 168                         if (nv_connector->edid->features.input_type)
 169                                 det_encoder = find_encoder_by_type(OUTPUT_TMDS);
 170                         else
 171                                 det_encoder = find_encoder_by_type(OUTPUT_ANALOG);
 172                 } else
 173                         det_encoder = find_encoder_by_type(OUTPUT_ANY);
 174                 ret = XF86OutputStatusConnected;
 175         } else if ((det_encoder = find_encoder_by_type(OUTPUT_ANALOG))) {
 176                 /* we don't have a load det function for early cards */
 177                 if (!pNv->twoHeads || pNv->NVArch == 0x11)
 178                         ret = XF86OutputStatusUnknown;
 179                 else if (pNv->twoHeads && nv_load_detect(pScrn, det_encoder))
 180                         ret = XF86OutputStatusConnected;
 181         } else if ((det_encoder = find_encoder_by_type(OUTPUT_LVDS))) {
 182                 if (det_encoder->dcb->lvdsconf.use_straps_for_mode &&
 183                     pNv->VBIOS.fp.native_mode)
 184                         ret = XF86OutputStatusConnected;
 185                 if (pNv->VBIOS.fp.edid) {
 186                         nv_connector->edid = xf86InterpretEDID(pScrn->scrnIndex, pNv->VBIOS.fp.edid);
 187                         xf86OutputSetEDID(output, nv_connector->edid);
 188                         ret = XF86OutputStatusConnected;
 189                 }
 190         }
 191
 192         if (ret != XF86OutputStatusDisconnected)
 193                 update_output_fields(output, det_encoder);
 194
 195         return ret;
 196 }
 197
 198 static DisplayModePtr
 199 get_native_mode_from_edid(xf86OutputPtr output, DisplayModePtr edid_modes)
 200 {
 201         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 202         struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
 203         ScrnInfoPtr pScrn = output->scrn;
 204         int max_h_active = 0, max_v_active = 0;
 205         int i;
 206         DisplayModePtr mode;
 207
 208         for (i = 0; i < DET_TIMINGS; i++) {
 209                 /* We only look at detailed timings atm */
 210                 if (nv_connector->edid->det_mon[i].type != DT)
 211                         continue;
 212                 /* Selecting only based on width ok? */
 213                 if (nv_connector->edid->det_mon[i].section.d_timings.h_active > max_h_active) {
 214                         max_h_active = nv_connector->edid->det_mon[i].section.d_timings.h_active;
 215                         max_v_active = nv_connector->edid->det_mon[i].section.d_timings.v_active;
 216                 }
 217         }
 218         if (!(max_h_active && max_v_active)) {
 219                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 220                            "No EDID detailed timings available for finding native mode\n");
 221                 return NULL;
 222         }
 223
 224         if (nv_encoder->native_mode) {
 225                 xfree(nv_encoder->native_mode);
 226                 nv_encoder->native_mode = NULL;
 227         }
 228
 229         for (mode = edid_modes; mode != NULL; mode = mode->next) {
 230                 if (mode->HDisplay == max_h_active &&
 231                         mode->VDisplay == max_v_active) {
 232                         /* Take the preferred mode when it exists. */
 233                         if (mode->type & M_T_PREFERRED) {
 234                                 nv_encoder->native_mode = xf86DuplicateMode(mode);
 235                                 break;
 236                         }
 237                         /* Find the highest refresh mode otherwise. */
 238                         if (!nv_encoder->native_mode || (mode->VRefresh > nv_encoder->native_mode->VRefresh)) {
 239                                 if (nv_encoder->native_mode)
 240                                         xfree(nv_encoder->native_mode);
 241                                 mode->type |= M_T_PREFERRED;
 242                                 nv_encoder->native_mode = xf86DuplicateMode(mode);
 243                         }
 244                 }
 245         }
 246
 247         return nv_encoder->native_mode;
 248 }
 249
 250 static DisplayModePtr
 251 nv_output_get_edid_modes(xf86OutputPtr output)
 252 {
 253         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 254         struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
 255         ScrnInfoPtr pScrn = output->scrn;
 256         DisplayModePtr edid_modes;
 257
 258         if (!(edid_modes = xf86OutputGetEDIDModes(output)))
 259                 return edid_modes;
 260
 261         if (nv_encoder->dcb->type == OUTPUT_TMDS || nv_encoder->dcb->type == OUTPUT_LVDS)
 262                 if (!get_native_mode_from_edid(output, edid_modes))
 263                         return NULL;
 264
 265         if (nv_encoder->dcb->type == OUTPUT_LVDS)
 266                 parse_lvds_manufacturer_table(pScrn, &NVPTR(pScrn)->VBIOS, nv_encoder->native_mode->Clock);
 267
 268         return edid_modes;
 269 }
 270
 271 static DisplayModePtr
 272 nv_lvds_output_get_modes(xf86OutputPtr output)
 273 {
 274         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 275         struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
 276         ScrnInfoPtr pScrn = output->scrn;
 277         NVPtr pNv = NVPTR(pScrn);
 278         DisplayModePtr modes;
 279
 280         /* panels only have one mode, and it doesn't change */
 281         if (nv_encoder->native_mode)
 282                 return xf86DuplicateMode(nv_encoder->native_mode);
 283
 284         if ((modes = nv_output_get_edid_modes(output)))
 285                 return modes;
 286
 287         if (!nv_encoder->dcb->lvdsconf.use_straps_for_mode || pNv->VBIOS.fp.native_mode == NULL)
 288                 return NULL;
 289
 290         nv_encoder->native_mode = xf86DuplicateMode(pNv->VBIOS.fp.native_mode);
 291
 292         return xf86DuplicateMode(pNv->VBIOS.fp.native_mode);
 293 }
 294
 295 static int nv_output_mode_valid(xf86OutputPtr output, DisplayModePtr mode)
 296 {
 297         struct nouveau_encoder *nv_encoder = to_nouveau_connector(output)->detected_encoder;
 298         NVPtr pNv = NVPTR(output->scrn);
 299
 300         if (!output->doubleScanAllowed && mode->Flags & V_DBLSCAN)
 301                 return MODE_NO_DBLESCAN;
 302         if (!output->interlaceAllowed && mode->Flags & V_INTERLACE)
 303                 return MODE_NO_INTERLACE;
 304
 305         if (nv_encoder->dcb->type == OUTPUT_ANALOG) {
 306                 if (mode->Clock > (pNv->twoStagePLL ? 400000 : 350000))
 307                         return MODE_CLOCK_HIGH;
 308                 if (mode->Clock < 12000)
 309                         return MODE_CLOCK_LOW;
 310         }
 311         if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS)
 312                 /* No modes > panel's native res */
 313                 if (mode->HDisplay > nv_encoder->native_mode->HDisplay ||
 314                     mode->VDisplay > nv_encoder->native_mode->VDisplay)
 315                         return MODE_PANEL;
 316         if (nv_encoder->dcb->type == OUTPUT_TMDS) {
 317                 if (nv_encoder->dcb->duallink_possible) {
 318                         if (mode->Clock > 330000) /* 2x165 MHz */
 319                                 return MODE_CLOCK_HIGH;
 320                 } else
 321                         if (mode->Clock > 165000) /* 165 MHz */
 322                                 return MODE_CLOCK_HIGH;
 323         }
 324
 325         return MODE_OK;
 326 }
 327
 328 static void
 329 nv_output_destroy(xf86OutputPtr output)
 330 {
 331         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 332         struct nouveau_encoder *nv_encoder;
 333         ScrnInfoPtr pScrn = output->scrn;
 334         NVPtr pNv = NVPTR(output->scrn);
 335         int i;
 336
 337         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s called\n", __func__);
 338
 339         if (!nv_connector)
 340                 return;
 341
 342         if (nv_connector->edid)
 343                 xfree(nv_connector->edid);
 344         FOR_EACH_ENCODER_IN_CONNECTOR(i, nv_connector, nv_encoder)
 345                 if (nv_encoder->native_mode)
 346                         xfree(nv_encoder->native_mode);
 347         xfree(nv_connector);
 348 }
 349
 350 static Atom scaling_mode_atom;
 351 #define SCALING_MODE_NAME "SCALING_MODE"
 352 static const struct {
 353         char *name;
 354         enum scaling_modes mode;
 355 } scaling_mode[] = {
 356         { "panel", SCALE_PANEL },
 357         { "fullscreen", SCALE_FULLSCREEN },
 358         { "aspect", SCALE_ASPECT },
 359         { "noscale", SCALE_NOSCALE },
 360         { NULL, SCALE_INVALID}
 361 };
 362
 363 static Atom dithering_atom;
 364 #define DITHERING_MODE_NAME "DITHERING"
 365
 366 static void
 367 nv_output_create_resources(xf86OutputPtr output)
 368 {
 369         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 370         ScrnInfoPtr pScrn = output->scrn;
 371         INT32 dithering_range[2] = { 0, 1 };
 372         int error, i;
 373
 374         /* may be called before encoder is picked, resources will be created
 375          * by update_output_fields()
 376          */
 377         if (!nv_encoder)
 378                 return;
 379
 380         /* no properties for vga */
 381         if (nv_encoder->dcb->type == OUTPUT_ANALOG)
 382                 return;
 383
 384         /*
 385          * Setup scaling mode property.
 386          */
 387         scaling_mode_atom = MakeAtom(SCALING_MODE_NAME, sizeof(SCALING_MODE_NAME) - 1, TRUE);
 388
 389         error = RRConfigureOutputProperty(output->randr_output,
 390                                         scaling_mode_atom, TRUE, FALSE, FALSE,
 391                                         0, NULL);
 392
 393         if (error != 0) {
 394                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 395                         "RRConfigureOutputProperty error, %d\n", error);
 396         }
 397
 398         char *existing_scale_name = NULL;
 399         for (i = 0; scaling_mode[i].name; i++)
 400                 if (scaling_mode[i].mode == nv_encoder->scaling_mode)
 401                         existing_scale_name = scaling_mode[i].name;
 402
 403         error = RRChangeOutputProperty(output->randr_output, scaling_mode_atom,
 404                                         XA_STRING, 8, PropModeReplace,
 405                                         strlen(existing_scale_name),
 406                                         existing_scale_name, FALSE, TRUE);
 407
 408         if (error != 0) {
 409                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 410                         "Failed to set scaling mode, %d\n", error);
 411         }
 412
 413         /*
 414          * Setup dithering property.
 415          */
 416         dithering_atom = MakeAtom(DITHERING_MODE_NAME, sizeof(DITHERING_MODE_NAME) - 1, TRUE);
 417
 418         error = RRConfigureOutputProperty(output->randr_output,
 419                                         dithering_atom, TRUE, TRUE, FALSE,
 420                                         2, dithering_range);
 421
 422         if (error != 0) {
 423                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 424                         "RRConfigureOutputProperty error, %d\n", error);
 425         }
 426
 427         /* promote bool into int32 to make RandR DIX and big endian happy */
 428         int32_t existing_dither = nv_encoder->dithering;
 429         error = RRChangeOutputProperty(output->randr_output, dithering_atom,
 430                                         XA_INTEGER, 32, PropModeReplace, 1,
 431                                         &existing_dither, FALSE, TRUE);
 432
 433         if (error != 0) {
 434                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 435                         "Failed to set dithering mode, %d\n", error);
 436         }
 437
 438         RRPostPendingProperties(output->randr_output);
 439 }
 440
 441 static Bool
 442 nv_output_set_property(xf86OutputPtr output, Atom property,
 443                                 RRPropertyValuePtr value)
 444 {
 445         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 446
 447         if (property == scaling_mode_atom) {
 448                 int32_t ret;
 449                 char *name = NULL;
 450
 451                 if (value->type != XA_STRING || value->format != 8)
 452                         return FALSE;
 453
 454                 name = (char *) value->data;
 455
 456                 /* Match a string to a scaling mode */
 457                 ret = nv_scaling_mode_lookup(name, value->size);
 458                 if (ret == SCALE_INVALID)
 459                         return FALSE;
 460
 461                 /* LVDS must always use gpu scaling. */
 462                 if (ret == SCALE_PANEL && nv_encoder->dcb->type == OUTPUT_LVDS)
 463                         return FALSE;
 464
 465                 nv_encoder->scaling_mode = ret;
 466         } else if (property == dithering_atom) {
 467                 if (value->type != XA_INTEGER || value->format != 32)
 468                         return FALSE;
 469
 470                 int32_t val = *(int32_t *) value->data;
 471
 472                 if (val < 0 || val > 1)
 473                         return FALSE;
 474
 475                 nv_encoder->dithering = val;
 476         }
 477
 478         return TRUE;
 479 }
 480
 481 static Bool
 482 nv_output_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
 483                      DisplayModePtr adjusted_mode)
 484 {
 485         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 486
 487         if (nv_connector->nv_encoder != nv_connector->detected_encoder) {
 488                 nv_connector->nv_encoder = nv_connector->detected_encoder;
 489                 if (output->randr_output) {
 490                         RRDeleteOutputProperty(output->randr_output, dithering_atom);
 491                         RRDeleteOutputProperty(output->randr_output, scaling_mode_atom);
 492                         output->funcs->create_resources(output);
 493                 }
 494         }
 495
 496         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 497
 498         /* For internal panels and gpu scaling on DVI we need the native mode */
 499         if (nv_encoder->dcb->type == OUTPUT_LVDS ||
 500             (nv_encoder->dcb->type == OUTPUT_TMDS && nv_encoder->scaling_mode != SCALE_PANEL)) {
 501                 adjusted_mode->HDisplay = nv_encoder->native_mode->HDisplay;
 502                 adjusted_mode->HSkew = nv_encoder->native_mode->HSkew;
 503                 adjusted_mode->HSyncStart = nv_encoder->native_mode->HSyncStart;
 504                 adjusted_mode->HSyncEnd = nv_encoder->native_mode->HSyncEnd;
 505                 adjusted_mode->HTotal = nv_encoder->native_mode->HTotal;
 506                 adjusted_mode->VDisplay = nv_encoder->native_mode->VDisplay;
 507                 adjusted_mode->VScan = nv_encoder->native_mode->VScan;
 508                 adjusted_mode->VSyncStart = nv_encoder->native_mode->VSyncStart;
 509                 adjusted_mode->VSyncEnd = nv_encoder->native_mode->VSyncEnd;
 510                 adjusted_mode->VTotal = nv_encoder->native_mode->VTotal;
 511                 adjusted_mode->Clock = nv_encoder->native_mode->Clock;
 512                 adjusted_mode->Flags = nv_encoder->native_mode->Flags;
 513
 514                 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
 515         }
 516
 517         return TRUE;
 518 }
 519
 520 static void nv_digital_output_prepare_sel_clk(NVPtr pNv, struct nouveau_encoder *nv_encoder, int head)
 521 {
 522         NVRegPtr state = &pNv->ModeReg;
 523         uint32_t bits1618 = nv_encoder->dcb->or & OUTPUT_A ? 0x10000 : 0x40000;
 524
 525         if (nv_encoder->dcb->location != LOC_ON_CHIP)
 526                 return;
 527
 528         /* SEL_CLK is only used on the primary ramdac
 529          * It toggles spread spectrum PLL output and sets the bindings of PLLs
 530          * to heads on digital outputs
 531          */
 532         if (head)
 533                 state->sel_clk |= bits1618;
 534         else
 535                 state->sel_clk &= ~bits1618;
 536
 537         /* nv30:
 538          *      bit 0           NVClk spread spectrum on/off
 539          *      bit 2           MemClk spread spectrum on/off
 540          *      bit 4           PixClk1 spread spectrum on/off toggle
 541          *      bit 6           PixClk2 spread spectrum on/off toggle
 542          *
 543          * nv40 (observations from bios behaviour and mmio traces):
 544          *      bits 4&6        as for nv30
 545          *      bits 5&7        head dependent as for bits 4&6, but do not appear with 4&6;
 546          *                      maybe a different spread mode
 547          *      bits 8&10       seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
 548          *      The logic behind turning spread spectrum on/off in the first place,
 549          *      and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
 550          *      entry has the necessary info)
 551          */
 552         if (nv_encoder->dcb->type == OUTPUT_LVDS && pNv->SavedReg.sel_clk & 0xf0) {
 553                 int shift = (pNv->SavedReg.sel_clk & 0x50) ? 0 : 1;
 554
 555                 state->sel_clk &= ~0xf0;
 556                 state->sel_clk |= (head ? 0x40 : 0x10) << shift;
 557         }
 558 }
 559
 560 static void
 561 nv_output_prepare(xf86OutputPtr output)
 562 {
 563         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 564         NVPtr pNv = NVPTR(output->scrn);
 565         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(output->crtc);
 566         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 567
 568         output->funcs->dpms(output, DPMSModeOff);
 569
 570         /* calculate some output specific CRTC regs now, so that they can be written in nv_crtc_set_mode */
 571         if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS)
 572                 nv_digital_output_prepare_sel_clk(pNv, nv_encoder, nv_crtc->head);
 573
 574         /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f etc.) which we don't alter */
 575         if (!(regp->CRTC[NV_CIO_CRE_LCD__INDEX] & 0x44)) {
 576                 if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS) {
 577                         regp->CRTC[NV_CIO_CRE_LCD__INDEX] &= ~0x30;
 578                         regp->CRTC[NV_CIO_CRE_LCD__INDEX] |= 0x3;
 579                         if (nv_crtc->head == 0)
 580                                 regp->CRTC[NV_CIO_CRE_LCD__INDEX] |= 0x8;
 581                         else
 582                                 regp->CRTC[NV_CIO_CRE_LCD__INDEX] &= ~0x8;
 583                         if (nv_encoder->dcb->location != LOC_ON_CHIP)
 584                                 regp->CRTC[NV_CIO_CRE_LCD__INDEX] |= (nv_encoder->dcb->or << 4) & 0x30;
 585                 } else
 586                         regp->CRTC[NV_CIO_CRE_LCD__INDEX] = 0;
 587         }
 588 }
 589
 590 static void
 591 nv_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 592 {
 593         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 594         ScrnInfoPtr pScrn = output->scrn;
 595         NVPtr pNv = NVPTR(pScrn);
 596         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(output->crtc);
 597
 598         xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 599                    "%s called for encoder %d\n", __func__, nv_encoder->dcb->index);
 600
 601         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG) {
 602                 uint32_t dac_offset = nv_output_ramdac_offset(nv_encoder);
 603                 uint32_t otherdac;
 604                 int i;
 605
 606                 /* bit 16-19 are bits that are set on some G70 cards,
 607                  * but don't seem to have much effect */
 608                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + dac_offset,
 609                               nv_crtc->head << 8 | NV_RAMDAC_OUTPUT_DAC_ENABLE);
 610                 /* force any other vga encoders to bind to the other crtc */
 611                 for (i = 0; i < pNv->dcb_table.entries; i++)
 612                         if (i != nv_encoder->dcb->index && pNv->encoders[i].dcb &&
 613                             pNv->encoders[i].dcb->type == OUTPUT_ANALOG) {
 614                                 dac_offset = nv_output_ramdac_offset(&pNv->encoders[i]);
 615                                 otherdac = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + dac_offset);
 616                                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + dac_offset,
 617                                               (otherdac & ~0x100) | (nv_crtc->head ^ 1) << 8);
 618                         }
 619         }
 620         if (nv_encoder->dcb->type == OUTPUT_TMDS)
 621                 run_tmds_table(pScrn, nv_encoder->dcb, nv_crtc->head, adjusted_mode->Clock);
 622         else if (nv_encoder->dcb->type == OUTPUT_LVDS)
 623                 call_lvds_script(pScrn, nv_encoder->dcb, nv_crtc->head, LVDS_RESET, adjusted_mode->Clock);
 624
 625         /* This could use refinement for flatpanels, but it should work this way */
 626         if (pNv->NVArch < 0x44)
 627                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + nv_output_ramdac_offset(nv_encoder), 0xf0000000);
 628         else
 629                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + nv_output_ramdac_offset(nv_encoder), 0x00100000);
 630 }
 631
 632 static void
 633 nv_output_commit(xf86OutputPtr output)
 634 {
 635         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 636         ScrnInfoPtr pScrn = output->scrn;
 637         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(output->crtc);
 638
 639         output->funcs->dpms(output, DPMSModeOn);
 640
 641         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Output %s is running on CRTC %d using output %c\n", output->name, nv_crtc->head, '@' + ffs(nv_encoder->dcb->or));
 642 }
 643
 644 static void dpms_update_fp_control(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 645 {
 646         NVPtr pNv = NVPTR(pScrn);
 647         struct nouveau_crtc *nv_crtc;
 648         NVCrtcRegPtr regp;
 649         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 650         int i;
 651
 652         if (mode == DPMSModeOn) {
 653                 nv_crtc = to_nouveau_crtc(crtc);
 654                 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 655
 656                 nv_crtc->fp_users |= 1 << nv_encoder->dcb->index;
 657                 NVWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control & ~0x20000022);
 658         } else
 659                 for (i = 0; i < xf86_config->num_crtc; i++) {
 660                         nv_crtc = to_nouveau_crtc(xf86_config->crtc[i]);
 661                         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 662
 663                         nv_crtc->fp_users &= ~(1 << nv_encoder->dcb->index);
 664                         if (!nv_crtc->fp_users) {
 665                                 /* cut the FP output */
 666                                 regp->fp_control |= 0x20000022;
 667                                 NVWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
 668                         }
 669                 }
 670 }
 671
 672 static void
 673 lvds_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 674 {
 675         NVPtr pNv = NVPTR(pScrn);
 676
 677         if (nv_encoder->last_dpms == mode)
 678                 return;
 679         nv_encoder->last_dpms = mode;
 680
 681         xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 682                    "Setting dpms mode %d on lvds encoder (output %d)\n", mode, nv_encoder->dcb->index);
 683
 684         if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
 685                 /* when removing an output, crtc may not be set, but PANEL_OFF must still be run */
 686                 int head = nv_get_digital_bound_head(pNv, nv_encoder->dcb->or);
 687                 int pclk = nv_encoder->native_mode->Clock;
 688
 689                 if (crtc)
 690                         head = to_nouveau_crtc(crtc)->head;
 691
 692                 if (mode == DPMSModeOn)
 693                         call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_ON, pclk);
 694                 else
 695                         call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_OFF, pclk);
 696         }
 697
 698         dpms_update_fp_control(pScrn, nv_encoder, crtc, mode);
 699
 700         if (mode == DPMSModeOn)
 701                 nv_digital_output_prepare_sel_clk(pNv, nv_encoder, to_nouveau_crtc(crtc)->head);
 702         else {
 703                 pNv->ModeReg.sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 704                 pNv->ModeReg.sel_clk &= ~0xf0;
 705         }
 706         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
 707 }
 708
 709 static void
 710 vga_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 711 {
 712         NVPtr pNv = NVPTR(pScrn);
 713
 714         if (nv_encoder->last_dpms == mode)
 715                 return;
 716         nv_encoder->last_dpms = mode;
 717
 718         xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 719                    "Setting dpms mode %d on vga encoder (output %d)\n", mode, nv_encoder->dcb->index);
 720
 721         if (pNv->twoHeads) {
 722                 uint32_t outputval = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder));
 723
 724                 if (mode == DPMSModeOff)
 725                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 726                                       outputval & ~NV_RAMDAC_OUTPUT_DAC_ENABLE);
 727                 else if (mode == DPMSModeOn)
 728                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 729                                       outputval | NV_RAMDAC_OUTPUT_DAC_ENABLE);
 730         }
 731 }
 732
 733 static void
 734 tmds_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 735 {
 736         NVPtr pNv = NVPTR(pScrn);
 737
 738         if (nv_encoder->last_dpms == mode)
 739                 return;
 740         nv_encoder->last_dpms = mode;
 741
 742         xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 743                    "Setting dpms mode %d on tmds encoder (output %d)\n", mode, nv_encoder->dcb->index);
 744
 745         dpms_update_fp_control(pScrn, nv_encoder, crtc, mode);
 746
 747         if (nv_encoder->dcb->location != LOC_ON_CHIP) {
 748                 struct nouveau_crtc *nv_crtc;
 749                 int i;
 750
 751                 if (mode == DPMSModeOn) {
 752                         nv_crtc = to_nouveau_crtc(crtc);
 753                         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LCD__INDEX,
 754                                        pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_CIO_CRE_LCD__INDEX]);
 755                 } else
 756                         for (i = 0; i <= pNv->twoHeads; i++)
 757                                 NVWriteVgaCrtc(pNv, i, NV_CIO_CRE_LCD__INDEX,
 758                                                NVReadVgaCrtc(pNv, i, NV_CIO_CRE_LCD__INDEX) & ~((nv_encoder->dcb->or << 4) & 0x30));
 759         }
 760 }
 761
 762 static void nv_output_dpms(xf86OutputPtr output, int mode)
 763 {
 764         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 765         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 766         ScrnInfoPtr pScrn = output->scrn;
 767         xf86CrtcPtr crtc = output->crtc;
 768         NVPtr pNv = NVPTR(pScrn);
 769         int i;
 770         void (* const encoder_dpms[4])(ScrnInfoPtr, struct nouveau_encoder *, xf86CrtcPtr, int) =
 771                 /* index matches DCB type */
 772                 { vga_encoder_dpms, NULL, tmds_encoder_dpms, lvds_encoder_dpms };
 773
 774         struct nouveau_encoder *nv_encoder_i;
 775         FOR_EACH_ENCODER_IN_CONNECTOR(i, nv_connector, nv_encoder_i)
 776                 if (nv_encoder_i != nv_encoder)
 777                         encoder_dpms[nv_encoder_i->dcb->type](pScrn, nv_encoder_i, crtc, DPMSModeOff);
 778
 779         if (nv_encoder) /* may be called before encoder is picked, but iteration above solves it */
 780                 encoder_dpms[nv_encoder->dcb->type](pScrn, nv_encoder, crtc, mode);
 781 }
 782
 783 static uint32_t nv_get_clock_from_crtc(ScrnInfoPtr pScrn, RIVA_HW_STATE *state, uint8_t crtc)
 784 {
 785         NVPtr pNv = NVPTR(pScrn);
 786         struct pll_lims pll_lim;
 787         uint32_t vplla = state->crtc_reg[crtc].vpll_a;
 788         uint32_t vpllb = state->crtc_reg[crtc].vpll_b;
 789         bool nv40_single = pNv->Architecture == 0x40 &&
 790                            ((!crtc && state->reg580 & NV_RAMDAC_580_VPLL1_ACTIVE) ||
 791                             (crtc && state->reg580 & NV_RAMDAC_580_VPLL2_ACTIVE));
 792
 793         if (!get_pll_limits(pScrn, crtc ? VPLL2 : VPLL1, &pll_lim))
 794                 return 0;
 795
 796         return nv_decode_pll_highregs(pNv, vplla, vpllb, nv40_single, pll_lim.refclk);
 797 }
 798
 799 void nv_encoder_save(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
 800 {
 801         NVPtr pNv = NVPTR(pScrn);
 802
 803         if (!nv_encoder->dcb)   /* uninitialised encoder */
 804                 return;
 805
 806         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
 807                 nv_encoder->restore.output = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder));
 808         if (nv_encoder->dcb->type == OUTPUT_TMDS || nv_encoder->dcb->type == OUTPUT_LVDS)
 809                 nv_encoder->restore.head = nv_get_digital_bound_head(pNv, nv_encoder->dcb->or);
 810 }
 811
 812 void nv_encoder_restore(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
 813 {
 814         NVPtr pNv = NVPTR(pScrn);
 815         int head = nv_encoder->restore.head;
 816
 817         if (!nv_encoder->dcb)   /* uninitialised encoder */
 818                 return;
 819
 820         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
 821                 NVWriteRAMDAC(pNv, 0,
 822                               NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 823                               nv_encoder->restore.output);
 824         if (nv_encoder->dcb->type == OUTPUT_LVDS)
 825                 call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_ON,
 826                                  nv_encoder->native_mode->Clock);
 827         if (nv_encoder->dcb->type == OUTPUT_TMDS) {
 828                 int clock = nv_get_clock_from_crtc(pScrn, &pNv->SavedReg, head);
 829
 830                 run_tmds_table(pScrn, nv_encoder->dcb, head, clock);
 831         }
 832
 833         nv_encoder->last_dpms = NV_DPMS_CLEARED;
 834 }
 835
 836 static const xf86OutputFuncsRec nv_output_funcs = {
 837         .dpms = nv_output_dpms,
 838         .mode_valid = nv_output_mode_valid,
 839         .mode_fixup = nv_output_mode_fixup,
 840         .mode_set = nv_output_mode_set,
 841         .detect = nv_output_detect,
 842         .get_modes = nv_output_get_edid_modes,
 843         .destroy = nv_output_destroy,
 844         .prepare = nv_output_prepare,
 845         .commit = nv_output_commit,
 846         .create_resources = nv_output_create_resources,
 847         .set_property = nv_output_set_property,
 848 };
 849
 850 static const xf86OutputFuncsRec nv_lvds_output_funcs = {
 851         .dpms = nv_output_dpms,
 852         .mode_valid = nv_output_mode_valid,
 853         .mode_fixup = nv_output_mode_fixup,
 854         .mode_set = nv_output_mode_set,
 855         .detect = nv_output_detect,
 856         .get_modes = nv_lvds_output_get_modes,
 857         .destroy = nv_output_destroy,
 858         .prepare = nv_output_prepare,
 859         .commit = nv_output_commit,
 860         .create_resources = nv_output_create_resources,
 861         .set_property = nv_output_set_property,
 862 };
 863
 864 static void
 865 nv_add_encoder(ScrnInfoPtr pScrn, struct dcb_entry *dcbent)
 866 {
 867         NVPtr pNv = NVPTR(pScrn);
 868         struct nouveau_encoder *nv_encoder = &pNv->encoders[dcbent->index];
 869
 870         nv_encoder->dcb = dcbent;
 871         nv_encoder->last_dpms = NV_DPMS_CLEARED;
 872         nv_encoder->dithering = (pNv->FPDither || (nv_encoder->dcb->type == OUTPUT_LVDS && !pNv->VBIOS.fp.if_is_24bit));
 873         if (pNv->fpScaler) /* GPU Scaling */
 874                 nv_encoder->scaling_mode = SCALE_ASPECT;
 875         else if (nv_encoder->dcb->type == OUTPUT_LVDS)
 876                 nv_encoder->scaling_mode = SCALE_NOSCALE;
 877         else
 878                 nv_encoder->scaling_mode = SCALE_PANEL;
 879         if (xf86GetOptValString(pNv->Options, OPTION_SCALING_MODE)) {
 880                 nv_encoder->scaling_mode = nv_scaling_mode_lookup(xf86GetOptValString(pNv->Options, OPTION_SCALING_MODE), -1);
 881                 if (nv_encoder->scaling_mode == SCALE_INVALID)
 882                         nv_encoder->scaling_mode = SCALE_ASPECT; /* default */
 883         }
 884 }
 885
 886 static void
 887 nv_add_connector(ScrnInfoPtr pScrn, int i2c_index, int encoders, const xf86OutputFuncsRec *output_funcs, char *outputname)
 888 {
 889         NVPtr pNv = NVPTR(pScrn);
 890         xf86OutputPtr output;
 891         struct nouveau_connector *nv_connector;
 892
 893         if (!(output = xf86OutputCreate(pScrn, output_funcs, outputname)))
 894                 return;
 895         if (!(nv_connector = xcalloc(1, sizeof (struct nouveau_connector)))) {
 896                 xf86OutputDestroy(output);
 897                 return;
 898         }
 899
 900         output->driver_private = nv_connector;
 901
 902         if (i2c_index < 0xf)
 903                 NV_I2CInit(pScrn, &nv_connector->pDDCBus, pNv->dcb_table.i2c_read[i2c_index], xstrdup(outputname));
 904         nv_connector->possible_encoders = encoders;
 905 }
 906
 907 void NvSetupOutputs(ScrnInfoPtr pScrn)
 908 {
 909         NVPtr pNv = NVPTR(pScrn);
 910         uint16_t connectors[0x10] = { 0 };
 911         struct dcb_entry *dcbent;
 912         int i, vga_count = 0, dvid_count = 0, dvii_count = 0, lvds_count = 0;
 913
 914         if (!(pNv->encoders = xcalloc(pNv->dcb_table.entries, sizeof (struct nouveau_encoder))))
 915                 return;
 916
 917         for (i = 0; i < pNv->dcb_table.entries; i++) {
 918                 dcbent = &pNv->dcb_table.entry[i];
 919
 920                 if (dcbent->type == OUTPUT_TV)
 921                         continue;
 922                 if (dcbent->type > 3) {
 923                         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DCB type %d not known\n", dcbent->type);
 924                         continue;
 925                 }
 926
 927                 connectors[dcbent->i2c_index] |= 1 << i;
 928
 929                 nv_add_encoder(pScrn, dcbent);
 930         }
 931
 932         for (i = 0; i < pNv->dcb_table.entries; i++) {
 933                 int i2c_index = pNv->dcb_table.entry[i].i2c_index;
 934                 uint16_t encoders = connectors[i2c_index];
 935                 char outputname[20];
 936                 xf86OutputFuncsRec const *funcs = &nv_output_funcs;
 937
 938                 if (!encoders)
 939                         continue;
 940
 941                 switch (pNv->dcb_table.entry[i].type) {
 942                 case OUTPUT_ANALOG:
 943                         if (!MULTIPLE_ENCODERS(encoders))
 944                                 sprintf(outputname, "VGA-%d", vga_count++);
 945                         else
 946                                 sprintf(outputname, "DVI-I-%d", dvii_count++);
 947                         break;
 948                 case OUTPUT_TMDS:
 949                         if (!MULTIPLE_ENCODERS(encoders))
 950                                 sprintf(outputname, "DVI-D-%d", dvid_count++);
 951                         else
 952                                 sprintf(outputname, "DVI-I-%d", dvii_count++);
 953                         break;
 954                 case OUTPUT_LVDS:
 955                         sprintf(outputname, "LVDS-%d", lvds_count++);
 956                         funcs = &nv_lvds_output_funcs;
 957                         break;
 958                 default:
 959                         continue;
 960                 }
 961
 962                 nv_add_connector(pScrn, i2c_index, encoders, funcs, outputname);
 963                 connectors[i2c_index] = 0; /* avoid connectors being added multiply */
 964         }
 965 }