2 * Copyright 2003 NVIDIA, Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "nv_include.h"
26 * Override VGA I/O routines.
28 static void NVWriteCrtc(vgaHWPtr pVga, CARD8 index, CARD8 value)
30 NVPtr pNv = (NVPtr)pVga->MMIOBase;
31 volatile CARD8 *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
32 VGA_WR08(ptr, pVga->IOBase + VGA_CRTC_INDEX_OFFSET, index);
33 VGA_WR08(ptr, pVga->IOBase + VGA_CRTC_DATA_OFFSET, value);
35 static CARD8 NVReadCrtc(vgaHWPtr pVga, CARD8 index)
37 NVPtr pNv = (NVPtr)pVga->MMIOBase;
38 volatile CARD8 *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
39 VGA_WR08(ptr, pVga->IOBase + VGA_CRTC_INDEX_OFFSET, index);
40 return (VGA_RD08(ptr, pVga->IOBase + VGA_CRTC_DATA_OFFSET));
42 static void NVWriteGr(vgaHWPtr pVga, CARD8 index, CARD8 value)
44 NVPtr pNv = (NVPtr)pVga->MMIOBase;
45 VGA_WR08(pNv->PVIO0, VGA_GRAPH_INDEX, index);
46 VGA_WR08(pNv->PVIO0, VGA_GRAPH_DATA, value);
48 static CARD8 NVReadGr(vgaHWPtr pVga, CARD8 index)
50 NVPtr pNv = (NVPtr)pVga->MMIOBase;
51 VGA_WR08(pNv->PVIO0, VGA_GRAPH_INDEX, index);
52 return (VGA_RD08(pNv->PVIO0, VGA_GRAPH_DATA));
54 static void NVWriteSeq(vgaHWPtr pVga, CARD8 index, CARD8 value)
56 NVPtr pNv = (NVPtr)pVga->MMIOBase;
57 VGA_WR08(pNv->PVIO0, VGA_SEQ_INDEX, index);
58 VGA_WR08(pNv->PVIO0, VGA_SEQ_DATA, value);
60 static CARD8 NVReadSeq(vgaHWPtr pVga, CARD8 index)
62 NVPtr pNv = (NVPtr)pVga->MMIOBase;
63 VGA_WR08(pNv->PVIO0, VGA_SEQ_INDEX, index);
64 return (VGA_RD08(pNv->PVIO0, VGA_SEQ_DATA));
66 static void NVWriteAttr(vgaHWPtr pVga, CARD8 index, CARD8 value)
68 NVPtr pNv = (NVPtr)pVga->MMIOBase;
69 volatile CARD8 *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
72 tmp = VGA_RD08(ptr, pVga->IOBase + VGA_IN_STAT_1_OFFSET);
73 if (pVga->paletteEnabled)
77 VGA_WR08(ptr, VGA_ATTR_INDEX, index);
78 VGA_WR08(ptr, VGA_ATTR_DATA_W, value);
80 static CARD8 NVReadAttr(vgaHWPtr pVga, CARD8 index)
82 NVPtr pNv = (NVPtr)pVga->MMIOBase;
83 volatile CARD8 *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
86 tmp = VGA_RD08(ptr, pVga->IOBase + VGA_IN_STAT_1_OFFSET);
87 if (pVga->paletteEnabled)
91 VGA_WR08(ptr, VGA_ATTR_INDEX, index);
92 return (VGA_RD08(ptr, VGA_ATTR_DATA_R));
94 static void NVWriteMiscOut(vgaHWPtr pVga, CARD8 value)
96 NVPtr pNv = (NVPtr)pVga->MMIOBase;
97 VGA_WR08(pNv->PVIO0, VGA_MISC_OUT_W, value);
99 static CARD8 NVReadMiscOut(vgaHWPtr pVga)
101 NVPtr pNv = (NVPtr)pVga->MMIOBase;
102 return (VGA_RD08(pNv->PVIO0, VGA_MISC_OUT_R));
104 static void NVEnablePalette(vgaHWPtr pVga)
106 NVPtr pNv = (NVPtr)pVga->MMIOBase;
107 volatile CARD8 *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
110 tmp = VGA_RD08(ptr, pVga->IOBase + VGA_IN_STAT_1_OFFSET);
111 VGA_WR08(ptr, VGA_ATTR_INDEX, 0x00);
112 pVga->paletteEnabled = TRUE;
114 static void NVDisablePalette(vgaHWPtr pVga)
116 NVPtr pNv = (NVPtr)pVga->MMIOBase;
117 volatile CARD8 *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
120 tmp = VGA_RD08(ptr, pVga->IOBase + VGA_IN_STAT_1_OFFSET);
121 VGA_WR08(ptr, VGA_ATTR_INDEX, 0x20);
122 pVga->paletteEnabled = FALSE;
124 static void NVWriteDacMask(vgaHWPtr pVga, CARD8 value)
126 NVPtr pNv = (NVPtr)pVga->MMIOBase;
127 volatile CARD8 *ptr = pNv->cur_head ? pNv->PDIO1 : pNv->PDIO0;
128 VGA_WR08(ptr, VGA_DAC_MASK, value);
130 static CARD8 NVReadDacMask(vgaHWPtr pVga)
132 NVPtr pNv = (NVPtr)pVga->MMIOBase;
133 volatile CARD8 *ptr = pNv->cur_head ? pNv->PDIO1 : pNv->PDIO0;
134 return (VGA_RD08(ptr, VGA_DAC_MASK));
136 static void NVWriteDacReadAddr(vgaHWPtr pVga, CARD8 value)
138 NVPtr pNv = (NVPtr)pVga->MMIOBase;
139 volatile CARD8 *ptr = pNv->cur_head ? pNv->PDIO1 : pNv->PDIO0;
140 VGA_WR08(ptr, VGA_DAC_READ_ADDR, value);
142 static void NVWriteDacWriteAddr(vgaHWPtr pVga, CARD8 value)
144 NVPtr pNv = (NVPtr)pVga->MMIOBase;
145 volatile CARD8 *ptr = pNv->cur_head ? pNv->PDIO1 : pNv->PDIO0;
146 VGA_WR08(ptr, VGA_DAC_WRITE_ADDR, value);
148 static void NVWriteDacData(vgaHWPtr pVga, CARD8 value)
150 NVPtr pNv = (NVPtr)pVga->MMIOBase;
151 volatile CARD8 *ptr = pNv->cur_head ? pNv->PDIO1 : pNv->PDIO0;
152 VGA_WR08(ptr, VGA_DAC_DATA, value);
154 static CARD8 NVReadDacData(vgaHWPtr pVga)
156 NVPtr pNv = (NVPtr)pVga->MMIOBase;
157 volatile CARD8 *ptr = pNv->cur_head ? pNv->PDIO1 : pNv->PDIO0;
158 return (VGA_RD08(ptr, VGA_DAC_DATA));
162 NVIsConnected (ScrnInfoPtr pScrn, int output)
164 NVPtr pNv = NVPTR(pScrn);
165 CARD32 reg52C, reg608, temp;
168 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
169 "Probing for analog device on output %s...\n",
172 reg52C = NVReadRAMDAC(pNv, output, NV_RAMDAC_OUTPUT);
173 reg608 = NVReadRAMDAC(pNv, output, NV_RAMDAC_TEST_CONTROL);
175 NVWriteRAMDAC(pNv, output, NV_RAMDAC_TEST_CONTROL, (reg608 & ~0x00010000));
177 NVWriteRAMDAC(pNv, output, NV_RAMDAC_OUTPUT, (reg52C & 0x0000FEEE));
180 temp = NVReadRAMDAC(pNv, output, NV_RAMDAC_OUTPUT);
181 NVWriteRAMDAC(pNv, output, NV_RAMDAC_OUTPUT, temp | 1);
183 NVWriteRAMDAC(pNv, output, NV_RAMDAC_TEST_DATA, 0x94050140);
184 temp = NVReadRAMDAC(pNv, output, NV_RAMDAC_TEST_CONTROL);
185 NVWriteRAMDAC(pNv, output, NV_RAMDAC_TEST_CONTROL, temp | 0x1000);
189 present = (NVReadRAMDAC(pNv, output, NV_RAMDAC_TEST_CONTROL) & (1 << 28)) ? TRUE : FALSE;
192 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, " ...found one\n");
194 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, " ...can't find one\n");
196 temp = NVReadRAMDAC(pNv, output, NV_RAMDAC_TEST_CONTROL);
197 NVWriteRAMDAC(pNv, output, NV_RAMDAC_TEST_CONTROL, temp & 0x000EFFF);
199 NVWriteRAMDAC(pNv, output, NV_RAMDAC_OUTPUT, reg52C);
200 NVWriteRAMDAC(pNv, output, NV_RAMDAC_TEST_CONTROL, reg608);
206 NVSelectHeadRegisters(ScrnInfoPtr pScrn, int head)
208 NVPtr pNv = NVPTR(pScrn);
210 pNv->cur_head = head;
214 NVProbeDDC (ScrnInfoPtr pScrn, int bus)
216 NVPtr pNv = NVPTR(pScrn);
217 xf86MonPtr MonInfo = NULL;
219 if(!pNv->I2C) return NULL;
221 pNv->DDCBase = bus ? 0x36 : 0x3e;
223 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
224 "Probing for EDID on I2C bus %s...\n", bus ? "B" : "A");
226 if ((MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, pNv->I2C))) {
227 xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
228 "DDC detected a %s:\n", MonInfo->features.input_type ?
230 xf86PrintEDID( MonInfo );
232 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
233 " ... none found\n");
239 static void nv4GetConfig (NVPtr pNv)
241 uint32_t reg_FB0 = nvReadFB(pNv, NV_PFB_BOOT_0);
243 if (reg_FB0 & 0x00000100)
244 pNv->RamAmountKBytes = ((reg_FB0 >> 12) & 0x0F) * 1024 * 2 + 1024 * 2;
246 switch (reg_FB0 & 0x00000003) {
248 pNv->RamAmountKBytes = 1024 * 32;
251 pNv->RamAmountKBytes = 1024 * 4;
254 pNv->RamAmountKBytes = 1024 * 8;
258 pNv->RamAmountKBytes = 1024 * 16;
262 pNv->CrystalFreqKHz = (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & 0x00000040) ? 14318 : 13500;
263 pNv->CURSOR = &(pNv->PRAMIN[0x5E00]);
264 pNv->MinVClockFreqKHz = 12000;
265 pNv->MaxVClockFreqKHz = 350000;
268 static void nForce_check_dimms(ScrnInfoPtr pScrn)
270 uint16_t mem_ctrlr_pciid = PCI_SLOT_READ_LONG(3, 0x00) >> 16;
272 if ((mem_ctrlr_pciid == 0x1a9) || (mem_ctrlr_pciid == 0x1ab) || (mem_ctrlr_pciid == 0x1ed)) {
275 dimm[0] = (PCI_SLOT_READ_LONG(2, 0x40) >> 8) & 0x4f;
276 dimm[1] = (PCI_SLOT_READ_LONG(2, 0x44) >> 8) & 0x4f;
277 dimm[2] = (PCI_SLOT_READ_LONG(2, 0x48) >> 8) & 0x4f;
279 if (dimm[0] + dimm[1] != dimm[2])
280 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
281 "Your nForce DIMMs are not arranged in optimal banks!\n");
285 static void nv10GetConfig(ScrnInfoPtr pScrn)
287 NVPtr pNv = NVPTR(pScrn);
288 uint32_t implementation = pNv->Chipset & 0x0ff0;
290 #if X_BYTE_ORDER == X_BIG_ENDIAN
291 if (!(nvReadMC(pNv, 0x0004) & 0x01000001))
292 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
293 "Card is in big endian mode, something is very wrong !\n");
296 if (implementation == CHIPSET_NFORCE) {
297 pNv->RamAmountKBytes = (((PCI_SLOT_READ_LONG(1, 0x7c) >> 6) & 31) + 1) * 1024;
298 nForce_check_dimms(pScrn);
299 } else if (implementation == CHIPSET_NFORCE2) {
300 pNv->RamAmountKBytes = (((PCI_SLOT_READ_LONG(1, 0x84) >> 4) & 127) + 1) * 1024;
301 nForce_check_dimms(pScrn);
303 pNv->RamAmountKBytes = (nvReadFB(pNv, NV_PFB_020C) & 0xFFF00000) >> 10;
305 if (pNv->RamAmountKBytes > 256*1024)
306 pNv->RamAmountKBytes = 256*1024;
308 pNv->CrystalFreqKHz = (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & (1 << 6)) ? 14318 : 13500;
309 if (pNv->twoHeads && implementation != CHIPSET_NV11)
310 if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & (1 << 22))
311 pNv->CrystalFreqKHz = 27000;
313 pNv->CURSOR = NULL; /* can't set this here */
314 pNv->MinVClockFreqKHz = 12000;
315 pNv->MaxVClockFreqKHz = pNv->twoStagePLL ? 400000 : 350000;
319 NVCommonSetup(ScrnInfoPtr pScrn)
321 NVPtr pNv = NVPTR(pScrn);
322 vgaHWPtr pVga = VGAHWPTR(pScrn);
323 uint16_t implementation = pNv->Chipset & 0x0ff0;
326 xf86MonPtr monitorA, monitorB;
327 int FlatPanel = -1; /* really means the CRTC is slaved */
328 bool Television = false;
331 * Override VGA I/O routines.
333 pVga->writeCrtc = NVWriteCrtc;
334 pVga->readCrtc = NVReadCrtc;
335 pVga->writeGr = NVWriteGr;
336 pVga->readGr = NVReadGr;
337 pVga->writeAttr = NVWriteAttr;
338 pVga->readAttr = NVReadAttr;
339 pVga->writeSeq = NVWriteSeq;
340 pVga->readSeq = NVReadSeq;
341 pVga->writeMiscOut = NVWriteMiscOut;
342 pVga->readMiscOut = NVReadMiscOut;
343 pVga->enablePalette = NVEnablePalette;
344 pVga->disablePalette = NVDisablePalette;
345 pVga->writeDacMask = NVWriteDacMask;
346 pVga->readDacMask = NVReadDacMask;
347 pVga->writeDacWriteAddr = NVWriteDacWriteAddr;
348 pVga->writeDacReadAddr = NVWriteDacReadAddr;
349 pVga->writeDacData = NVWriteDacData;
350 pVga->readDacData = NVReadDacData;
352 * Note: There are different pointers to the CRTC/AR and GR/SEQ registers.
353 * Bastardize the intended uses of these to make it work.
355 pVga->MMIOBase = (CARD8 *)pNv;
356 pVga->MMIOOffset = 0;
358 #ifndef XSERVER_LIBPCIACCESS
359 pNv->REGS = xf86MapPciMem(pScrn->scrnIndex,
360 VIDMEM_MMIO | VIDMEM_READSIDEEFFECT,
361 pNv->PciTag, pNv->IOAddress, 0x01000000);
362 pNv->FB_BAR = xf86MapPciMem(pScrn->scrnIndex,
363 VIDMEM_MMIO | VIDMEM_READSIDEEFFECT,
364 pNv->PciTag, pNv->VRAMPhysical, 0x10000);
366 /* 0x01000000 is the size */
367 pci_device_map_range(pNv->PciInfo, pNv->IOAddress, 0x01000000, PCI_DEV_MAP_FLAG_WRITABLE, (void *)&pNv->REGS);
368 pci_device_map_range(pNv->PciInfo, pNv->VRAMPhysical, 0x10000, PCI_DEV_MAP_FLAG_WRITABLE, (void *)&pNv->FB_BAR);
369 #endif /* XSERVER_LIBPCIACCESS */
371 pNv->PRAMIN = pNv->REGS + (NV_PRAMIN_OFFSET/4);
372 pNv->PGRAPH = pNv->REGS + (NV_PGRAPH_OFFSET/4);
374 /* 8 bit registers */
375 pNv->PCIO0 = (uint8_t *)pNv->REGS + NV_PCIO0_OFFSET;
376 pNv->PDIO0 = (uint8_t *)pNv->REGS + NV_PDIO0_OFFSET;
377 pNv->PVIO0 = (uint8_t *)pNv->REGS + NV_PVIO0_OFFSET;
378 pNv->PCIO1 = pNv->PCIO0 + NV_PCIO_SIZE;
379 pNv->PDIO1 = pNv->PDIO0 + NV_PDIO_SIZE;
380 pNv->PVIO1 = pNv->PVIO0 + NV_PVIO_SIZE;
382 pNv->alphaCursor = (pNv->NVArch >= 0x11);
384 pNv->twoHeads = (pNv->Architecture >= NV_ARCH_10) &&
385 (implementation != CHIPSET_NV10) &&
386 (implementation != CHIPSET_NV15) &&
387 (implementation != CHIPSET_NFORCE) &&
388 (implementation != CHIPSET_NV20);
390 pNv->fpScaler = (pNv->FpScale && pNv->twoHeads && implementation != CHIPSET_NV11);
392 /* nv30 and nv35 have two stage PLLs, but use only one register; they are dealt with separately */
393 pNv->twoStagePLL = (implementation == CHIPSET_NV31) ||
394 (implementation == CHIPSET_NV36) ||
395 (pNv->Architecture >= NV_ARCH_40);
397 pNv->WaitVSyncPossible = (pNv->Architecture >= NV_ARCH_10) &&
398 (implementation != CHIPSET_NV10);
400 pNv->BlendingPossible = ((pNv->Chipset & 0xffff) > CHIPSET_NV04);
402 /* look for known laptop chips */
403 /* FIXME still probably missing some ids (for randr12, pre-nv40 mobile should be auto-detected) */
404 switch(pNv->Chipset & 0xffff) {
472 pNv->Television = FALSE;
475 pNv->vtOWNER = NVReadVgaCrtc(pNv, 0, NV_CIO_CRE_44);
476 if (pNv->NVArch == 0x11) { /* reading OWNER is broken on nv11 */
477 if (nvReadMC(pNv, NV_PBUS_DEBUG_1) & (1 << 28)) /* heads tied, restore both */
480 uint8_t slaved_on_A, slaved_on_B;
483 NVLockVgaCrtc(pNv, 1, false);
485 slaved_on_B = NVReadVgaCrtc(pNv, 1, NV_CIO_CRE_PIXEL_INDEX) & 0x80;
487 tvB = !(NVReadVgaCrtc(pNv, 1, NV_CIO_CRE_LCD__INDEX) & 0x01);
490 NVLockVgaCrtc(pNv, 0, false);
492 slaved_on_A = NVReadVgaCrtc(pNv, 0, NV_CIO_CRE_PIXEL_INDEX) & 0x80;
494 tvA = !(NVReadVgaCrtc(pNv, 0, NV_CIO_CRE_LCD__INDEX) & 0x01);
496 if (slaved_on_A && !tvA)
498 else if (slaved_on_B && !tvB)
500 else if (slaved_on_A)
502 else if (slaved_on_B)
509 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Initial CRTC_OWNER is %d\n", pNv->vtOWNER);
512 /* Parse the bios to initialize the card */
515 if (pNv->Architecture == NV_ARCH_04)
518 nv10GetConfig(pScrn);
520 if (!pNv->randr12_enable) {
522 NVSelectHeadRegisters(pScrn, 0);
524 NVLockUnlock(pScrn, 0);
530 pNv->crtc_active[0] = TRUE;
531 pNv->crtc_active[1] = FALSE;
532 if((monitorA = NVProbeDDC(pScrn, 0))) {
533 FlatPanel = monitorA->features.input_type ? 1 : 0;
535 /* NV4 doesn't support FlatPanels */
536 if((pNv->Chipset & 0x0fff) <= CHIPSET_NV04)
539 if(nvReadCurVGA(pNv, NV_CIO_CRE_PIXEL_INDEX) & 0x80) {
540 if(!(nvReadCurVGA(pNv, NV_CIO_CRE_LCD__INDEX) & 0x01))
546 xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
547 "HW is currently programmed for %s\n",
548 FlatPanel ? (Television ? "TV" : "DFP") : "CRT");
551 if(pNv->FlatPanel == -1) {
552 pNv->FlatPanel = FlatPanel;
553 pNv->Television = Television;
555 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
556 "Forcing display type to %s as specified\n",
557 pNv->FlatPanel ? "DFP" : "CRT");
560 CARD8 outputAfromCRTC, outputBfromCRTC;
561 pNv->crtc_active[0] = FALSE;
562 pNv->crtc_active[1] = FALSE;
563 CARD8 slaved_on_A, slaved_on_B;
564 Bool analog_on_A, analog_on_B;
568 if(implementation != CHIPSET_NV11) {
569 if(NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT) & 0x100)
573 if(NVReadRAMDAC(pNv, 1, NV_RAMDAC_OUTPUT) & 0x100)
577 analog_on_A = NVIsConnected(pScrn, 0);
578 analog_on_B = NVIsConnected(pScrn, 1);
588 nvWriteCurVGA(pNv, NV_CIO_CRE_44, 3);
589 NVSelectHeadRegisters(pScrn, 1);
590 NVLockUnlock(pScrn, 0);
592 slaved_on_B = nvReadCurVGA(pNv, NV_CIO_CRE_PIXEL_INDEX) & 0x80;
594 tvB = !(nvReadCurVGA(pNv, NV_CIO_CRE_LCD__INDEX) & 0x01);
597 nvWriteCurVGA(pNv, NV_CIO_CRE_44, 0);
598 NVSelectHeadRegisters(pScrn, 0);
599 NVLockUnlock(pScrn, 0);
601 slaved_on_A = nvReadCurVGA(pNv, NV_CIO_CRE_PIXEL_INDEX) & 0x80;
603 tvA = !(nvReadCurVGA(pNv, NV_CIO_CRE_LCD__INDEX) & 0x01);
606 oldhead = NVReadCRTC(pNv, 0, NV_CRTC_FSEL);
607 NVWriteCRTC(pNv, 0, NV_CRTC_FSEL, oldhead | 0x00000010);
609 monitorA = NVProbeDDC(pScrn, 0);
610 monitorB = NVProbeDDC(pScrn, 1);
612 if(slaved_on_A && !tvA) {
613 pNv->crtc_active[0] = TRUE;
615 xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
616 "CRTC 0 is currently programmed for DFP\n");
618 if(slaved_on_B && !tvB) {
619 pNv->crtc_active[1] = TRUE;
621 xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
622 "CRTC 1 is currently programmed for DFP\n");
625 pNv->crtc_active[outputAfromCRTC] = TRUE;
627 xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
628 "CRTC %i appears to have a CRT attached\n", pNv->crtc_active[1]);
631 pNv->crtc_active[outputBfromCRTC] = TRUE;
633 xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
634 "CRTC %i appears to have a CRT attached\n", pNv->crtc_active[1]);
637 pNv->crtc_active[0] = TRUE;
640 xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
641 "CRTC 0 is currently programmed for TV\n");
644 pNv->crtc_active[1] = TRUE;
647 xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
648 "CRTC 1 is currently programmed for TV\n");
651 FlatPanel = monitorA->features.input_type ? 1 : 0;
654 FlatPanel = monitorB->features.input_type ? 1 : 0;
657 if(pNv->FlatPanel == -1) {
658 if(FlatPanel != -1) {
659 pNv->FlatPanel = FlatPanel;
660 pNv->Television = Television;
662 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
663 "Unable to detect display type...\n");
665 xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT,
666 "...On a laptop, assuming DFP\n");
669 xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT,
670 "...Using default of CRT\n");
675 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
676 "Forcing display type to %s as specified\n",
677 pNv->FlatPanel ? "DFP" : "CRT");
680 if(!(pNv->crtc_active[0]) && !(pNv->crtc_active[1])) {
681 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
682 "Unable to detect which CRTC is used...\n");
684 pNv->crtc_active[1] = TRUE;
686 pNv->crtc_active[0] = TRUE;
688 xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT,
689 "...Defaulting to CRTCNumber %i\n", pNv->crtc_active[1]);
693 if((monitorA->features.input_type && pNv->FlatPanel) ||
694 (!monitorA->features.input_type && !pNv->FlatPanel))
707 if((monitorB->features.input_type && !pNv->FlatPanel) ||
708 (!monitorB->features.input_type && pNv->FlatPanel))
717 if(implementation == CHIPSET_NV11)
718 cr44 = pNv->crtc_active[1] * 0x3;
720 NVWriteCRTC(pNv, 0, NV_CRTC_FSEL, oldhead);
722 nvWriteCurVGA(pNv, NV_CIO_CRE_44, cr44);
723 NVSelectHeadRegisters(pScrn, pNv->crtc_active[1]);
726 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
727 "Using %s on CRTC %i\n",
728 pNv->FlatPanel ? (pNv->Television ? "TV" : "DFP") : "CRT",
729 pNv->crtc_active[1]);
731 if(pNv->FlatPanel && !pNv->Television) {
732 pNv->fpWidth = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_HDISP_END) + 1;
733 pNv->fpHeight = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_VDISP_END) + 1;
734 pNv->fpSyncs = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_CONTROL) & 0x30000033;
735 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Panel size is %i x %i\n",
736 pNv->fpWidth, pNv->fpHeight);
740 xf86SetDDCproperties(pScrn, monitorA);
742 if(!pNv->FlatPanel || (pScrn->depth != 24) || !pNv->twoHeads)
743 pNv->FPDither = FALSE;
746 if(pNv->FlatPanel && pNv->twoHeads) {
747 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_TMDS_CONTROL, 0x00010004);
748 if(NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_TMDS_DATA) & 1)
750 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel is %s\n",
751 pNv->LVDS ? "LVDS" : "TMDS");