git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  50 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  51 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  52 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  53 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  54 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  55 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  56 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  57
  58 static uint32_t NVCrtcReadCRTC(xf86CrtcPtr crtc, uint32_t reg)
  59 {
  60         ScrnInfoPtr pScrn = crtc->scrn;
  61         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  62         NVPtr pNv = NVPTR(pScrn);
  63
  64         return NVReadCRTC(pNv, nv_crtc->head, reg);
  65 }
  66
  67 void NVCrtcWriteCRTC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  68 {
  69         ScrnInfoPtr pScrn = crtc->scrn;
  70         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  71         NVPtr pNv = NVPTR(pScrn);
  72
  73         NVWriteCRTC(pNv, nv_crtc->head, reg, val);
  74 }
  75
  76 static uint32_t NVCrtcReadRAMDAC(xf86CrtcPtr crtc, uint32_t reg)
  77 {
  78         ScrnInfoPtr pScrn = crtc->scrn;
  79         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  80         NVPtr pNv = NVPTR(pScrn);
  81
  82         return NVReadRAMDAC(pNv, nv_crtc->head, reg);
  83 }
  84
  85 void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  86 {
  87         ScrnInfoPtr pScrn = crtc->scrn;
  88         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  89         NVPtr pNv = NVPTR(pScrn);
  90
  91         NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
  92 }
  93
  94 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool lock)
  95 {
  96         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  97         ScrnInfoPtr pScrn = crtc->scrn;
  98         NVPtr pNv = NVPTR(pScrn);
  99
 100         if (pNv->twoHeads)
 101                 NVSetOwner(pScrn, nv_crtc->head);
 102         NVLockVgaCrtc(pNv, nv_crtc->head, lock);
 103 }
 104
 105 static xf86OutputPtr
 106 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 107 {
 108         ScrnInfoPtr pScrn = crtc->scrn;
 109         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 110         int i;
 111         for (i = 0; i < xf86_config->num_output; i++) {
 112                 xf86OutputPtr output = xf86_config->output[i];
 113
 114                 if (output->crtc == crtc) {
 115                         return output;
 116                 }
 117         }
 118
 119         return NULL;
 120 }
 121
 122 static xf86CrtcPtr
 123 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 124 {
 125         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 126         int i;
 127
 128         for (i = 0; i < xf86_config->num_crtc; i++) {
 129                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 130                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 131                 if (nv_crtc->head == index)
 132                         return crtc;
 133         }
 134
 135         return NULL;
 136 }
 137
 138 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 139 /* They are only valid for NV4x, appearantly reordered for NV5x */
 140 /* gpu pll: 0x4000 + 0x4004
 141  * unknown pll: 0x4008 + 0x400c
 142  * vpll1: 0x4010 + 0x4014
 143  * vpll2: 0x4018 + 0x401c
 144  * unknown pll: 0x4020 + 0x4024
 145  * unknown pll: 0x4038 + 0x403c
 146  * Some of the unknown's are probably memory pll's.
 147  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 148  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 149  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 150  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 151  *     bit8: A switch that turns of the second divider and multiplier off.
 152  *     bit12: Also a switch, i haven't seen it yet.
 153  *     bit16-19: p-divider
 154  *     but 28-31: Something related to the mode that is used (see bit8).
 155  * 2) bit0-7: m-divider (a)
 156  *     bit8-15: n-multiplier (a)
 157  *     bit16-23: m-divider (b)
 158  *     bit24-31: n-multiplier (b)
 159  */
 160
 161 /* Modifying the gpu pll for example requires:
 162  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 163  * This is not needed for the vpll's which have their own bits.
 164  */
 165
 166 static void nv_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
 167
 168 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 169 {
 170         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 171         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 172         ScrnInfoPtr pScrn = crtc->scrn;
 173         NVPtr pNv = NVPTR(pScrn);
 174         /* The TMDS_PLL switch is on the actual ramdac */
 175         int fp_head = nv_crtc->head ^ state->crosswired;
 176         uint32_t fp_debug_0 = NVReadRAMDAC(pNv, fp_head, NV_RAMDAC_FP_DEBUG_0);
 177
 178         if (regp->vpll_changed) {
 179                 uint32_t savedc040 = nvReadMC(pNv, 0xc040);
 180
 181                 NVWriteRAMDAC(pNv, fp_head, NV_RAMDAC_FP_DEBUG_0,
 182                         fp_debug_0 | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 183
 184                 /* Wait for the situation to stabilise */
 185                 usleep(5000);
 186
 187                 /* for vpll1 change bits 16 and 17 are disabled */
 188                 /* for vpll2 change bits 18 and 19 are disabled */
 189                 nvWriteMC(pNv, 0xc040, savedc040 & ~(3 << (16 + nv_crtc->head * 2)));
 190
 191                 nv_crtc_load_state_pll(crtc, state);
 192
 193                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_580 %08X\n", state->reg580);
 194                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
 195
 196                 /* We need to wait a while */
 197                 usleep(5000);
 198                 nvWriteMC(pNv, 0xc040, savedc040);
 199
 200                 NVWriteRAMDAC(pNv, fp_head, NV_RAMDAC_FP_DEBUG_0, fp_debug_0);
 201         }
 202 }
 203
 204 static void nv_crtc_save_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 205 {
 206         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 207         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 208         NVPtr pNv = NVPTR(crtc->scrn);
 209
 210         if (nv_crtc->head) {
 211                 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 212                 if (pNv->twoStagePLL && pNv->NVArch != 0x30)
 213                         regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 214         } else {
 215                 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 216                 if (pNv->twoStagePLL && pNv->NVArch != 0x30)
 217                         regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 218         }
 219         if (pNv->twoHeads)
 220                 state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 221         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 222         if (pNv->Architecture == NV_ARCH_40)
 223                 state->reg580 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_580);
 224 }
 225
 226 static void nv_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 227 {
 228         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 229         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 230         ScrnInfoPtr pScrn = crtc->scrn;
 231         NVPtr pNv = NVPTR(pScrn);
 232
 233         /* This sequence is important, the NV28 is very sensitive in this area. */
 234         /* Keep pllsel last and sel_clk first. */
 235         if (pNv->twoHeads) {
 236                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_SEL_CLK %08X\n", state->sel_clk);
 237                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
 238         }
 239
 240         if (regp->vpll_changed) {
 241                 regp->vpll_changed = false;
 242
 243                 if (nv_crtc->head) {
 244                         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL2 %08X\n", regp->vpll_a);
 245                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, regp->vpll_a);
 246                         if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 247                                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL2_B %08X\n", regp->vpll_b);
 248                                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, regp->vpll_b);
 249                         }
 250                 } else {
 251                         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL %08X\n", regp->vpll_a);
 252                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, regp->vpll_a);
 253                         if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 254                                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL_B %08X\n", regp->vpll_b);
 255                                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, regp->vpll_b);
 256                         }
 257                 }
 258         }
 259
 260         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_PLL_SELECT %08X\n", state->pllsel);
 261         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 262 }
 263
 264 /* Calculate extended mode parameters (SVGA) and save in a mode state structure */
 265 static void nv_crtc_calc_state_ext(xf86CrtcPtr crtc, DisplayModePtr mode, int dotClock)
 266 {
 267         ScrnInfoPtr pScrn = crtc->scrn;
 268         NVPtr pNv = NVPTR(pScrn);
 269         uint32_t pixelDepth, VClk = 0;
 270         uint32_t CursorStart;
 271         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 272         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 273         RIVA_HW_STATE *state = &pNv->ModeReg;
 274         uint32_t old_clock_a = 0, old_clock_b = 0;
 275         struct pll_lims pll_lim;
 276         int NM1 = 0xbeef, NM2 = 0xdead, log2P = 0;
 277         uint32_t g70_pll_special_bits = 0;
 278         Bool nv4x_single_stage_pll_mode = FALSE;
 279         int bpp;
 280
 281         /* Store old clock. */
 282         old_clock_a = regp->vpll_a;
 283         old_clock_b = regp->vpll_b;
 284
 285         /*
 286          * Extended RIVA registers.
 287          */
 288
 289         /* This is pitch related, not mode related. */
 290         if (pScrn->depth < 24)
 291                 bpp = pScrn->depth;
 292         else
 293                 bpp = 32;
 294         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 295                 bpp = pNv->console_mode[nv_crtc->head].bpp;
 296         }
 297
 298         pixelDepth = (bpp + 1)/8;
 299
 300         if (nv_crtc->head == 0) {
 301                 if (!get_pll_limits(pScrn, VPLL1, &pll_lim))
 302                         return;
 303         } else
 304                 if (!get_pll_limits(pScrn, VPLL2, &pll_lim))
 305                         return;
 306
 307         if (pNv->twoStagePLL) {
 308                 if (dotClock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* use a single VCO */
 309                         nv4x_single_stage_pll_mode = TRUE;
 310                         /* Turn the second set of divider and multiplier off */
 311                         /* Bogus data, the same nvidia uses */
 312                         NM2 = 0x11f;
 313                         VClk = getMNP_single(pScrn, &pll_lim, dotClock, &NM1, &log2P);
 314                 } else
 315                         VClk = getMNP_double(pScrn, &pll_lim, dotClock, &NM1, &NM2, &log2P);
 316         } else
 317                 VClk = getMNP_single(pScrn, &pll_lim, dotClock, &NM1, &log2P);
 318
 319         /* Are these all the (relevant) G70 cards? */
 320         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 321                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 322                 /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 323                 if (nv4x_single_stage_pll_mode)
 324                         g70_pll_special_bits = 0x1;
 325                 else
 326                         g70_pll_special_bits = 0x3;
 327         }
 328
 329         if (pNv->NVArch == 0x30)
 330                 /* See nvregisters.xml for details. */
 331                 regp->vpll_a = log2P << 16 | NM1 | (NM2 & 7) << 4 | ((NM2 >> 8) & 7) << 19 | ((NM2 >> 11) & 3) << 24 | NV30_RAMDAC_ENABLE_VCO2;
 332         else
 333                 regp->vpll_a = g70_pll_special_bits << 30 | log2P << 16 | NM1;
 334         regp->vpll_b = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 335
 336         if (nv4x_single_stage_pll_mode) {
 337                 if (nv_crtc->head == 0)
 338                         state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 339                 else
 340                         state->reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 341         } else {
 342                 if (nv_crtc->head == 0)
 343                         state->reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 344                 else
 345                         state->reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 346         }
 347
 348         if (!pNv->twoStagePLL || nv4x_single_stage_pll_mode)
 349                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n %d m %d log2p %d\n", NM1 >> 8, NM1 & 0xff, log2P);
 350         else
 351                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P);
 352
 353         /* Changing clocks gives a delay, which is not always needed. */
 354         if (old_clock_a != regp->vpll_a || old_clock_b != regp->vpll_b)
 355                 regp->vpll_changed = true;
 356
 357         switch (pNv->Architecture) {
 358         case NV_ARCH_04:
 359                 nv4UpdateArbitrationSettings(VClk,
 360                                                 pixelDepth * 8,
 361                                                 &(state->arbitration0),
 362                                                 &(state->arbitration1),
 363                                                 pNv);
 364                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 365                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 366                 if (mode->Flags & V_DBLSCAN)
 367                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 368                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 369                 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 370                 state->config = 0x00001114;
 371                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = mode->CrtcHDisplay < 1280 ? 0x04 : 0x00;
 372                 break;
 373         case NV_ARCH_10:
 374         case NV_ARCH_20:
 375         case NV_ARCH_30:
 376         default:
 377                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 378                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 379                         state->arbitration0 = 128;
 380                         state->arbitration1 = 0x0480;
 381                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 382                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 383                         nForceUpdateArbitrationSettings(VClk,
 384                                                 pixelDepth * 8,
 385                                                 &(state->arbitration0),
 386                                                 &(state->arbitration1),
 387                                                 pNv);
 388                 } else if (pNv->Architecture < NV_ARCH_30) {
 389                         nv10UpdateArbitrationSettings(VClk,
 390                                                 pixelDepth * 8,
 391                                                 &(state->arbitration0),
 392                                                 &(state->arbitration1),
 393                                                 pNv);
 394                 } else {
 395                         nv30UpdateArbitrationSettings(pNv,
 396                                                 &(state->arbitration0),
 397                                                 &(state->arbitration1));
 398                 }
 399
 400                 if (nv_crtc->head == 1) {
 401                         CursorStart = pNv->Cursor2->offset;
 402                 } else {
 403                         CursorStart = pNv->Cursor->offset;
 404                 }
 405
 406                 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 407                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 408                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 409                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 410                 } else {
 411                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x0;
 412                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0x0;
 413                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x0;
 414                 }
 415
 416                 if (mode->Flags & V_DBLSCAN)
 417                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 418
 419                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
 420                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = mode->CrtcHDisplay < 1280 ? 0x04 : 0x00;
 421                 break;
 422         }
 423
 424         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 425                 /* This is a bit of a guess. */
 426                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] |= 0xB8;
 427         }
 428
 429         /* The NV40 seems to have more similarities to NV3x than other cards. */
 430         if (pNv->NVArch < 0x41) {
 431                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
 432                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
 433         }
 434
 435         if (nv_crtc->head == 1) {
 436                 if (!nv4x_single_stage_pll_mode) {
 437                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 438                 } else {
 439                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 440                 }
 441                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
 442         } else {
 443                 if (!nv4x_single_stage_pll_mode) {
 444                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 445                 } else {
 446                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 447                 }
 448                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
 449         }
 450
 451         /* The blob uses this always, so let's do the same */
 452         if (pNv->Architecture == NV_ARCH_40) {
 453                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
 454         }
 455
 456         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
 457         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
 458         if (pNv->Architecture >= NV_ARCH_30) {
 459                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
 460         }
 461
 462         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 463                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = ((mode->CrtcHDisplay/16) & 0x700) >> 3;
 464         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 465                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((mode->CrtcHDisplay*bpp)/64) & 0x700) >> 3;
 466         } else { /* framebuffer can be larger than crtc scanout area. */
 467                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((pScrn->displayWidth/8) * pixelDepth) & 0x700) >> 3;
 468         }
 469         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
 470 }
 471
 472 static void
 473 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
 474 {
 475         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 476         ScrnInfoPtr pScrn = crtc->scrn;
 477         NVPtr pNv = NVPTR(pScrn);
 478         unsigned char seq1 = 0, crtc17 = 0;
 479         unsigned char crtc1A;
 480
 481         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_dpms is called for CRTC %d with mode %d.\n", nv_crtc->head, mode);
 482
 483         if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
 484                 return;
 485
 486         nv_crtc->last_dpms = mode;
 487
 488         if (pNv->twoHeads)
 489                 NVSetOwner(pScrn, nv_crtc->head);
 490
 491         crtc1A = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
 492         switch(mode) {
 493                 case DPMSModeStandby:
 494                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
 495                 seq1 = 0x20;
 496                 crtc17 = 0x80;
 497                 crtc1A |= 0x80;
 498                 break;
 499         case DPMSModeSuspend:
 500                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
 501                 seq1 = 0x20;
 502                 crtc17 = 0x80;
 503                 crtc1A |= 0x40;
 504                 break;
 505         case DPMSModeOff:
 506                 /* Screen: Off; HSync: Off, VSync: Off */
 507                 seq1 = 0x20;
 508                 crtc17 = 0x00;
 509                 crtc1A |= 0xC0;
 510                 break;
 511         case DPMSModeOn:
 512         default:
 513                 /* Screen: On; HSync: On, VSync: On */
 514                 seq1 = 0x00;
 515                 crtc17 = 0x80;
 516                 break;
 517         }
 518
 519         NVVgaSeqReset(pNv, nv_crtc->head, true);
 520         /* Each head has it's own sequencer, so we can turn it off when we want */
 521         seq1 |= (NVReadVgaSeq(pNv, nv_crtc->head, 0x01) & ~0x20);
 522         NVWriteVgaSeq(pNv, nv_crtc->head, 0x1, seq1);
 523         crtc17 |= (NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_MODECTL) & ~0x80);
 524         usleep(10000);
 525         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_MODECTL, crtc17);
 526         NVVgaSeqReset(pNv, nv_crtc->head, false);
 527
 528         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1, crtc1A);
 529 }
 530
 531 static Bool
 532 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
 533                      DisplayModePtr adjusted_mode)
 534 {
 535         return TRUE;
 536 }
 537
 538 static void
 539 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 540 {
 541         ScrnInfoPtr pScrn = crtc->scrn;
 542         NVPtr pNv = NVPTR(pScrn);
 543         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 544         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 545         int depth = pScrn->depth;
 546
 547         /* Calculate our timings */
 548         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
 549         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
 550         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
 551         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
 552         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
 553         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
 554         int vertDisplay         = mode->CrtcVDisplay                    - 1;
 555         int vertStart           = mode->CrtcVSyncStart          - 1;
 556         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
 557         int vertTotal           = mode->CrtcVTotal                      - 2;
 558         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
 559         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
 560
 561         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 562         bool fp_output = false;
 563         int i;
 564
 565         for (i = 0; i < xf86_config->num_output; i++) {
 566                 xf86OutputPtr output = xf86_config->output[i];
 567                 NVOutputPrivatePtr nv_output = output->driver_private;
 568
 569                 if (output->crtc == crtc && (nv_output->type == OUTPUT_LVDS || nv_output->type == OUTPUT_TMDS))
 570                         fp_output = true;
 571         }
 572
 573         /* This is pitch/memory size related. */
 574         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE))
 575                 depth = pNv->console_mode[nv_crtc->head].bpp;
 576
 577         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Mode clock: %d\n", mode->Clock);
 578         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Adjusted mode clock: %d\n", adjusted_mode->Clock);
 579
 580         if (fp_output) {
 581                 vertStart = vertTotal - 3;
 582                 vertEnd = vertTotal - 2;
 583                 vertBlankStart = vertStart;
 584                 horizStart = horizTotal - 5;
 585                 horizEnd = horizTotal - 2;
 586                 horizBlankEnd = horizTotal + 4;
 587                 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10)
 588                         /* This reportedly works around some video overlay bandwidth problems */
 589                         horizTotal += 2;
 590         }
 591
 592         if (mode->Flags & V_INTERLACE)
 593                 vertTotal |= 1;
 594
 595 #if 0
 596         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
 597         ErrorF("horizStart: 0x%X \n", horizStart);
 598         ErrorF("horizEnd: 0x%X \n", horizEnd);
 599         ErrorF("horizTotal: 0x%X \n", horizTotal);
 600         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
 601         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
 602         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
 603         ErrorF("vertStart: 0x%X \n", vertStart);
 604         ErrorF("vertEnd: 0x%X \n", vertEnd);
 605         ErrorF("vertTotal: 0x%X \n", vertTotal);
 606         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
 607         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
 608 #endif
 609
 610         /*
 611         * compute correct Hsync & Vsync polarity
 612         */
 613         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
 614                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
 615
 616                 regp->MiscOutReg = 0x23;
 617                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
 618                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
 619         } else {
 620                 int VDisplay = mode->VDisplay;
 621                 if (mode->Flags & V_DBLSCAN)
 622                         VDisplay *= 2;
 623                 if (mode->VScan > 1)
 624                         VDisplay *= mode->VScan;
 625                 if (VDisplay < 400) {
 626                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
 627                 } else if (VDisplay < 480) {
 628                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
 629                 } else if (VDisplay < 768) {
 630                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
 631                 } else {
 632                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
 633                 }
 634         }
 635
 636         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
 637
 638         /*
 639         * Time Sequencer
 640         */
 641         regp->Sequencer[0] = 0x00;
 642         /* 0x20 disables the sequencer */
 643         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 644                 if (mode->HDisplay == 720) {
 645                         regp->Sequencer[1] = 0x21; /* enable 9/8 mode */
 646                 } else {
 647                         regp->Sequencer[1] = 0x20;
 648                 }
 649         } else {
 650                 if (mode->Flags & V_CLKDIV2) {
 651                         regp->Sequencer[1] = 0x29;
 652                 } else {
 653                         regp->Sequencer[1] = 0x21;
 654                 }
 655         }
 656         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 657                 regp->Sequencer[2] = 0x03; /* select 2 out of 4 planes */
 658         } else {
 659                 regp->Sequencer[2] = 0x0F;
 660         }
 661         regp->Sequencer[3] = 0x00;                     /* Font select */
 662         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 663                 regp->Sequencer[4] = 0x02;
 664         } else {
 665                 regp->Sequencer[4] = 0x0E;                             /* Misc */
 666         }
 667
 668         /*
 669         * CRTC Controller
 670         */
 671         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
 672         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
 673         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
 674         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
 675                                 | SetBit(7);
 676         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
 677         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
 678                                 | SetBitField(horizEnd,4:0,4:0);
 679         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
 680         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
 681                                 | SetBitField(vertDisplay,8:8,1:1)
 682                                 | SetBitField(vertStart,8:8,2:2)
 683                                 | SetBitField(vertBlankStart,8:8,3:3)
 684                                 | SetBit(4)
 685                                 | SetBitField(vertTotal,9:9,5:5)
 686                                 | SetBitField(vertDisplay,9:9,6:6)
 687                                 | SetBitField(vertStart,9:9,7:7);
 688         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
 689         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
 690                                 | SetBit(6)
 691                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00)
 692                                 | (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0xF : 0x00); /* 8x15 chars */
 693         if (NVMatchModePrivate(mode, NV_MODE_VGA)) { /* Were do these cursor offsets come from? */
 694                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0xD; /* start scanline */
 695                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0xE; /* end scanline */
 696         } else {
 697                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0x00;
 698                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0x00;
 699         }
 700         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
 701         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
 702         regp->CRTC[0xe] = 0x00;
 703         regp->CRTC[0xf] = 0x00;
 704         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
 705         /* What is the meaning of bit5, it is empty in the vga spec. */
 706         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) |
 707                                                                         (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0 : SetBit(5));
 708         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
 709         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 710                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = (mode->CrtcHDisplay/16);
 711         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 712                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((mode->CrtcHDisplay*depth)/64);
 713         } else { /* framebuffer can be larger than crtc scanout area. */
 714                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pScrn->bitsPerPixel/8));
 715         }
 716         if (depth == 4) { /* How can these values be calculated? */
 717                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x1F;
 718         } else {
 719                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x00;
 720         }
 721         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
 722         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
 723         /* 0x80 enables the sequencer, we don't want that */
 724         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 725                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xA3 & ~0x80;
 726         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 727                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
 728         } else {
 729                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
 730         }
 731         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
 732
 733         /*
 734          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
 735          */
 736
 737         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
 738                                 | SetBitField(vertBlankStart,10:10,3:3)
 739                                 | SetBitField(vertStart,10:10,2:2)
 740                                 | SetBitField(vertDisplay,10:10,1:1)
 741                                 | SetBitField(vertTotal,10:10,0:0);
 742
 743         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
 744                                 | SetBitField(horizDisplay,8:8,1:1)
 745                                 | SetBitField(horizBlankStart,8:8,2:2)
 746                                 | SetBitField(horizStart,8:8,3:3);
 747
 748         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
 749                                 | SetBitField(vertDisplay,11:11,2:2)
 750                                 | SetBitField(vertStart,11:11,4:4)
 751                                 | SetBitField(vertBlankStart,11:11,6:6);
 752
 753         if(mode->Flags & V_INTERLACE) {
 754                 horizTotal = (horizTotal >> 1) & ~1;
 755                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
 756                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
 757         } else {
 758                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
 759         }
 760
 761         /*
 762         * Graphics Display Controller
 763         */
 764         regp->Graphics[0] = 0x00;
 765         regp->Graphics[1] = 0x00;
 766         regp->Graphics[2] = 0x00;
 767         regp->Graphics[3] = 0x00;
 768         regp->Graphics[4] = 0x00;
 769         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 770                 regp->Graphics[5] = 0x10;
 771                 regp->Graphics[6] = 0x0E; /* map 32k mem */
 772                 regp->Graphics[7] = 0x00;
 773         } else {
 774                 regp->Graphics[5] = 0x40; /* 256 color mode */
 775                 regp->Graphics[6] = 0x05; /* map 64k mem + graphic mode */
 776                 regp->Graphics[7] = 0x0F;
 777         }
 778         regp->Graphics[8] = 0xFF;
 779
 780         regp->Attribute[0]  = 0x00; /* standard colormap translation */
 781         regp->Attribute[1]  = 0x01;
 782         regp->Attribute[2]  = 0x02;
 783         regp->Attribute[3]  = 0x03;
 784         regp->Attribute[4]  = 0x04;
 785         regp->Attribute[5]  = 0x05;
 786         regp->Attribute[6]  = 0x06;
 787         regp->Attribute[7]  = 0x07;
 788         regp->Attribute[8]  = 0x08;
 789         regp->Attribute[9]  = 0x09;
 790         regp->Attribute[10] = 0x0A;
 791         regp->Attribute[11] = 0x0B;
 792         regp->Attribute[12] = 0x0C;
 793         regp->Attribute[13] = 0x0D;
 794         regp->Attribute[14] = 0x0E;
 795         regp->Attribute[15] = 0x0F;
 796         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 797                 regp->Attribute[16] = 0x0C; /* Line Graphics Enable + Blink enable */
 798         } else {
 799                 regp->Attribute[16] = 0x01; /* Enable graphic mode */
 800         }
 801         /* Non-vga */
 802         regp->Attribute[17] = 0x00;
 803         regp->Attribute[18] = 0x0F; /* enable all color planes */
 804         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 805                 regp->Attribute[19] = 0x08; /* shift bits by 8 */
 806         } else {
 807                 regp->Attribute[19] = 0x00;
 808         }
 809         regp->Attribute[20] = 0x00;
 810 }
 811
 812 /**
 813  * Sets up registers for the given mode/adjusted_mode pair.
 814  *
 815  * The clocks, CRTCs and outputs attached to this CRTC must be off.
 816  *
 817  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
 818  * be easily turned on/off after this.
 819  */
 820 static void
 821 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 822 {
 823         ScrnInfoPtr pScrn = crtc->scrn;
 824         NVPtr pNv = NVPTR(pScrn);
 825         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 826         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 827         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
 828         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 829         bool lvds_output = false;
 830         bool fp_output = false;
 831         int i;
 832
 833         for (i = 0; i < xf86_config->num_output; i++) {
 834                 xf86OutputPtr output = xf86_config->output[i];
 835                 NVOutputPrivatePtr nv_output = output->driver_private;
 836
 837                 if (output->crtc == crtc && nv_output->type == OUTPUT_LVDS)
 838                         lvds_output = true;
 839                 if (lvds_output || (output->crtc == crtc && nv_output->type == OUTPUT_TMDS))
 840                         fp_output = true;
 841         }
 842
 843         /* Registers not directly related to the (s)vga mode */
 844
 845         /* bit2 = 0 -> fine pitched crtc granularity */
 846         /* The rest disables double buffering on CRTC access */
 847         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
 848
 849         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
 850                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
 851                 if (nv_crtc->head == 0) {
 852                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
 853                 }
 854
 855                 if (fp_output) {
 856                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0);
 857                         if (!NVMatchModePrivate(mode, NV_MODE_VGA)) {
 858                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 1);
 859                         }
 860                 }
 861         } else {
 862                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
 863                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
 864         }
 865
 866         /* Sometimes 0x10 is used, what is this? */
 867         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
 868         /* Some kind of tmds switch for older cards */
 869         if (pNv->Architecture < NV_ARCH_40) {
 870                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
 871         }
 872
 873         /* What is the meaning of this register? */
 874         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
 875         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
 876
 877         regp->head = 0;
 878
 879         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
 880         /* But what are those special conditions? */
 881         if (pNv->Architecture <= NV_ARCH_30 && fp_output) {
 882                 if (nv_crtc->head == 1)
 883                         regp->head |= NV_CRTC_FSEL_FPP1;
 884                 else if (pNv->twoHeads)
 885                         regp->head |= NV_CRTC_FSEL_FPP2;
 886         } else if (nv_crtc->head == 1 && pNv->NVArch > 0x44)
 887                 /* Most G70 cards have FPP2 set on the secondary CRTC. */
 888                 regp->head |= NV_CRTC_FSEL_FPP2;
 889         /* Except for rare conditions I2C is enabled on the primary crtc */
 890         if (nv_crtc->head == 0)
 891                 regp->head |= NV_CRTC_FSEL_I2C;
 892
 893         /* Set overlay to desired crtc. */
 894         if (pNv->overlayAdaptor) {
 895                 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
 896                 if (pPriv->overlayCRTC == nv_crtc->head)
 897                         regp->head |= NV_CRTC_FSEL_OVERLAY;
 898         }
 899
 900         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
 901         /* This fixes my cursor corruption issue */
 902         regp->cursorConfig = 0x0;
 903         if(mode->Flags & V_DBLSCAN)
 904                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
 905         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 906                 regp->cursorConfig |=   (NV_CRTC_CURSOR_CONFIG_32BPP |
 907                                                         NV_CRTC_CURSOR_CONFIG_64PIXELS |
 908                                                         NV_CRTC_CURSOR_CONFIG_64LINES |
 909                                                         NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND);
 910         } else {
 911                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES;
 912         }
 913
 914         /* Unblock some timings */
 915         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
 916         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
 917
 918         /* What is the purpose of this register? */
 919         /* 0x14 may be disabled? */
 920         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
 921
 922         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
 923         if (lvds_output) {
 924                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
 925         } else if (fp_output) {
 926                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
 927         } else {
 928                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
 929         }
 930
 931         /* These values seem to vary */
 932         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
 933         regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = savep->CRTC[NV_VGA_CRTCX_SCRATCH4];
 934
 935         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 936                 regp->CRTC[NV_VGA_CRTCX_45] = 0x0;
 937         } else {
 938                 regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
 939         }
 940
 941         /* What does this do?:
 942          * bit0: crtc0
 943          * bit6: lvds
 944          * bit7: lvds + tmds (only in X)
 945          */
 946         if (nv_crtc->head == 0)
 947                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
 948         else
 949                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
 950
 951         if (lvds_output)
 952                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x40;
 953
 954         if (fp_output && !NVMatchModePrivate(mode, NV_MODE_VGA))
 955                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
 956
 957         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) { /* we need consistent restore. */
 958                 regp->CRTC[NV_VGA_CRTCX_52] = savep->CRTC[NV_VGA_CRTCX_52];
 959         } else {
 960                 /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1.*/
 961                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->SavedReg.crtc_reg[0].CRTC[NV_VGA_CRTCX_52];
 962                 if (!nv_crtc->head)
 963                         regp->CRTC[NV_VGA_CRTCX_52] += 4;
 964         }
 965
 966         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 967                 regp->unk830 = 0;
 968                 regp->unk834 = 0;
 969         } else {
 970                 regp->unk830 = mode->CrtcVDisplay - 3;
 971                 regp->unk834 = mode->CrtcVDisplay - 1;
 972         }
 973
 974         if (pNv->twoHeads)
 975                 /* This is what the blob does */
 976                 regp->unk850 = NVReadCRTC(pNv, 0, NV_CRTC_0850);
 977
 978         /* Never ever modify gpio, unless you know very well what you're doing */
 979         regp->gpio = NVReadCRTC(pNv, 0, NV_CRTC_GPIO);
 980
 981         if (pNv->twoHeads)
 982                 regp->gpio_ext = NVReadCRTC(pNv, 0, NV_CRTC_GPIO_EXT);
 983
 984         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 985                 regp->config = 0x0; /* VGA mode */
 986         } else {
 987                 regp->config = 0x2; /* HSYNC mode */
 988         }
 989
 990         /* Some misc regs */
 991         if (pNv->Architecture == NV_ARCH_40) {
 992                 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
 993                 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
 994         }
 995
 996         /* Calculate the state that is common to all crtcs (stored in the state struct) */
 997         nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->Clock);
 998
 999         /* Enable slaved mode */
1000         if (fp_output)
1001                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1002
1003         /* Generic PRAMDAC regs */
1004
1005         if (pNv->Architecture >= NV_ARCH_10)
1006                 /* Only bit that bios and blob set. */
1007                 regp->nv10_cursync = (1 << 25);
1008
1009         uint8_t depth;
1010         /* This is mode related, not pitch. */
1011         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE))
1012                 depth = pNv->console_mode[nv_crtc->head].depth;
1013         else
1014                 depth = pScrn->depth;
1015
1016         switch (depth) {
1017                 case 4:
1018                         regp->general = 0x00000100;
1019                         break;
1020                 case 24:
1021                 case 15:
1022                         regp->general = 0x00100100;
1023                         break;
1024                 case 32:
1025                 case 16:
1026                 case 8:
1027                 default:
1028                         regp->general = 0x00101100;
1029                         break;
1030         }
1031         if (depth > 8 && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1032                 regp->general |= 0x30; /* enable palette mode */
1033         }
1034         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1035                 /* PIPE_LONG mode, something to do with the size of the cursor? */
1036                 regp->general |= (1<<29);
1037         }
1038
1039         /* Some values the blob sets */
1040         regp->unk_a20 = 0x0;
1041         regp->unk_a24 = 0xfffff;
1042         regp->unk_a34 = 0x1;
1043 }
1044
1045 /* this could be set in nv_output, but would require some rework of load/save */
1046 static void
1047 nv_crtc_mode_set_fp_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1048 {
1049         ScrnInfoPtr pScrn = crtc->scrn;
1050         NVPtr pNv = NVPTR(pScrn);
1051         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1052         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1053         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1054         NVOutputPrivatePtr nv_output = NULL;
1055         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1056         bool is_fp = false;
1057         bool is_lvds = false;
1058         int i;
1059
1060         for (i = 0; i < xf86_config->num_output; i++) {
1061                 xf86OutputPtr output = xf86_config->output[i];
1062                 /* assuming one fp output per crtc seems ok */
1063                 nv_output = output->driver_private;
1064
1065                 if (output->crtc == crtc && nv_output->type == OUTPUT_LVDS)
1066                         is_lvds = true;
1067                 if (is_lvds || (output->crtc == crtc && nv_output->type == OUTPUT_TMDS)) {
1068                         is_fp = true;
1069                         if (nv_crtc->head != (nv_output->or & OUTPUT_C) >> 2)
1070                                 pNv->ModeReg.crosswired = true;
1071                         else
1072                                 pNv->ModeReg.crosswired = false;
1073                         break;
1074                 }
1075         }
1076         if (!is_fp)
1077                 return;
1078
1079         regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1080         regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1081         regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1;
1082         regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1083         regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1084         regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1085         regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1086
1087         regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1088         regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1089         regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
1090         regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1091         regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1092         regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1093         regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1094
1095 #if 0
1096         ErrorF("Horizontal:\n");
1097         ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1098         ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1099         ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1100         ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1101         ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1102         ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1103         ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1104
1105         ErrorF("Vertical:\n");
1106         ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1107         ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1108         ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1109         ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1110         ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1111         ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1112         ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1113 #endif
1114
1115         /*
1116         * bit0: positive vsync
1117         * bit4: positive hsync
1118         * bit8: enable center mode
1119         * bit9: enable native mode
1120         * bit24: 12/24 bit interface (12bit=on, 24bit=off)
1121         * bit26: a bit sometimes seen on some g70 cards
1122         * bit28: fp display enable bit
1123         * bit31: set for dual link LVDS
1124         * nv10reg contains a few more things, but i don't quite get what it all means.
1125         */
1126
1127         regp->fp_control = (savep->fp_control & 0x04100000) |
1128                            NV_RAMDAC_FP_CONTROL_DISPEN_POS;
1129
1130         /* Deal with vsync/hsync polarity */
1131         /* LVDS screens do set this, but modes with +ve syncs are very rare */
1132         if (adjusted_mode->Flags & V_PVSYNC)
1133                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1134         if (adjusted_mode->Flags & V_PHSYNC)
1135                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1136
1137         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) /* seems to be used almost always */
1138                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1139         else if (nv_output->scaling_mode == SCALE_PANEL || nv_output->scaling_mode == SCALE_NOSCALE) /* panel needs to scale */
1140                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1141         /* This is also true for panel scaling, so we must put the panel scale check first */
1142         else if (mode->Clock == adjusted_mode->Clock) /* native mode */
1143                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1144         else /* gpu needs to scale */
1145                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1146
1147         if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
1148                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_WIDTH_12;
1149
1150         if (is_lvds && pNv->VBIOS.fp.dual_link)
1151                 regp->fp_control |= (8 << 28);
1152
1153         /* Use the generic value, and enable x-scaling, y-scaling, and the TMDS enable bit */
1154         regp->debug_0 = 0x01101191;
1155         /* We want automatic scaling */
1156         regp->debug_1 = 0;
1157         /* This can override HTOTAL and VTOTAL */
1158         regp->debug_2 = 0;
1159
1160         if (nv_output->scaling_mode == SCALE_ASPECT) {
1161                 /* Use 20.12 fixed point format to avoid floats */
1162                 uint32_t panel_ratio = (1 << 12) * nv_output->fpWidth / nv_output->fpHeight;
1163                 uint32_t aspect_ratio = (1 << 12) * mode->HDisplay / mode->VDisplay;
1164                 uint32_t h_scale = (1 << 12) * mode->HDisplay / nv_output->fpWidth;
1165                 uint32_t v_scale = (1 << 12) * mode->VDisplay / nv_output->fpHeight;
1166                 #define ONE_TENTH ((1 << 12) / 10)
1167
1168                 /* GPU scaling happens automatically at a ratio of 1.33 */
1169                 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1170                 if (h_scale != (1 << 12) && (panel_ratio > aspect_ratio + ONE_TENTH)) {
1171                         uint32_t diff;
1172
1173                         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Maintaining aspect ratio requires vertical black bars.\n");
1174
1175                         /* Scaling in both directions needs to the same */
1176                         h_scale = v_scale;
1177
1178                         /* Set a new horizontal scale factor and enable testmode (bit12) */
1179                         regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1180
1181                         diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1182                         regp->fp_horiz_regs[REG_DISP_VALID_START] += diff / 2;
1183                         regp->fp_horiz_regs[REG_DISP_VALID_END] -= diff / 2;
1184                 }
1185
1186                 /* Same scaling, just for panels with aspect ratios smaller than 1 */
1187                 if (v_scale != (1 << 12) && (panel_ratio < aspect_ratio - ONE_TENTH)) {
1188                         uint32_t diff;
1189
1190                         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Maintaining aspect ratio requires horizontal black bars.\n");
1191
1192                         /* Scaling in both directions needs to the same */
1193                         v_scale = h_scale;
1194
1195                         /* Set a new vertical scale factor and enable testmode (bit28) */
1196                         regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1197
1198                         diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1199                         regp->fp_vert_regs[REG_DISP_VALID_START] += diff / 2;
1200                         regp->fp_vert_regs[REG_DISP_VALID_END] -= diff / 2;
1201                 }
1202         }
1203
1204         /* Flatpanel support needs at least a NV10 */
1205         if (pNv->twoHeads && (pNv->FPDither || (is_lvds && !pNv->VBIOS.fp.if_is_24bit))) {
1206                 nv_crtc->ditherEnabled = TRUE;
1207                 if (pNv->NVArch == 0x11)
1208                         regp->dither = savep->dither | 0x00010000;
1209                 else {
1210                         int i;
1211                         regp->dither = savep->dither | 0x00000001;
1212                         for (i = 0; i < 3; i++) {
1213                                 regp->dither_regs[i] = 0xe4e4e4e4;
1214                                 regp->dither_regs[i + 3] = 0x44444444;
1215                         }
1216                 }
1217         } else {
1218                 nv_crtc->ditherEnabled = FALSE;
1219                 regp->dither = savep->dither;
1220         }
1221 }
1222
1223 /**
1224  * Sets up registers for the given mode/adjusted_mode pair.
1225  *
1226  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1227  *
1228  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1229  * be easily turned on/off after this.
1230  */
1231 static void
1232 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1233                  DisplayModePtr adjusted_mode,
1234                  int x, int y)
1235 {
1236         ScrnInfoPtr pScrn = crtc->scrn;
1237         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1238         NVPtr pNv = NVPTR(pScrn);
1239
1240         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_mode_set is called for CRTC %d.\n", nv_crtc->head);
1241
1242         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
1243         xf86PrintModeline(pScrn->scrnIndex, mode);
1244         if (pNv->twoHeads)
1245                 NVSetOwner(pScrn, nv_crtc->head);
1246
1247         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
1248
1249         /* calculated in output_prepare, nv40 needs it written before calculating PLLs */
1250         if (pNv->Architecture == NV_ARCH_40) {
1251                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_SEL_CLK %08X\n", pNv->ModeReg.sel_clk);
1252                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
1253         }
1254         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1255         nv_crtc_mode_set_fp_regs(crtc, mode, adjusted_mode);
1256
1257         NVVgaProtect(pNv, nv_crtc->head, true);
1258         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
1259         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
1260         if (pScrn->depth > 8)
1261                 nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
1262         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1263         if (pNv->Architecture == NV_ARCH_40)
1264                 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
1265         else
1266                 nv_crtc_load_state_pll(crtc, &pNv->ModeReg);
1267
1268         NVVgaProtect(pNv, nv_crtc->head, false);
1269
1270         NVCrtcSetBase(crtc, x, y, NVMatchModePrivate(mode, NV_MODE_CONSOLE));
1271
1272 #if X_BYTE_ORDER == X_BIG_ENDIAN
1273         /* turn on LFB swapping */
1274         {
1275                 unsigned char tmp;
1276
1277                 tmp = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SWAPPING);
1278                 tmp |= (1 << 7);
1279                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SWAPPING, tmp);
1280         }
1281 #endif
1282 }
1283
1284 static void nv_crtc_save(xf86CrtcPtr crtc)
1285 {
1286         ScrnInfoPtr pScrn = crtc->scrn;
1287         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1288         NVPtr pNv = NVPTR(pScrn);
1289
1290         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_save is called for CRTC %d.\n", nv_crtc->head);
1291
1292         /* We just came back from terminal, so unlock */
1293         NVCrtcLockUnlock(crtc, FALSE);
1294
1295         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
1296         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
1297         nv_crtc_save_state_palette(crtc, &pNv->SavedReg);
1298         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
1299         nv_crtc_save_state_pll(crtc, &pNv->SavedReg);
1300
1301         /* init some state to saved value */
1302         pNv->ModeReg.reg580 = pNv->SavedReg.reg580;
1303         pNv->ModeReg.sel_clk = pNv->SavedReg.sel_clk & ~(0x5 << 16);
1304 }
1305
1306 static void nv_crtc_restore(xf86CrtcPtr crtc)
1307 {
1308         ScrnInfoPtr pScrn = crtc->scrn;
1309         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1310         NVPtr pNv = NVPTR(pScrn);
1311         RIVA_HW_STATE *state;
1312         NVCrtcRegPtr savep;
1313
1314         state = &pNv->SavedReg;
1315         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1316
1317         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_restore is called for CRTC %d.\n", nv_crtc->head);
1318
1319         /* Just to be safe */
1320         NVCrtcLockUnlock(crtc, FALSE);
1321
1322         NVVgaProtect(pNv, nv_crtc->head, true);
1323         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
1324         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
1325         nv_crtc_load_state_palette(crtc, &pNv->SavedReg);
1326         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1327
1328         /* Force restoring vpll. */
1329         savep->vpll_changed = true;
1330
1331         if (pNv->Architecture == NV_ARCH_40)
1332                 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
1333         else
1334                 nv_crtc_load_state_pll(crtc, &pNv->SavedReg);
1335         NVVgaProtect(pNv, nv_crtc->head, false);
1336
1337         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1338 }
1339
1340 static void
1341 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
1342 {
1343         ScrnInfoPtr pScrn = crtc->scrn;
1344         NVPtr pNv = NVPTR(pScrn);
1345
1346         if (pNv->twoHeads) {
1347                 uint32_t val = 0;
1348
1349                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1350
1351                 if (set) {
1352                         NVCrtcRegPtr regp;
1353
1354                         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1355                         val = regp->head;
1356                 }
1357
1358                 NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, val);
1359         }
1360 }
1361
1362 static void nv_crtc_prepare(xf86CrtcPtr crtc)
1363 {
1364         ScrnInfoPtr pScrn = crtc->scrn;
1365         NVPtr pNv = NVPTR(pScrn);
1366         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1367
1368         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_prepare is called for CRTC %d.\n", nv_crtc->head);
1369
1370         /* Just in case */
1371         NVCrtcLockUnlock(crtc, 0);
1372
1373         NVResetCrtcConfig(crtc, FALSE);
1374
1375         crtc->funcs->dpms(crtc, DPMSModeOff);
1376
1377         /* Sync the engine before adjust mode */
1378         if (pNv->EXADriverPtr) {
1379                 exaMarkSync(pScrn->pScreen);
1380                 exaWaitSync(pScrn->pScreen);
1381         }
1382
1383         NVBlankScreen(pScrn, nv_crtc->head, true);
1384
1385         /* Some more preperation. */
1386         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
1387         if (pNv->Architecture == NV_ARCH_40) {
1388                 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1389                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1390         }
1391 }
1392
1393 static void nv_crtc_commit(xf86CrtcPtr crtc)
1394 {
1395         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1396         ScrnInfoPtr pScrn = crtc->scrn;
1397         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_commit for CRTC %d.\n", nv_crtc->head);
1398
1399         crtc->funcs->dpms (crtc, DPMSModeOn);
1400
1401         if (crtc->scrn->pScreen != NULL) {
1402                 NVPtr pNv = NVPTR(crtc->scrn);
1403
1404                 xf86_reload_cursors (crtc->scrn->pScreen);
1405                 if (!pNv->alphaCursor) {
1406                         /* this works round the fact that xf86_reload_cursors
1407                          * will quite happily show the hw cursor when it knows
1408                          * the hardware can't do alpha, and the current cursor
1409                          * has an alpha channel
1410                          */
1411                         xf86ForceHWCursor(crtc->scrn->pScreen, 1);
1412                         xf86ForceHWCursor(crtc->scrn->pScreen, 0);
1413                 }
1414         }
1415
1416         NVResetCrtcConfig(crtc, TRUE);
1417 }
1418
1419 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1420 {
1421         return FALSE;
1422 }
1423
1424 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1425 {
1426 }
1427
1428 static void
1429 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
1430                                         int size)
1431 {
1432         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1433         ScrnInfoPtr pScrn = crtc->scrn;
1434         NVPtr pNv = NVPTR(pScrn);
1435         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1436         int i, j;
1437
1438         switch (pScrn->depth) {
1439         case 15:
1440                 /* R5G5B5 */
1441                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
1442                 for (i = 0; i < 32; i++) {
1443                         for (j = 0; j < 8; j++) {
1444                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1445                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
1446                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1447                         }
1448                 }
1449                 break;
1450         case 16:
1451                 /* R5G6B5 */
1452                 /* First deal with the 5 bit colors */
1453                 for (i = 0; i < 32; i++) {
1454                         for (j = 0; j < 8; j++) {
1455                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1456                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1457                         }
1458                 }
1459                 /* Now deal with the 6 bit color */
1460                 for (i = 0; i < 64; i++) {
1461                         for (j = 0; j < 4; j++) {
1462                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
1463                         }
1464                 }
1465                 break;
1466         default:
1467                 /* R8G8B8 */
1468                 for (i = 0; i < 256; i++) {
1469                         regp->DAC[i * 3] = red[i] >> 8;
1470                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
1471                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
1472                 }
1473                 break;
1474         }
1475
1476         nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
1477 }
1478
1479 /**
1480  * Allocates memory for a locked-in-framebuffer shadow of the given
1481  * width and height for this CRTC's rotated shadow framebuffer.
1482  */
1483
1484 static void *
1485 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
1486 {
1487         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1488         ScrnInfoPtr pScrn = crtc->scrn;
1489 #if !NOUVEAU_EXA_PIXMAPS
1490         ScreenPtr pScreen = pScrn->pScreen;
1491 #endif /* !NOUVEAU_EXA_PIXMAPS */
1492         NVPtr pNv = NVPTR(pScrn);
1493         void *offset;
1494
1495         unsigned long rotate_pitch;
1496         int size, align = 64;
1497
1498         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_shadow_allocate is called.\n");
1499
1500         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1501         size = rotate_pitch * height;
1502
1503         assert(nv_crtc->shadow == NULL);
1504 #if NOUVEAU_EXA_PIXMAPS
1505         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
1506                         align, size, &nv_crtc->shadow)) {
1507                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to allocate memory for shadow buffer!\n");
1508                 return NULL;
1509         }
1510
1511         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
1512                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1513                                 "Failed to map shadow buffer.\n");
1514                 return NULL;
1515         }
1516
1517         offset = nv_crtc->shadow->map;
1518 #else
1519         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
1520         if (nv_crtc->shadow == NULL) {
1521                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1522                         "Couldn't allocate shadow memory for rotated CRTC.\n");
1523                 return NULL;
1524         }
1525         offset = pNv->FB->map + nv_crtc->shadow->offset;
1526 #endif /* NOUVEAU_EXA_PIXMAPS */
1527
1528         return offset;
1529 }
1530
1531 /**
1532  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
1533  */
1534 static PixmapPtr
1535 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
1536 {
1537         ScrnInfoPtr pScrn = crtc->scrn;
1538 #if NOUVEAU_EXA_PIXMAPS
1539         ScreenPtr pScreen = pScrn->pScreen;
1540         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1541 #endif /* NOUVEAU_EXA_PIXMAPS */
1542         unsigned long rotate_pitch;
1543         PixmapPtr rotate_pixmap;
1544 #if NOUVEAU_EXA_PIXMAPS
1545         struct nouveau_pixmap *nvpix;
1546 #endif /* NOUVEAU_EXA_PIXMAPS */
1547
1548         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_shadow_create is called.\n");
1549
1550         if (!data)
1551                 data = crtc->funcs->shadow_allocate (crtc, width, height);
1552
1553         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1554
1555 #if NOUVEAU_EXA_PIXMAPS
1556         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
1557         rotate_pixmap = pScreen->CreatePixmap(pScreen,
1558                                                                 0, /* width */
1559                                                                 0, /* height */
1560         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
1561                                                                 pScrn->depth,
1562                                                                 0);
1563         #else
1564                                                                 pScrn->depth);
1565         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
1566 #else
1567         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
1568                                                                 width, height,
1569                                                                 pScrn->depth,
1570                                                                 pScrn->bitsPerPixel,
1571                                                                 rotate_pitch,
1572                                                                 data);
1573 #endif /* NOUVEAU_EXA_PIXMAPS */
1574
1575         if (rotate_pixmap == NULL) {
1576                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1577                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
1578         }
1579
1580 #if NOUVEAU_EXA_PIXMAPS
1581         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1582         if (!nvpix) {
1583                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No initial shadow private available for rotation.\n");
1584         } else {
1585                 nvpix->bo = nv_crtc->shadow;
1586                 nvpix->mapped = TRUE;
1587         }
1588
1589         /* Modify the pixmap to actually be the one we need. */
1590         pScreen->ModifyPixmapHeader(rotate_pixmap,
1591                                         width,
1592                                         height,
1593                                         pScrn->depth,
1594                                         pScrn->bitsPerPixel,
1595                                         rotate_pitch,
1596                                         data);
1597
1598         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1599         if (!nvpix || !nvpix->bo)
1600                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No final shadow private available for rotation.\n");
1601 #endif /* NOUVEAU_EXA_PIXMAPS */
1602
1603         return rotate_pixmap;
1604 }
1605
1606 static void
1607 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
1608 {
1609         ScrnInfoPtr pScrn = crtc->scrn;
1610         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1611         ScreenPtr pScreen = pScrn->pScreen;
1612
1613         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_shadow_destroy is called.\n");
1614
1615         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
1616                 pScreen->DestroyPixmap(rotate_pixmap);
1617         }
1618
1619 #if !NOUVEAU_EXA_PIXMAPS
1620         if (data && nv_crtc->shadow) {
1621                 exaOffscreenFree(pScreen, nv_crtc->shadow);
1622         }
1623 #endif /* !NOUVEAU_EXA_PIXMAPS */
1624
1625         nv_crtc->shadow = NULL;
1626 }
1627
1628 /* NV04-NV10 doesn't support alpha cursors */
1629 static const xf86CrtcFuncsRec nv_crtc_funcs = {
1630         .dpms = nv_crtc_dpms,
1631         .save = nv_crtc_save, /* XXX */
1632         .restore = nv_crtc_restore, /* XXX */
1633         .mode_fixup = nv_crtc_mode_fixup,
1634         .mode_set = nv_crtc_mode_set,
1635         .prepare = nv_crtc_prepare,
1636         .commit = nv_crtc_commit,
1637         .destroy = NULL, /* XXX */
1638         .lock = nv_crtc_lock,
1639         .unlock = nv_crtc_unlock,
1640         .set_cursor_colors = nv_crtc_set_cursor_colors,
1641         .set_cursor_position = nv_crtc_set_cursor_position,
1642         .show_cursor = nv_crtc_show_cursor,
1643         .hide_cursor = nv_crtc_hide_cursor,
1644         .load_cursor_image = nv_crtc_load_cursor_image,
1645         .gamma_set = nv_crtc_gamma_set,
1646         .shadow_create = nv_crtc_shadow_create,
1647         .shadow_allocate = nv_crtc_shadow_allocate,
1648         .shadow_destroy = nv_crtc_shadow_destroy,
1649 };
1650
1651 /* NV11 and up has support for alpha cursors. */
1652 /* Due to different maximum sizes we cannot allow it to use normal cursors */
1653 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
1654         .dpms = nv_crtc_dpms,
1655         .save = nv_crtc_save, /* XXX */
1656         .restore = nv_crtc_restore, /* XXX */
1657         .mode_fixup = nv_crtc_mode_fixup,
1658         .mode_set = nv_crtc_mode_set,
1659         .prepare = nv_crtc_prepare,
1660         .commit = nv_crtc_commit,
1661         .destroy = NULL, /* XXX */
1662         .lock = nv_crtc_lock,
1663         .unlock = nv_crtc_unlock,
1664         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
1665         .set_cursor_position = nv_crtc_set_cursor_position,
1666         .show_cursor = nv_crtc_show_cursor,
1667         .hide_cursor = nv_crtc_hide_cursor,
1668         .load_cursor_argb = nv_crtc_load_cursor_argb,
1669         .gamma_set = nv_crtc_gamma_set,
1670         .shadow_create = nv_crtc_shadow_create,
1671         .shadow_allocate = nv_crtc_shadow_allocate,
1672         .shadow_destroy = nv_crtc_shadow_destroy,
1673 };
1674
1675
1676 void
1677 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
1678 {
1679         NVPtr pNv = NVPTR(pScrn);
1680         xf86CrtcPtr crtc;
1681         NVCrtcPrivatePtr nv_crtc;
1682         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[crtc_num];
1683         int i;
1684
1685         if (pNv->NVArch >= 0x11)
1686                 crtc = xf86CrtcCreate(pScrn, &nv11_crtc_funcs);
1687         else
1688                 crtc = xf86CrtcCreate(pScrn, &nv_crtc_funcs);
1689         if (crtc == NULL)
1690                 return;
1691
1692         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
1693         nv_crtc->head = crtc_num;
1694         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1695         nv_crtc->ditherEnabled = pNv->FPDither;
1696
1697         crtc->driver_private = nv_crtc;
1698
1699         /* Initialise the default LUT table. */
1700         for (i = 0; i < 256; i++) {
1701                 regp->DAC[i*3] = i;
1702                 regp->DAC[(i*3)+1] = i;
1703                 regp->DAC[(i*3)+2] = i;
1704         }
1705
1706         NVCrtcLockUnlock(crtc, FALSE);
1707 }
1708
1709 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1710 {
1711         ScrnInfoPtr pScrn = crtc->scrn;
1712         NVPtr pNv = NVPTR(pScrn);
1713         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1714         int i;
1715         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1716
1717         NVWritePVIO(pNv, nv_crtc->head, VGA_MISC_OUT_W, regp->MiscOutReg);
1718
1719         for (i = 0; i < 5; i++)
1720                 NVWriteVgaSeq(pNv, nv_crtc->head, i, regp->Sequencer[i]);
1721
1722         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
1723         NVWriteVgaCrtc(pNv, nv_crtc->head, 17, regp->CRTC[17] & ~0x80);
1724
1725         for (i = 0; i < 25; i++)
1726                 NVWriteVgaCrtc(pNv, nv_crtc->head, i, regp->CRTC[i]);
1727
1728         for (i = 0; i < 9; i++)
1729                 NVWriteVgaGr(pNv, nv_crtc->head, i, regp->Graphics[i]);
1730
1731         NVSetEnablePalette(pNv, nv_crtc->head, true);
1732         for (i = 0; i < 21; i++)
1733                 NVWriteVgaAttr(pNv, nv_crtc->head, i, regp->Attribute[i]);
1734
1735         NVSetEnablePalette(pNv, nv_crtc->head, false);
1736 }
1737
1738 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
1739 {
1740         ScrnInfoPtr pScrn = crtc->scrn;
1741         NVPtr pNv = NVPTR(pScrn);
1742         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1743         NVCrtcRegPtr regp;
1744         int i;
1745
1746         regp = &state->crtc_reg[nv_crtc->head];
1747
1748         if (pNv->Architecture >= NV_ARCH_10) {
1749                 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
1750                 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
1751                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
1752                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
1753                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1754                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1755                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1756                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1757                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
1758
1759                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
1760                 NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
1761                 NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
1762                 NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
1763                 if (pNv->Architecture == NV_ARCH_40) {
1764                         NVCrtcWriteCRTC(crtc, NV_CRTC_0850, regp->unk850);
1765                         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO_EXT, regp->gpio_ext);
1766                 }
1767
1768                 if (pNv->Architecture == NV_ARCH_40) {
1769                         uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1770                         if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
1771                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 | 0x10000);
1772                         } else {
1773                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1774                         }
1775                 }
1776         }
1777
1778         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
1779         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio);
1780
1781         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
1782         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
1783         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
1784         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
1785         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
1786         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
1787         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
1788         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
1789         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
1790         if (pNv->Architecture >= NV_ARCH_30)
1791                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
1792
1793         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
1794         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
1795         if (pNv->Architecture == NV_ARCH_40) /* HW bug */
1796                 nv_crtc_fix_nv40_hw_cursor(pScrn, nv_crtc->head);
1797         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
1798         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
1799
1800         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
1801         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
1802         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SCRATCH4, regp->CRTC[NV_VGA_CRTCX_SCRATCH4]);
1803         if (pNv->Architecture >= NV_ARCH_10) {
1804                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
1805                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
1806                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
1807                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
1808         }
1809         /* NV11 and NV20 stop at 0x52. */
1810         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1811                 if (override)
1812                         for (i = 0; i < 0x10; i++)
1813                                 NVWriteVgaCrtc5758(pNv, nv_crtc->head, i, regp->CR58[i]);
1814
1815                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
1816                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
1817
1818                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
1819
1820                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
1821                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
1822         }
1823
1824         /* Setting 1 on this value gives you interrupts for every vblank period. */
1825         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_EN_0, 0);
1826         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
1827 }
1828
1829 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1830 {
1831         ScrnInfoPtr pScrn = crtc->scrn;
1832         NVPtr pNv = NVPTR(pScrn);
1833         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1834         int i;
1835         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1836
1837         regp->MiscOutReg = NVReadPVIO(pNv, nv_crtc->head, VGA_MISC_OUT_R);
1838
1839         for (i = 0; i < 25; i++)
1840                 regp->CRTC[i] = NVReadVgaCrtc(pNv, nv_crtc->head, i);
1841
1842         NVSetEnablePalette(pNv, nv_crtc->head, true);
1843         for (i = 0; i < 21; i++)
1844                 regp->Attribute[i] = NVReadVgaAttr(pNv, nv_crtc->head, i);
1845         NVSetEnablePalette(pNv, nv_crtc->head, false);
1846
1847         for (i = 0; i < 9; i++)
1848                 regp->Graphics[i] = NVReadVgaGr(pNv, nv_crtc->head, i);
1849
1850         for (i = 0; i < 5; i++)
1851                 regp->Sequencer[i] = NVReadVgaSeq(pNv, nv_crtc->head, i);
1852 }
1853
1854 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1855 {
1856         ScrnInfoPtr pScrn = crtc->scrn;
1857         NVPtr pNv = NVPTR(pScrn);
1858         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1859         NVCrtcRegPtr regp;
1860         int i;
1861
1862         regp = &state->crtc_reg[nv_crtc->head];
1863
1864         regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD);
1865         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT0);
1866         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1);
1867         regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LSR);
1868         regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_PIXEL);
1869         regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_HEB);
1870         regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO1);
1871
1872         regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO0);
1873         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM);
1874         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_BUFFER);
1875         if (pNv->Architecture >= NV_ARCH_30)
1876                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM_NV30);
1877         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL0);
1878         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL1);
1879         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL2);
1880         regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_INTERLACE);
1881
1882         if (pNv->Architecture >= NV_ARCH_10) {
1883                 regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
1884                 regp->unk834 = NVCrtcReadCRTC(crtc, NV_CRTC_0834);
1885                 if (pNv->Architecture == NV_ARCH_40) {
1886                         regp->unk850 = NVCrtcReadCRTC(crtc, NV_CRTC_0850);
1887                         regp->gpio_ext = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO_EXT);
1888                 }
1889                 if (pNv->twoHeads) {
1890                         regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL);
1891                         regp->crtcOwner = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_OWNER);
1892                 }
1893                 regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG);
1894         }
1895
1896         regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO);
1897         regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
1898
1899         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_26);
1900         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_3B);
1901         regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SCRATCH4);
1902         if (pNv->Architecture >= NV_ARCH_10) {
1903                 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_EXTRA);
1904                 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_45);
1905                 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_4B);
1906                 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_52);
1907         }
1908         /* NV11 and NV20 don't have this, they stop at 0x52. */
1909         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1910                 for (i = 0; i < 0x10; i++)
1911                         regp->CR58[i] = NVReadVgaCrtc5758(pNv, nv_crtc->head, i);
1912
1913                 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_59);
1914                 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_HTIMING);
1915                 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_VTIMING);
1916
1917                 regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_85);
1918                 regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_86);
1919         }
1920 }
1921
1922 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1923 {
1924         ScrnInfoPtr pScrn = crtc->scrn;
1925         NVPtr pNv = NVPTR(pScrn);
1926         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1927         NVCrtcRegPtr regp;
1928         int i;
1929
1930         regp = &state->crtc_reg[nv_crtc->head];
1931
1932         regp->general = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL);
1933
1934         if (pNv->twoHeads) {
1935                 regp->fp_control        = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_CONTROL);
1936                 regp->debug_0   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0);
1937                 regp->debug_1   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1);
1938                 regp->debug_2   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2);
1939
1940                 regp->unk_a20 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A20);
1941                 regp->unk_a24 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A24);
1942                 regp->unk_a34 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A34);
1943         }
1944
1945         if (pNv->NVArch == 0x11) {
1946                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_DITHER_NV11);
1947         } else if (pNv->twoHeads) {
1948                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DITHER);
1949                 for (i = 0; i < 3; i++) {
1950                         regp->dither_regs[i] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4);
1951                         regp->dither_regs[i + 3] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4);
1952                 }
1953         }
1954         if (pNv->Architecture >= NV_ARCH_10)
1955                 regp->nv10_cursync = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC);
1956
1957         /* The regs below are 0 for non-flatpanels, so you can load and save them */
1958
1959         for (i = 0; i < 7; i++) {
1960                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
1961                 regp->fp_horiz_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1962         }
1963
1964         for (i = 0; i < 7; i++) {
1965                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
1966                 regp->fp_vert_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1967         }
1968 }
1969
1970 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1971 {
1972         ScrnInfoPtr pScrn = crtc->scrn;
1973         NVPtr pNv = NVPTR(pScrn);
1974         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1975         NVCrtcRegPtr regp;
1976         int i;
1977
1978         regp = &state->crtc_reg[nv_crtc->head];
1979
1980         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL, regp->general);
1981
1982         if (pNv->twoHeads) {
1983                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_CONTROL, regp->fp_control);
1984                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
1985                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
1986                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
1987                 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
1988                         uint32_t reg890 = NVCrtcReadRAMDAC(crtc, NV30_RAMDAC_890);
1989                         NVCrtcWriteRAMDAC(crtc, NV30_RAMDAC_89C, reg890);
1990                 }
1991
1992                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A20, regp->unk_a20);
1993                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A24, regp->unk_a24);
1994                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A34, regp->unk_a34);
1995         }
1996
1997         if (pNv->NVArch == 0x11) {
1998                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_DITHER_NV11, regp->dither);
1999         } else if (pNv->twoHeads) {
2000                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DITHER, regp->dither);
2001                 for (i = 0; i < 3; i++) {
2002                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4, regp->dither_regs[i]);
2003                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4, regp->dither_regs[i + 3]);
2004                 }
2005         }
2006         if (pNv->Architecture >= NV_ARCH_10)
2007                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2008
2009         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2010
2011         for (i = 0; i < 7; i++) {
2012                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2013                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_horiz_regs[i]);
2014         }
2015
2016         for (i = 0; i < 7; i++) {
2017                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2018                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_vert_regs[i]);
2019         }
2020 }
2021
2022 void
2023 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y, Bool bios_restore)
2024 {
2025         ScrnInfoPtr pScrn = crtc->scrn;
2026         NVPtr pNv = NVPTR(pScrn);
2027         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2028         uint32_t start = 0;
2029
2030         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVCrtcSetBase is called with coordinates: x: %d y: %d\n", x, y);
2031
2032         if (bios_restore) {
2033                 start = pNv->console_mode[nv_crtc->head].fb_start;
2034         } else {
2035                 start += ((y * pScrn->displayWidth + x) * (pScrn->bitsPerPixel/8));
2036                 if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
2037 #if NOUVEAU_EXA_PIXMAPS
2038                         start = nv_crtc->shadow->offset;
2039 #else
2040                         start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
2041 #endif
2042                 } else {
2043                         start += pNv->FB->offset;
2044                 }
2045         }
2046
2047         /* 30 bits addresses in 32 bits according to haiku */
2048         NVCrtcWriteCRTC(crtc, NV_CRTC_START, start & 0xfffffffc);
2049
2050         /* set NV4/NV10 byte adress: (bit0 - 1) */
2051         NVWriteVgaAttr(pNv, nv_crtc->head, 0x13, (start & 0x3) << 1);
2052
2053         crtc->x = x;
2054         crtc->y = y;
2055 }
2056
2057 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2058 {
2059         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2060         NVPtr pNv = NVPTR(crtc->scrn);
2061         uint32_t mmiobase = nv_crtc->head ? NV_PDIO1_OFFSET : NV_PDIO0_OFFSET;
2062         int i;
2063
2064         VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff);
2065         VGA_WR08(pNv->REGS, VGA_DAC_READ_ADDR + mmiobase, 0x0);
2066
2067         for (i = 0; i < 768; i++) {
2068                 state->crtc_reg[nv_crtc->head].DAC[i] = NV_RD08(pNv->REGS, VGA_DAC_DATA + mmiobase);
2069                 DDXMMIOH("nv_crtc_save_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
2070         }
2071
2072         NVSetEnablePalette(pNv, nv_crtc->head, false);
2073 }
2074 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2075 {
2076         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2077         NVPtr pNv = NVPTR(crtc->scrn);
2078         uint32_t mmiobase = nv_crtc->head ? NV_PDIO1_OFFSET : NV_PDIO0_OFFSET;
2079         int i;
2080
2081         VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff);
2082         VGA_WR08(pNv->REGS, VGA_DAC_WRITE_ADDR + mmiobase, 0x0);
2083
2084         for (i = 0; i < 768; i++) {
2085                 DDXMMIOH("nv_crtc_load_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
2086                 NV_WR08(pNv->REGS, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
2087         }
2088
2089         NVSetEnablePalette(pNv, nv_crtc->head, false);
2090 }
2091
2092 /*************************************************************************** \
2093 |*                                                                           *|
2094 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
2095 |*                                                                           *|
2096 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
2097 |*     international laws.  Users and possessors of this source code are     *|
2098 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
2099 |*     use this code in individual and commercial software.                  *|
2100 |*                                                                           *|
2101 |*     Any use of this source code must include,  in the user documenta-     *|
2102 |*     tion and  internal comments to the code,  notices to the end user     *|
2103 |*     as follows:                                                           *|
2104 |*                                                                           *|
2105 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
2106 |*                                                                           *|
2107 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
2108 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
2109 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
2110 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
2111 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
2112 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
2113 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
2114 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
2115 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
2116 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
2117 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
2118 |*                                                                           *|
2119 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
2120 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
2121 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
2122 |*     computer  software  documentation,"  as such  terms  are  used in     *|
2123 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
2124 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
2125 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
2126 |*     all U.S. Government End Users  acquire the source code  with only     *|
2127 |*     those rights set forth herein.                                        *|
2128 |*                                                                           *|
2129  \***************************************************************************/