git.oblomov.eu Git - nouveau/blob - src/nv_output.c

   1 /*
   2  * Copyright 2003 NVIDIA, Corporation
   3  * Copyright 2006 Dave Airlie
   4  * Copyright 2007 Maarten Maathuis
   5  * Copyright 2007-2008 Stuart Bennett
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  23  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #include <X11/Xatom.h>
  28 #include "nv_include.h"
  29
  30 #define MULTIPLE_ENCODERS(e) (e & (e - 1))
  31 #define FOR_EACH_ENCODER_IN_CONNECTOR(i, c, e)  for (i = 0; i < pNv->dcb_table.entries; i++)    \
  32                                                         if (c->possible_encoders & (1 << i) &&  \
  33                                                             (e = &pNv->encoders[i]))
  34
  35 static int nv_output_ramdac_offset(struct nouveau_encoder *nv_encoder)
  36 {
  37         int offset = 0;
  38
  39         if (nv_encoder->dcb->or & (8 | OUTPUT_C))
  40                 offset += 0x68;
  41         if (nv_encoder->dcb->or & (8 | OUTPUT_B))
  42                 offset += 0x2000;
  43
  44         return offset;
  45 }
  46
  47 static Bool
  48 nv_load_detect(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
  49 {
  50         NVPtr pNv = NVPTR(pScrn);
  51         uint32_t testval, regoffset = nv_output_ramdac_offset(nv_encoder);
  52         uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, saved_rtest_ctrl, temp;
  53         int present = 0;
  54
  55 #define RGB_TEST_DATA(r,g,b) (r << 0 | g << 10 | b << 20)
  56         testval = RGB_TEST_DATA(0x140, 0x140, 0x140); /* 0x94050140 */
  57         if (pNv->VBIOS.dactestval)
  58                 testval = pNv->VBIOS.dactestval;
  59
  60         saved_rtest_ctrl = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset);
  61         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl & ~0x00010000);
  62
  63         if (pNv->NVArch >= 0x17) {
  64                 saved_powerctrl_2 = nvReadMC(pNv, NV_PBUS_POWERCTRL_2);
  65
  66                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);
  67                 if (regoffset == 0x68) {
  68                         saved_powerctrl_4 = nvReadMC(pNv, NV_PBUS_POWERCTRL_4);
  69                         nvWriteMC(pNv, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);
  70                 }
  71         }
  72
  73         usleep(4000);
  74
  75         saved_routput = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset);
  76         /* nv driver and nv31 use 0xfffffeee
  77          * nv34 and 6600 use 0xfffffece */
  78         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, saved_routput & 0xfffffece);
  79         usleep(1000);
  80
  81         temp = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset);
  82         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, temp | 1);
  83
  84         /* no regoffset on purpose */
  85         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_DATA, 1 << 31 | testval);
  86         temp = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL);
  87         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL, temp | 0x1000);
  88         usleep(1000);
  89
  90         present = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset) & (1 << 28);
  91
  92         /* no regoffset on purpose */
  93         temp = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL);
  94         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL, temp & 0xffffefff);
  95         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_DATA, 0);
  96
  97         /* bios does something more complex for restoring, but I think this is good enough */
  98         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, saved_routput);
  99         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl);
 100         if (pNv->NVArch >= 0x17) {
 101                 if (regoffset == 0x68)
 102                         nvWriteMC(pNv, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);
 103                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);
 104         }
 105
 106         if (present) {
 107                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Load detected on output %c\n", '@' + ffs(nv_encoder->dcb->or));
 108                 return TRUE;
 109         }
 110
 111         return FALSE;
 112 }
 113
 114 static void
 115 update_output_fields(xf86OutputPtr output, struct nouveau_encoder *det_encoder)
 116 {
 117         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 118         NVPtr pNv = NVPTR(output->scrn);
 119
 120         if (nv_connector->detected_encoder == det_encoder)
 121                 return;
 122
 123         nv_connector->detected_encoder = det_encoder;
 124         output->possible_crtcs = det_encoder->dcb->heads;
 125         if (det_encoder->dcb->type == OUTPUT_LVDS || det_encoder->dcb->type == OUTPUT_TMDS) {
 126                 output->doubleScanAllowed = false;
 127                 output->interlaceAllowed = false;
 128         } else {
 129                 output->doubleScanAllowed = true;
 130                 if (pNv->Architecture == NV_ARCH_20 ||
 131                    (pNv->Architecture == NV_ARCH_10 &&
 132                     (pNv->Chipset & 0x0ff0) != CHIPSET_NV10 &&
 133                     (pNv->Chipset & 0x0ff0) != CHIPSET_NV15))
 134                         /* HW is broken */
 135                         output->interlaceAllowed = false;
 136                 else
 137                         output->interlaceAllowed = true;
 138         }
 139 }
 140
 141 static xf86OutputStatus
 142 nv_output_detect(xf86OutputPtr output)
 143 {
 144         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 145         ScrnInfoPtr pScrn = output->scrn;
 146         NVPtr pNv = NVPTR(pScrn);
 147         struct nouveau_encoder *det_encoder;
 148         xf86OutputStatus ret = XF86OutputStatusDisconnected;
 149
 150         struct nouveau_encoder *find_encoder_by_type(NVOutputType type)
 151         {
 152                 int i;
 153                 for (i = 0; i < pNv->dcb_table.entries; i++)
 154                         if (nv_connector->possible_encoders & (1 << i) &&
 155                             (type == OUTPUT_ANY || pNv->encoders[i].dcb->type == type))
 156                                 return &pNv->encoders[i];
 157                 return NULL;
 158         }
 159
 160         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_detect is called.\n");
 161
 162         if (nv_connector->pDDCBus &&
 163             (nv_connector->edid = xf86OutputGetEDID(output, nv_connector->pDDCBus),
 164              xf86OutputSetEDID(output, nv_connector->edid), nv_connector->edid)) {
 165                 if (MULTIPLE_ENCODERS(nv_connector->possible_encoders)) {
 166                         if (nv_connector->edid->features.input_type)
 167                                 det_encoder = find_encoder_by_type(OUTPUT_TMDS);
 168                         else
 169                                 det_encoder = find_encoder_by_type(OUTPUT_ANALOG);
 170                 } else
 171                         det_encoder = find_encoder_by_type(OUTPUT_ANY);
 172                 ret = XF86OutputStatusConnected;
 173         } else if ((det_encoder = find_encoder_by_type(OUTPUT_ANALOG))) {
 174                 /* we don't have a load det function for early cards */
 175                 if (!pNv->twoHeads || pNv->NVArch == 0x11)
 176                         ret = XF86OutputStatusUnknown;
 177                 else if (pNv->twoHeads && nv_load_detect(pScrn, det_encoder))
 178                         ret = XF86OutputStatusConnected;
 179         } else if ((det_encoder = find_encoder_by_type(OUTPUT_LVDS))) {
 180                 if (det_encoder->dcb->lvdsconf.use_straps_for_mode &&
 181                     pNv->VBIOS.fp.native_mode)
 182                         ret = XF86OutputStatusConnected;
 183                 if (pNv->VBIOS.fp.edid) {
 184                         xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 185                                    "Will use hardcoded BIOS FP EDID\n");
 186                         nv_connector->edid = xf86InterpretEDID(pScrn->scrnIndex, pNv->VBIOS.fp.edid);
 187                         xf86OutputSetEDID(output, nv_connector->edid);
 188                         ret = XF86OutputStatusConnected;
 189                 }
 190         }
 191
 192         if (ret != XF86OutputStatusDisconnected)
 193                 update_output_fields(output, det_encoder);
 194
 195         return ret;
 196 }
 197
 198 static DisplayModePtr
 199 get_native_mode_from_edid(xf86OutputPtr output, DisplayModePtr edid_modes)
 200 {
 201         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 202         struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
 203         ScrnInfoPtr pScrn = output->scrn;
 204         int max_h_active = 0, max_v_active = 0;
 205         int i;
 206         DisplayModePtr mode;
 207
 208         for (i = 0; i < DET_TIMINGS; i++) {
 209                 /* We only look at detailed timings atm */
 210                 if (nv_connector->edid->det_mon[i].type != DT)
 211                         continue;
 212                 /* Selecting only based on width ok? */
 213                 if (nv_connector->edid->det_mon[i].section.d_timings.h_active > max_h_active) {
 214                         max_h_active = nv_connector->edid->det_mon[i].section.d_timings.h_active;
 215                         max_v_active = nv_connector->edid->det_mon[i].section.d_timings.v_active;
 216                 }
 217         }
 218         if (!(max_h_active && max_v_active)) {
 219                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No EDID detailed timings available, bailing out.\n");
 220                 return NULL;
 221         }
 222
 223         if (nv_encoder->native_mode) {
 224                 xfree(nv_encoder->native_mode);
 225                 nv_encoder->native_mode = NULL;
 226         }
 227
 228         for (mode = edid_modes; mode != NULL; mode = mode->next) {
 229                 if (mode->HDisplay == max_h_active &&
 230                         mode->VDisplay == max_v_active) {
 231                         /* Take the preferred mode when it exists. */
 232                         if (mode->type & M_T_PREFERRED) {
 233                                 nv_encoder->native_mode = xf86DuplicateMode(mode);
 234                                 break;
 235                         }
 236                         /* Find the highest refresh mode otherwise. */
 237                         if (!nv_encoder->native_mode || (mode->VRefresh > nv_encoder->native_mode->VRefresh)) {
 238                                 if (nv_encoder->native_mode)
 239                                         xfree(nv_encoder->native_mode);
 240                                 mode->type |= M_T_PREFERRED;
 241                                 nv_encoder->native_mode = xf86DuplicateMode(mode);
 242                         }
 243                 }
 244         }
 245
 246         return nv_encoder->native_mode;
 247 }
 248
 249 static DisplayModePtr
 250 nv_output_get_edid_modes(xf86OutputPtr output)
 251 {
 252         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 253         struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
 254         ScrnInfoPtr pScrn = output->scrn;
 255         DisplayModePtr edid_modes;
 256
 257         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_get_edid_modes is called.\n");
 258
 259         if (!(edid_modes = xf86OutputGetEDIDModes(output)))
 260                 return edid_modes;
 261
 262         if (nv_encoder->dcb->type == OUTPUT_TMDS || nv_encoder->dcb->type == OUTPUT_LVDS)
 263                 if (!get_native_mode_from_edid(output, edid_modes))
 264                         return NULL;
 265
 266         if (nv_encoder->dcb->type == OUTPUT_LVDS) {
 267                 static bool dual_link_correction_done = false;
 268
 269                 if (!dual_link_correction_done) {
 270                         parse_lvds_manufacturer_table(pScrn, &NVPTR(pScrn)->VBIOS, nv_encoder->native_mode->Clock);
 271                         dual_link_correction_done = true;
 272                 }
 273         }
 274
 275         return edid_modes;
 276 }
 277
 278 static DisplayModePtr
 279 nv_lvds_output_get_modes(xf86OutputPtr output)
 280 {
 281         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 282         struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
 283         ScrnInfoPtr pScrn = output->scrn;
 284         NVPtr pNv = NVPTR(pScrn);
 285         DisplayModePtr modes;
 286
 287         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_lvds_output_get_modes is called.\n");
 288
 289         if ((modes = nv_output_get_edid_modes(output)))
 290                 return modes;
 291
 292         if (!nv_encoder->dcb->lvdsconf.use_straps_for_mode || pNv->VBIOS.fp.native_mode == NULL)
 293                 return NULL;
 294
 295         if (nv_encoder->native_mode)
 296                 xfree(nv_encoder->native_mode);
 297         nv_encoder->native_mode = xf86DuplicateMode(pNv->VBIOS.fp.native_mode);
 298
 299         return xf86DuplicateMode(pNv->VBIOS.fp.native_mode);
 300 }
 301
 302 static int nv_output_mode_valid(xf86OutputPtr output, DisplayModePtr mode)
 303 {
 304         struct nouveau_encoder *nv_encoder = to_nouveau_connector(output)->detected_encoder;
 305         NVPtr pNv = NVPTR(output->scrn);
 306
 307         if (!output->doubleScanAllowed && mode->Flags & V_DBLSCAN)
 308                 return MODE_NO_DBLESCAN;
 309         if (!output->interlaceAllowed && mode->Flags & V_INTERLACE)
 310                 return MODE_NO_INTERLACE;
 311
 312         if (nv_encoder->dcb->type == OUTPUT_ANALOG) {
 313                 if (mode->Clock > (pNv->twoStagePLL ? 400000 : 350000))
 314                         return MODE_CLOCK_HIGH;
 315                 if (mode->Clock < 12000)
 316                         return MODE_CLOCK_LOW;
 317         }
 318         if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS)
 319                 /* No modes > panel's native res */
 320                 if (mode->HDisplay > nv_encoder->native_mode->HDisplay ||
 321                     mode->VDisplay > nv_encoder->native_mode->VDisplay)
 322                         return MODE_PANEL;
 323         if (nv_encoder->dcb->type == OUTPUT_TMDS) {
 324                 if (nv_encoder->dcb->duallink_possible) {
 325                         if (mode->Clock > 330000) /* 2x165 MHz */
 326                                 return MODE_CLOCK_HIGH;
 327                 } else
 328                         if (mode->Clock > 165000) /* 165 MHz */
 329                                 return MODE_CLOCK_HIGH;
 330         }
 331
 332         return MODE_OK;
 333 }
 334
 335 static void
 336 nv_output_destroy (xf86OutputPtr output)
 337 {
 338         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 339         struct nouveau_encoder *nv_encoder;
 340         ScrnInfoPtr pScrn = output->scrn;
 341         NVPtr pNv = NVPTR(output->scrn);
 342         int i;
 343
 344         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_destroy is called.\n");
 345
 346         if (!nv_connector)
 347                 return;
 348
 349         if (nv_connector->edid)
 350                 xfree(nv_connector->edid);
 351         FOR_EACH_ENCODER_IN_CONNECTOR(i, nv_connector, nv_encoder)
 352                 if (nv_encoder->native_mode)
 353                         xfree(nv_encoder->native_mode);
 354         xfree(nv_connector);
 355 }
 356
 357 static Atom scaling_mode_atom;
 358 #define SCALING_MODE_NAME "SCALING_MODE"
 359 static const struct {
 360         char *name;
 361         enum scaling_modes mode;
 362 } scaling_mode[] = {
 363         { "panel", SCALE_PANEL },
 364         { "fullscreen", SCALE_FULLSCREEN },
 365         { "aspect", SCALE_ASPECT },
 366         { "noscale", SCALE_NOSCALE },
 367         { NULL, SCALE_INVALID}
 368 };
 369
 370 static Atom dithering_atom;
 371 #define DITHERING_MODE_NAME "DITHERING"
 372
 373 static void
 374 nv_output_create_resources(xf86OutputPtr output)
 375 {
 376         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 377         ScrnInfoPtr pScrn = output->scrn;
 378         INT32 dithering_range[2] = { 0, 1 };
 379         int error, i;
 380
 381         /* may be called before encoder is picked, resources will be created
 382          * by update_output_fields()
 383          */
 384         if (!nv_encoder)
 385                 return;
 386
 387         /* no properties for vga */
 388         if (nv_encoder->dcb->type == OUTPUT_ANALOG)
 389                 return;
 390
 391         /*
 392          * Setup scaling mode property.
 393          */
 394         scaling_mode_atom = MakeAtom(SCALING_MODE_NAME, sizeof(SCALING_MODE_NAME) - 1, TRUE);
 395
 396         error = RRConfigureOutputProperty(output->randr_output,
 397                                         scaling_mode_atom, TRUE, FALSE, FALSE,
 398                                         0, NULL);
 399
 400         if (error != 0) {
 401                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 402                         "RRConfigureOutputProperty error, %d\n", error);
 403         }
 404
 405         char *existing_scale_name = NULL;
 406         for (i = 0; scaling_mode[i].name; i++)
 407                 if (scaling_mode[i].mode == nv_encoder->scaling_mode)
 408                         existing_scale_name = scaling_mode[i].name;
 409
 410         error = RRChangeOutputProperty(output->randr_output, scaling_mode_atom,
 411                                         XA_STRING, 8, PropModeReplace,
 412                                         strlen(existing_scale_name),
 413                                         existing_scale_name, FALSE, TRUE);
 414
 415         if (error != 0) {
 416                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 417                         "Failed to set scaling mode, %d\n", error);
 418         }
 419
 420         /*
 421          * Setup dithering property.
 422          */
 423         dithering_atom = MakeAtom(DITHERING_MODE_NAME, sizeof(DITHERING_MODE_NAME) - 1, TRUE);
 424
 425         error = RRConfigureOutputProperty(output->randr_output,
 426                                         dithering_atom, TRUE, TRUE, FALSE,
 427                                         2, dithering_range);
 428
 429         if (error != 0) {
 430                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 431                         "RRConfigureOutputProperty error, %d\n", error);
 432         }
 433
 434         /* promote bool into int32 to make RandR DIX and big endian happy */
 435         int32_t existing_dither = nv_encoder->dithering;
 436         error = RRChangeOutputProperty(output->randr_output, dithering_atom,
 437                                         XA_INTEGER, 32, PropModeReplace, 1,
 438                                         &existing_dither, FALSE, TRUE);
 439
 440         if (error != 0) {
 441                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 442                         "Failed to set dithering mode, %d\n", error);
 443         }
 444
 445         RRPostPendingProperties(output->randr_output);
 446 }
 447
 448 static Bool
 449 nv_output_set_property(xf86OutputPtr output, Atom property,
 450                                 RRPropertyValuePtr value)
 451 {
 452         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 453
 454         if (property == scaling_mode_atom) {
 455                 int32_t ret;
 456                 char *name = NULL;
 457
 458                 if (value->type != XA_STRING || value->format != 8)
 459                         return FALSE;
 460
 461                 name = (char *) value->data;
 462
 463                 /* Match a string to a scaling mode */
 464                 ret = nv_scaling_mode_lookup(name, value->size);
 465                 if (ret == SCALE_INVALID)
 466                         return FALSE;
 467
 468                 /* LVDS must always use gpu scaling. */
 469                 if (ret == SCALE_PANEL && nv_encoder->dcb->type == OUTPUT_LVDS)
 470                         return FALSE;
 471
 472                 nv_encoder->scaling_mode = ret;
 473         } else if (property == dithering_atom) {
 474                 if (value->type != XA_INTEGER || value->format != 32)
 475                         return FALSE;
 476
 477                 int32_t val = *(int32_t *) value->data;
 478
 479                 if (val < 0 || val > 1)
 480                         return FALSE;
 481
 482                 nv_encoder->dithering = val;
 483         }
 484
 485         return TRUE;
 486 }
 487
 488 static Bool
 489 nv_output_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
 490                      DisplayModePtr adjusted_mode)
 491 {
 492         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 493
 494         if (nv_connector->nv_encoder != nv_connector->detected_encoder) {
 495                 nv_connector->nv_encoder = nv_connector->detected_encoder;
 496                 if (output->randr_output) {
 497                         RRDeleteOutputProperty(output->randr_output, dithering_atom);
 498                         RRDeleteOutputProperty(output->randr_output, scaling_mode_atom);
 499                         output->funcs->create_resources(output);
 500                 }
 501         }
 502
 503         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 504         ScrnInfoPtr pScrn = output->scrn;
 505
 506         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_mode_fixup is called.\n");
 507
 508         /* For internal panels and gpu scaling on DVI we need the native mode */
 509         if (nv_encoder->dcb->type == OUTPUT_LVDS ||
 510             (nv_encoder->dcb->type == OUTPUT_TMDS && nv_encoder->scaling_mode != SCALE_PANEL)) {
 511                 adjusted_mode->HDisplay = nv_encoder->native_mode->HDisplay;
 512                 adjusted_mode->HSkew = nv_encoder->native_mode->HSkew;
 513                 adjusted_mode->HSyncStart = nv_encoder->native_mode->HSyncStart;
 514                 adjusted_mode->HSyncEnd = nv_encoder->native_mode->HSyncEnd;
 515                 adjusted_mode->HTotal = nv_encoder->native_mode->HTotal;
 516                 adjusted_mode->VDisplay = nv_encoder->native_mode->VDisplay;
 517                 adjusted_mode->VScan = nv_encoder->native_mode->VScan;
 518                 adjusted_mode->VSyncStart = nv_encoder->native_mode->VSyncStart;
 519                 adjusted_mode->VSyncEnd = nv_encoder->native_mode->VSyncEnd;
 520                 adjusted_mode->VTotal = nv_encoder->native_mode->VTotal;
 521                 adjusted_mode->Clock = nv_encoder->native_mode->Clock;
 522                 adjusted_mode->Flags = nv_encoder->native_mode->Flags;
 523
 524                 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
 525         }
 526
 527         return TRUE;
 528 }
 529
 530 static void nv_digital_output_prepare_sel_clk(NVPtr pNv, struct nouveau_encoder *nv_encoder, int head)
 531 {
 532         NVRegPtr state = &pNv->ModeReg;
 533         uint32_t bits1618 = nv_encoder->dcb->or & OUTPUT_A ? 0x10000 : 0x40000;
 534
 535         if (nv_encoder->dcb->location != LOC_ON_CHIP)
 536                 return;
 537
 538         /* SEL_CLK is only used on the primary ramdac
 539          * It toggles spread spectrum PLL output and sets the bindings of PLLs
 540          * to heads on digital outputs
 541          */
 542         if (head)
 543                 state->sel_clk |= bits1618;
 544         else
 545                 state->sel_clk &= ~bits1618;
 546
 547         /* nv30:
 548          *      bit 0           NVClk spread spectrum on/off
 549          *      bit 2           MemClk spread spectrum on/off
 550          *      bit 4           PixClk1 spread spectrum on/off toggle
 551          *      bit 6           PixClk2 spread spectrum on/off toggle
 552          *
 553          * nv40 (observations from bios behaviour and mmio traces):
 554          *      bits 4&6        as for nv30
 555          *      bits 5&7        head dependent as for bits 4&6, but do not appear with 4&6;
 556          *                      maybe a different spread mode
 557          *      bits 8&10       seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
 558          *      The logic behind turning spread spectrum on/off in the first place,
 559          *      and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
 560          *      entry has the necessary info)
 561          */
 562         if (nv_encoder->dcb->type == OUTPUT_LVDS && pNv->SavedReg.sel_clk & 0xf0) {
 563                 int shift = (pNv->SavedReg.sel_clk & 0x50) ? 0 : 1;
 564
 565                 state->sel_clk &= ~0xf0;
 566                 state->sel_clk |= (head ? 0x40 : 0x10) << shift;
 567         }
 568 }
 569
 570 static void
 571 nv_output_prepare(xf86OutputPtr output)
 572 {
 573         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 574         ScrnInfoPtr pScrn = output->scrn;
 575         NVPtr pNv = NVPTR(output->scrn);
 576         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(output->crtc);
 577         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 578
 579         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_prepare is called.\n");
 580
 581         output->funcs->dpms(output, DPMSModeOff);
 582
 583         /* calculate some output specific CRTC regs now, so that they can be written in nv_crtc_set_mode */
 584         if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS)
 585                 nv_digital_output_prepare_sel_clk(pNv, nv_encoder, nv_crtc->head);
 586
 587         /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f etc.) which we don't alter */
 588         if (!(regp->CRTC[NV_VGA_CRTCX_LCD] & 0x44)) {
 589                 if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS) {
 590                         regp->CRTC[NV_VGA_CRTCX_LCD] &= ~0x30;
 591                         regp->CRTC[NV_VGA_CRTCX_LCD] |= 0x3;
 592                         if (nv_crtc->head == 0)
 593                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= 0x8;
 594                         else
 595                                 regp->CRTC[NV_VGA_CRTCX_LCD] &= ~0x8;
 596                         if (nv_encoder->dcb->location != LOC_ON_CHIP)
 597                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (nv_encoder->dcb->or << 4) & 0x30;
 598                 } else
 599                         regp->CRTC[NV_VGA_CRTCX_LCD] = 0;
 600         }
 601 }
 602
 603 static void
 604 nv_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 605 {
 606         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 607         ScrnInfoPtr pScrn = output->scrn;
 608         NVPtr pNv = NVPTR(pScrn);
 609         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(output->crtc);
 610
 611         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_mode_set is called.\n");
 612
 613         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
 614                 /* bit 16-19 are bits that are set on some G70 cards,
 615                  * but don't seem to have much effect */
 616                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 617                               nv_crtc->head << 8 | NV_RAMDAC_OUTPUT_DAC_ENABLE);
 618         if (nv_encoder->dcb->type == OUTPUT_TMDS)
 619                 run_tmds_table(pScrn, nv_encoder->dcb, nv_crtc->head, adjusted_mode->Clock);
 620         else if (nv_encoder->dcb->type == OUTPUT_LVDS)
 621                 call_lvds_script(pScrn, nv_encoder->dcb, nv_crtc->head, LVDS_RESET, adjusted_mode->Clock);
 622
 623         /* This could use refinement for flatpanels, but it should work this way */
 624         if (pNv->NVArch < 0x44)
 625                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + nv_output_ramdac_offset(nv_encoder), 0xf0000000);
 626         else
 627                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + nv_output_ramdac_offset(nv_encoder), 0x00100000);
 628 }
 629
 630 static void
 631 nv_output_commit(xf86OutputPtr output)
 632 {
 633         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 634         ScrnInfoPtr pScrn = output->scrn;
 635         xf86CrtcPtr crtc = output->crtc;
 636         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 637
 638         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_commit is called.\n");
 639
 640         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Output %s is running on CRTC %d using output %c\n", output->name, nv_crtc->head, '@' + ffs(nv_encoder->dcb->or));
 641
 642         output->funcs->dpms(output, DPMSModeOn);
 643 }
 644
 645 static void dpms_update_fp_control(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 646 {
 647         NVPtr pNv = NVPTR(pScrn);
 648         struct nouveau_crtc *nv_crtc;
 649         NVCrtcRegPtr regp;
 650         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 651         int i;
 652
 653         if (mode == DPMSModeOn) {
 654                 nv_crtc = to_nouveau_crtc(crtc);
 655                 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 656
 657                 nv_crtc->fp_users |= 1 << nv_encoder->dcb->index;
 658                 NVWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control & ~0x20000022);
 659         } else
 660                 for (i = 0; i <= pNv->twoHeads; i++) {
 661                         nv_crtc = to_nouveau_crtc(xf86_config->crtc[i]);
 662                         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 663
 664                         nv_crtc->fp_users &= ~(1 << nv_encoder->dcb->index);
 665                         if (!nv_crtc->fp_users) {
 666                                 /* cut the FP output */
 667                                 regp->fp_control |= 0x20000022;
 668                                 NVWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
 669                         }
 670                 }
 671 }
 672
 673 static void
 674 lvds_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 675 {
 676         NVPtr pNv = NVPTR(pScrn);
 677
 678         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "lvds_encoder_dpms is called with mode %d\n", mode);
 679
 680         if (nv_encoder->last_dpms == mode)
 681                 return;
 682         nv_encoder->last_dpms = mode;
 683
 684         if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
 685                 /* when removing an output, crtc may not be set, but PANEL_OFF must still be run */
 686                 int head = nv_get_digital_bound_head(pNv, nv_encoder->dcb->or);
 687                 int pclk = nv_encoder->native_mode->Clock;
 688
 689                 if (crtc)
 690                         head = to_nouveau_crtc(crtc)->head;
 691
 692                 if (mode == DPMSModeOn)
 693                         call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_ON, pclk);
 694                 else
 695                         call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_OFF, pclk);
 696         }
 697
 698         dpms_update_fp_control(pScrn, nv_encoder, crtc, mode);
 699
 700         if (mode == DPMSModeOn)
 701                 nv_digital_output_prepare_sel_clk(pNv, nv_encoder, to_nouveau_crtc(crtc)->head);
 702         else {
 703                 pNv->ModeReg.sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 704                 pNv->ModeReg.sel_clk &= ~0xf0;
 705         }
 706         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
 707 }
 708
 709 static void
 710 vga_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 711 {
 712         NVPtr pNv = NVPTR(pScrn);
 713
 714         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vga_encoder_dpms is called with mode %d\n", mode);
 715
 716         if (nv_encoder->last_dpms == mode)
 717                 return;
 718         nv_encoder->last_dpms = mode;
 719
 720         if (pNv->twoHeads) {
 721                 uint32_t outputval = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder));
 722
 723                 if (mode == DPMSModeOff)
 724                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 725                                       outputval & ~NV_RAMDAC_OUTPUT_DAC_ENABLE);
 726                 else if (mode == DPMSModeOn)
 727                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 728                                       outputval | NV_RAMDAC_OUTPUT_DAC_ENABLE);
 729         }
 730 }
 731
 732 static void
 733 tmds_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 734 {
 735         NVPtr pNv = NVPTR(pScrn);
 736
 737         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "tmds_encoder_dpms is called with mode %d\n", mode);
 738
 739         if (nv_encoder->last_dpms == mode)
 740                 return;
 741         nv_encoder->last_dpms = mode;
 742
 743         dpms_update_fp_control(pScrn, nv_encoder, crtc, mode);
 744
 745         if (nv_encoder->dcb->location != LOC_ON_CHIP) {
 746                 struct nouveau_crtc *nv_crtc;
 747                 int i;
 748
 749                 if (mode == DPMSModeOn) {
 750                         nv_crtc = to_nouveau_crtc(crtc);
 751                         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD,
 752                                        pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_VGA_CRTCX_LCD]);
 753                 } else
 754                         for (i = 0; i <= pNv->twoHeads; i++)
 755                                 NVWriteVgaCrtc(pNv, i, NV_VGA_CRTCX_LCD,
 756                                                NVReadVgaCrtc(pNv, i, NV_VGA_CRTCX_LCD) & ~((nv_encoder->dcb->or << 4) & 0x30));
 757         }
 758 }
 759
 760 static void nv_output_dpms(xf86OutputPtr output, int mode)
 761 {
 762         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 763         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 764         ScrnInfoPtr pScrn = output->scrn;
 765         xf86CrtcPtr crtc = output->crtc;
 766         NVPtr pNv = NVPTR(pScrn);
 767         int i;
 768         void (* const encoder_dpms[4])(ScrnInfoPtr, struct nouveau_encoder *, xf86CrtcPtr, int) =
 769                 /* index matches DCB type */
 770                 { vga_encoder_dpms, NULL, tmds_encoder_dpms, lvds_encoder_dpms };
 771
 772         struct nouveau_encoder *nv_encoder_i;
 773         FOR_EACH_ENCODER_IN_CONNECTOR(i, nv_connector, nv_encoder_i)
 774                 if (nv_encoder_i != nv_encoder)
 775                         encoder_dpms[nv_encoder_i->dcb->type](pScrn, nv_encoder_i, crtc, DPMSModeOff);
 776
 777         if (nv_encoder) /* may be called before encoder is picked, but iteration above solves it */
 778                 encoder_dpms[nv_encoder->dcb->type](pScrn, nv_encoder, crtc, mode);
 779 }
 780
 781 static uint32_t nv_get_clock_from_crtc(ScrnInfoPtr pScrn, RIVA_HW_STATE *state, uint8_t crtc)
 782 {
 783         NVPtr pNv = NVPTR(pScrn);
 784         struct pll_lims pll_lim;
 785         uint32_t vplla = state->crtc_reg[crtc].vpll_a;
 786         uint32_t vpllb = state->crtc_reg[crtc].vpll_b;
 787         bool nv40_single = pNv->Architecture == 0x40 &&
 788                            ((!crtc && state->reg580 & NV_RAMDAC_580_VPLL1_ACTIVE) ||
 789                             (crtc && state->reg580 & NV_RAMDAC_580_VPLL2_ACTIVE));
 790
 791         if (!get_pll_limits(pScrn, crtc ? VPLL2 : VPLL1, &pll_lim))
 792                 return 0;
 793
 794         return nv_decode_pll_highregs(pNv, vplla, vpllb, nv40_single, pll_lim.refclk);
 795 }
 796
 797 void nv_encoder_save(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
 798 {
 799         NVPtr pNv = NVPTR(pScrn);
 800
 801         if (!nv_encoder->dcb)   /* uninitialised encoder */
 802                 return;
 803
 804         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_encoder_save is called.\n");
 805
 806         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
 807                 nv_encoder->restore.output = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder));
 808         if (nv_encoder->dcb->type == OUTPUT_TMDS || nv_encoder->dcb->type == OUTPUT_LVDS)
 809                 nv_encoder->restore.head = nv_get_digital_bound_head(pNv, nv_encoder->dcb->or);
 810 }
 811
 812 void nv_encoder_restore(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
 813 {
 814         NVPtr pNv = NVPTR(pScrn);
 815         int head = nv_encoder->restore.head;
 816
 817         if (!nv_encoder->dcb)   /* uninitialised encoder */
 818                 return;
 819
 820         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_encoder_restore is called.\n");
 821
 822         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
 823                 NVWriteRAMDAC(pNv, 0,
 824                               NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 825                               nv_encoder->restore.output);
 826         if (nv_encoder->dcb->type == OUTPUT_LVDS)
 827                 call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_ON,
 828                                  nv_encoder->native_mode->Clock);
 829         if (nv_encoder->dcb->type == OUTPUT_TMDS) {
 830                 int clock = nv_get_clock_from_crtc(pScrn, &pNv->SavedReg, head);
 831
 832                 run_tmds_table(pScrn, nv_encoder->dcb, head, clock);
 833         }
 834
 835         nv_encoder->last_dpms = NV_DPMS_CLEARED;
 836 }
 837
 838 static const xf86OutputFuncsRec nv_output_funcs = {
 839         .dpms = nv_output_dpms,
 840         .mode_valid = nv_output_mode_valid,
 841         .mode_fixup = nv_output_mode_fixup,
 842         .mode_set = nv_output_mode_set,
 843         .detect = nv_output_detect,
 844         .get_modes = nv_output_get_edid_modes,
 845         .destroy = nv_output_destroy,
 846         .prepare = nv_output_prepare,
 847         .commit = nv_output_commit,
 848         .create_resources = nv_output_create_resources,
 849         .set_property = nv_output_set_property,
 850 };
 851
 852 static const xf86OutputFuncsRec nv_lvds_output_funcs = {
 853         .dpms = nv_output_dpms,
 854         .mode_valid = nv_output_mode_valid,
 855         .mode_fixup = nv_output_mode_fixup,
 856         .mode_set = nv_output_mode_set,
 857         .detect = nv_output_detect,
 858         .get_modes = nv_lvds_output_get_modes,
 859         .destroy = nv_output_destroy,
 860         .prepare = nv_output_prepare,
 861         .commit = nv_output_commit,
 862         .create_resources = nv_output_create_resources,
 863         .set_property = nv_output_set_property,
 864 };
 865
 866 static void
 867 nv_add_encoder(ScrnInfoPtr pScrn, struct dcb_entry *dcbent)
 868 {
 869         NVPtr pNv = NVPTR(pScrn);
 870         struct nouveau_encoder *nv_encoder = &pNv->encoders[dcbent->index];
 871
 872         nv_encoder->dcb = dcbent;
 873         nv_encoder->last_dpms = NV_DPMS_CLEARED;
 874         nv_encoder->dithering = (pNv->FPDither || (nv_encoder->dcb->type == OUTPUT_LVDS && !pNv->VBIOS.fp.if_is_24bit));
 875         if (pNv->fpScaler) /* GPU Scaling */
 876                 nv_encoder->scaling_mode = SCALE_ASPECT;
 877         else if (nv_encoder->dcb->type == OUTPUT_LVDS)
 878                 nv_encoder->scaling_mode = SCALE_NOSCALE;
 879         else
 880                 nv_encoder->scaling_mode = SCALE_PANEL;
 881         if (xf86GetOptValString(pNv->Options, OPTION_SCALING_MODE)) {
 882                 nv_encoder->scaling_mode = nv_scaling_mode_lookup(xf86GetOptValString(pNv->Options, OPTION_SCALING_MODE), -1);
 883                 if (nv_encoder->scaling_mode == SCALE_INVALID)
 884                         nv_encoder->scaling_mode = SCALE_ASPECT; /* default */
 885         }
 886 }
 887
 888 static void
 889 nv_add_connector(ScrnInfoPtr pScrn, int i2c_index, int encoders, const xf86OutputFuncsRec *output_funcs, char *outputname)
 890 {
 891         NVPtr pNv = NVPTR(pScrn);
 892         xf86OutputPtr output;
 893         struct nouveau_connector *nv_connector;
 894
 895         if (!(output = xf86OutputCreate(pScrn, output_funcs, outputname)))
 896                 return;
 897         if (!(nv_connector = xnfcalloc(sizeof (struct nouveau_connector), 1)))
 898                 return;
 899
 900         output->driver_private = nv_connector;
 901
 902         if (i2c_index < 0xf)
 903                 NV_I2CInit(pScrn, &nv_connector->pDDCBus, pNv->dcb_table.i2c_read[i2c_index], xstrdup(outputname));
 904         nv_connector->possible_encoders = encoders;
 905 }
 906
 907 void NvSetupOutputs(ScrnInfoPtr pScrn)
 908 {
 909         NVPtr pNv = NVPTR(pScrn);
 910         uint16_t connectors[0x10];
 911         struct dcb_entry *dcbent;
 912         int i, vga_count = 0, dvid_count = 0, dvii_count = 0, lvds_count = 0;
 913
 914         if (!(pNv->encoders = xnfcalloc(pNv->dcb_table.entries, sizeof (struct nouveau_encoder))))
 915                 return;
 916
 917         memset(connectors, 0, sizeof (connectors));
 918
 919         for (i = 0; i < pNv->dcb_table.entries; i++) {
 920                 dcbent = &pNv->dcb_table.entry[i];
 921
 922                 if (dcbent->type == OUTPUT_TV)
 923                         continue;
 924                 if (dcbent->type > 3) {
 925                         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DCB type %d not known\n", dcbent->type);
 926                         continue;
 927                 }
 928
 929                 connectors[dcbent->i2c_index] |= 1 << i;
 930
 931                 nv_add_encoder(pScrn, dcbent);
 932         }
 933
 934         for (i = 0; i < pNv->dcb_table.entries; i++) {
 935                 int i2c_index = pNv->dcb_table.entry[i].i2c_index;
 936                 uint16_t encoders = connectors[i2c_index];
 937                 char outputname[20];
 938                 xf86OutputFuncsRec const *funcs = &nv_output_funcs;
 939
 940                 if (!encoders)
 941                         continue;
 942
 943                 switch (pNv->dcb_table.entry[i].type) {
 944                 case OUTPUT_ANALOG:
 945                         if (!MULTIPLE_ENCODERS(encoders))
 946                                 sprintf(outputname, "VGA-%d", vga_count++);
 947                         else
 948                                 sprintf(outputname, "DVI-I-%d", dvii_count++);
 949                         break;
 950                 case OUTPUT_TMDS:
 951                         if (!MULTIPLE_ENCODERS(encoders))
 952                                 sprintf(outputname, "DVI-D-%d", dvid_count++);
 953                         else
 954                                 sprintf(outputname, "DVI-I-%d", dvii_count++);
 955                         break;
 956                 case OUTPUT_LVDS:
 957                         sprintf(outputname, "LVDS-%d", lvds_count++);
 958                         funcs = &nv_lvds_output_funcs;
 959                         break;
 960                 default:
 961                         continue;
 962                 }
 963
 964                 nv_add_connector(pScrn, i2c_index, encoders, funcs, outputname);
 965                 connectors[i2c_index] = 0; /* avoid connectors being added multiply */
 966         }
 967 }