git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  50 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  51 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  52 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  53 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  54 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  55 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  56 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  57
  58 static uint32_t NVCrtcReadCRTC(xf86CrtcPtr crtc, uint32_t reg)
  59 {
  60         ScrnInfoPtr pScrn = crtc->scrn;
  61         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  62         NVPtr pNv = NVPTR(pScrn);
  63
  64         return NVReadCRTC(pNv, nv_crtc->head, reg);
  65 }
  66
  67 void NVCrtcWriteCRTC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  68 {
  69         ScrnInfoPtr pScrn = crtc->scrn;
  70         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  71         NVPtr pNv = NVPTR(pScrn);
  72
  73         NVWriteCRTC(pNv, nv_crtc->head, reg, val);
  74 }
  75
  76 static uint32_t NVCrtcReadRAMDAC(xf86CrtcPtr crtc, uint32_t reg)
  77 {
  78         ScrnInfoPtr pScrn = crtc->scrn;
  79         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  80         NVPtr pNv = NVPTR(pScrn);
  81
  82         return NVReadRAMDAC(pNv, nv_crtc->head, reg);
  83 }
  84
  85 void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  86 {
  87         ScrnInfoPtr pScrn = crtc->scrn;
  88         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  89         NVPtr pNv = NVPTR(pScrn);
  90
  91         NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
  92 }
  93
  94 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool lock)
  95 {
  96         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  97         ScrnInfoPtr pScrn = crtc->scrn;
  98         NVPtr pNv = NVPTR(pScrn);
  99
 100         if (pNv->twoHeads)
 101                 NVSetOwner(pScrn, nv_crtc->head);
 102         NVLockVgaCrtc(pNv, nv_crtc->head, lock);
 103 }
 104
 105 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 106 /* They are only valid for NV4x, appearantly reordered for NV5x */
 107 /* gpu pll: 0x4000 + 0x4004
 108  * unknown pll: 0x4008 + 0x400c
 109  * vpll1: 0x4010 + 0x4014
 110  * vpll2: 0x4018 + 0x401c
 111  * unknown pll: 0x4020 + 0x4024
 112  * unknown pll: 0x4038 + 0x403c
 113  * Some of the unknown's are probably memory pll's.
 114  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 115  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 116  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 117  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 118  *     bit8: A switch that turns of the second divider and multiplier off.
 119  *     bit12: Also a switch, i haven't seen it yet.
 120  *     bit16-19: p-divider
 121  *     but 28-31: Something related to the mode that is used (see bit8).
 122  * 2) bit0-7: m-divider (a)
 123  *     bit8-15: n-multiplier (a)
 124  *     bit16-23: m-divider (b)
 125  *     bit24-31: n-multiplier (b)
 126  */
 127
 128 /* Modifying the gpu pll for example requires:
 129  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 130  * This is not needed for the vpll's which have their own bits.
 131  */
 132
 133 static void nv_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
 134
 135 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 136 {
 137         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 138         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 139         ScrnInfoPtr pScrn = crtc->scrn;
 140         NVPtr pNv = NVPTR(pScrn);
 141         /* The TMDS_PLL switch is on the actual ramdac */
 142 //      int fp_head = nv_crtc->head ^ state->crosswired;
 143 //      uint32_t fp_debug_0 = NVReadRAMDAC(pNv, fp_head, NV_RAMDAC_FP_DEBUG_0);
 144
 145         if (regp->vpll_changed) {
 146                 uint32_t savedc040 = nvReadMC(pNv, 0xc040);
 147
 148 //              NVWriteRAMDAC(pNv, fp_head, NV_RAMDAC_FP_DEBUG_0,
 149 //                      fp_debug_0 | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 150
 151                 /* Wait for the situation to stabilise */
 152                 usleep(5000);
 153
 154                 /* for vpll1 change bits 16 and 17 are disabled */
 155                 /* for vpll2 change bits 18 and 19 are disabled */
 156                 nvWriteMC(pNv, 0xc040, savedc040 & ~(3 << (16 + nv_crtc->head * 2)));
 157
 158                 nv_crtc_load_state_pll(crtc, state);
 159
 160                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_580 %08X\n", state->reg580);
 161                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
 162
 163                 /* We need to wait a while */
 164                 usleep(5000);
 165                 nvWriteMC(pNv, 0xc040, savedc040);
 166
 167 //              NVWriteRAMDAC(pNv, fp_head, NV_RAMDAC_FP_DEBUG_0, fp_debug_0);
 168         }
 169 }
 170
 171 static void nv_crtc_save_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 172 {
 173         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 174         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 175         NVPtr pNv = NVPTR(crtc->scrn);
 176
 177         if (nv_crtc->head) {
 178                 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 179                 if (pNv->twoStagePLL && pNv->NVArch != 0x30)
 180                         regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 181         } else {
 182                 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 183                 if (pNv->twoStagePLL && pNv->NVArch != 0x30)
 184                         regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 185         }
 186         if (pNv->twoHeads)
 187                 state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 188         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 189         if (pNv->Architecture == NV_ARCH_40)
 190                 state->reg580 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_580);
 191 }
 192
 193 static void nv_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 194 {
 195         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 196         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 197         ScrnInfoPtr pScrn = crtc->scrn;
 198         NVPtr pNv = NVPTR(pScrn);
 199
 200         /* This sequence is important, the NV28 is very sensitive in this area. */
 201         /* Keep pllsel last and sel_clk first. */
 202         if (pNv->twoHeads) {
 203                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_SEL_CLK %08X\n", state->sel_clk);
 204                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
 205         }
 206
 207         if (regp->vpll_changed) {
 208                 regp->vpll_changed = false;
 209
 210                 if (nv_crtc->head) {
 211                         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL2 %08X\n", regp->vpll_a);
 212                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, regp->vpll_a);
 213                         if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 214                                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL2_B %08X\n", regp->vpll_b);
 215                                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, regp->vpll_b);
 216                         }
 217                 } else {
 218                         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL %08X\n", regp->vpll_a);
 219                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, regp->vpll_a);
 220                         if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 221                                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL_B %08X\n", regp->vpll_b);
 222                                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, regp->vpll_b);
 223                         }
 224                 }
 225         }
 226
 227         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_PLL_SELECT %08X\n", state->pllsel);
 228         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 229 }
 230
 231 /* Calculate extended mode parameters (SVGA) and save in a mode state structure */
 232 static void nv_crtc_calc_state_ext(xf86CrtcPtr crtc, DisplayModePtr mode, int dotClock)
 233 {
 234         ScrnInfoPtr pScrn = crtc->scrn;
 235         NVPtr pNv = NVPTR(pScrn);
 236         uint32_t pixelDepth, VClk = 0;
 237         uint32_t CursorStart;
 238         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 239         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 240         RIVA_HW_STATE *state = &pNv->ModeReg;
 241         uint32_t old_clock_a = 0, old_clock_b = 0;
 242         struct pll_lims pll_lim;
 243         int NM1 = 0xbeef, NM2 = 0xdead, log2P = 0;
 244         uint32_t g70_pll_special_bits = 0;
 245         Bool nv4x_single_stage_pll_mode = FALSE;
 246         int bpp;
 247
 248         /* Store old clock. */
 249         old_clock_a = regp->vpll_a;
 250         old_clock_b = regp->vpll_b;
 251
 252         /*
 253          * Extended RIVA registers.
 254          */
 255
 256         /* This is pitch related, not mode related. */
 257         if (pScrn->depth < 24)
 258                 bpp = pScrn->depth;
 259         else
 260                 bpp = 32;
 261         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 262                 bpp = pNv->console_mode[nv_crtc->head].bpp;
 263         }
 264
 265         pixelDepth = (bpp + 1)/8;
 266
 267         if (nv_crtc->head == 0) {
 268                 if (!get_pll_limits(pScrn, VPLL1, &pll_lim))
 269                         return;
 270         } else
 271                 if (!get_pll_limits(pScrn, VPLL2, &pll_lim))
 272                         return;
 273
 274         if (pNv->twoStagePLL) {
 275                 if (dotClock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* use a single VCO */
 276                         nv4x_single_stage_pll_mode = TRUE;
 277                         /* Turn the second set of divider and multiplier off */
 278                         /* Bogus data, the same nvidia uses */
 279                         NM2 = 0x11f;
 280                         VClk = getMNP_single(pScrn, &pll_lim, dotClock, &NM1, &log2P);
 281                 } else
 282                         VClk = getMNP_double(pScrn, &pll_lim, dotClock, &NM1, &NM2, &log2P);
 283         } else
 284                 VClk = getMNP_single(pScrn, &pll_lim, dotClock, &NM1, &log2P);
 285
 286         /* Are these all the (relevant) G70 cards? */
 287         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 288                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 289                 /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 290                 if (nv4x_single_stage_pll_mode)
 291                         g70_pll_special_bits = 0x1;
 292                 else
 293                         g70_pll_special_bits = 0x3;
 294         }
 295
 296         if (pNv->NVArch == 0x30)
 297                 /* See nvregisters.xml for details. */
 298                 regp->vpll_a = log2P << 16 | NM1 | (NM2 & 7) << 4 | ((NM2 >> 8) & 7) << 19 | ((NM2 >> 11) & 3) << 24 | NV30_RAMDAC_ENABLE_VCO2;
 299         else
 300                 regp->vpll_a = g70_pll_special_bits << 30 | log2P << 16 | NM1;
 301         regp->vpll_b = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 302
 303         if (nv4x_single_stage_pll_mode) {
 304                 if (nv_crtc->head == 0)
 305                         state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 306                 else
 307                         state->reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 308         } else {
 309                 if (nv_crtc->head == 0)
 310                         state->reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 311                 else
 312                         state->reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 313         }
 314
 315         if (!pNv->twoStagePLL || nv4x_single_stage_pll_mode)
 316                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n %d m %d log2p %d\n", NM1 >> 8, NM1 & 0xff, log2P);
 317         else
 318                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P);
 319
 320         /* Changing clocks gives a delay, which is not always needed. */
 321         if (old_clock_a != regp->vpll_a || old_clock_b != regp->vpll_b)
 322                 regp->vpll_changed = true;
 323
 324         switch (pNv->Architecture) {
 325         case NV_ARCH_04:
 326                 nv4UpdateArbitrationSettings(VClk,
 327                                                 pixelDepth * 8,
 328                                                 &(state->arbitration0),
 329                                                 &(state->arbitration1),
 330                                                 pNv);
 331                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 332                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 333                 if (mode->Flags & V_DBLSCAN)
 334                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 335                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 336                 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 337                 state->config = 0x00001114;
 338                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = mode->CrtcHDisplay < 1280 ? 0x04 : 0x00;
 339                 break;
 340         case NV_ARCH_10:
 341         case NV_ARCH_20:
 342         case NV_ARCH_30:
 343         default:
 344                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 345                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 346                         state->arbitration0 = 128;
 347                         state->arbitration1 = 0x0480;
 348                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 349                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 350                         nForceUpdateArbitrationSettings(VClk,
 351                                                 pixelDepth * 8,
 352                                                 &(state->arbitration0),
 353                                                 &(state->arbitration1),
 354                                                 pNv);
 355                 } else if (pNv->Architecture < NV_ARCH_30) {
 356                         nv10UpdateArbitrationSettings(VClk,
 357                                                 pixelDepth * 8,
 358                                                 &(state->arbitration0),
 359                                                 &(state->arbitration1),
 360                                                 pNv);
 361                 } else {
 362                         nv30UpdateArbitrationSettings(pNv,
 363                                                 &(state->arbitration0),
 364                                                 &(state->arbitration1));
 365                 }
 366
 367                 if (nv_crtc->head == 1) {
 368                         CursorStart = pNv->Cursor2->offset;
 369                 } else {
 370                         CursorStart = pNv->Cursor->offset;
 371                 }
 372
 373                 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 374                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 375                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 376                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 377                 } else {
 378                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x0;
 379                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0x0;
 380                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x0;
 381                 }
 382
 383                 if (mode->Flags & V_DBLSCAN)
 384                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 385
 386                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
 387                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = mode->CrtcHDisplay < 1280 ? 0x04 : 0x00;
 388                 break;
 389         }
 390
 391         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 392                 /* This is a bit of a guess. */
 393                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] |= 0xB8;
 394         }
 395
 396         /* The NV40 seems to have more similarities to NV3x than other cards. */
 397         if (pNv->NVArch < 0x41) {
 398                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
 399                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
 400         }
 401
 402         if (nv_crtc->head == 1) {
 403                 if (!nv4x_single_stage_pll_mode) {
 404                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 405                 } else {
 406                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 407                 }
 408                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
 409         } else {
 410                 if (!nv4x_single_stage_pll_mode) {
 411                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 412                 } else {
 413                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 414                 }
 415                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
 416         }
 417
 418         /* The blob uses this always, so let's do the same */
 419         if (pNv->Architecture == NV_ARCH_40) {
 420                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
 421         }
 422
 423         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
 424         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
 425         if (pNv->Architecture >= NV_ARCH_30) {
 426                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
 427         }
 428
 429         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 430                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = ((mode->CrtcHDisplay/16) & 0x700) >> 3;
 431         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 432                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((mode->CrtcHDisplay*bpp)/64) & 0x700) >> 3;
 433         } else { /* framebuffer can be larger than crtc scanout area. */
 434                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((pScrn->displayWidth/8) * pixelDepth) & 0x700) >> 3;
 435         }
 436         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
 437 }
 438
 439 static void
 440 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
 441 {
 442         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 443         ScrnInfoPtr pScrn = crtc->scrn;
 444         NVPtr pNv = NVPTR(pScrn);
 445         unsigned char seq1 = 0, crtc17 = 0;
 446         unsigned char crtc1A;
 447
 448         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_dpms is called for CRTC %d with mode %d.\n", nv_crtc->head, mode);
 449
 450         if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
 451                 return;
 452
 453         nv_crtc->last_dpms = mode;
 454
 455         if (pNv->twoHeads)
 456                 NVSetOwner(pScrn, nv_crtc->head);
 457
 458         crtc1A = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
 459         switch(mode) {
 460                 case DPMSModeStandby:
 461                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
 462                 seq1 = 0x20;
 463                 crtc17 = 0x80;
 464                 crtc1A |= 0x80;
 465                 break;
 466         case DPMSModeSuspend:
 467                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
 468                 seq1 = 0x20;
 469                 crtc17 = 0x80;
 470                 crtc1A |= 0x40;
 471                 break;
 472         case DPMSModeOff:
 473                 /* Screen: Off; HSync: Off, VSync: Off */
 474                 seq1 = 0x20;
 475                 crtc17 = 0x00;
 476                 crtc1A |= 0xC0;
 477                 break;
 478         case DPMSModeOn:
 479         default:
 480                 /* Screen: On; HSync: On, VSync: On */
 481                 seq1 = 0x00;
 482                 crtc17 = 0x80;
 483                 break;
 484         }
 485
 486         NVVgaSeqReset(pNv, nv_crtc->head, true);
 487         /* Each head has it's own sequencer, so we can turn it off when we want */
 488         seq1 |= (NVReadVgaSeq(pNv, nv_crtc->head, 0x01) & ~0x20);
 489         NVWriteVgaSeq(pNv, nv_crtc->head, 0x1, seq1);
 490         crtc17 |= (NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_MODECTL) & ~0x80);
 491         usleep(10000);
 492         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_MODECTL, crtc17);
 493         NVVgaSeqReset(pNv, nv_crtc->head, false);
 494
 495         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1, crtc1A);
 496 }
 497
 498 static Bool
 499 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
 500                      DisplayModePtr adjusted_mode)
 501 {
 502         return TRUE;
 503 }
 504
 505 static void
 506 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 507 {
 508         ScrnInfoPtr pScrn = crtc->scrn;
 509         NVPtr pNv = NVPTR(pScrn);
 510         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 511         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 512         int depth = pScrn->depth;
 513
 514         /* Calculate our timings */
 515         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
 516         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
 517         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
 518         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
 519         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
 520         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
 521         int vertDisplay         = mode->CrtcVDisplay                    - 1;
 522         int vertStart           = mode->CrtcVSyncStart          - 1;
 523         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
 524         int vertTotal           = mode->CrtcVTotal                      - 2;
 525         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
 526         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
 527
 528         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 529         bool fp_output = false;
 530         int i;
 531
 532         for (i = 0; i < xf86_config->num_output; i++) {
 533                 xf86OutputPtr output = xf86_config->output[i];
 534                 NVOutputPrivatePtr nv_output = output->driver_private;
 535
 536                 if (output->crtc == crtc && (nv_output->type == OUTPUT_LVDS || nv_output->type == OUTPUT_TMDS))
 537                         fp_output = true;
 538         }
 539
 540         /* This is pitch/memory size related. */
 541         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE))
 542                 depth = pNv->console_mode[nv_crtc->head].bpp;
 543
 544         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Mode clock: %d\n", mode->Clock);
 545         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Adjusted mode clock: %d\n", adjusted_mode->Clock);
 546
 547         if (fp_output) {
 548                 vertStart = vertTotal - 3;
 549                 vertEnd = vertTotal - 2;
 550                 vertBlankStart = vertStart;
 551                 horizStart = horizTotal - 5;
 552                 horizEnd = horizTotal - 2;
 553                 horizBlankEnd = horizTotal + 4;
 554                 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10)
 555                         /* This reportedly works around some video overlay bandwidth problems */
 556                         horizTotal += 2;
 557         }
 558
 559         if (mode->Flags & V_INTERLACE)
 560                 vertTotal |= 1;
 561
 562 #if 0
 563         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
 564         ErrorF("horizStart: 0x%X \n", horizStart);
 565         ErrorF("horizEnd: 0x%X \n", horizEnd);
 566         ErrorF("horizTotal: 0x%X \n", horizTotal);
 567         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
 568         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
 569         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
 570         ErrorF("vertStart: 0x%X \n", vertStart);
 571         ErrorF("vertEnd: 0x%X \n", vertEnd);
 572         ErrorF("vertTotal: 0x%X \n", vertTotal);
 573         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
 574         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
 575 #endif
 576
 577         /*
 578         * compute correct Hsync & Vsync polarity
 579         */
 580         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
 581                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
 582
 583                 regp->MiscOutReg = 0x23;
 584                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
 585                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
 586         } else {
 587                 int VDisplay = mode->VDisplay;
 588                 if (mode->Flags & V_DBLSCAN)
 589                         VDisplay *= 2;
 590                 if (mode->VScan > 1)
 591                         VDisplay *= mode->VScan;
 592                 if (VDisplay < 400) {
 593                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
 594                 } else if (VDisplay < 480) {
 595                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
 596                 } else if (VDisplay < 768) {
 597                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
 598                 } else {
 599                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
 600                 }
 601         }
 602
 603         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
 604
 605         /*
 606         * Time Sequencer
 607         */
 608         regp->Sequencer[0] = 0x00;
 609         /* 0x20 disables the sequencer */
 610         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 611                 if (mode->HDisplay == 720) {
 612                         regp->Sequencer[1] = 0x21; /* enable 9/8 mode */
 613                 } else {
 614                         regp->Sequencer[1] = 0x20;
 615                 }
 616         } else {
 617                 if (mode->Flags & V_CLKDIV2) {
 618                         regp->Sequencer[1] = 0x29;
 619                 } else {
 620                         regp->Sequencer[1] = 0x21;
 621                 }
 622         }
 623         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 624                 regp->Sequencer[2] = 0x03; /* select 2 out of 4 planes */
 625         } else {
 626                 regp->Sequencer[2] = 0x0F;
 627         }
 628         regp->Sequencer[3] = 0x00;                     /* Font select */
 629         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 630                 regp->Sequencer[4] = 0x02;
 631         } else {
 632                 regp->Sequencer[4] = 0x0E;                             /* Misc */
 633         }
 634
 635         /*
 636         * CRTC Controller
 637         */
 638         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
 639         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
 640         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
 641         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
 642                                 | SetBit(7);
 643         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
 644         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
 645                                 | SetBitField(horizEnd,4:0,4:0);
 646         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
 647         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
 648                                 | SetBitField(vertDisplay,8:8,1:1)
 649                                 | SetBitField(vertStart,8:8,2:2)
 650                                 | SetBitField(vertBlankStart,8:8,3:3)
 651                                 | SetBit(4)
 652                                 | SetBitField(vertTotal,9:9,5:5)
 653                                 | SetBitField(vertDisplay,9:9,6:6)
 654                                 | SetBitField(vertStart,9:9,7:7);
 655         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
 656         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
 657                                 | SetBit(6)
 658                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00)
 659                                 | (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0xF : 0x00); /* 8x15 chars */
 660         if (NVMatchModePrivate(mode, NV_MODE_VGA)) { /* Were do these cursor offsets come from? */
 661                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0xD; /* start scanline */
 662                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0xE; /* end scanline */
 663         } else {
 664                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0x00;
 665                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0x00;
 666         }
 667         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
 668         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
 669         regp->CRTC[0xe] = 0x00;
 670         regp->CRTC[0xf] = 0x00;
 671         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
 672         /* What is the meaning of bit5, it is empty in the vga spec. */
 673         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) |
 674                                                                         (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0 : SetBit(5));
 675         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
 676         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 677                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = (mode->CrtcHDisplay/16);
 678         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 679                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((mode->CrtcHDisplay*depth)/64);
 680         } else { /* framebuffer can be larger than crtc scanout area. */
 681                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pScrn->bitsPerPixel/8));
 682         }
 683         if (depth == 4) { /* How can these values be calculated? */
 684                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x1F;
 685         } else {
 686                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x00;
 687         }
 688         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
 689         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
 690         /* 0x80 enables the sequencer, we don't want that */
 691         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 692                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xA3 & ~0x80;
 693         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 694                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
 695         } else {
 696                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
 697         }
 698         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
 699
 700         /*
 701          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
 702          */
 703
 704         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
 705                                 | SetBitField(vertBlankStart,10:10,3:3)
 706                                 | SetBitField(vertStart,10:10,2:2)
 707                                 | SetBitField(vertDisplay,10:10,1:1)
 708                                 | SetBitField(vertTotal,10:10,0:0);
 709
 710         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
 711                                 | SetBitField(horizDisplay,8:8,1:1)
 712                                 | SetBitField(horizBlankStart,8:8,2:2)
 713                                 | SetBitField(horizStart,8:8,3:3);
 714
 715         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
 716                                 | SetBitField(vertDisplay,11:11,2:2)
 717                                 | SetBitField(vertStart,11:11,4:4)
 718                                 | SetBitField(vertBlankStart,11:11,6:6);
 719
 720         if(mode->Flags & V_INTERLACE) {
 721                 horizTotal = (horizTotal >> 1) & ~1;
 722                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
 723                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
 724         } else {
 725                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
 726         }
 727
 728         /*
 729         * Graphics Display Controller
 730         */
 731         regp->Graphics[0] = 0x00;
 732         regp->Graphics[1] = 0x00;
 733         regp->Graphics[2] = 0x00;
 734         regp->Graphics[3] = 0x00;
 735         regp->Graphics[4] = 0x00;
 736         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 737                 regp->Graphics[5] = 0x10;
 738                 regp->Graphics[6] = 0x0E; /* map 32k mem */
 739                 regp->Graphics[7] = 0x00;
 740         } else {
 741                 regp->Graphics[5] = 0x40; /* 256 color mode */
 742                 regp->Graphics[6] = 0x05; /* map 64k mem + graphic mode */
 743                 regp->Graphics[7] = 0x0F;
 744         }
 745         regp->Graphics[8] = 0xFF;
 746
 747         regp->Attribute[0]  = 0x00; /* standard colormap translation */
 748         regp->Attribute[1]  = 0x01;
 749         regp->Attribute[2]  = 0x02;
 750         regp->Attribute[3]  = 0x03;
 751         regp->Attribute[4]  = 0x04;
 752         regp->Attribute[5]  = 0x05;
 753         regp->Attribute[6]  = 0x06;
 754         regp->Attribute[7]  = 0x07;
 755         regp->Attribute[8]  = 0x08;
 756         regp->Attribute[9]  = 0x09;
 757         regp->Attribute[10] = 0x0A;
 758         regp->Attribute[11] = 0x0B;
 759         regp->Attribute[12] = 0x0C;
 760         regp->Attribute[13] = 0x0D;
 761         regp->Attribute[14] = 0x0E;
 762         regp->Attribute[15] = 0x0F;
 763         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 764                 regp->Attribute[16] = 0x0C; /* Line Graphics Enable + Blink enable */
 765         } else {
 766                 regp->Attribute[16] = 0x01; /* Enable graphic mode */
 767         }
 768         /* Non-vga */
 769         regp->Attribute[17] = 0x00;
 770         regp->Attribute[18] = 0x0F; /* enable all color planes */
 771         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 772                 regp->Attribute[19] = 0x08; /* shift bits by 8 */
 773         } else {
 774                 regp->Attribute[19] = 0x00;
 775         }
 776         regp->Attribute[20] = 0x00;
 777 }
 778
 779 /**
 780  * Sets up registers for the given mode/adjusted_mode pair.
 781  *
 782  * The clocks, CRTCs and outputs attached to this CRTC must be off.
 783  *
 784  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
 785  * be easily turned on/off after this.
 786  */
 787 static void
 788 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 789 {
 790         ScrnInfoPtr pScrn = crtc->scrn;
 791         NVPtr pNv = NVPTR(pScrn);
 792         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 793         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 794         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
 795         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 796         bool lvds_output = false;
 797         bool fp_output = false;
 798         int i;
 799
 800         for (i = 0; i < xf86_config->num_output; i++) {
 801                 xf86OutputPtr output = xf86_config->output[i];
 802                 NVOutputPrivatePtr nv_output = output->driver_private;
 803
 804                 if (output->crtc == crtc && nv_output->type == OUTPUT_LVDS)
 805                         lvds_output = true;
 806                 if (lvds_output || (output->crtc == crtc && nv_output->type == OUTPUT_TMDS))
 807                         fp_output = true;
 808         }
 809
 810         /* Registers not directly related to the (s)vga mode */
 811
 812         /* bit2 = 0 -> fine pitched crtc granularity */
 813         /* The rest disables double buffering on CRTC access */
 814         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
 815
 816         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
 817                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
 818                 if (nv_crtc->head == 0) {
 819                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
 820                 }
 821
 822                 if (fp_output) {
 823                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0);
 824                         if (!NVMatchModePrivate(mode, NV_MODE_VGA)) {
 825                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 1);
 826                         }
 827                 }
 828         } else {
 829                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
 830                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
 831         }
 832
 833         /* Sometimes 0x10 is used, what is this? */
 834         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
 835         /* Some kind of tmds switch for older cards */
 836         if (pNv->Architecture < NV_ARCH_40) {
 837                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
 838         }
 839
 840         /* What is the meaning of this register? */
 841         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
 842         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
 843
 844         regp->head = 0;
 845
 846         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
 847         /* But what are those special conditions? */
 848         if (pNv->Architecture <= NV_ARCH_30 && fp_output) {
 849                 if (nv_crtc->head == 1)
 850                         regp->head |= NV_CRTC_FSEL_FPP1;
 851                 else if (pNv->twoHeads)
 852                         regp->head |= NV_CRTC_FSEL_FPP2;
 853         } else if (nv_crtc->head == 1 && pNv->NVArch > 0x44)
 854                 /* Most G70 cards have FPP2 set on the secondary CRTC. */
 855                 regp->head |= NV_CRTC_FSEL_FPP2;
 856         /* Except for rare conditions I2C is enabled on the primary crtc */
 857         if (nv_crtc->head == 0)
 858                 regp->head |= NV_CRTC_FSEL_I2C;
 859
 860         /* Set overlay to desired crtc. */
 861         if (pNv->overlayAdaptor) {
 862                 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
 863                 if (pPriv->overlayCRTC == nv_crtc->head)
 864                         regp->head |= NV_CRTC_FSEL_OVERLAY;
 865         }
 866
 867         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
 868         /* This fixes my cursor corruption issue */
 869         regp->cursorConfig = 0x0;
 870         if(mode->Flags & V_DBLSCAN)
 871                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
 872         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 873                 regp->cursorConfig |=   (NV_CRTC_CURSOR_CONFIG_32BPP |
 874                                                         NV_CRTC_CURSOR_CONFIG_64PIXELS |
 875                                                         NV_CRTC_CURSOR_CONFIG_64LINES |
 876                                                         NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND);
 877         } else {
 878                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES;
 879         }
 880
 881         /* Unblock some timings */
 882         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
 883         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
 884
 885         /* What is the purpose of this register? */
 886         /* 0x14 may be disabled? */
 887         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
 888
 889         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
 890         if (lvds_output) {
 891                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
 892         } else if (fp_output) {
 893                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
 894         } else {
 895                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
 896         }
 897
 898         /* These values seem to vary */
 899         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
 900         regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = savep->CRTC[NV_VGA_CRTCX_SCRATCH4];
 901
 902         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 903                 regp->CRTC[NV_VGA_CRTCX_45] = 0x0;
 904         } else {
 905                 regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
 906         }
 907
 908         /* What does this do?:
 909          * bit0: crtc0
 910          * bit6: lvds
 911          * bit7: lvds + tmds (only in X)
 912          */
 913         if (nv_crtc->head == 0)
 914                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
 915         else
 916                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
 917
 918         if (lvds_output)
 919                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x40;
 920
 921         if (fp_output && !NVMatchModePrivate(mode, NV_MODE_VGA))
 922                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
 923
 924         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) { /* we need consistent restore. */
 925                 regp->CRTC[NV_VGA_CRTCX_52] = savep->CRTC[NV_VGA_CRTCX_52];
 926         } else {
 927                 /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1.*/
 928                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->SavedReg.crtc_reg[0].CRTC[NV_VGA_CRTCX_52];
 929                 if (!nv_crtc->head)
 930                         regp->CRTC[NV_VGA_CRTCX_52] += 4;
 931         }
 932
 933         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 934                 regp->unk830 = 0;
 935                 regp->unk834 = 0;
 936         } else {
 937                 regp->unk830 = mode->CrtcVDisplay - 3;
 938                 regp->unk834 = mode->CrtcVDisplay - 1;
 939         }
 940
 941         if (pNv->twoHeads)
 942                 /* This is what the blob does */
 943                 regp->unk850 = NVReadCRTC(pNv, 0, NV_CRTC_0850);
 944
 945         /* Never ever modify gpio, unless you know very well what you're doing */
 946         regp->gpio = NVReadCRTC(pNv, 0, NV_CRTC_GPIO);
 947
 948         if (pNv->twoHeads)
 949                 regp->gpio_ext = NVReadCRTC(pNv, 0, NV_CRTC_GPIO_EXT);
 950
 951         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 952                 regp->config = 0x0; /* VGA mode */
 953         } else {
 954                 regp->config = 0x2; /* HSYNC mode */
 955         }
 956
 957         /* Some misc regs */
 958         if (pNv->Architecture == NV_ARCH_40) {
 959                 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
 960                 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
 961         }
 962
 963         /* Calculate the state that is common to all crtcs (stored in the state struct) */
 964         nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->Clock);
 965
 966         /* Enable slaved mode */
 967         if (fp_output)
 968                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
 969
 970         /* Generic PRAMDAC regs */
 971
 972         if (pNv->Architecture >= NV_ARCH_10)
 973                 /* Only bit that bios and blob set. */
 974                 regp->nv10_cursync = (1 << 25);
 975
 976         uint8_t depth;
 977         /* This is mode related, not pitch. */
 978         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE))
 979                 depth = pNv->console_mode[nv_crtc->head].depth;
 980         else
 981                 depth = pScrn->depth;
 982
 983         switch (depth) {
 984                 case 4:
 985                         regp->general = 0x00000100;
 986                         break;
 987                 case 24:
 988                 case 15:
 989                         regp->general = 0x00100100;
 990                         break;
 991                 case 32:
 992                 case 16:
 993                 case 8:
 994                 default:
 995                         regp->general = 0x00101100;
 996                         break;
 997         }
 998         if (depth > 8 && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 999                 regp->general |= 0x30; /* enable palette mode */
1000         }
1001         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1002                 /* PIPE_LONG mode, something to do with the size of the cursor? */
1003                 regp->general |= (1<<29);
1004         }
1005
1006         /* Some values the blob sets */
1007         regp->unk_a20 = 0x0;
1008         regp->unk_a24 = 0xfffff;
1009         regp->unk_a34 = 0x1;
1010 }
1011
1012 /* this could be set in nv_output, but would require some rework of load/save */
1013 static void
1014 nv_crtc_mode_set_fp_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1015 {
1016         ScrnInfoPtr pScrn = crtc->scrn;
1017         NVPtr pNv = NVPTR(pScrn);
1018         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1019         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1020         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1021         NVOutputPrivatePtr nv_output = NULL;
1022         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1023         bool is_fp = false;
1024         bool is_lvds = false;
1025         int i;
1026
1027         for (i = 0; i < xf86_config->num_output; i++) {
1028                 xf86OutputPtr output = xf86_config->output[i];
1029                 /* assuming one fp output per crtc seems ok */
1030                 nv_output = output->driver_private;
1031
1032                 if (output->crtc == crtc && nv_output->type == OUTPUT_LVDS)
1033                         is_lvds = true;
1034                 if (is_lvds || (output->crtc == crtc && nv_output->type == OUTPUT_TMDS)) {
1035                         is_fp = true;
1036                         if (nv_crtc->head != (nv_output->or & OUTPUT_C) >> 2)
1037                                 pNv->ModeReg.crosswired = true;
1038                         else
1039                                 pNv->ModeReg.crosswired = false;
1040                         break;
1041                 }
1042         }
1043         if (!is_fp)
1044                 return;
1045
1046         regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1047         regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1048         regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1;
1049         regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1050         regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1051         regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1052         regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1053
1054         regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1055         regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1056         regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
1057         regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1058         regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1059         regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1060         regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1061
1062 #if 0
1063         ErrorF("Horizontal:\n");
1064         ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1065         ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1066         ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1067         ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1068         ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1069         ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1070         ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1071
1072         ErrorF("Vertical:\n");
1073         ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1074         ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1075         ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1076         ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1077         ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1078         ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1079         ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1080 #endif
1081
1082         /*
1083         * bit0: positive vsync
1084         * bit4: positive hsync
1085         * bit8: enable center mode
1086         * bit9: enable native mode
1087         * bit24: 12/24 bit interface (12bit=on, 24bit=off)
1088         * bit26: a bit sometimes seen on some g70 cards
1089         * bit28: fp display enable bit
1090         * bit31: set for dual link LVDS
1091         * nv10reg contains a few more things, but i don't quite get what it all means.
1092         */
1093
1094         regp->fp_control = (savep->fp_control & 0x04100000) |
1095                            NV_RAMDAC_FP_CONTROL_DISPEN_POS;
1096
1097         /* Deal with vsync/hsync polarity */
1098         /* LVDS screens do set this, but modes with +ve syncs are very rare */
1099         if (adjusted_mode->Flags & V_PVSYNC)
1100                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1101         if (adjusted_mode->Flags & V_PHSYNC)
1102                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1103
1104         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) /* seems to be used almost always */
1105                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1106         else if (nv_output->scaling_mode == SCALE_PANEL || nv_output->scaling_mode == SCALE_NOSCALE) /* panel needs to scale */
1107                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1108         /* This is also true for panel scaling, so we must put the panel scale check first */
1109         else if (mode->Clock == adjusted_mode->Clock) /* native mode */
1110                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1111         else /* gpu needs to scale */
1112                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1113
1114         if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
1115                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_WIDTH_12;
1116
1117         if (is_lvds && pNv->VBIOS.fp.dual_link)
1118                 regp->fp_control |= (8 << 28);
1119
1120         /* Use the generic value, and enable x-scaling, y-scaling, and the TMDS enable bit */
1121         regp->debug_0 = 0x01101191;
1122         /* We want automatic scaling */
1123         regp->debug_1 = 0;
1124         /* This can override HTOTAL and VTOTAL */
1125         regp->debug_2 = 0;
1126
1127         if (nv_output->scaling_mode == SCALE_ASPECT) {
1128                 /* Use 20.12 fixed point format to avoid floats */
1129                 uint32_t panel_ratio = (1 << 12) * nv_output->fpWidth / nv_output->fpHeight;
1130                 uint32_t aspect_ratio = (1 << 12) * mode->HDisplay / mode->VDisplay;
1131                 uint32_t h_scale = (1 << 12) * mode->HDisplay / nv_output->fpWidth;
1132                 uint32_t v_scale = (1 << 12) * mode->VDisplay / nv_output->fpHeight;
1133                 #define ONE_TENTH ((1 << 12) / 10)
1134
1135                 /* GPU scaling happens automatically at a ratio of 1.33 */
1136                 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1137                 if (h_scale != (1 << 12) && (panel_ratio > aspect_ratio + ONE_TENTH)) {
1138                         uint32_t diff;
1139
1140                         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Maintaining aspect ratio requires vertical black bars.\n");
1141
1142                         /* Scaling in both directions needs to the same */
1143                         h_scale = v_scale;
1144
1145                         /* Set a new horizontal scale factor and enable testmode (bit12) */
1146                         regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1147
1148                         diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1149                         regp->fp_horiz_regs[REG_DISP_VALID_START] += diff / 2;
1150                         regp->fp_horiz_regs[REG_DISP_VALID_END] -= diff / 2;
1151                 }
1152
1153                 /* Same scaling, just for panels with aspect ratios smaller than 1 */
1154                 if (v_scale != (1 << 12) && (panel_ratio < aspect_ratio - ONE_TENTH)) {
1155                         uint32_t diff;
1156
1157                         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Maintaining aspect ratio requires horizontal black bars.\n");
1158
1159                         /* Scaling in both directions needs to the same */
1160                         v_scale = h_scale;
1161
1162                         /* Set a new vertical scale factor and enable testmode (bit28) */
1163                         regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1164
1165                         diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1166                         regp->fp_vert_regs[REG_DISP_VALID_START] += diff / 2;
1167                         regp->fp_vert_regs[REG_DISP_VALID_END] -= diff / 2;
1168                 }
1169         }
1170
1171         /* Flatpanel support needs at least a NV10 */
1172         if (pNv->twoHeads) {
1173                 /* Output property. */
1174                 if (nv_output && nv_output->dithering) {
1175                         if (pNv->NVArch == 0x11)
1176                                 regp->dither = savep->dither | 0x00010000;
1177                         else {
1178                                 int i;
1179                                 regp->dither = savep->dither | 0x00000001;
1180                                 for (i = 0; i < 3; i++) {
1181                                         regp->dither_regs[i] = 0xe4e4e4e4;
1182                                         regp->dither_regs[i + 3] = 0x44444444;
1183                                 }
1184                         }
1185                 } else {
1186                         if (pNv->NVArch != 0x11) {
1187                                 /* reset them */
1188                                 int i;
1189                                 for (i = 0; i < 3; i++) {
1190                                         regp->dither_regs[i] = savep->dither_regs[i];
1191                                         regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
1192                                 }
1193                         }
1194                         regp->dither = savep->dither;
1195                 }
1196         } else {
1197                 regp->dither = savep->dither;
1198         }
1199 }
1200
1201 /**
1202  * Sets up registers for the given mode/adjusted_mode pair.
1203  *
1204  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1205  *
1206  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1207  * be easily turned on/off after this.
1208  */
1209 static void
1210 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1211                  DisplayModePtr adjusted_mode,
1212                  int x, int y)
1213 {
1214         ScrnInfoPtr pScrn = crtc->scrn;
1215         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1216         NVPtr pNv = NVPTR(pScrn);
1217
1218         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_mode_set is called for CRTC %d.\n", nv_crtc->head);
1219
1220         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
1221         xf86PrintModeline(pScrn->scrnIndex, mode);
1222         if (pNv->twoHeads)
1223                 NVSetOwner(pScrn, nv_crtc->head);
1224
1225         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
1226
1227         /* calculated in output_prepare, nv40 needs it written before calculating PLLs */
1228         if (pNv->Architecture == NV_ARCH_40) {
1229                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_SEL_CLK %08X\n", pNv->ModeReg.sel_clk);
1230                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
1231         }
1232         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1233         nv_crtc_mode_set_fp_regs(crtc, mode, adjusted_mode);
1234
1235         NVVgaProtect(pNv, nv_crtc->head, true);
1236         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
1237         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
1238         if (pScrn->depth > 8)
1239                 nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
1240         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1241         if (pNv->Architecture == NV_ARCH_40)
1242                 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
1243         else
1244                 nv_crtc_load_state_pll(crtc, &pNv->ModeReg);
1245
1246         NVVgaProtect(pNv, nv_crtc->head, false);
1247
1248         NVCrtcSetBase(crtc, x, y, NVMatchModePrivate(mode, NV_MODE_CONSOLE));
1249
1250 #if X_BYTE_ORDER == X_BIG_ENDIAN
1251         /* turn on LFB swapping */
1252         {
1253                 unsigned char tmp;
1254
1255                 tmp = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SWAPPING);
1256                 tmp |= (1 << 7);
1257                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SWAPPING, tmp);
1258         }
1259 #endif
1260 }
1261
1262 static void nv_crtc_save(xf86CrtcPtr crtc)
1263 {
1264         ScrnInfoPtr pScrn = crtc->scrn;
1265         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1266         NVPtr pNv = NVPTR(pScrn);
1267
1268         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_save is called for CRTC %d.\n", nv_crtc->head);
1269
1270         /* We just came back from terminal, so unlock */
1271         NVCrtcLockUnlock(crtc, FALSE);
1272
1273         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
1274         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
1275         nv_crtc_save_state_palette(crtc, &pNv->SavedReg);
1276         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
1277         nv_crtc_save_state_pll(crtc, &pNv->SavedReg);
1278
1279         /* init some state to saved value */
1280         pNv->ModeReg.reg580 = pNv->SavedReg.reg580;
1281         pNv->ModeReg.sel_clk = pNv->SavedReg.sel_clk & ~(0x5 << 16);
1282 }
1283
1284 static void nv_crtc_restore(xf86CrtcPtr crtc)
1285 {
1286         ScrnInfoPtr pScrn = crtc->scrn;
1287         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1288         NVPtr pNv = NVPTR(pScrn);
1289         RIVA_HW_STATE *state;
1290         NVCrtcRegPtr savep;
1291
1292         state = &pNv->SavedReg;
1293         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1294
1295         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_restore is called for CRTC %d.\n", nv_crtc->head);
1296
1297         /* Just to be safe */
1298         NVCrtcLockUnlock(crtc, FALSE);
1299
1300         NVVgaProtect(pNv, nv_crtc->head, true);
1301         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
1302         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
1303         nv_crtc_load_state_palette(crtc, &pNv->SavedReg);
1304         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1305
1306         /* Force restoring vpll. */
1307         savep->vpll_changed = true;
1308
1309         if (pNv->Architecture == NV_ARCH_40)
1310                 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
1311         else
1312                 nv_crtc_load_state_pll(crtc, &pNv->SavedReg);
1313         NVVgaProtect(pNv, nv_crtc->head, false);
1314
1315         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1316 }
1317
1318 static void
1319 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
1320 {
1321         ScrnInfoPtr pScrn = crtc->scrn;
1322         NVPtr pNv = NVPTR(pScrn);
1323
1324         if (pNv->twoHeads) {
1325                 uint32_t val = 0;
1326
1327                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1328
1329                 if (set) {
1330                         NVCrtcRegPtr regp;
1331
1332                         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1333                         val = regp->head;
1334                 }
1335
1336                 NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, val);
1337         }
1338 }
1339
1340 static void nv_crtc_prepare(xf86CrtcPtr crtc)
1341 {
1342         ScrnInfoPtr pScrn = crtc->scrn;
1343         NVPtr pNv = NVPTR(pScrn);
1344         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1345
1346         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_prepare is called for CRTC %d.\n", nv_crtc->head);
1347
1348         /* Just in case */
1349         NVCrtcLockUnlock(crtc, 0);
1350
1351         NVResetCrtcConfig(crtc, FALSE);
1352
1353         crtc->funcs->dpms(crtc, DPMSModeOff);
1354
1355         /* Sync the engine before adjust mode */
1356         if (pNv->EXADriverPtr) {
1357                 exaMarkSync(pScrn->pScreen);
1358                 exaWaitSync(pScrn->pScreen);
1359         }
1360
1361         NVBlankScreen(pScrn, nv_crtc->head, true);
1362
1363         /* Some more preperation. */
1364         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
1365         if (pNv->Architecture == NV_ARCH_40) {
1366                 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1367                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1368         }
1369 }
1370
1371 static void nv_crtc_commit(xf86CrtcPtr crtc)
1372 {
1373         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1374         ScrnInfoPtr pScrn = crtc->scrn;
1375         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_commit for CRTC %d.\n", nv_crtc->head);
1376
1377         crtc->funcs->dpms (crtc, DPMSModeOn);
1378
1379         if (crtc->scrn->pScreen != NULL) {
1380                 NVPtr pNv = NVPTR(crtc->scrn);
1381
1382                 xf86_reload_cursors (crtc->scrn->pScreen);
1383                 if (!pNv->alphaCursor) {
1384                         /* this works round the fact that xf86_reload_cursors
1385                          * will quite happily show the hw cursor when it knows
1386                          * the hardware can't do alpha, and the current cursor
1387                          * has an alpha channel
1388                          */
1389                         xf86ForceHWCursor(crtc->scrn->pScreen, 1);
1390                         xf86ForceHWCursor(crtc->scrn->pScreen, 0);
1391                 }
1392         }
1393
1394         NVResetCrtcConfig(crtc, TRUE);
1395 }
1396
1397 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1398 {
1399         return FALSE;
1400 }
1401
1402 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1403 {
1404 }
1405
1406 static void
1407 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
1408                                         int size)
1409 {
1410         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1411         ScrnInfoPtr pScrn = crtc->scrn;
1412         NVPtr pNv = NVPTR(pScrn);
1413         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1414         int i, j;
1415
1416         switch (pScrn->depth) {
1417         case 15:
1418                 /* R5G5B5 */
1419                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
1420                 for (i = 0; i < 32; i++) {
1421                         for (j = 0; j < 8; j++) {
1422                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1423                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
1424                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1425                         }
1426                 }
1427                 break;
1428         case 16:
1429                 /* R5G6B5 */
1430                 /* First deal with the 5 bit colors */
1431                 for (i = 0; i < 32; i++) {
1432                         for (j = 0; j < 8; j++) {
1433                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1434                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1435                         }
1436                 }
1437                 /* Now deal with the 6 bit color */
1438                 for (i = 0; i < 64; i++) {
1439                         for (j = 0; j < 4; j++) {
1440                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
1441                         }
1442                 }
1443                 break;
1444         default:
1445                 /* R8G8B8 */
1446                 for (i = 0; i < 256; i++) {
1447                         regp->DAC[i * 3] = red[i] >> 8;
1448                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
1449                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
1450                 }
1451                 break;
1452         }
1453
1454         nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
1455 }
1456
1457 /**
1458  * Allocates memory for a locked-in-framebuffer shadow of the given
1459  * width and height for this CRTC's rotated shadow framebuffer.
1460  */
1461
1462 static void *
1463 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
1464 {
1465         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1466         ScrnInfoPtr pScrn = crtc->scrn;
1467 #if !NOUVEAU_EXA_PIXMAPS
1468         ScreenPtr pScreen = pScrn->pScreen;
1469 #endif /* !NOUVEAU_EXA_PIXMAPS */
1470         NVPtr pNv = NVPTR(pScrn);
1471         void *offset;
1472
1473         unsigned long rotate_pitch;
1474         int size, align = 64;
1475
1476         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_shadow_allocate is called.\n");
1477
1478         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1479         size = rotate_pitch * height;
1480
1481         assert(nv_crtc->shadow == NULL);
1482 #if NOUVEAU_EXA_PIXMAPS
1483         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
1484                         align, size, &nv_crtc->shadow)) {
1485                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to allocate memory for shadow buffer!\n");
1486                 return NULL;
1487         }
1488
1489         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
1490                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1491                                 "Failed to map shadow buffer.\n");
1492                 return NULL;
1493         }
1494
1495         offset = nv_crtc->shadow->map;
1496 #else
1497         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
1498         if (nv_crtc->shadow == NULL) {
1499                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1500                         "Couldn't allocate shadow memory for rotated CRTC.\n");
1501                 return NULL;
1502         }
1503         offset = pNv->FB->map + nv_crtc->shadow->offset;
1504 #endif /* NOUVEAU_EXA_PIXMAPS */
1505
1506         return offset;
1507 }
1508
1509 /**
1510  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
1511  */
1512 static PixmapPtr
1513 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
1514 {
1515         ScrnInfoPtr pScrn = crtc->scrn;
1516 #if NOUVEAU_EXA_PIXMAPS
1517         ScreenPtr pScreen = pScrn->pScreen;
1518         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1519 #endif /* NOUVEAU_EXA_PIXMAPS */
1520         unsigned long rotate_pitch;
1521         PixmapPtr rotate_pixmap;
1522 #if NOUVEAU_EXA_PIXMAPS
1523         struct nouveau_pixmap *nvpix;
1524 #endif /* NOUVEAU_EXA_PIXMAPS */
1525
1526         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_shadow_create is called.\n");
1527
1528         if (!data)
1529                 data = crtc->funcs->shadow_allocate (crtc, width, height);
1530
1531         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1532
1533 #if NOUVEAU_EXA_PIXMAPS
1534         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
1535         rotate_pixmap = pScreen->CreatePixmap(pScreen,
1536                                                                 0, /* width */
1537                                                                 0, /* height */
1538         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
1539                                                                 pScrn->depth,
1540                                                                 0);
1541         #else
1542                                                                 pScrn->depth);
1543         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
1544 #else
1545         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
1546                                                                 width, height,
1547                                                                 pScrn->depth,
1548                                                                 pScrn->bitsPerPixel,
1549                                                                 rotate_pitch,
1550                                                                 data);
1551 #endif /* NOUVEAU_EXA_PIXMAPS */
1552
1553         if (rotate_pixmap == NULL) {
1554                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1555                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
1556         }
1557
1558 #if NOUVEAU_EXA_PIXMAPS
1559         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1560         if (!nvpix) {
1561                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No initial shadow private available for rotation.\n");
1562         } else {
1563                 nvpix->bo = nv_crtc->shadow;
1564                 nvpix->mapped = TRUE;
1565         }
1566
1567         /* Modify the pixmap to actually be the one we need. */
1568         pScreen->ModifyPixmapHeader(rotate_pixmap,
1569                                         width,
1570                                         height,
1571                                         pScrn->depth,
1572                                         pScrn->bitsPerPixel,
1573                                         rotate_pitch,
1574                                         data);
1575
1576         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1577         if (!nvpix || !nvpix->bo)
1578                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No final shadow private available for rotation.\n");
1579 #endif /* NOUVEAU_EXA_PIXMAPS */
1580
1581         return rotate_pixmap;
1582 }
1583
1584 static void
1585 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
1586 {
1587         ScrnInfoPtr pScrn = crtc->scrn;
1588         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1589         ScreenPtr pScreen = pScrn->pScreen;
1590
1591         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_shadow_destroy is called.\n");
1592
1593         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
1594                 pScreen->DestroyPixmap(rotate_pixmap);
1595         }
1596
1597 #if !NOUVEAU_EXA_PIXMAPS
1598         if (data && nv_crtc->shadow) {
1599                 exaOffscreenFree(pScreen, nv_crtc->shadow);
1600         }
1601 #endif /* !NOUVEAU_EXA_PIXMAPS */
1602
1603         nv_crtc->shadow = NULL;
1604 }
1605
1606 /* NV04-NV10 doesn't support alpha cursors */
1607 static const xf86CrtcFuncsRec nv_crtc_funcs = {
1608         .dpms = nv_crtc_dpms,
1609         .save = nv_crtc_save, /* XXX */
1610         .restore = nv_crtc_restore, /* XXX */
1611         .mode_fixup = nv_crtc_mode_fixup,
1612         .mode_set = nv_crtc_mode_set,
1613         .prepare = nv_crtc_prepare,
1614         .commit = nv_crtc_commit,
1615         .destroy = NULL, /* XXX */
1616         .lock = nv_crtc_lock,
1617         .unlock = nv_crtc_unlock,
1618         .set_cursor_colors = nv_crtc_set_cursor_colors,
1619         .set_cursor_position = nv_crtc_set_cursor_position,
1620         .show_cursor = nv_crtc_show_cursor,
1621         .hide_cursor = nv_crtc_hide_cursor,
1622         .load_cursor_image = nv_crtc_load_cursor_image,
1623         .gamma_set = nv_crtc_gamma_set,
1624         .shadow_create = nv_crtc_shadow_create,
1625         .shadow_allocate = nv_crtc_shadow_allocate,
1626         .shadow_destroy = nv_crtc_shadow_destroy,
1627 };
1628
1629 /* NV11 and up has support for alpha cursors. */
1630 /* Due to different maximum sizes we cannot allow it to use normal cursors */
1631 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
1632         .dpms = nv_crtc_dpms,
1633         .save = nv_crtc_save, /* XXX */
1634         .restore = nv_crtc_restore, /* XXX */
1635         .mode_fixup = nv_crtc_mode_fixup,
1636         .mode_set = nv_crtc_mode_set,
1637         .prepare = nv_crtc_prepare,
1638         .commit = nv_crtc_commit,
1639         .destroy = NULL, /* XXX */
1640         .lock = nv_crtc_lock,
1641         .unlock = nv_crtc_unlock,
1642         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
1643         .set_cursor_position = nv_crtc_set_cursor_position,
1644         .show_cursor = nv_crtc_show_cursor,
1645         .hide_cursor = nv_crtc_hide_cursor,
1646         .load_cursor_argb = nv_crtc_load_cursor_argb,
1647         .gamma_set = nv_crtc_gamma_set,
1648         .shadow_create = nv_crtc_shadow_create,
1649         .shadow_allocate = nv_crtc_shadow_allocate,
1650         .shadow_destroy = nv_crtc_shadow_destroy,
1651 };
1652
1653
1654 void
1655 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
1656 {
1657         NVPtr pNv = NVPTR(pScrn);
1658         xf86CrtcPtr crtc;
1659         NVCrtcPrivatePtr nv_crtc;
1660         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[crtc_num];
1661         int i;
1662
1663         if (pNv->Architecture == NV_ARCH_50)
1664                 crtc = xf86CrtcCreate(pScrn, nv50_get_crtc_funcs());
1665         else if (pNv->NVArch >= 0x11)
1666                 crtc = xf86CrtcCreate(pScrn, &nv11_crtc_funcs);
1667         else
1668                 crtc = xf86CrtcCreate(pScrn, &nv_crtc_funcs);
1669         if (crtc == NULL)
1670                 return;
1671
1672         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
1673         nv_crtc->head = crtc_num;
1674         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1675
1676         crtc->driver_private = nv_crtc;
1677
1678         if (pNv->Architecture == NV_ARCH_50)
1679                 return;
1680
1681         /* Initialise the default LUT table. */
1682         for (i = 0; i < 256; i++) {
1683                 regp->DAC[i*3] = i;
1684                 regp->DAC[(i*3)+1] = i;
1685                 regp->DAC[(i*3)+2] = i;
1686         }
1687
1688         NVCrtcLockUnlock(crtc, FALSE);
1689 }
1690
1691 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1692 {
1693         ScrnInfoPtr pScrn = crtc->scrn;
1694         NVPtr pNv = NVPTR(pScrn);
1695         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1696         int i;
1697         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1698
1699         NVWritePVIO(pNv, nv_crtc->head, VGA_MISC_OUT_W, regp->MiscOutReg);
1700
1701         for (i = 0; i < 5; i++)
1702                 NVWriteVgaSeq(pNv, nv_crtc->head, i, regp->Sequencer[i]);
1703
1704         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
1705         NVWriteVgaCrtc(pNv, nv_crtc->head, 17, regp->CRTC[17] & ~0x80);
1706
1707         for (i = 0; i < 25; i++)
1708                 NVWriteVgaCrtc(pNv, nv_crtc->head, i, regp->CRTC[i]);
1709
1710         for (i = 0; i < 9; i++)
1711                 NVWriteVgaGr(pNv, nv_crtc->head, i, regp->Graphics[i]);
1712
1713         NVSetEnablePalette(pNv, nv_crtc->head, true);
1714         for (i = 0; i < 21; i++)
1715                 NVWriteVgaAttr(pNv, nv_crtc->head, i, regp->Attribute[i]);
1716
1717         NVSetEnablePalette(pNv, nv_crtc->head, false);
1718 }
1719
1720 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
1721 {
1722         ScrnInfoPtr pScrn = crtc->scrn;
1723         NVPtr pNv = NVPTR(pScrn);
1724         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1725         NVCrtcRegPtr regp;
1726         int i;
1727
1728         regp = &state->crtc_reg[nv_crtc->head];
1729
1730         if (pNv->Architecture >= NV_ARCH_10) {
1731                 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
1732                 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
1733                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
1734                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
1735                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1736                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1737                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1738                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1739                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
1740
1741                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
1742                 NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
1743                 NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
1744                 NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
1745                 if (pNv->Architecture == NV_ARCH_40) {
1746                         NVCrtcWriteCRTC(crtc, NV_CRTC_0850, regp->unk850);
1747                         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO_EXT, regp->gpio_ext);
1748                 }
1749
1750                 if (pNv->Architecture == NV_ARCH_40) {
1751                         uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1752                         if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
1753                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 | 0x10000);
1754                         } else {
1755                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1756                         }
1757                 }
1758         }
1759
1760         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
1761         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio);
1762
1763         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
1764         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
1765         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
1766         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
1767         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
1768         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
1769         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
1770         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
1771         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
1772         if (pNv->Architecture >= NV_ARCH_30)
1773                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
1774
1775         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
1776         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
1777         if (pNv->Architecture == NV_ARCH_40) /* HW bug */
1778                 nv_crtc_fix_nv40_hw_cursor(pScrn, nv_crtc->head);
1779         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
1780         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
1781
1782         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
1783         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
1784         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SCRATCH4, regp->CRTC[NV_VGA_CRTCX_SCRATCH4]);
1785         if (pNv->Architecture >= NV_ARCH_10) {
1786                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
1787                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
1788                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
1789                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
1790         }
1791         /* NV11 and NV20 stop at 0x52. */
1792         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1793                 if (override)
1794                         for (i = 0; i < 0x10; i++)
1795                                 NVWriteVgaCrtc5758(pNv, nv_crtc->head, i, regp->CR58[i]);
1796
1797                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
1798                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
1799
1800                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
1801
1802                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
1803                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
1804         }
1805
1806         /* Setting 1 on this value gives you interrupts for every vblank period. */
1807         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_EN_0, 0);
1808         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
1809 }
1810
1811 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1812 {
1813         ScrnInfoPtr pScrn = crtc->scrn;
1814         NVPtr pNv = NVPTR(pScrn);
1815         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1816         int i;
1817         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1818
1819         regp->MiscOutReg = NVReadPVIO(pNv, nv_crtc->head, VGA_MISC_OUT_R);
1820
1821         for (i = 0; i < 25; i++)
1822                 regp->CRTC[i] = NVReadVgaCrtc(pNv, nv_crtc->head, i);
1823
1824         NVSetEnablePalette(pNv, nv_crtc->head, true);
1825         for (i = 0; i < 21; i++)
1826                 regp->Attribute[i] = NVReadVgaAttr(pNv, nv_crtc->head, i);
1827         NVSetEnablePalette(pNv, nv_crtc->head, false);
1828
1829         for (i = 0; i < 9; i++)
1830                 regp->Graphics[i] = NVReadVgaGr(pNv, nv_crtc->head, i);
1831
1832         for (i = 0; i < 5; i++)
1833                 regp->Sequencer[i] = NVReadVgaSeq(pNv, nv_crtc->head, i);
1834 }
1835
1836 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1837 {
1838         ScrnInfoPtr pScrn = crtc->scrn;
1839         NVPtr pNv = NVPTR(pScrn);
1840         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1841         NVCrtcRegPtr regp;
1842         int i;
1843
1844         regp = &state->crtc_reg[nv_crtc->head];
1845
1846         regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD);
1847         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT0);
1848         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1);
1849         regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LSR);
1850         regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_PIXEL);
1851         regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_HEB);
1852         regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO1);
1853
1854         regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO0);
1855         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM);
1856         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_BUFFER);
1857         if (pNv->Architecture >= NV_ARCH_30)
1858                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM_NV30);
1859         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL0);
1860         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL1);
1861         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL2);
1862         regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_INTERLACE);
1863
1864         if (pNv->Architecture >= NV_ARCH_10) {
1865                 regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
1866                 regp->unk834 = NVCrtcReadCRTC(crtc, NV_CRTC_0834);
1867                 if (pNv->Architecture == NV_ARCH_40) {
1868                         regp->unk850 = NVCrtcReadCRTC(crtc, NV_CRTC_0850);
1869                         regp->gpio_ext = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO_EXT);
1870                 }
1871                 if (pNv->twoHeads) {
1872                         regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL);
1873                         regp->crtcOwner = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_OWNER);
1874                 }
1875                 regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG);
1876         }
1877
1878         regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO);
1879         regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
1880
1881         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_26);
1882         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_3B);
1883         regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SCRATCH4);
1884         if (pNv->Architecture >= NV_ARCH_10) {
1885                 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_EXTRA);
1886                 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_45);
1887                 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_4B);
1888                 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_52);
1889         }
1890         /* NV11 and NV20 don't have this, they stop at 0x52. */
1891         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1892                 for (i = 0; i < 0x10; i++)
1893                         regp->CR58[i] = NVReadVgaCrtc5758(pNv, nv_crtc->head, i);
1894
1895                 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_59);
1896                 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_HTIMING);
1897                 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_VTIMING);
1898
1899                 regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_85);
1900                 regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_86);
1901         }
1902 }
1903
1904 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1905 {
1906         ScrnInfoPtr pScrn = crtc->scrn;
1907         NVPtr pNv = NVPTR(pScrn);
1908         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1909         NVCrtcRegPtr regp;
1910         int i;
1911
1912         regp = &state->crtc_reg[nv_crtc->head];
1913
1914         regp->general = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL);
1915
1916         if (pNv->twoHeads) {
1917                 regp->fp_control        = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_CONTROL);
1918                 regp->debug_0   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0);
1919                 regp->debug_1   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1);
1920                 regp->debug_2   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2);
1921
1922                 regp->unk_a20 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A20);
1923                 regp->unk_a24 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A24);
1924                 regp->unk_a34 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A34);
1925         }
1926
1927         if (pNv->NVArch == 0x11) {
1928                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_DITHER_NV11);
1929         } else if (pNv->twoHeads) {
1930                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DITHER);
1931                 for (i = 0; i < 3; i++) {
1932                         regp->dither_regs[i] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4);
1933                         regp->dither_regs[i + 3] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4);
1934                 }
1935         }
1936         if (pNv->Architecture >= NV_ARCH_10)
1937                 regp->nv10_cursync = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC);
1938
1939         /* The regs below are 0 for non-flatpanels, so you can load and save them */
1940
1941         for (i = 0; i < 7; i++) {
1942                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
1943                 regp->fp_horiz_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1944         }
1945
1946         for (i = 0; i < 7; i++) {
1947                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
1948                 regp->fp_vert_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1949         }
1950 }
1951
1952 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1953 {
1954         ScrnInfoPtr pScrn = crtc->scrn;
1955         NVPtr pNv = NVPTR(pScrn);
1956         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1957         NVCrtcRegPtr regp;
1958         int i;
1959
1960         regp = &state->crtc_reg[nv_crtc->head];
1961
1962         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL, regp->general);
1963
1964         if (pNv->twoHeads) {
1965                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_CONTROL, regp->fp_control);
1966                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
1967                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
1968                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
1969                 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
1970                         uint32_t reg890 = NVCrtcReadRAMDAC(crtc, NV30_RAMDAC_890);
1971                         NVCrtcWriteRAMDAC(crtc, NV30_RAMDAC_89C, reg890);
1972                 }
1973
1974                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A20, regp->unk_a20);
1975                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A24, regp->unk_a24);
1976                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A34, regp->unk_a34);
1977         }
1978
1979         if (pNv->NVArch == 0x11) {
1980                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_DITHER_NV11, regp->dither);
1981         } else if (pNv->twoHeads) {
1982                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DITHER, regp->dither);
1983                 for (i = 0; i < 3; i++) {
1984                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4, regp->dither_regs[i]);
1985                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4, regp->dither_regs[i + 3]);
1986                 }
1987         }
1988         if (pNv->Architecture >= NV_ARCH_10)
1989                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
1990
1991         /* The regs below are 0 for non-flatpanels, so you can load and save them */
1992
1993         for (i = 0; i < 7; i++) {
1994                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
1995                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_horiz_regs[i]);
1996         }
1997
1998         for (i = 0; i < 7; i++) {
1999                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2000                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_vert_regs[i]);
2001         }
2002 }
2003
2004 void
2005 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y, Bool bios_restore)
2006 {
2007         ScrnInfoPtr pScrn = crtc->scrn;
2008         NVPtr pNv = NVPTR(pScrn);
2009         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2010         uint32_t start = 0;
2011
2012         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVCrtcSetBase is called with coordinates: x: %d y: %d\n", x, y);
2013
2014         if (bios_restore) {
2015                 start = pNv->console_mode[nv_crtc->head].fb_start;
2016         } else {
2017                 start += ((y * pScrn->displayWidth + x) * (pScrn->bitsPerPixel/8));
2018                 if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
2019 #if NOUVEAU_EXA_PIXMAPS
2020                         start = nv_crtc->shadow->offset;
2021 #else
2022                         start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
2023 #endif
2024                 } else {
2025                         start += pNv->FB->offset;
2026                 }
2027         }
2028
2029         /* 30 bits addresses in 32 bits according to haiku */
2030         NVCrtcWriteCRTC(crtc, NV_CRTC_START, start & 0xfffffffc);
2031
2032         /* set NV4/NV10 byte adress: (bit0 - 1) */
2033         NVWriteVgaAttr(pNv, nv_crtc->head, 0x13, (start & 0x3) << 1);
2034
2035         crtc->x = x;
2036         crtc->y = y;
2037 }
2038
2039 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2040 {
2041         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2042         NVPtr pNv = NVPTR(crtc->scrn);
2043         uint32_t mmiobase = nv_crtc->head ? NV_PDIO1_OFFSET : NV_PDIO0_OFFSET;
2044         int i;
2045
2046         VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff);
2047         VGA_WR08(pNv->REGS, VGA_DAC_READ_ADDR + mmiobase, 0x0);
2048
2049         for (i = 0; i < 768; i++) {
2050                 state->crtc_reg[nv_crtc->head].DAC[i] = NV_RD08(pNv->REGS, VGA_DAC_DATA + mmiobase);
2051                 DDXMMIOH("nv_crtc_save_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
2052         }
2053
2054         NVSetEnablePalette(pNv, nv_crtc->head, false);
2055 }
2056 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2057 {
2058         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2059         NVPtr pNv = NVPTR(crtc->scrn);
2060         uint32_t mmiobase = nv_crtc->head ? NV_PDIO1_OFFSET : NV_PDIO0_OFFSET;
2061         int i;
2062
2063         VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff);
2064         VGA_WR08(pNv->REGS, VGA_DAC_WRITE_ADDR + mmiobase, 0x0);
2065
2066         for (i = 0; i < 768; i++) {
2067                 DDXMMIOH("nv_crtc_load_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
2068                 NV_WR08(pNv->REGS, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
2069         }
2070
2071         NVSetEnablePalette(pNv, nv_crtc->head, false);
2072 }
2073
2074 /*************************************************************************** \
2075 |*                                                                           *|
2076 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
2077 |*                                                                           *|
2078 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
2079 |*     international laws.  Users and possessors of this source code are     *|
2080 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
2081 |*     use this code in individual and commercial software.                  *|
2082 |*                                                                           *|
2083 |*     Any use of this source code must include,  in the user documenta-     *|
2084 |*     tion and  internal comments to the code,  notices to the end user     *|
2085 |*     as follows:                                                           *|
2086 |*                                                                           *|
2087 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
2088 |*                                                                           *|
2089 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
2090 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
2091 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
2092 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
2093 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
2094 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
2095 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
2096 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
2097 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
2098 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
2099 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
2100 |*                                                                           *|
2101 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
2102 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
2103 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
2104 |*     computer  software  documentation,"  as such  terms  are  used in     *|
2105 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
2106 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
2107 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
2108 |*     all U.S. Government End Users  acquire the source code  with only     *|
2109 |*     those rights set forth herein.                                        *|
2110 |*                                                                           *|
2111  \***************************************************************************/