2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2008 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "nv_include.h"
28 #if defined(__FreeBSD__) || defined(__NetBSD__)
29 #define bswap_16 bswap16
30 #define bswap_32 bswap32
36 /* FIXME: put these somewhere */
37 #define SEQ_INDEX VGA_SEQ_INDEX
38 #define NV_VGA_CRTCX_OWNER_HEADA 0x0
39 #define NV_VGA_CRTCX_OWNER_HEADB 0x3
40 #define FEATURE_MOBILE 0x10
44 static int crtchead = 0;
46 /* this will need remembering across a suspend */
47 static uint32_t saved_nv_pfb_cfg0;
54 static uint16_t le16_to_cpu(const uint16_t x)
56 #if X_BYTE_ORDER == X_BIG_ENDIAN
63 static uint32_t le32_to_cpu(const uint32_t x)
65 #if X_BYTE_ORDER == X_BIG_ENDIAN
72 static bool nv_cksum(const uint8_t *data, unsigned int length)
74 /* there's a few checksums in the BIOS, so here's a generic checking function */
78 for (i = 0; i < length; i++)
87 static int score_vbios(ScrnInfoPtr pScrn, const uint8_t *data)
89 /* check for BIOS signature */
90 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
91 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
92 "... BIOS signature not found\n");
96 if (nv_cksum(data, data[2] * 512)) {
97 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
98 "... BIOS checksum invalid\n");
99 /* probably ought to set a do_not_execute flag for table parsing here,
100 * assuming most BIOSen are valid */
103 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "... appears to be valid\n");
108 static void load_vbios_prom(NVPtr pNv, uint8_t *data)
112 /* enable ROM access */
113 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED);
114 for (i = 0; i < NV_PROM_SIZE; i++) {
115 /* according to nvclock, we need that to work around a 6600GT/6800LE bug */
116 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
117 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
118 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
119 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
120 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
122 /* disable ROM access */
123 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
126 static void load_vbios_pramin(NVPtr pNv, uint8_t *data)
128 uint32_t old_bar0_pramin = 0;
131 if (pNv->Architecture >= NV_ARCH_50) {
132 uint32_t vbios_vram = (NV_RD32(pNv->REGS, 0x619f04) & ~0xff) << 8;
135 vbios_vram = (NV_RD32(pNv->REGS, 0x1700) << 16) + 0xf0000;
137 old_bar0_pramin = NV_RD32(pNv->REGS, 0x1700);
138 NV_WR32(pNv->REGS, 0x1700, vbios_vram >> 16);
141 for (i = 0; i < NV_PROM_SIZE; i++)
142 data[i] = NV_RD08(pNv->REGS, NV_PRAMIN_OFFSET + i);
144 if (pNv->Architecture >= NV_ARCH_50)
145 NV_WR32(pNv->REGS, 0x1700, old_bar0_pramin);
148 static void load_vbios_pci(NVPtr pNv, uint8_t *data)
150 #if XSERVER_LIBPCIACCESS
151 pci_device_read_rom(pNv->PciInfo, data);
153 xf86ReadPciBIOS(0, pNv->PciTag, 0, data, NV_PROM_SIZE);
157 static bool NVShadowVBIOS(ScrnInfoPtr pScrn, uint8_t *data)
159 NVPtr pNv = NVPTR(pScrn);
162 void (*loadbios)(NVPtr, uint8_t *);
166 { "PROM", load_vbios_prom },
168 { "PRAMIN", load_vbios_pramin },
170 { "PCI ROM", load_vbios_pci }
175 for (i = 0; i < sizeof(method) / sizeof(struct methods); i++) {
176 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
177 "Attempting to load BIOS image from %s\n", method[i].desc);
178 method[i].loadbios(pNv, data);
179 if ((method[i].score = score_vbios(pScrn, data)) == 2)
183 for (i = 0; i < sizeof(method) / sizeof(struct methods); i++)
184 if (method[i].score == 1) {
185 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
186 "Using BIOS image from %s\n", method[i].desc);
187 method[i].loadbios(pNv, data);
199 int length_multiplier;
200 bool (*handler)(ScrnInfoPtr pScrn, bios_t *, uint16_t, init_exec_t *);
209 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec);
211 #define MACRO_INDEX_SIZE 2
213 #define CONDITION_SIZE 12
214 #define IO_FLAG_CONDITION_SIZE 9
215 #define MEM_INIT_SIZE 66
217 static void still_alive(void)
223 static int nv_valid_reg(ScrnInfoPtr pScrn, uint32_t reg)
225 NVPtr pNv = NVPTR(pScrn);
227 /* C51 has misaligned regs on purpose. Marvellous */
228 if ((reg & 0x3 && pNv->VBIOS.chip_version != 0x51) ||
229 (reg & 0x2 && pNv->VBIOS.chip_version == 0x51)) {
230 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
231 "========== misaligned reg 0x%08X ==========\n", reg);
235 #define WITHIN(x,y,z) ((x>=y)&&(x<=y+z))
236 if (WITHIN(reg,NV_PMC_OFFSET,NV_PMC_SIZE))
238 if (WITHIN(reg,NV_PBUS_OFFSET,NV_PBUS_SIZE))
240 if (WITHIN(reg,NV_PFIFO_OFFSET,NV_PFIFO_SIZE))
242 if (pNv->VBIOS.chip_version >= 0x80 && WITHIN(reg, NV50_DISPLAY_OFFSET, NV50_DISPLAY_SIZE))
244 /* maybe a little large, but it will do for the moment. */
245 if (pNv->VBIOS.chip_version >= 0x80 && WITHIN(reg, 0x1000, 0xEFFF))
247 if (pNv->VBIOS.chip_version >= 0x30 && WITHIN(reg,0x4000,0x600))
249 if (pNv->VBIOS.chip_version >= 0x40 && WITHIN(reg,0xc000,0x48))
251 if (pNv->VBIOS.chip_version >= 0x17 && reg == 0x0000d204)
253 if (pNv->VBIOS.chip_version >= 0x40) {
254 if (reg == 0x00011014 || reg == 0x00020328)
256 if (WITHIN(reg,0x88000,NV_PBUS_SIZE)) /* new PBUS */
259 if (WITHIN(reg,NV_PFB_OFFSET,NV_PFB_SIZE))
261 if (WITHIN(reg,NV_PEXTDEV_OFFSET,NV_PEXTDEV_SIZE))
263 if (WITHIN(reg,NV_PCRTC0_OFFSET,NV_PCRTC0_SIZE * 2))
265 if (WITHIN(reg,NV_PRAMDAC0_OFFSET,NV_PRAMDAC0_SIZE * 2))
267 if (pNv->VBIOS.chip_version >= 0x17 && reg == 0x0070fff0)
269 if (pNv->VBIOS.chip_version == 0x51 && WITHIN(reg,NV_PRAMIN_OFFSET,NV_PRAMIN_SIZE))
273 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
274 "========== unknown reg 0x%08X ==========\n", reg);
279 static bool nv_valid_idx_port(ScrnInfoPtr pScrn, uint16_t port)
281 /* if adding more ports here, the read/write functions below will need
282 * updating so that the correct mmio range (PCIO, PDIO, PVIO) is used
283 * for the port in question
285 if (port == CRTC_INDEX_COLOR)
287 if (port == SEQ_INDEX)
290 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
291 "========== unknown indexed io port 0x%04X ==========\n", port);
296 static bool nv_valid_port(ScrnInfoPtr pScrn, uint16_t port)
298 /* if adding more ports here, the read/write functions below will need
299 * updating so that the correct mmio range (PCIO, PDIO, PVIO) is used
300 * for the port in question
302 if (port == VGA_ENABLE)
305 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
306 "========== unknown io port 0x%04X ==========\n", port);
311 static uint32_t nv32_rd(ScrnInfoPtr pScrn, uint32_t reg)
313 NVPtr pNv = NVPTR(pScrn);
316 if (!nv_valid_reg(pScrn, reg))
319 /* C51 sometimes uses regs with bit0 set in the address. For these
320 * cases there should exist a translation in a BIOS table to an IO
321 * port address which the BIOS uses for accessing the reg
323 * These only seem to appear for the power control regs to a flat panel
324 * and in C51 mmio traces the normal regs for 0x1308 and 0x1310 are
325 * used - hence the mask below. An S3 suspend-resume mmio trace from a
326 * C51 will be required to see if this is true for the power microcode
327 * in 0x14.., or whether the direct IO port access method is needed
332 data = NV_RD32(pNv->REGS, reg);
335 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
336 " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
341 static void nv32_wr(ScrnInfoPtr pScrn, uint32_t reg, uint32_t data)
343 NVPtr pNv = NVPTR(pScrn);
345 if (!nv_valid_reg(pScrn, reg))
348 /* see note in nv32_rd */
355 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
356 " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
358 if (pNv->VBIOS.execute) {
360 NV_WR32(pNv->REGS, reg, data);
364 static uint8_t nv_idx_port_rd(ScrnInfoPtr pScrn, uint16_t port, uint8_t index)
366 NVPtr pNv = NVPTR(pScrn);
369 if (!nv_valid_idx_port(pScrn, port))
372 if (port == SEQ_INDEX)
373 data = NVReadVgaSeq(pNv, crtchead, index);
374 else /* assume CRTC_INDEX_COLOR */
375 data = NVReadVgaCrtc(pNv, crtchead, index);
378 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
379 " Indexed IO read: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
380 port, index, crtchead, data);
385 static void nv_idx_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t index, uint8_t data)
387 NVPtr pNv = NVPTR(pScrn);
389 if (!nv_valid_idx_port(pScrn, port))
392 /* The current head is maintained in a file scope variable crtchead.
393 * We trap changes to CRTCX_OWNER and update the head variable
394 * and hence the register set written.
395 * As CRTCX_OWNER only exists on CRTC0, we update crtchead to head0
396 * in advance of the write, and to head1 after the write
398 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data != NV_VGA_CRTCX_OWNER_HEADB)
402 nv_idx_port_rd(pScrn, port, index);
404 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
405 " Indexed IO write: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
406 port, index, crtchead, data);
408 if (pNv->VBIOS.execute) {
410 if (port == SEQ_INDEX)
411 NVWriteVgaSeq(pNv, crtchead, index, data);
412 else /* assume CRTC_INDEX_COLOR */
413 NVWriteVgaCrtc(pNv, crtchead, index, data);
416 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data == NV_VGA_CRTCX_OWNER_HEADB)
420 static uint8_t nv_port_rd(ScrnInfoPtr pScrn, uint16_t port)
422 NVPtr pNv = NVPTR(pScrn);
425 if (!nv_valid_port(pScrn, port))
428 data = NVReadPVIO(pNv, crtchead, port);
431 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
432 " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
433 port, crtchead, data);
438 static void nv_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t data)
440 NVPtr pNv = NVPTR(pScrn);
442 if (!nv_valid_port(pScrn, port))
446 nv_port_rd(pScrn, port);
448 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
449 " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
450 port, crtchead, data);
452 if (pNv->VBIOS.execute) {
454 NVWritePVIO(pNv, crtchead, port, data);
458 #define ACCESS_UNLOCK 0
459 #define ACCESS_LOCK 1
460 static void crtc_access(ScrnInfoPtr pScrn, bool lock)
462 NVPtr pNv = NVPTR(pScrn);
465 NVSetOwner(pScrn, 0);
466 NVLockVgaCrtc(pNv, 0, lock);
468 NVSetOwner(pScrn, 1);
469 NVLockVgaCrtc(pNv, 1, lock);
470 NVSetOwner(pScrn, crtchead);
474 static bool io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, uint8_t cond)
476 /* The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
477 * for the CRTC index; 1 byte for the mask to apply to the value
478 * retrieved from the CRTC; 1 byte for the shift right to apply to the
479 * masked CRTC value; 2 bytes for the offset to the flag array, to
480 * which the shifted value is added; 1 byte for the mask applied to the
481 * value read from the flag array; and 1 byte for the value to compare
482 * against the masked byte from the flag table.
485 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
486 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[condptr])));
487 uint8_t crtcindex = bios->data[condptr + 2];
488 uint8_t mask = bios->data[condptr + 3];
489 uint8_t shift = bios->data[condptr + 4];
490 uint16_t flagarray = le16_to_cpu(*((uint16_t *)(&bios->data[condptr + 5])));
491 uint8_t flagarraymask = bios->data[condptr + 7];
492 uint8_t cmpval = bios->data[condptr + 8];
496 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
497 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, Cmpval: 0x%02X\n",
498 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
500 data = nv_idx_port_rd(pScrn, crtcport, crtcindex);
502 data = bios->data[flagarray + ((data & mask) >> shift)];
503 data &= flagarraymask;
506 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
507 "0x%04X: Checking if 0x%02X equals 0x%02X\n",
508 offset, data, cmpval);
516 int getMNP_single(ScrnInfoPtr pScrn, struct pll_lims *pll_lim, int clk, int *bestNM, int *bestlog2P)
518 /* Find M, N and P for a single stage PLL
520 * Note that some bioses (NV3x) have lookup tables of precomputed MNP
521 * values, but we're too lazy to use those atm
523 * "clk" parameter in kHz
524 * returns calculated clock
527 bios_t *bios = &NVPTR(pScrn)->VBIOS;
528 int minvco = pll_lim->vco1.minfreq, maxvco = pll_lim->vco1.maxfreq;
529 int minM = pll_lim->vco1.min_m, maxM = pll_lim->vco1.max_m;
530 int minN = pll_lim->vco1.min_n, maxN = pll_lim->vco1.max_n;
531 int minU = pll_lim->vco1.min_inputfreq, maxU = pll_lim->vco1.max_inputfreq;
533 int crystal = pll_lim->refclk;
536 int delta, bestdelta = INT_MAX;
539 /* this division verified for nv20, nv18, nv28 (Haiku), and nv34 */
540 /* possibly correlated with introduction of 27MHz crystal */
541 if (bios->chip_version <= 0x16 || bios->chip_version == 0x20) {
547 } else if (bios->chip_version < 0x40) {
555 } else /* nv4x may be subject to the nv17+ limits, but assume not for now */
558 if ((clk << maxlog2P) < minvco) {
559 minvco = clk << maxlog2P;
562 if (clk + clk/200 > maxvco) /* +0.5% */
563 maxvco = clk + clk/200;
565 /* NV34 goes maxlog2P->0, NV20 goes 0->maxlog2P */
566 for (log2P = 0; log2P <= maxlog2P; log2P++) {
575 for (M = minM; M <= maxM; M++) {
576 if (crystal/M < minU)
578 if (crystal/M > maxU)
581 /* add crystal/2 to round better */
582 N = (clkP * M + crystal/2) / crystal;
589 /* more rounding additions */
590 calcclk = ((N * crystal + P/2) / P + M/2) / M;
591 delta = abs(calcclk - clk);
592 /* we do an exhaustive search rather than terminating
593 * on an optimality condition...
595 if (delta < bestdelta) {
598 *bestNM = N << 8 | M;
600 if (delta == 0) /* except this one */
609 int getMNP_double(ScrnInfoPtr pScrn, struct pll_lims *pll_lim, int clk, int *bestNM1, int *bestNM2, int *bestlog2P)
611 /* Find M, N and P for a two stage PLL
613 * Note that some bioses (NV30+) have lookup tables of precomputed MNP
614 * values, but we're too lazy to use those atm
616 * "clk" parameter in kHz
617 * returns calculated clock
620 int minvco1 = pll_lim->vco1.minfreq, maxvco1 = pll_lim->vco1.maxfreq;
621 int minvco2 = pll_lim->vco2.minfreq, maxvco2 = pll_lim->vco2.maxfreq;
622 int minU1 = pll_lim->vco1.min_inputfreq, minU2 = pll_lim->vco2.min_inputfreq;
623 int maxU1 = pll_lim->vco1.max_inputfreq, maxU2 = pll_lim->vco2.max_inputfreq;
624 int minM1 = pll_lim->vco1.min_m, maxM1 = pll_lim->vco1.max_m;
625 int minN1 = pll_lim->vco1.min_n, maxN1 = pll_lim->vco1.max_n;
626 int minM2 = pll_lim->vco2.min_m, maxM2 = pll_lim->vco2.max_m;
627 int minN2 = pll_lim->vco2.min_n, maxN2 = pll_lim->vco2.max_n;
628 int crystal = pll_lim->refclk;
629 bool fixedgain2 = (minM2 == maxM2 && minN2 == maxN2);
630 int M1, N1, M2, N2, log2P;
631 int clkP, calcclk1, calcclk2, calcclkout;
632 int delta, bestdelta = INT_MAX;
635 int vco2 = (maxvco2 - maxvco2/200) / 2;
636 for (log2P = 0; clk && log2P < 6 && clk <= (vco2 >> log2P); log2P++) /* log2P is maximum of 6 */
640 if (maxvco2 < clk + clk/200) /* +0.5% */
641 maxvco2 = clk + clk/200;
643 for (M1 = minM1; M1 <= maxM1; M1++) {
644 if (crystal/M1 < minU1)
646 if (crystal/M1 > maxU1)
649 for (N1 = minN1; N1 <= maxN1; N1++) {
650 calcclk1 = crystal * N1 / M1;
651 if (calcclk1 < minvco1)
653 if (calcclk1 > maxvco1)
656 for (M2 = minM2; M2 <= maxM2; M2++) {
657 if (calcclk1/M2 < minU2)
659 if (calcclk1/M2 > maxU2)
662 /* add calcclk1/2 to round better */
663 N2 = (clkP * M2 + calcclk1/2) / calcclk1;
670 if (NVPTR(pScrn)->VBIOS.chip_version < 0x60)
671 if (N2/M2 < 4 || N2/M2 > 10)
674 calcclk2 = calcclk1 * N2 / M2;
675 if (calcclk2 < minvco2)
677 if (calcclk2 > maxvco2)
682 calcclkout = calcclk2 >> log2P;
683 delta = abs(calcclkout - clk);
684 /* we do an exhaustive search rather than terminating
685 * on an optimality condition...
687 if (delta < bestdelta) {
689 bestclk = calcclkout;
690 *bestNM1 = N1 << 8 | M1;
691 *bestNM2 = N2 << 8 | M2;
693 if (delta == 0) /* except this one */
703 static void setPLL_single(ScrnInfoPtr pScrn, uint32_t reg, int NM, int log2P)
705 bios_t *bios = &NVPTR(pScrn)->VBIOS;
706 uint32_t oldpll = nv32_rd(pScrn, reg);
707 uint32_t pll = (oldpll & 0xfff80000) | log2P << 16 | NM;
708 uint32_t saved_powerctrl_1 = 0;
709 int shift_powerctrl_1 = -4;
712 return; /* already set */
714 /* nv18 doesn't change POWERCTRL_1 for VPLL*; does gf4 need special-casing? */
715 if (bios->chip_version >= 0x17 && bios->chip_version != 0x20) {
717 case NV_RAMDAC_VPLL2:
718 shift_powerctrl_1 += 4;
720 shift_powerctrl_1 += 4;
722 shift_powerctrl_1 += 4;
723 case NV_RAMDAC_NVPLL:
724 shift_powerctrl_1 += 4;
727 if (shift_powerctrl_1 >= 0) {
728 saved_powerctrl_1 = nv32_rd(pScrn, NV_PBUS_POWERCTRL_1);
729 nv32_wr(pScrn, NV_PBUS_POWERCTRL_1, (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 1 << shift_powerctrl_1);
734 nv32_wr(pScrn, reg, (oldpll & 0xffff0000) | NM);
740 /* then write P as well */
741 nv32_wr(pScrn, reg, pll);
743 if (shift_powerctrl_1 >= 0)
744 nv32_wr(pScrn, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
747 static void setPLL_double_highregs(ScrnInfoPtr pScrn, uint32_t reg1, int NM1, int NM2, int log2P)
749 bios_t *bios = &NVPTR(pScrn)->VBIOS;
750 bool nv3035 = bios->chip_version == 0x30 || bios->chip_version == 0x35;
751 uint32_t reg2 = reg1 + ((reg1 == NV_RAMDAC_VPLL2) ? 0x5c : 0x70);
752 uint32_t oldpll1 = nv32_rd(pScrn, reg1), oldpll2 = !nv3035 ? nv32_rd(pScrn, reg2) : 0;
753 uint32_t pll1 = (oldpll1 & 0xfff80000) | log2P << 16 | NM1;
754 uint32_t pll2 = !nv3035 ? (oldpll2 & 0x7fff0000) | 1 << 31 | NM2 : 0;
755 uint32_t saved_powerctrl_1 = 0, savedc040 = 0, maskc040 = ~0;
756 int shift_powerctrl_1 = -1;
757 bool single_stage = !NM2 || (((NM2 >> 8) & 0xff) == (NM2 & 0xff));
760 pll1 = (pll1 & 0xfcc7ffff) | (NM2 & (0x18 << 8)) << 13 | (NM2 & (0x7 << 8)) << 11 | 8 << 4 | (NM2 & 7) << 4;
762 if (oldpll1 == pll1 && oldpll2 == pll2)
763 return; /* already set */
765 if (reg1 == NV_RAMDAC_NVPLL) {
766 shift_powerctrl_1 = 0;
767 maskc040 = ~(3 << 20);
769 if (reg1 == NV_RAMDAC_MPLL) {
770 shift_powerctrl_1 = 4;
771 maskc040 = ~(3 << 22);
773 if (shift_powerctrl_1 >= 0) {
774 saved_powerctrl_1 = nv32_rd(pScrn, NV_PBUS_POWERCTRL_1);
775 nv32_wr(pScrn, NV_PBUS_POWERCTRL_1, (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 1 << shift_powerctrl_1);
778 if (bios->chip_version >= 0x40) {
779 savedc040 = nv32_rd(pScrn, 0xc040);
780 nv32_wr(pScrn, 0xc040, savedc040 & maskc040);
783 if (reg1 == NV_RAMDAC_VPLL)
784 nv32_wr(pScrn, NV_RAMDAC_580, nv32_rd(pScrn, NV_RAMDAC_580) & ~NV_RAMDAC_580_VPLL1_ACTIVE);
785 if (reg1 == NV_RAMDAC_VPLL2)
786 nv32_wr(pScrn, NV_RAMDAC_580, nv32_rd(pScrn, NV_RAMDAC_580) & ~NV_RAMDAC_580_VPLL2_ACTIVE);
788 if (reg1 == NV_RAMDAC_VPLL)
789 nv32_wr(pScrn, NV_RAMDAC_580, nv32_rd(pScrn, NV_RAMDAC_580) | NV_RAMDAC_580_VPLL1_ACTIVE);
790 if (reg1 == NV_RAMDAC_VPLL2)
791 nv32_wr(pScrn, NV_RAMDAC_580, nv32_rd(pScrn, NV_RAMDAC_580) | NV_RAMDAC_580_VPLL2_ACTIVE);
797 nv32_wr(pScrn, reg2, pll2);
798 nv32_wr(pScrn, reg1, pll1);
800 if (shift_powerctrl_1 >= 0) {
801 nv32_wr(pScrn, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
802 if (bios->chip_version >= 0x40)
803 nv32_wr(pScrn, 0xc040, savedc040);
807 static void setPLL_double_lowregs(ScrnInfoPtr pScrn, uint32_t NMNMreg, int NM1, int NM2, int log2P)
809 /* When setting PLLs, there is a merry game of disabling and enabling
810 * various bits of hardware during the process. This function is a
811 * synthesis of six nv40 traces, nearly each card doing a subtly
812 * different thing. With luck all the necessary bits for each card are
813 * combined herein. Without luck it deviates from each card's formula
814 * so as to not work on any :)
817 uint32_t Preg = NMNMreg - 4;
818 uint32_t oldPval = nv32_rd(pScrn, Preg);
819 uint32_t NMNM = NM2 << 16 | NM1;
820 uint32_t Pval = (oldPval & ((Preg == 0x4020) ? ~(0x11 << 16) : ~(1 << 16))) | 0xc << 28 | log2P << 16;
821 uint32_t saved4600 = 0;
822 /* some cards have different maskc040s */
823 uint32_t maskc040 = ~(3 << 14), savedc040;
824 bool single_stage = !NM2 || (((NM2 >> 8) & 0xff) == (NM2 & 0xff));
826 if (nv32_rd(pScrn, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
832 maskc040 = ~(0xc << 24);
834 if (Preg == 0x4020) {
835 struct pll_lims pll_lim;
838 if (!get_pll_limits(pScrn, Preg, &pll_lim))
841 Pval2 = log2P + pll_lim.log2p_bias;
842 if (Pval2 > pll_lim.max_log2p_bias)
843 Pval2 = pll_lim.max_log2p_bias;
844 Pval |= 1 << 28 | Pval2 << 20;
846 saved4600 = nv32_rd(pScrn, 0x4600);
847 nv32_wr(pScrn, 0x4600, saved4600 | 8 << 28);
850 Pval |= (Preg == 0x4020) ? 1 << 12 : 1 << 8;
852 nv32_wr(pScrn, Preg, oldPval | 1 << 28);
853 nv32_wr(pScrn, Preg, Pval & ~(4 << 28));
854 if (Preg == 0x4020) {
856 nv32_wr(pScrn, 0x4020, Pval & ~(0xc << 28));
857 nv32_wr(pScrn, 0x4038, Pval & ~(0xc << 28));
860 savedc040 = nv32_rd(pScrn, 0xc040);
861 nv32_wr(pScrn, 0xc040, savedc040 & maskc040);
863 nv32_wr(pScrn, NMNMreg, NMNM);
864 if (NMNMreg == 0x4024)
865 nv32_wr(pScrn, 0x403c, NMNM);
867 nv32_wr(pScrn, Preg, Pval);
868 if (Preg == 0x4020) {
870 nv32_wr(pScrn, 0x4020, Pval);
871 nv32_wr(pScrn, 0x4038, Pval);
872 nv32_wr(pScrn, 0x4600, saved4600);
875 nv32_wr(pScrn, 0xc040, savedc040);
877 if (Preg == 0x4020) {
878 nv32_wr(pScrn, 0x4020, Pval & ~(1 << 28));
879 nv32_wr(pScrn, 0x4038, Pval & ~(1 << 28));
883 static void setPLL(ScrnInfoPtr pScrn, bios_t *bios, uint32_t reg, uint32_t clk)
886 struct pll_lims pll_lim;
887 int NM1 = 0xbeef, NM2 = 0xdead, log2P;
889 /* high regs (such as in the mac g5 table) are not -= 4 */
890 if (!get_pll_limits(pScrn, reg > 0x405c ? reg : reg - 4, &pll_lim))
893 if (bios->chip_version >= 0x40 || bios->chip_version == 0x30 ||
894 bios->chip_version == 0x31 || bios->chip_version == 0x35 ||
895 bios->chip_version == 0x36) {
896 getMNP_double(pScrn, &pll_lim, clk, &NM1, &NM2, &log2P);
898 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
899 "Could not find a suitable set of coefficients, giving up\n");
903 setPLL_double_highregs(pScrn, reg, NM1, NM2, log2P);
905 setPLL_double_lowregs(pScrn, reg, NM1, NM2, log2P);
907 getMNP_single(pScrn, &pll_lim, clk, &NM1, &log2P);
908 setPLL_single(pScrn, reg, NM1, log2P);
913 static bool init_prog(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
915 /* INIT_PROG opcode: 0x31
917 * offset (8 bit): opcode
918 * offset + 1 (32 bit): reg
919 * offset + 5 (32 bit): and mask
920 * offset + 9 (8 bit): shift right
921 * offset + 10 (8 bit): number of configurations
922 * offset + 11 (32 bit): register
923 * offset + 15 (32 bit): configuration 1
926 * Starting at offset + 15 there are "number of configurations"
927 * 32 bit values. To find out which configuration value to use
928 * read "CRTC reg" on the CRTC controller with index "CRTC index"
929 * and bitwise AND this value with "and mask" and then bit shift the
930 * result "shift right" bits to the right.
931 * Assign "register" with appropriate configuration value.
934 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
935 CARD32 and = *((CARD32 *) (&bios->data[offset + 5]));
936 CARD8 shiftr = *((CARD8 *) (&bios->data[offset + 9]));
937 CARD8 nr = *((CARD8 *) (&bios->data[offset + 10]));
938 CARD32 reg2 = *((CARD32 *) (&bios->data[offset + 11]));
940 CARD32 configval, tmp;
942 if (iexec->execute) {
943 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%04X\n", offset,
946 tmp = nv32_rd(pScrn, reg);
947 configuration = (tmp & and) >> shiftr;
949 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONFIGURATION TO USE: 0x%02X\n",
950 offset, configuration);
952 if (configuration <= nr) {
955 *((CARD32 *) (&bios->data[offset + 15 + configuration * 4]));
957 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%08X, VALUE: 0x%08X\n", offset,
960 tmp = nv32_rd(pScrn, reg2);
961 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n",
963 nv32_wr(pScrn, reg2, configval);
970 static bool init_io_restrict_prog(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
972 /* INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
974 * offset (8 bit): opcode
975 * offset + 1 (16 bit): CRTC port
976 * offset + 3 (8 bit): CRTC index
977 * offset + 4 (8 bit): mask
978 * offset + 5 (8 bit): shift
979 * offset + 6 (8 bit): count
980 * offset + 7 (32 bit): register
981 * offset + 11 (32 bit): configuration 1
984 * Starting at offset + 11 there are "count" 32 bit values.
985 * To find out which value to use read index "CRTC index" on "CRTC port",
986 * AND this value with "mask" and then bit shift right "shift" bits.
987 * Read the appropriate value using this index and write to "register"
990 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
991 uint8_t crtcindex = bios->data[offset + 3];
992 uint8_t mask = bios->data[offset + 4];
993 uint8_t shift = bios->data[offset + 5];
994 uint8_t count = bios->data[offset + 6];
995 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
1002 if (DEBUGLEVEL >= 6)
1003 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1004 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1005 offset, crtcport, crtcindex, mask, shift, count, reg);
1007 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1008 if (config > count) {
1009 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1010 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1011 offset, config, count);
1015 configval = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
1017 if (DEBUGLEVEL >= 6)
1018 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1019 "0x%04X: Writing config %02X\n", offset, config);
1021 nv32_wr(pScrn, reg, configval);
1026 static bool init_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1028 /* INIT_REPEAT opcode: 0x33 ('3')
1030 * offset (8 bit): opcode
1031 * offset + 1 (8 bit): count
1033 * Execute script following this opcode up to INIT_REPEAT_END
1037 uint8_t count = bios->data[offset + 1];
1040 /* no iexec->execute check by design */
1042 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1043 "0x%04X: REPEATING FOLLOWING SEGMENT %d TIMES\n",
1046 iexec->repeat = true;
1048 /* count - 1, as the script block will execute once when we leave this
1049 * opcode -- this is compatible with bios behaviour as:
1050 * a) the block is always executed at least once, even if count == 0
1051 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
1054 for (i = 0; i < count - 1; i++)
1055 parse_init_table(pScrn, bios, offset + 2, iexec);
1057 iexec->repeat = false;
1062 static bool init_io_restrict_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1064 /* INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
1066 * offset (8 bit): opcode
1067 * offset + 1 (16 bit): CRTC port
1068 * offset + 3 (8 bit): CRTC index
1069 * offset + 4 (8 bit): mask
1070 * offset + 5 (8 bit): shift
1071 * offset + 6 (8 bit): IO flag condition index
1072 * offset + 7 (8 bit): count
1073 * offset + 8 (32 bit): register
1074 * offset + 12 (16 bit): frequency 1
1077 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
1078 * Set PLL register "register" to coefficients for frequency n,
1079 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1080 * "mask" and shifted right by "shift". If "IO flag condition index" > 0,
1081 * and condition met, double frequency before setting it.
1084 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1085 uint8_t crtcindex = bios->data[offset + 3];
1086 uint8_t mask = bios->data[offset + 4];
1087 uint8_t shift = bios->data[offset + 5];
1088 int8_t io_flag_condition_idx = bios->data[offset + 6];
1089 uint8_t count = bios->data[offset + 7];
1090 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 8])));
1094 if (!iexec->execute)
1097 if (DEBUGLEVEL >= 6)
1098 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1099 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, IO Flag Condition: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1100 offset, crtcport, crtcindex, mask, shift, io_flag_condition_idx, count, reg);
1102 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1103 if (config > count) {
1104 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1105 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1106 offset, config, count);
1110 freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 12 + config * 2])));
1112 if (io_flag_condition_idx > 0) {
1113 if (io_flag_condition(pScrn, bios, offset, io_flag_condition_idx)) {
1114 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1115 "0x%04X: CONDITION FULFILLED - FREQ DOUBLED\n", offset);
1118 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1119 "0x%04X: CONDITION IS NOT FULFILLED. FREQ UNCHANGED\n", offset);
1122 if (DEBUGLEVEL >= 6)
1123 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1124 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1125 offset, reg, config, freq);
1127 setPLL(pScrn, bios, reg, freq * 10);
1132 static bool init_end_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1134 /* INIT_END_REPEAT opcode: 0x36 ('6')
1136 * offset (8 bit): opcode
1138 * Marks the end of the block for INIT_REPEAT to repeat
1141 /* no iexec->execute check by design */
1143 /* iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1144 * we're not in repeat mode
1152 static bool init_copy(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1154 /* INIT_COPY opcode: 0x37 ('7')
1156 * offset (8 bit): opcode
1157 * offset + 1 (32 bit): register
1158 * offset + 5 (8 bit): shift
1159 * offset + 6 (8 bit): srcmask
1160 * offset + 7 (16 bit): CRTC port
1161 * offset + 9 (8 bit): CRTC index
1162 * offset + 10 (8 bit): mask
1164 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1165 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC port
1168 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1169 uint8_t shift = bios->data[offset + 5];
1170 uint8_t srcmask = bios->data[offset + 6];
1171 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 7])));
1172 uint8_t crtcindex = bios->data[offset + 9];
1173 uint8_t mask = bios->data[offset + 10];
1177 if (!iexec->execute)
1180 if (DEBUGLEVEL >= 6)
1181 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1182 "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1183 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1185 data = nv32_rd(pScrn, reg);
1190 data <<= (0x100 - shift);
1194 crtcdata = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) | (uint8_t)data;
1195 nv_idx_port_wr(pScrn, crtcport, crtcindex, crtcdata);
1200 static bool init_not(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1202 /* INIT_NOT opcode: 0x38 ('8')
1204 * offset (8 bit): opcode
1206 * Invert the current execute / no-execute condition (i.e. "else")
1209 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1210 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1212 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1213 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", offset);
1215 iexec->execute = !iexec->execute;
1219 static bool init_io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1221 /* INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1223 * offset (8 bit): opcode
1224 * offset + 1 (8 bit): condition number
1226 * Check condition "condition number" in the IO flag condition table.
1227 * If condition not met skip subsequent opcodes until condition is
1228 * inverted (INIT_NOT), or we hit INIT_RESUME
1231 uint8_t cond = bios->data[offset + 1];
1233 if (!iexec->execute)
1236 if (io_flag_condition(pScrn, bios, offset, cond))
1237 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1238 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
1240 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1241 "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
1242 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1243 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1244 iexec->execute = false;
1250 static bool init_idx_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1252 /* INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1254 * offset (8 bit): opcode
1255 * offset + 1 (32 bit): control register
1256 * offset + 5 (32 bit): data register
1257 * offset + 9 (32 bit): mask
1258 * offset + 13 (32 bit): data
1259 * offset + 17 (8 bit): count
1260 * offset + 18 (8 bit): address 1
1261 * offset + 19 (8 bit): data 1
1264 * For each of "count" address and data pairs, write "data n" to "data register",
1265 * read the current value of "control register", and write it back once ANDed
1266 * with "mask", ORed with "data", and ORed with "address n"
1269 uint32_t controlreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1270 uint32_t datareg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1271 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1272 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 13])));
1273 uint8_t count = bios->data[offset + 17];
1277 if (!iexec->execute)
1280 if (DEBUGLEVEL >= 6)
1281 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1282 "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1283 offset, controlreg, datareg, mask, data, count);
1285 for (i = 0; i < count; i++) {
1286 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1287 uint8_t instdata = bios->data[offset + 19 + i * 2];
1289 if (DEBUGLEVEL >= 6)
1290 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1291 "0x%04X: Address: 0x%02X, Data: 0x%02X\n", offset, instaddress, instdata);
1293 nv32_wr(pScrn, datareg, instdata);
1294 value = (nv32_rd(pScrn, controlreg) & mask) | data | instaddress;
1295 nv32_wr(pScrn, controlreg, value);
1301 static bool init_io_restrict_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1303 /* INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1305 * offset (8 bit): opcode
1306 * offset + 1 (16 bit): CRTC port
1307 * offset + 3 (8 bit): CRTC index
1308 * offset + 4 (8 bit): mask
1309 * offset + 5 (8 bit): shift
1310 * offset + 6 (8 bit): count
1311 * offset + 7 (32 bit): register
1312 * offset + 11 (32 bit): frequency 1
1315 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1316 * Set PLL register "register" to coefficients for frequency n,
1317 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1318 * "mask" and shifted right by "shift".
1321 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1322 uint8_t crtcindex = bios->data[offset + 3];
1323 uint8_t mask = bios->data[offset + 4];
1324 uint8_t shift = bios->data[offset + 5];
1325 uint8_t count = bios->data[offset + 6];
1326 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
1330 if (!iexec->execute)
1333 if (DEBUGLEVEL >= 6)
1334 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1335 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1336 offset, crtcport, crtcindex, mask, shift, count, reg);
1341 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1342 if (config > count) {
1343 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1344 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1345 offset, config, count);
1349 freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
1351 if (DEBUGLEVEL >= 6)
1352 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1353 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1354 offset, reg, config, freq);
1356 setPLL(pScrn, bios, reg, freq);
1361 static bool init_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1363 /* INIT_PLL2 opcode: 0x4B ('K')
1365 * offset (8 bit): opcode
1366 * offset + 1 (32 bit): register
1367 * offset + 5 (32 bit): freq
1369 * Set PLL register "register" to coefficients for frequency "freq"
1372 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1373 uint32_t freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1375 if (!iexec->execute)
1378 if (DEBUGLEVEL >= 6)
1379 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1380 "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1383 setPLL(pScrn, bios, reg, freq);
1388 static uint32_t get_tmds_index_reg(ScrnInfoPtr pScrn, uint8_t mlv)
1390 /* For mlv < 0x80, it is an index into a table of TMDS base addresses
1391 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
1392 * to index a table of offsets to the basic 0x6808b0 address
1393 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
1394 * to index a table of offsets to the basic 0x6808b0 address, and then flip the offset by 8
1397 NVPtr pNv = NVPTR(pScrn);
1398 const int pramdac_offset[13] = {0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000};
1399 const uint32_t pramdac_table[4] = {0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8};
1402 /* here we assume that the DCB table has already been parsed */
1405 /* This register needs to be written to set index for reading CR58 */
1406 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_57, 0);
1407 dcb_entry = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_58);
1408 if (dcb_entry > pNv->dcb_table.entries) {
1409 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1410 "CR58 doesn't have a valid DCB entry currently (%02X)\n", dcb_entry);
1413 dacoffset = pramdac_offset[pNv->dcb_table.entry[dcb_entry].or];
1416 return (0x6808b0 + dacoffset);
1418 if (mlv > (sizeof(pramdac_table) / sizeof(uint32_t))) {
1419 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1420 "Magic Lookup Value too big (%02X)\n", mlv);
1423 return pramdac_table[mlv];
1427 static bool init_tmds(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1429 /* INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1431 * offset (8 bit): opcode
1432 * offset + 1 (8 bit): magic lookup value
1433 * offset + 2 (8 bit): TMDS address
1434 * offset + 3 (8 bit): mask
1435 * offset + 4 (8 bit): data
1437 * Read the data reg for TMDS address "TMDS address", AND it with mask
1438 * and OR it with data, then write it back
1439 * "magic lookup value" determines which TMDS base address register is used --
1440 * see get_tmds_index_reg()
1443 uint8_t mlv = bios->data[offset + 1];
1444 uint32_t tmdsaddr = bios->data[offset + 2];
1445 uint8_t mask = bios->data[offset + 3];
1446 uint8_t data = bios->data[offset + 4];
1447 uint32_t reg, value;
1449 if (!iexec->execute)
1452 if (DEBUGLEVEL >= 6)
1453 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1454 "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1455 offset, mlv, tmdsaddr, mask, data);
1457 if (!(reg = get_tmds_index_reg(pScrn, mlv)))
1460 nv32_wr(pScrn, reg, tmdsaddr | 0x10000);
1461 value = (nv32_rd(pScrn, reg + 4) & mask) | data;
1462 nv32_wr(pScrn, reg + 4, value);
1463 nv32_wr(pScrn, reg, tmdsaddr);
1468 static bool init_zm_tmds_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1470 /* INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1472 * offset (8 bit): opcode
1473 * offset + 1 (8 bit): magic lookup value
1474 * offset + 2 (8 bit): count
1475 * offset + 3 (8 bit): addr 1
1476 * offset + 4 (8 bit): data 1
1479 * For each of "count" TMDS address and data pairs write "data n" to "addr n"
1480 * "magic lookup value" determines which TMDS base address register is used --
1481 * see get_tmds_index_reg()
1484 uint8_t mlv = bios->data[offset + 1];
1485 uint8_t count = bios->data[offset + 2];
1489 if (!iexec->execute)
1492 if (DEBUGLEVEL >= 6)
1493 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1494 "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1495 offset, mlv, count);
1497 if (!(reg = get_tmds_index_reg(pScrn, mlv)))
1500 for (i = 0; i < count; i++) {
1501 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1502 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1504 nv32_wr(pScrn, reg + 4, tmdsdata);
1505 nv32_wr(pScrn, reg, tmdsaddr);
1511 static bool init_cr_idx_adr_latch(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1513 /* INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1515 * offset (8 bit): opcode
1516 * offset + 1 (8 bit): CRTC index1
1517 * offset + 2 (8 bit): CRTC index2
1518 * offset + 3 (8 bit): baseaddr
1519 * offset + 4 (8 bit): count
1520 * offset + 5 (8 bit): data 1
1523 * For each of "count" address and data pairs, write "baseaddr + n" to
1524 * "CRTC index1" and "data n" to "CRTC index2"
1525 * Once complete, restore initial value read from "CRTC index1"
1527 uint8_t crtcindex1 = bios->data[offset + 1];
1528 uint8_t crtcindex2 = bios->data[offset + 2];
1529 uint8_t baseaddr = bios->data[offset + 3];
1530 uint8_t count = bios->data[offset + 4];
1531 uint8_t oldaddr, data;
1534 if (!iexec->execute)
1537 if (DEBUGLEVEL >= 6)
1538 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1539 "0x%04X: Index1: 0x%02X, Index2: 0x%02X, BaseAddr: 0x%02X, Count: 0x%02X\n",
1540 offset, crtcindex1, crtcindex2, baseaddr, count);
1542 oldaddr = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex1);
1544 for (i = 0; i < count; i++) {
1545 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, baseaddr + i);
1547 data = bios->data[offset + 5 + i];
1548 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex2, data);
1551 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, oldaddr);
1556 static bool init_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1558 /* INIT_CR opcode: 0x52 ('R')
1560 * offset (8 bit): opcode
1561 * offset + 1 (8 bit): CRTC index
1562 * offset + 2 (8 bit): mask
1563 * offset + 3 (8 bit): data
1565 * Assign the value of at "CRTC index" ANDed with mask and ORed with data
1566 * back to "CRTC index"
1569 uint8_t crtcindex = bios->data[offset + 1];
1570 uint8_t mask = bios->data[offset + 2];
1571 uint8_t data = bios->data[offset + 3];
1574 if (!iexec->execute)
1577 if (DEBUGLEVEL >= 6)
1578 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1579 "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1580 offset, crtcindex, mask, data);
1582 value = (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex) & mask) | data;
1583 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, value);
1588 static bool init_zm_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1590 /* INIT_ZM_CR opcode: 0x53 ('S')
1592 * offset (8 bit): opcode
1593 * offset + 1 (8 bit): CRTC index
1594 * offset + 2 (8 bit): value
1596 * Assign "value" to CRTC register with index "CRTC index".
1599 uint8_t crtcindex = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1600 uint8_t data = bios->data[offset + 2];
1602 if (!iexec->execute)
1605 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, data);
1610 static bool init_zm_cr_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1612 /* INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1614 * offset (8 bit): opcode
1615 * offset + 1 (8 bit): count
1616 * offset + 2 (8 bit): CRTC index 1
1617 * offset + 3 (8 bit): value 1
1620 * For "count", assign "value n" to CRTC register with index "CRTC index n".
1623 uint8_t count = bios->data[offset + 1];
1626 if (!iexec->execute)
1629 for (i = 0; i < count; i++)
1630 init_zm_cr(pScrn, bios, offset + 2 + 2 * i - 1, iexec);
1635 static bool init_condition_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1637 /* INIT_CONDITION_TIME opcode: 0x56 ('V')
1639 * offset (8 bit): opcode
1640 * offset + 1 (8 bit): condition number
1641 * offset + 2 (8 bit): retries / 50
1643 * Check condition "condition number" in the condition table.
1644 * The condition table entry has 4 bytes for the address of the
1645 * register to check, 4 bytes for a mask and 4 for a test value.
1646 * If condition not met sleep for 2ms, and repeat upto "retries" times.
1647 * If still not met after retries, clear execution flag for this table.
1650 uint8_t cond = bios->data[offset + 1];
1651 uint16_t retries = bios->data[offset + 2];
1652 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
1653 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
1654 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
1655 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
1658 if (!iexec->execute)
1663 if (DEBUGLEVEL >= 6)
1664 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1665 "0x%04X: Cond: 0x%02X, Retries: 0x%02X\n", offset, cond, retries);
1667 for (; retries > 0; retries--) {
1668 data = nv32_rd(pScrn, reg) & mask;
1670 if (DEBUGLEVEL >= 6)
1671 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1672 "0x%04X: Checking if 0x%08X equals 0x%08X\n",
1673 offset, data, cmpval);
1675 if (data != cmpval) {
1676 if (DEBUGLEVEL >= 6)
1677 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1678 "0x%04X: Condition not met, sleeping for 2ms\n", offset);
1681 if (DEBUGLEVEL >= 6)
1682 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1683 "0x%04X: Condition met, continuing\n", offset);
1688 if (data != cmpval) {
1689 if (DEBUGLEVEL >= 6)
1690 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1691 "0x%04X: Condition still not met, skiping following opcodes\n", offset);
1692 iexec->execute = false;
1698 static bool init_zm_reg_sequence(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1700 /* INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1702 * offset (8 bit): opcode
1703 * offset + 1 (32 bit): base register
1704 * offset + 5 (8 bit): count
1705 * offset + 6 (32 bit): value 1
1708 * Starting at offset + 6 there are "count" 32 bit values.
1709 * For "count" iterations set "base register" + 4 * current_iteration
1710 * to "value current_iteration"
1713 uint32_t basereg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1714 uint32_t count = bios->data[offset + 5];
1717 if (!iexec->execute)
1720 if (DEBUGLEVEL >= 6)
1721 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1722 "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1723 offset, basereg, count);
1725 for (i = 0; i < count; i++) {
1726 uint32_t reg = basereg + i * 4;
1727 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + i * 4])));
1729 nv32_wr(pScrn, reg, data);
1736 static bool init_indirect_reg(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1738 /* INIT_INDIRECT_REG opcode: 0x5A
1740 * offset (8 bit): opcode
1741 * offset + 1 (32 bit): register
1742 * offset + 5 (16 bit): adress offset (in bios)
1744 * Lookup value at offset data in the bios and write it to reg
1746 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
1747 CARD16 data = le16_to_cpu(*((CARD16 *) (&bios->data[offset + 5])));
1748 CARD32 data2 = bios->data[data];
1750 if (iexec->execute) {
1751 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1752 "0x%04X: REG: 0x%04X, DATA AT: 0x%04X, VALUE IS: 0x%08X\n",
1753 offset, reg, data, data2);
1755 if (DEBUGLEVEL >= 6) {
1757 tmpval = nv32_rd(pScrn, reg);
1758 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n", offset, tmpval);
1761 nv32_wr(pScrn, reg, data2);
1767 static bool init_sub_direct(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1769 /* INIT_SUB_DIRECT opcode: 0x5B ('[')
1771 * offset (8 bit): opcode
1772 * offset + 1 (16 bit): subroutine offset (in bios)
1774 * Calls a subroutine that will execute commands until INIT_DONE
1778 uint16_t sub_offset = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1780 if (!iexec->execute)
1783 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: EXECUTING SUB-ROUTINE AT 0x%04X\n",
1784 offset, sub_offset);
1786 parse_init_table(pScrn, bios, sub_offset, iexec);
1788 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: END OF SUB-ROUTINE AT 0x%04X\n",
1789 offset, sub_offset);
1794 static bool init_copy_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1796 /* INIT_COPY_NV_REG opcode: 0x5F ('_')
1798 * offset (8 bit): opcode
1799 * offset + 1 (32 bit): src reg
1800 * offset + 5 (8 bit): shift
1801 * offset + 6 (32 bit): src mask
1802 * offset + 10 (32 bit): xor
1803 * offset + 14 (32 bit): dst reg
1804 * offset + 18 (32 bit): dst mask
1806 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1807 * "src mask", then XOR with "xor". Write this OR'd with
1808 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1811 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1812 uint8_t shift = bios->data[offset + 5];
1813 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1814 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1815 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1816 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1817 uint32_t srcvalue, dstvalue;
1819 if (!iexec->execute)
1822 if (DEBUGLEVEL >= 6)
1823 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1824 "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1825 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1827 srcvalue = nv32_rd(pScrn, srcreg);
1832 srcvalue <<= (0x100 - shift);
1834 srcvalue = (srcvalue & srcmask) ^ xor;
1836 dstvalue = nv32_rd(pScrn, dstreg) & dstmask;
1838 nv32_wr(pScrn, dstreg, dstvalue | srcvalue);
1843 static bool init_zm_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1845 /* INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1847 * offset (8 bit): opcode
1848 * offset + 1 (16 bit): CRTC port
1849 * offset + 3 (8 bit): CRTC index
1850 * offset + 4 (8 bit): data
1852 * Write "data" to index "CRTC index" of "CRTC port"
1854 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1855 uint8_t crtcindex = bios->data[offset + 3];
1856 uint8_t data = bios->data[offset + 4];
1858 if (!iexec->execute)
1861 nv_idx_port_wr(pScrn, crtcport, crtcindex, data);
1866 static bool init_compute_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1868 /* INIT_COMPUTE_MEM opcode: 0x63 ('c')
1870 * offset (8 bit): opcode
1872 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
1873 * that the hardware can correctly calculate how much VRAM it has
1874 * (and subsequently report that value in 0x10020C)
1876 * The implementation of this opcode in general consists of two parts:
1877 * 1) determination of the memory bus width
1878 * 2) determination of how many of the card's RAM pads have ICs attached
1880 * 1) is done by a cunning combination of writes to offsets 0x1c and
1881 * 0x3c in the framebuffer, and seeing whether the written values are
1882 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
1884 * 2) is done by a cunning combination of writes to an offset slightly
1885 * less than the maximum memory reported by 0x10020C, then seeing if
1886 * the test pattern can be read back. This then affects bits 12-15 of
1889 * In this context a "cunning combination" may include multiple reads
1890 * and writes to varying locations, often alternating the test pattern
1891 * and 0, doubtless to make sure buffers are filled, residual charges
1892 * on tracks are removed etc.
1894 * Unfortunately, the "cunning combination"s mentioned above, and the
1895 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
1898 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
1899 * we started was correct, and use that instead
1902 /* no iexec->execute check by design */
1904 /* on every card I've seen, this step gets done for us earlier in the init scripts
1905 uint8_t crdata = nv_idx_port_rd(pScrn, SEQ_INDEX, 0x01);
1906 nv_idx_port_wr(pScrn, SEQ_INDEX, 0x01, crdata | 0x20);
1909 /* this also has probably been done in the scripts, but an mmio trace of
1910 * s3 resume shows nvidia doing it anyway (unlike the SEQ_INDEX write)
1912 nv32_wr(pScrn, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
1914 /* write back the saved configuration value */
1915 nv32_wr(pScrn, NV_PFB_CFG0, saved_nv_pfb_cfg0);
1920 static bool init_reset(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1922 /* INIT_RESET opcode: 0x65 ('e')
1924 * offset (8 bit): opcode
1925 * offset + 1 (32 bit): register
1926 * offset + 5 (32 bit): value1
1927 * offset + 9 (32 bit): value2
1929 * Assign "value1" to "register", then assign "value2" to "register"
1932 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1933 uint32_t value1 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1934 uint32_t value2 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1935 uint32_t pci_nv_19, pci_nv_20;
1937 /* no iexec->execute check by design */
1939 pci_nv_19 = nv32_rd(pScrn, NV_PBUS_PCI_NV_19);
1940 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, 0);
1941 nv32_wr(pScrn, reg, value1);
1945 nv32_wr(pScrn, reg, value2);
1946 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, pci_nv_19);
1948 pci_nv_20 = nv32_rd(pScrn, NV_PBUS_PCI_NV_20);
1949 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
1950 nv32_wr(pScrn, NV_PBUS_PCI_NV_20, pci_nv_20);
1955 static bool init_configure_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1957 /* INIT_CONFIGURE_MEM opcode: 0x66 ('f')
1959 * offset (8 bit): opcode
1961 * Equivalent to INIT_DONE on bios version 3 or greater.
1962 * For early bios versions, sets up the memory registers, using values
1963 * taken from the memory init table
1966 /* no iexec->execute check by design */
1968 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_SCRATCH4) >> 4);
1969 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
1972 if (bios->major_version > 2)
1975 nv_idx_port_wr(pScrn, SEQ_INDEX, 0x01, nv_idx_port_rd(pScrn, SEQ_INDEX, 0x01) | 0x20);
1977 if (bios->data[meminitoffs] & 1)
1978 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
1980 for (reg = le32_to_cpu(*(uint32_t *)&bios->data[seqtbloffs]);
1982 reg = le32_to_cpu(*(uint32_t *)&bios->data[seqtbloffs += 4])) {
1986 data = NV_PFB_PRE_CMD_PRECHARGE;
1989 data = NV_PFB_PAD_CKE_NORMAL;
1992 data = NV_PFB_REF_CMD_REFRESH;
1995 data = le32_to_cpu(*(uint32_t *)&bios->data[meminitdata]);
1997 if (data == 0xffffffff)
2001 nv32_wr(pScrn, reg, data);
2007 static bool init_configure_clk(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2009 /* INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2011 * offset (8 bit): opcode
2013 * Equivalent to INIT_DONE on bios version 3 or greater.
2014 * For early bios versions, sets up the NVClk and MClk PLLs, using
2015 * values taken from the memory init table
2018 /* no iexec->execute check by design */
2020 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_SCRATCH4) >> 4);
2023 if (bios->major_version > 2)
2026 clock = le16_to_cpu(*(uint16_t *)&bios->data[meminitoffs + 4]) * 10;
2027 setPLL(pScrn, bios, NV_RAMDAC_NVPLL, clock);
2029 clock = le16_to_cpu(*(uint16_t *)&bios->data[meminitoffs + 2]) * 10;
2030 if (bios->data[meminitoffs] & 1) /* DDR */
2032 setPLL(pScrn, bios, NV_RAMDAC_MPLL, clock);
2037 static bool init_configure_preinit(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2039 /* INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2041 * offset (8 bit): opcode
2043 * Equivalent to INIT_DONE on bios version 3 or greater.
2044 * For early bios versions, does early init, loading ram and crystal
2045 * configuration from straps into CR3C
2048 /* no iexec->execute check by design */
2050 uint32_t straps = nv32_rd(pScrn, NV_PEXTDEV_BOOT_0);
2051 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6));
2053 if (bios->major_version > 2)
2056 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_SCRATCH4, cr3c);
2061 static bool init_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2063 /* INIT_IO opcode: 0x69 ('i')
2065 * offset (8 bit): opcode
2066 * offset + 1 (16 bit): CRTC port
2067 * offset + 3 (8 bit): mask
2068 * offset + 4 (8 bit): data
2070 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2073 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2074 uint8_t mask = bios->data[offset + 3];
2075 uint8_t data = bios->data[offset + 4];
2077 if (!iexec->execute)
2080 if (DEBUGLEVEL >= 6)
2081 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2082 "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2083 offset, crtcport, mask, data);
2085 nv_port_wr(pScrn, crtcport, (nv_port_rd(pScrn, crtcport) & mask) | data);
2090 static bool init_sub(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2092 /* INIT_SUB opcode: 0x6B ('k')
2094 * offset (8 bit): opcode
2095 * offset + 1 (8 bit): script number
2097 * Execute script number "script number", as a subroutine
2100 uint8_t sub = bios->data[offset + 1];
2102 if (!iexec->execute)
2105 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2106 "0x%04X: EXECUTING SUB-SCRIPT %d\n", offset, sub);
2108 parse_init_table(pScrn, bios,
2109 le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + sub * 2]))),
2112 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2113 "0x%04X: END OF SUB-SCRIPT %d\n", offset, sub);
2118 static bool init_ram_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2120 /* INIT_RAM_CONDITION opcode: 0x6D ('m')
2122 * offset (8 bit): opcode
2123 * offset + 1 (8 bit): mask
2124 * offset + 2 (8 bit): cmpval
2126 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval".
2127 * If condition not met skip subsequent opcodes until condition is
2128 * inverted (INIT_NOT), or we hit INIT_RESUME
2131 uint8_t mask = bios->data[offset + 1];
2132 uint8_t cmpval = bios->data[offset + 2];
2135 if (!iexec->execute)
2138 data = nv32_rd(pScrn, NV_PFB_BOOT_0) & mask;
2140 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2141 "0x%04X: Checking if 0x%08X equals 0x%08X\n", offset, data, cmpval);
2144 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2145 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
2147 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2148 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2149 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2150 iexec->execute = false;
2156 static bool init_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2158 /* INIT_NV_REG opcode: 0x6E ('n')
2160 * offset (8 bit): opcode
2161 * offset + 1 (32 bit): register
2162 * offset + 5 (32 bit): mask
2163 * offset + 9 (32 bit): data
2165 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2168 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2169 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2170 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
2172 if (!iexec->execute)
2175 if (DEBUGLEVEL >= 6)
2176 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2177 "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2178 offset, reg, mask, data);
2180 nv32_wr(pScrn, reg, (nv32_rd(pScrn, reg) & mask) | data);
2185 static bool init_macro(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2187 /* INIT_MACRO opcode: 0x6F ('o')
2189 * offset (8 bit): opcode
2190 * offset + 1 (8 bit): macro number
2192 * Look up macro index "macro number" in the macro index table.
2193 * The macro index table entry has 1 byte for the index in the macro table,
2194 * and 1 byte for the number of times to repeat the macro.
2195 * The macro table entry has 4 bytes for the register address and
2196 * 4 bytes for the value to write to that register
2199 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2200 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2201 uint8_t macro_tbl_idx = bios->data[tmp];
2202 uint8_t count = bios->data[tmp + 1];
2206 if (!iexec->execute)
2209 if (DEBUGLEVEL >= 6)
2210 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2211 "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, Count: 0x%02X\n",
2212 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2214 for (i = 0; i < count; i++) {
2215 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2217 reg = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr])));
2218 data = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr + 4])));
2220 nv32_wr(pScrn, reg, data);
2226 static bool init_done(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2228 /* INIT_DONE opcode: 0x71 ('q')
2230 * offset (8 bit): opcode
2232 * End the current script
2235 /* mild retval abuse to stop parsing this table */
2239 static bool init_resume(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2241 /* INIT_RESUME opcode: 0x72 ('r')
2243 * offset (8 bit): opcode
2245 * End the current execute / no-execute condition
2251 iexec->execute = true;
2252 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2253 "0x%04X: ---- EXECUTING FOLLOWING COMMANDS ----\n", offset);
2259 static bool init_ram_condition2(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
2261 /* INIT_RAM_CONDITION2 opcode: 0x73
2263 * offset (8 bit): opcode
2264 * offset + 1 (8 bit): and mask
2265 * offset + 2 (8 bit): cmpval
2267 * Test if (NV_EXTDEV_BOOT & and mask) matches cmpval
2269 NVPtr pNv = NVPTR(pScrn);
2270 CARD32 and = *((CARD32 *) (&bios->data[offset + 1]));
2271 CARD32 cmpval = *((CARD32 *) (&bios->data[offset + 5]));
2274 if (iexec->execute) {
2275 data=(nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT))∧
2277 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2278 "0x%04X: CHECKING IF REGVAL: 0x%08X equals COND: 0x%08X\n",
2279 offset, data, cmpval);
2281 if (data == cmpval) {
2282 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2283 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n",
2286 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2287 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2288 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2289 iexec->execute = false;
2296 static bool init_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2298 /* INIT_TIME opcode: 0x74 ('t')
2300 * offset (8 bit): opcode
2301 * offset + 1 (16 bit): time
2303 * Sleep for "time" microseconds.
2306 uint16_t time = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2308 if (!iexec->execute)
2311 if (DEBUGLEVEL >= 6)
2312 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2313 "0x%04X: Sleeping for 0x%04X microseconds\n", offset, time);
2320 static bool init_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2322 /* INIT_CONDITION opcode: 0x75 ('u')
2324 * offset (8 bit): opcode
2325 * offset + 1 (8 bit): condition number
2327 * Check condition "condition number" in the condition table.
2328 * The condition table entry has 4 bytes for the address of the
2329 * register to check, 4 bytes for a mask and 4 for a test value.
2330 * If condition not met skip subsequent opcodes until condition is
2331 * inverted (INIT_NOT), or we hit INIT_RESUME
2334 uint8_t cond = bios->data[offset + 1];
2335 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
2336 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
2337 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
2338 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
2341 if (!iexec->execute)
2344 if (DEBUGLEVEL >= 6)
2345 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2346 "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X, Cmpval: 0x%08X\n",
2347 offset, cond, reg, mask, cmpval);
2349 data = nv32_rd(pScrn, reg) & mask;
2351 if (DEBUGLEVEL >= 6)
2352 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2353 "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2354 offset, data, cmpval);
2356 if (data == cmpval) {
2357 if (DEBUGLEVEL >= 6)
2358 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2359 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
2361 if (DEBUGLEVEL >= 6)
2362 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2363 "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2364 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2365 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2366 iexec->execute = false;
2372 static bool init_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2374 /* INIT_INDEX_IO opcode: 0x78 ('x')
2376 * offset (8 bit): opcode
2377 * offset + 1 (16 bit): CRTC port
2378 * offset + 3 (8 bit): CRTC index
2379 * offset + 4 (8 bit): mask
2380 * offset + 5 (8 bit): data
2382 * Read value at index "CRTC index" on "CRTC port", AND with "mask", OR with "data", write-back
2385 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2386 uint8_t crtcindex = bios->data[offset + 3];
2387 uint8_t mask = bios->data[offset + 4];
2388 uint8_t data = bios->data[offset + 5];
2391 if (!iexec->execute)
2394 if (DEBUGLEVEL >= 6)
2395 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2396 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
2397 offset, crtcport, crtcindex, mask, data);
2399 value = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) | data;
2400 nv_idx_port_wr(pScrn, crtcport, crtcindex, value);
2405 static bool init_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2407 /* INIT_PLL opcode: 0x79 ('y')
2409 * offset (8 bit): opcode
2410 * offset + 1 (32 bit): register
2411 * offset + 5 (16 bit): freq
2413 * Set PLL register "register" to coefficients for frequency (10kHz) "freq"
2416 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2417 uint16_t freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 5])));
2419 if (!iexec->execute)
2422 if (DEBUGLEVEL >= 6)
2423 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2424 "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n",
2427 setPLL(pScrn, bios, reg, freq * 10);
2432 static bool init_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2434 /* INIT_ZM_REG opcode: 0x7A ('z')
2436 * offset (8 bit): opcode
2437 * offset + 1 (32 bit): register
2438 * offset + 5 (32 bit): value
2440 * Assign "value" to "register"
2443 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2444 uint32_t value = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2446 if (!iexec->execute)
2449 nv32_wr(pScrn, reg, value);
2454 static bool init_8e(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2456 /* INIT_8E opcode: 0x8E ('')
2458 * offset (8 bit): opcode
2460 * The purpose of this opcode is unclear (being for nv50 cards), and
2461 * the literal functionality can be seen in the code below.
2463 * A brief synopsis is that for each entry in a table pointed to by the
2464 * DCB table header, depending on the settings of various bits, various
2465 * other bits in registers 0xe100, 0xe104, and 0xe108, are set or
2469 uint16_t dcbptr = le16_to_cpu(*(uint16_t *)&bios->data[0x36]);
2470 uint16_t init8etblptr = le16_to_cpu(*(uint16_t *)&bios->data[dcbptr + 10]);
2471 uint8_t headerlen = bios->data[init8etblptr + 1];
2472 uint8_t entries = bios->data[init8etblptr + 2];
2473 uint8_t recordlen = bios->data[init8etblptr + 3];
2477 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2478 "No Display Configuration Block pointer found\n");
2481 if (bios->data[dcbptr] != 0x40) {
2482 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2483 "DCB table not version 4.0\n");
2486 if (!init8etblptr) {
2487 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
2488 "Invalid pointer to INIT_8E table\n");
2492 for (i = 0; i < entries; i++) {
2493 uint32_t entry = le32_to_cpu(*(uint32_t *)&bios->data[init8etblptr + headerlen + recordlen * i]);
2494 int shift = (entry & 0x1f) * 4;
2496 uint32_t reg = 0xe104;
2499 if ((entry & 0xff00) == 0xff00)
2508 mask = ~(3 << shift);
2509 if (entry & (1 << 24))
2510 data = (entry >> 21);
2512 data = (entry >> 19);
2513 data = ((data & 3) ^ 2) << shift;
2515 if (DEBUGLEVEL >= 6)
2516 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2517 "0x%04X: Entry: 0x%08X, Reg: 0x%08X, Shift: 0x%02X, Mask: 0x%08X, Data: 0x%08X\n",
2518 offset, entry, reg, shift, mask, data);
2520 nv32_wr(pScrn, reg, (nv32_rd(pScrn, reg) & mask) | data);
2523 shift = entry & 0x1f;
2525 mask = ~(1 << 16 | 1);
2526 mask = mask << shift | mask >> (32 - shift);
2528 if ((entry & (3 << 25)) == (1 << 25))
2530 if ((entry & (3 << 25)) == (2 << 25))
2534 if (DEBUGLEVEL >= 6)
2535 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2536 "0x%04X: Entry: 0x%08X, Reg: 0x%08X, Shift: 0x%02X, Mask: 0x%08X, Data: 0x%08X\n",
2537 offset, entry, reg, shift, mask, data);
2539 nv32_wr(pScrn, reg, (nv32_rd(pScrn, reg) & mask) | data);
2545 /* hack to avoid moving the itbl_entry array before this function */
2546 int init_ram_restrict_zm_reg_group_blocklen = 0;
2548 static bool init_ram_restrict_zm_reg_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2550 /* INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2552 * offset (8 bit): opcode
2553 * offset + 1 (32 bit): reg
2554 * offset + 5 (8 bit): regincrement
2555 * offset + 6 (8 bit): count
2556 * offset + 7 (32 bit): value 1,1
2559 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2560 * ram_restrict_table_ptr. The value read from here is 'n', and
2561 * "value 1,n" gets written to "reg". This repeats "count" times and on
2562 * each iteration 'm', "reg" increases by "regincrement" and
2563 * "value m,n" is used. The extent of n is limited by a number read
2564 * from the 'M' BIT table, herein called "blocklen"
2567 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2568 uint8_t regincrement = bios->data[offset + 5];
2569 uint8_t count = bios->data[offset + 6];
2570 uint32_t strap_ramcfg, data;
2575 /* previously set by 'M' BIT table */
2576 blocklen = init_ram_restrict_zm_reg_group_blocklen;
2578 if (!iexec->execute)
2582 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2583 "0x%04X: Zero block length - has the M table been parsed?\n", offset);
2587 strap_ramcfg = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2588 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2590 if (DEBUGLEVEL >= 6)
2591 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2592 "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2593 offset, reg, regincrement, count, strap_ramcfg, index);
2595 for (i = 0; i < count; i++) {
2596 data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7 + index * 4 + blocklen * i])));
2598 nv32_wr(pScrn, reg, data);
2600 reg += regincrement;
2606 static bool init_copy_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2608 /* INIT_COPY_ZM_REG opcode: 0x90 ('')
2610 * offset (8 bit): opcode
2611 * offset + 1 (32 bit): src reg
2612 * offset + 5 (32 bit): dst reg
2614 * Put contents of "src reg" into "dst reg"
2617 uint32_t srcreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2618 uint32_t dstreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2620 if (!iexec->execute)
2623 nv32_wr(pScrn, dstreg, nv32_rd(pScrn, srcreg));
2628 static bool init_zm_reg_group_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2630 /* INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2632 * offset (8 bit): opcode
2633 * offset + 1 (32 bit): dst reg
2634 * offset + 5 (8 bit): count
2635 * offset + 6 (32 bit): data 1
2638 * For each of "count" values write "data n" to "dst reg"
2641 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2642 uint8_t count = bios->data[offset + 5];
2645 if (!iexec->execute)
2648 for (i = 0; i < count; i++) {
2649 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + 4 * i])));
2650 nv32_wr(pScrn, reg, data);
2656 static bool init_reserved(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2658 /* INIT_RESERVED opcode: 0x92 ('')
2660 * offset (8 bit): opcode
2662 * Seemingly does nothing
2668 static init_tbl_entry_t itbl_entry[] = {
2669 /* command name , id , length , offset , mult , command handler */
2670 // { "INIT_PROG" , 0x31, 15 , 10 , 4 , init_prog },
2671 { "INIT_IO_RESTRICT_PROG" , 0x32, 11 , 6 , 4 , init_io_restrict_prog },
2672 { "INIT_REPEAT" , 0x33, 2 , 0 , 0 , init_repeat },
2673 { "INIT_IO_RESTRICT_PLL" , 0x34, 12 , 7 , 2 , init_io_restrict_pll },
2674 { "INIT_END_REPEAT" , 0x36, 1 , 0 , 0 , init_end_repeat },
2675 { "INIT_COPY" , 0x37, 11 , 0 , 0 , init_copy },
2676 { "INIT_NOT" , 0x38, 1 , 0 , 0 , init_not },
2677 { "INIT_IO_FLAG_CONDITION" , 0x39, 2 , 0 , 0 , init_io_flag_condition },
2678 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, 18 , 17 , 2 , init_idx_addr_latched },
2679 { "INIT_IO_RESTRICT_PLL2" , 0x4A, 11 , 6 , 4 , init_io_restrict_pll2 },
2680 { "INIT_PLL2" , 0x4B, 9 , 0 , 0 , init_pll2 },
2681 /* { "INIT_I2C_BYTE" , 0x4C, x , x , x , init_i2c_byte }, */
2682 /* { "INIT_ZM_I2C_BYTE" , 0x4D, x , x , x , init_zm_i2c_byte }, */
2683 /* { "INIT_ZM_I2C" , 0x4E, x , x , x , init_zm_i2c }, */
2684 { "INIT_TMDS" , 0x4F, 5 , 0 , 0 , init_tmds },
2685 { "INIT_ZM_TMDS_GROUP" , 0x50, 3 , 2 , 2 , init_zm_tmds_group },
2686 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, 5 , 4 , 1 , init_cr_idx_adr_latch },
2687 { "INIT_CR" , 0x52, 4 , 0 , 0 , init_cr },
2688 { "INIT_ZM_CR" , 0x53, 3 , 0 , 0 , init_zm_cr },
2689 { "INIT_ZM_CR_GROUP" , 0x54, 2 , 1 , 2 , init_zm_cr_group },
2690 { "INIT_CONDITION_TIME" , 0x56, 3 , 0 , 0 , init_condition_time },
2691 { "INIT_ZM_REG_SEQUENCE" , 0x58, 6 , 5 , 4 , init_zm_reg_sequence },
2692 // { "INIT_INDIRECT_REG" , 0x5A, 7 , 0 , 0 , init_indirect_reg },
2693 { "INIT_SUB_DIRECT" , 0x5B, 3 , 0 , 0 , init_sub_direct },
2694 { "INIT_COPY_NV_REG" , 0x5F, 22 , 0 , 0 , init_copy_nv_reg },
2695 { "INIT_ZM_INDEX_IO" , 0x62, 5 , 0 , 0 , init_zm_index_io },
2696 { "INIT_COMPUTE_MEM" , 0x63, 1 , 0 , 0 , init_compute_mem },
2697 { "INIT_RESET" , 0x65, 13 , 0 , 0 , init_reset },
2698 { "INIT_CONFIGURE_MEM" , 0x66, 1 , 0 , 0 , init_configure_mem },
2699 { "INIT_CONFIGURE_CLK" , 0x67, 1 , 0 , 0 , init_configure_clk },
2700 { "INIT_CONFIGURE_PREINIT" , 0x68, 1 , 0 , 0 , init_configure_preinit },
2701 { "INIT_IO" , 0x69, 5 , 0 , 0 , init_io },
2702 { "INIT_SUB" , 0x6B, 2 , 0 , 0 , init_sub },
2703 { "INIT_RAM_CONDITION" , 0x6D, 3 , 0 , 0 , init_ram_condition },
2704 { "INIT_NV_REG" , 0x6E, 13 , 0 , 0 , init_nv_reg },
2705 { "INIT_MACRO" , 0x6F, 2 , 0 , 0 , init_macro },
2706 { "INIT_DONE" , 0x71, 1 , 0 , 0 , init_done },
2707 { "INIT_RESUME" , 0x72, 1 , 0 , 0 , init_resume },
2708 // { "INIT_RAM_CONDITION2" , 0x73, 9 , 0 , 0 , init_ram_condition2 },
2709 { "INIT_TIME" , 0x74, 3 , 0 , 0 , init_time },
2710 { "INIT_CONDITION" , 0x75, 2 , 0 , 0 , init_condition },
2711 /* { "INIT_IO_CONDITION" , 0x76, x , x , x , init_io_condition }, */
2712 { "INIT_INDEX_IO" , 0x78, 6 , 0 , 0 , init_index_io },
2713 { "INIT_PLL" , 0x79, 7 , 0 , 0 , init_pll },
2714 { "INIT_ZM_REG" , 0x7A, 9 , 0 , 0 , init_zm_reg },
2715 { "INIT_8E" , 0x8E, 1 , 0 , 0 , init_8e },
2716 /* INIT_RAM_RESTRICT_ZM_REG_GROUP's mult is loaded by M table in BIT */
2717 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, 7 , 6 , 0 , init_ram_restrict_zm_reg_group },
2718 { "INIT_COPY_ZM_REG" , 0x90, 9 , 0 , 0 , init_copy_zm_reg },
2719 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, 6 , 5 , 4 , init_zm_reg_group_addr_latched },
2720 { "INIT_RESERVED" , 0x92, 1 , 0 , 0 , init_reserved },
2721 { 0 , 0 , 0 , 0 , 0 , 0 }
2724 static unsigned int get_init_table_entry_length(bios_t *bios, unsigned int offset, int i)
2726 /* Calculates the length of a given init table entry. */
2727 return itbl_entry[i].length + bios->data[offset + itbl_entry[i].length_offset]*itbl_entry[i].length_multiplier;
2730 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec)
2732 /* Parses all commands in a init table. */
2734 /* We start out executing all commands found in the
2735 * init table. Some op codes may change the status
2736 * of this variable to SKIP, which will cause
2737 * the following op codes to perform no operation until
2738 * the value is changed back to EXECUTE.
2744 /* Loop until INIT_DONE causes us to break out of the loop
2745 * (or until offset > bios length just in case... )
2746 * (and no more than 10000 iterations just in case... ) */
2747 while ((offset < bios->length) && (count++ < 10000)) {
2748 id = bios->data[offset];
2750 /* Find matching id in itbl_entry */
2751 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
2754 if (itbl_entry[i].name) {
2755 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ (0x%02X) - %s ]\n",
2756 offset, itbl_entry[i].id, itbl_entry[i].name);
2758 /* execute eventual command handler */
2759 if (itbl_entry[i].handler)
2760 if (!(*itbl_entry[i].handler)(pScrn, bios, offset, iexec))
2763 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2764 "0x%04X: Init table command not found: 0x%02X\n", offset, id);
2768 /* Add the offset of the current command including all data
2769 * of that command. The offset will then be pointing on the
2772 offset += get_init_table_entry_length(bios, offset, i);
2776 static void parse_init_tables(ScrnInfoPtr pScrn, bios_t *bios)
2778 /* Loops and calls parse_init_table() for each present table. */
2782 init_exec_t iexec = {true, false};
2784 while ((table = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + i]))))) {
2785 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2786 "0x%04X: Parsing init table %d\n", table, i / 2);
2787 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2788 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", table);
2790 parse_init_table(pScrn, bios, table, &iexec);
2795 static void link_head_and_output(ScrnInfoPtr pScrn, struct dcb_entry *dcbent, int head)
2797 /* The BIOS scripts don't do this for us, sadly
2798 * Luckily we do know the values ;-)
2800 * head < 0 indicates we wish to force a setting with the overrideval
2801 * (for VT restore etc.)
2804 NVPtr pNv = NVPTR(pScrn);
2805 int ramdac = (dcbent->or & OUTPUT_C) >> 2;
2806 uint8_t tmds04 = 0x80;
2811 if (dcbent->type == OUTPUT_LVDS)
2814 nv_write_tmds(pNv, dcbent->or, 0, 0x04, tmds04);
2816 if (dcbent->type == OUTPUT_LVDS && pNv->VBIOS.fp.dual_link)
2817 nv_write_tmds(pNv, dcbent->or, 1, 0x04, tmds04 ^ 0x08);
2820 static uint16_t clkcmptable(bios_t *bios, uint16_t clktable, int pxclk)
2822 int compare_record_len, i = 0;
2823 uint16_t compareclk, scriptptr = 0;
2825 if (bios->major_version < 5) /* pre BIT */
2826 compare_record_len = 3;
2828 compare_record_len = 4;
2831 compareclk = le16_to_cpu(*((uint16_t *)&bios->data[clktable + compare_record_len * i]));
2832 if (pxclk >= compareclk * 10) {
2833 if (bios->major_version < 5) {
2834 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
2835 scriptptr = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + tmdssub * 2])));
2837 scriptptr = le16_to_cpu(*((uint16_t *)&bios->data[clktable + 2 + compare_record_len * i]));
2841 } while (compareclk);
2846 static void rundigitaloutscript(ScrnInfoPtr pScrn, uint16_t scriptptr, struct dcb_entry *dcbent, int head)
2848 bios_t *bios = &NVPTR(pScrn)->VBIOS;
2849 init_exec_t iexec = {true, false};
2851 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing digital output script table\n", scriptptr);
2852 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER,
2853 head ? NV_VGA_CRTCX_OWNER_HEADB : NV_VGA_CRTCX_OWNER_HEADA);
2854 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_57, 0);
2855 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_58, dcbent->index);
2856 parse_init_table(pScrn, bios, scriptptr, &iexec);
2858 link_head_and_output(pScrn, dcbent, head);
2861 static void call_lvds_manufacturer_script(ScrnInfoPtr pScrn, struct dcb_entry *dcbent, int head, enum LVDS_script script)
2863 NVPtr pNv = NVPTR(pScrn);
2864 bios_t *bios = &pNv->VBIOS;
2865 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
2866 uint16_t scriptofs = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + sub * 2])));
2868 if (!bios->fp.xlated_entry || !sub || !scriptofs)
2871 rundigitaloutscript(pScrn, scriptofs, dcbent, head);
2873 if (script == LVDS_PANEL_OFF)
2874 /* off-on delay in ms */
2875 usleep(le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.xlated_entry + 7]));
2877 /* Powerbook specific quirks */
2878 if (script == LVDS_RESET && ((pNv->Chipset & 0xffff) == 0x0179 || (pNv->Chipset & 0xffff) == 0x0329))
2879 nv_write_tmds(pNv, dcbent->or, 0, 0x02, 0x72);
2880 if ((pNv->Chipset & 0xffff) == 0x0179 || (pNv->Chipset & 0xffff) == 0x0189 || (pNv->Chipset & 0xffff) == 0x0329) {
2881 if (script == LVDS_PANEL_ON) {
2882 nv32_wr(pScrn, NV_PBUS_DEBUG_DUALHEAD_CTL, nv32_rd(pScrn, NV_PBUS_DEBUG_DUALHEAD_CTL) | (1 << 31));
2883 nv32_wr(pScrn, NV_CRTC_GPIO_EXT, nv32_rd(pScrn, NV_CRTC_GPIO_EXT) | 1);
2885 if (script == LVDS_PANEL_OFF) {
2886 nv32_wr(pScrn, NV_PBUS_DEBUG_DUALHEAD_CTL, nv32_rd(pScrn, NV_PBUS_DEBUG_DUALHEAD_CTL) & ~(1 << 31));
2887 nv32_wr(pScrn, NV_CRTC_GPIO_EXT, nv32_rd(pScrn, NV_CRTC_GPIO_EXT) & ~3);
2893 static void run_lvds_table(ScrnInfoPtr pScrn, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
2895 /* The BIT LVDS table's header has the information to setup the
2896 * necessary registers. Following the standard 4 byte header are:
2897 * A bitmask byte and a dual-link transition pxclk value for use in
2898 * selecting the init script when not using straps; 4 script pointers
2899 * for panel power, selected by output and on/off; and 8 table pointers
2900 * for panel init, the needed one determined by output, and bits in the
2901 * conf byte. These tables are similar to the TMDS tables, consisting
2902 * of a list of pxclks and script pointers.
2905 NVPtr pNv = NVPTR(pScrn);
2906 bios_t *bios = &pNv->VBIOS;
2907 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
2908 uint16_t scriptptr = 0, clktable;
2909 uint8_t clktableptr = 0;
2911 /* for now we assume version 3.0 table - g80 support will need some changes */
2916 case LVDS_BACKLIGHT_ON:
2918 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
2920 case LVDS_BACKLIGHT_OFF:
2921 case LVDS_PANEL_OFF:
2922 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
2925 if (dcbent->lvdsconf.use_straps_for_mode) {
2926 if (bios->fp.dual_link)
2928 if (bios->fp.BITbit1)
2931 uint8_t fallback = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
2932 int fallbackcmpval = (dcbent->or == 4) ? 4 : 1;
2934 if (bios->fp.dual_link) {
2936 fallbackcmpval *= 2;
2938 if (fallbackcmpval & fallback)
2942 /* adding outputset * 8 may not be correct */
2943 clktable = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 15 + clktableptr * 2 + outputset * 8]);
2945 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Pixel clock comparison table not found\n");
2948 scriptptr = clkcmptable(bios, clktable, pxclk);
2952 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "LVDS output init script not found\n");
2955 rundigitaloutscript(pScrn, scriptptr, dcbent, head);
2958 void call_lvds_script(ScrnInfoPtr pScrn, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
2960 /* LVDS operations are multiplexed in an effort to present a single API
2961 * which works with two vastly differing underlying structures.
2962 * This acts as the demux
2965 bios_t *bios = &NVPTR(pScrn)->VBIOS;
2966 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
2967 uint32_t sel_clk_binding;
2968 static int last_invoc = 0;
2970 if (last_invoc == (script << 1 | head) || !lvds_ver)
2973 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
2974 call_lvds_script(pScrn, dcbent, head, LVDS_RESET, pxclk);
2975 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
2976 call_lvds_script(pScrn, dcbent, head, LVDS_PANEL_OFF, pxclk);
2978 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Calling LVDS script %d:\n", script);
2980 /* don't let script change pll->head binding */
2981 sel_clk_binding = nv32_rd(pScrn, NV_RAMDAC_SEL_CLK) & 0x50000;
2983 if (lvds_ver < 0x30)
2984 call_lvds_manufacturer_script(pScrn, dcbent, head, script);
2986 run_lvds_table(pScrn, dcbent, head, script, pxclk);
2988 last_invoc = (script << 1 | head);
2990 nv32_wr(pScrn, NV_RAMDAC_SEL_CLK, (nv32_rd(pScrn, NV_RAMDAC_SEL_CLK) & ~0x50000) | sel_clk_binding);
2991 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
2992 nv32_wr(pScrn, NV_PBUS_POWERCTRL_2, 0);
2996 uint16_t fptablepointer;
2997 uint16_t fpxlatetableptr;
3001 struct lvdstableheader {
3002 uint8_t lvds_ver, headerlen, recordlen;
3005 static void parse_lvds_manufacturer_table_header(ScrnInfoPtr pScrn, bios_t *bios, struct lvdstableheader *lth)
3007 /* BMP version (0xa) LVDS table has a simple header of version and
3008 * record length. The BIT LVDS table has the typical BIT table header:
3009 * version byte, header length byte, record length byte, and a byte for
3010 * the maximum number of records that can be held in the table */
3012 uint8_t lvds_ver, headerlen, recordlen;
3014 memset(lth, 0, sizeof(struct lvdstableheader));
3016 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3017 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3018 "Pointer to LVDS manufacturer table invalid\n");
3022 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3025 case 0x0a: /* pre NV40 */
3027 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3029 case 0x30: /* NV4x */
3030 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3031 if (headerlen < 0x1f) {
3032 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3033 "LVDS table header not understood\n");
3036 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3038 case 0x40: /* G80/G90 */
3039 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3040 if (headerlen < 0x7) {
3041 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3042 "LVDS table header not understood\n");
3045 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3048 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3049 "LVDS table revision %d.%d not currently supported\n",
3050 lvds_ver >> 4, lvds_ver & 0xf);
3054 lth->lvds_ver = lvds_ver;
3055 lth->headerlen = headerlen;
3056 lth->recordlen = recordlen;
3059 static void parse_fp_mode_table(ScrnInfoPtr pScrn, bios_t *bios, struct fppointers *fpp)
3062 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
3064 struct lvdstableheader lth;
3066 DisplayModePtr mode;
3068 if (fpp->fptablepointer == 0x0) {
3069 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3070 "Pointer to flat panel table invalid\n");
3074 fptable = &bios->data[fpp->fptablepointer];
3075 fptable_ver = fptable[0];
3077 switch (fptable_ver) {
3078 /* BMP version 0x5.0x11 BIOSen have version 1 like tables, but no version field,
3079 * and miss one of the spread spectrum/PWM bytes.
3080 * This could affect early GF2Go parts (not seen any appropriate ROMs though).
3081 * Here we assume that a version of 0x05 matches this case (combining with a
3082 * BMP version check would be better), as the common case for the panel type
3083 * field is 0x0005, and that is in fact what we are reading the first byte of. */
3084 case 0x05: /* some NV10, 11, 15, 16 */
3088 case 0x10: /* some NV15/16, and NV11+ */
3092 case 0x20: /* NV40+ */
3093 headerlen = fptable[1];
3094 recordlen = fptable[2];
3095 fpentries = fptable[3];
3096 /* fptable[4] is the minimum RAMDAC_FP_HCRTC->RAMDAC_FP_HSYNC_START gap */
3097 bios->digital_min_front_porch = fptable[4];
3101 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3102 "FP table revision %d.%d not currently supported\n",
3103 fptable_ver >> 4, fptable_ver & 0xf);
3107 /* non mobile only needs to set digital_min_front_porch */
3108 if (!(bios->feature_byte & FEATURE_MOBILE))
3111 parse_lvds_manufacturer_table_header(pScrn, bios, <h);
3113 switch (lth.lvds_ver) {
3115 /* make sure to match the 0xff strapping check below */
3116 if ((bios->fp.strapping & 0xf) == 0xf)
3117 bios->data[fpp->fpxlatetableptr + 0xf] = 0xf;
3121 fpp->fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + lth.headerlen + 1;
3122 fpp->xlatwidth = lth.recordlen;
3124 if (fpp->fpxlatetableptr == 0x0) {
3125 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3126 "Pointer to flat panel xlat table invalid\n");
3130 /* Query all modes and find one with a matching clock. */
3131 /* Note that this only serves as a backup solution if ddc fails. */
3132 if (lth.lvds_ver == 0x40) {
3133 uint32_t clock, needed_clock;
3134 int i, index = 0xF, matches = 0;
3135 needed_clock = nv32_rd(pScrn, 0x00616404) & 0xFFFFF;
3136 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "LVDS clock seems to be %d KHz.\n", needed_clock);
3138 for (i = 0; i < fpentries; i++) {
3139 modeofs = headerlen + recordlen * i;
3140 clock = le16_to_cpu(*(uint16_t *)&fptable[modeofs]) * 10;
3141 if (clock == needed_clock) {
3148 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found a mode with matching clock\n");
3150 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found %d modes, this is not useful\n", matches);
3155 fpindex = bios->data[fpp->fpxlatetableptr + index * fpp->xlatwidth];
3156 bios->fp.strapping = ((fpindex & 0xF) << 4) | (fpindex & 0xF);
3158 fpindex = bios->data[fpp->fpxlatetableptr + bios->fp.strapping * fpp->xlatwidth];
3159 bios->fp.strapping |= fpindex << 4;
3162 if (fpindex > fpentries) {
3163 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3164 "Bad flat panel table index\n");
3168 /* reserved values - means that ddc or hard coded edid should be used */
3169 if (bios->fp.strapping == 0xff) {
3170 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Ignoring FP table\n");
3174 if (!(mode = xcalloc(1, sizeof(DisplayModeRec))))
3177 modeofs = headerlen + recordlen * fpindex + ofs;
3178 mode->Clock = le16_to_cpu(*(uint16_t *)&fptable[modeofs]) * 10;
3179 mode->HDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 4] + 1);
3180 mode->HSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 10] + 1);
3181 mode->HSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 12] + 1);
3182 mode->HTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 14] + 1);
3183 mode->VDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 18] + 1);
3184 mode->VSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 24] + 1);
3185 mode->VSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 26] + 1);
3186 mode->VTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 28] + 1);
3187 mode->Flags |= (fptable[modeofs + 30] & 0x10) ? V_PHSYNC : V_NHSYNC;
3188 mode->Flags |= (fptable[modeofs + 30] & 0x1) ? V_PVSYNC : V_NVSYNC;
3191 * bytes 1-2 are "panel type", including bits on whether Colour/mono, single/dual link, and type (TFT etc.)
3192 * bytes 3-6 are bits per colour in RGBX
3195 * 13-14 is HValid Start
3196 * 15-16 is HValid End
3197 * bytes 38-39 relate to spread spectrum settings
3198 * bytes 40-43 are something to do with PWM */
3200 mode->prev = mode->next = NULL;
3201 mode->status = MODE_OK;
3202 mode->type = M_T_DRIVER | M_T_PREFERRED;
3203 xf86SetModeDefaultName(mode);
3205 // if (XF86_CRTC_CONFIG_PTR(pScrn)->debug_modes) {
3206 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3207 "Found flat panel mode in BIOS tables:\n");
3208 xf86PrintModeline(pScrn->scrnIndex, mode);
3211 bios->fp.native_mode = mode;
3214 void parse_lvds_manufacturer_table(ScrnInfoPtr pScrn, bios_t *bios, int pxclk)
3216 /* The LVDS table header is (mostly) described in
3217 * parse_lvds_manufacturer_table_header(): the BIT header additionally
3218 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
3219 * straps are not being used for the panel, this specifies the frequency
3220 * at which modes should be set up in the dual link style.
3222 * Following the header, the BMP (ver 0xa) table has several records,
3223 * indexed by a seperate xlat table, indexed in turn by the fp strap in
3224 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
3225 * numbers for use by INIT_SUB which controlled panel init and power,
3226 * and finally a dword of ms to sleep between power off and on
3229 * In the BIT versions, the table following the header serves as an
3230 * integrated config and xlat table: the records in the table are
3231 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
3232 * two bytes - the first as a config byte, the second for indexing the
3233 * fp mode table pointed to by the BIT 'D' table
3235 * Due to the stage at which DDC is used in X's DDX design, the EDID res
3236 * for a panel isn't known at init, so the tests against the pixel clock
3237 * in the EDID case for selection of the correct table entry and setting
3238 * of the dual link flag cannot be done until later - this function may
3239 * be called at runtime with a non-zero pxclk argument to perform these
3243 unsigned int lvdsmanufacturerindex = 0;
3244 struct lvdstableheader lth;
3247 parse_lvds_manufacturer_table_header(pScrn, bios, <h);
3249 switch (lth.lvds_ver) {
3250 case 0: /* header parsing failed */
3252 case 0x0a: /* pre NV40 */
3253 lvdsmanufacturerindex = bios->data[bios->fp.fpxlatemanufacturertableptr + (bios->fp.strapping & 0xf)];
3255 /* we're done if this isn't the EDID panel case */
3256 if (pxclk == 0 || (bios->fp.strapping & 0xf) != 0xf)
3259 /* change in behaviour guessed at nv30; see datapoints below */
3260 if (bios->chip_version < 0x30) {
3261 /* nv17 behaviour */
3262 lvdsmanufacturerindex = bios->fp.if_is_24bit ? 2 : 0;
3263 if (pxclk >= bios->fp.duallink_transition_clk)
3264 lvdsmanufacturerindex++;
3266 /* nv31, nv34 behaviour */
3267 lvdsmanufacturerindex = 0;
3268 if (pxclk >= bios->fp.duallink_transition_clk)
3269 lvdsmanufacturerindex = 2;
3270 if (pxclk >= 140000)
3271 lvdsmanufacturerindex = 3;
3274 /* nvidia set the high nibble of (cr57=f, cr58) to
3275 * lvdsmanufacturerindex in this case; we don't */
3277 case 0x30: /* NV4x */
3278 lvdsmanufacturerindex = bios->fp.strapping & 0xf;
3280 case 0x40: /* G80/G90 */
3281 lvdsmanufacturerindex = bios->fp.strapping & 0xf;
3284 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3285 "LVDS table revision not currently supported\n");
3289 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
3290 switch (lth.lvds_ver) {
3292 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
3293 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
3294 bios->fp.dual_link = bios->data[lvdsofs] & 4;
3295 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
3296 bios->fp.if_is_24bit = bios->data[lvdsofs] & 16;
3299 /* My money would be on there being a 24 bit interface bit in this table,
3300 * but I have no example of a laptop bios with a 24 bit panel to confirm that.
3301 * Hence we shout loudly if any bit other than bit 0 is set (I've not even
3304 if (bios->data[lvdsofs] > 1)
3305 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3306 "You have a very unusual laptop display; please report it\n");
3307 /* no sign of the "power off for reset" or "reset for panel on" bits, but it's safer to assume we should */
3308 bios->fp.power_off_for_reset = true;
3309 bios->fp.reset_after_pclk_change = true;
3310 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3311 bios->fp.BITbit1 = bios->data[lvdsofs] & 2;
3312 bios->fp.duallink_transition_clk = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3315 /* fairly sure, but not 100% */
3316 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3317 bios->fp.duallink_transition_clk = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3321 /* set dual_link flag for EDID case */
3322 if ((bios->fp.strapping & 0xf) == 0xf && pxclk) {
3323 if (pxclk >= bios->fp.duallink_transition_clk)
3324 bios->fp.dual_link = true;
3326 bios->fp.dual_link = false;
3330 void run_tmds_table(ScrnInfoPtr pScrn, struct dcb_entry *dcbent, int head, int pxclk)
3332 /* the pxclk parameter is in kHz
3334 * This runs the TMDS regs setting code found on BIT bios cards
3336 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
3337 * ffs(or) == 3, use the second.
3340 NVPtr pNv = NVPTR(pScrn);
3341 bios_t *bios = &pNv->VBIOS;
3342 uint16_t clktable = 0, scriptptr;
3343 uint32_t sel_clk_binding;
3345 if (dcbent->location != LOC_ON_CHIP)
3348 switch (ffs(dcbent->or)) {
3350 clktable = bios->tmds.output0_script_ptr;
3354 clktable = bios->tmds.output1_script_ptr;
3359 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Pixel clock comparison table not found\n");
3363 scriptptr = clkcmptable(bios, clktable, pxclk);
3366 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "TMDS output init script not found\n");
3370 /* don't let script change pll->head binding */
3371 sel_clk_binding = nv32_rd(pScrn, NV_RAMDAC_SEL_CLK) & 0x50000;
3372 rundigitaloutscript(pScrn, scriptptr, dcbent, head);
3373 nv32_wr(pScrn, NV_RAMDAC_SEL_CLK, (nv32_rd(pScrn, NV_RAMDAC_SEL_CLK) & ~0x50000) | sel_clk_binding);
3376 static int get_fp_strap(ScrnInfoPtr pScrn, bios_t *bios)
3378 /* the fp strap is normally dictated by the "User Strap" in
3379 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3380 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3381 * by the PCI subsystem ID during POST, but not before the previous user
3382 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3383 * read and used instead
3386 /* Now comes the G80/G90 story, i've only got one hint.
3387 * I can read back the clock freq from register 0x00616404.
3388 * So for the moment just write 0xF here.
3391 if (bios->chip_version >= 0x80)
3394 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
3395 return (NVReadVgaCrtc5758(NVPTR(pScrn), 0, 0xf) & 0xf);
3397 return ((nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 16) & 0xf);
3400 static void parse_bios_version(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset)
3402 /* offset + 0 (8 bits): Micro version
3403 * offset + 1 (8 bits): Minor version
3404 * offset + 2 (8 bits): Chip version
3405 * offset + 3 (8 bits): Major version
3408 bios->major_version = bios->data[offset + 3];
3409 bios->chip_version = bios->data[offset + 2];
3410 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios version %02x.%02x.%02x.%02x\n",
3411 bios->data[offset + 3], bios->data[offset + 2],
3412 bios->data[offset + 1], bios->data[offset]);
3415 bool get_pll_limits(ScrnInfoPtr pScrn, uint32_t limit_match, struct pll_lims *pll_lim)
3419 * Version 0x10: NV31
3420 * One byte header (version), one record of 24 bytes
3421 * Version 0x11: NV36 - Not implemented
3422 * Seems to have same record style as 0x10, but 3 records rather than 1
3423 * Version 0x20: Found on Geforce 6 cards
3424 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
3425 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
3426 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
3427 * length in general, some (integrated) have an extra configuration byte
3430 NVPtr pNv = NVPTR(pScrn);
3431 bios_t *bios = &pNv->VBIOS;
3432 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
3434 uint32_t crystal_strap_mask, crystal_straps;
3436 if (!bios->pll_limit_tbl_ptr) {
3437 if (bios->chip_version >= 0x40 || bios->chip_version == 0x31 || bios->chip_version == 0x36) {
3438 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Pointer to PLL limits table invalid\n");
3442 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
3444 if (DEBUGLEVEL >= 7)
3445 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3446 "Found PLL limits table version 0x%X\n", pll_lim_ver);
3449 crystal_strap_mask = 1 << 6;
3450 /* open coded pNv->twoHeads test */
3451 if (bios->chip_version > 0x10 && bios->chip_version != 0x15 &&
3452 bios->chip_version != 0x1a && bios->chip_version != 0x20)
3453 crystal_strap_mask |= 1 << 22;
3454 crystal_straps = nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & crystal_strap_mask;
3456 switch (pll_lim_ver) {
3457 /* we use version 0 to indicate a pre limit table bios (single stage pll)
3458 * and load the hard coded limits instead */
3462 case 0x11: /* strictly v0x11 has 3 entries, but the last two don't seem to get used */
3470 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
3471 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
3472 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
3475 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3476 "PLL limits table revision not currently supported\n");
3480 /* initialize all members to zero */
3481 memset(pll_lim, 0, sizeof(struct pll_lims));
3483 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
3484 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex;
3486 pll_lim->vco1.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs])));
3487 pll_lim->vco1.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 4])));
3488 pll_lim->vco2.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 8])));
3489 pll_lim->vco2.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 12])));
3490 pll_lim->vco1.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 16])));
3491 pll_lim->vco2.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 20])));
3492 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
3494 /* these values taken from nv30/31/36 */
3495 pll_lim->vco1.min_n = 0x1;
3496 if (bios->chip_version == 0x36)
3497 pll_lim->vco1.min_n = 0x5;
3498 pll_lim->vco1.max_n = 0xff;
3499 pll_lim->vco1.min_m = 0x1;
3500 pll_lim->vco1.max_m = 0xd;
3501 pll_lim->vco2.min_n = 0x4;
3502 /* on nv30, 31, 36 (i.e. all cards with two stage PLLs with this
3503 * table version (apart from nv35)), N2 is compared to
3504 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
3507 pll_lim->vco2.max_n = 0x28;
3508 if (bios->chip_version == 0x30 || bios->chip_version == 0x35)
3509 /* only 5 bits available for N2 on nv30/35 */
3510 pll_lim->vco2.max_n = 0x1f;
3511 pll_lim->vco2.min_m = 0x1;
3512 pll_lim->vco2.max_m = 0x4;
3513 } else if (pll_lim_ver) { /* ver 0x20, 0x21 */
3514 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
3515 uint32_t reg = 0; /* default match */
3518 /* first entry is default match, if nothing better. warn if reg field nonzero */
3519 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs])))
3520 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3521 "Default PLL limit entry has non-zero register field\n");
3523 if (limit_match > MAX_PLL_TYPES)
3524 /* we've been passed a reg as the match */
3526 else /* limit match is a pll type */
3527 for (i = 1; i < entries && !reg; i++) {
3528 uint32_t cmpreg = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + recordlen * i])));
3530 if (limit_match == NVPLL && (cmpreg == NV_RAMDAC_NVPLL || cmpreg == 0x4000))
3532 if (limit_match == MPLL && (cmpreg == NV_RAMDAC_MPLL || cmpreg == 0x4020))
3534 if (limit_match == VPLL1 && (cmpreg == NV_RAMDAC_VPLL || cmpreg == 0x4010))
3536 if (limit_match == VPLL2 && (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018))
3540 for (i = 1; i < entries; i++)
3541 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs + recordlen * i])) == reg) {
3546 plloffs += recordlen * pllindex;
3548 if (DEBUGLEVEL >= 6)
3549 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Loading PLL limits for reg 0x%08x\n",
3550 pllindex ? reg : 0);
3552 /* frequencies are stored in tables in MHz, kHz are more useful, so we convert */
3554 /* What output frequencies can each VCO generate? */
3555 pll_lim->vco1.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 4]))) * 1000;
3556 pll_lim->vco1.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 6]))) * 1000;
3557 pll_lim->vco2.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 8]))) * 1000;
3558 pll_lim->vco2.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 10]))) * 1000;
3560 /* What input frequencies do they accept (past the m-divider)? */
3561 pll_lim->vco1.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 12]))) * 1000;
3562 pll_lim->vco2.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 14]))) * 1000;
3563 pll_lim->vco1.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 16]))) * 1000;
3564 pll_lim->vco2.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 18]))) * 1000;
3566 /* What values are accepted as multiplier and divider? */
3567 pll_lim->vco1.min_n = bios->data[plloffs + 20];
3568 pll_lim->vco1.max_n = bios->data[plloffs + 21];
3569 pll_lim->vco1.min_m = bios->data[plloffs + 22];
3570 pll_lim->vco1.max_m = bios->data[plloffs + 23];
3571 pll_lim->vco2.min_n = bios->data[plloffs + 24];
3572 pll_lim->vco2.max_n = bios->data[plloffs + 25];
3573 pll_lim->vco2.min_m = bios->data[plloffs + 26];
3574 pll_lim->vco2.max_m = bios->data[plloffs + 27];
3576 pll_lim->unk1c = bios->data[plloffs + 28];
3577 pll_lim->max_log2p_bias = bios->data[plloffs + 29];
3578 pll_lim->log2p_bias = bios->data[plloffs + 30];
3580 if (recordlen > 0x22)
3581 pll_lim->refclk = le32_to_cpu(*((uint32_t *)&bios->data[plloffs + 31]));
3583 if (recordlen > 0x23)
3584 if (bios->data[plloffs + 35])
3585 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3586 "Bits set in PLL configuration byte (%x)\n", bios->data[plloffs + 35]);
3588 /* C51 special not seen elsewhere */
3589 if (bios->chip_version == 0x51 && !pll_lim->refclk) {
3590 uint32_t sel_clk = nv32_rd(pScrn, NV_RAMDAC_SEL_CLK);
3592 if (((limit_match == NV_RAMDAC_VPLL || limit_match == VPLL1) && sel_clk & 0x20) ||
3593 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) {
3594 if (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_REVISION) < 0xa3)
3595 pll_lim->refclk = 200000;
3597 pll_lim->refclk = 25000;
3602 /* By now any valid limit table ought to have set a max frequency for
3603 * vco1, so if it's zero it's either a pre limit table bios, or one
3604 * with an empty limit table (seen on nv18)
3606 if (!pll_lim->vco1.maxfreq) {
3607 pll_lim->vco1.minfreq = bios->fminvco;
3608 pll_lim->vco1.maxfreq = bios->fmaxvco;
3609 pll_lim->vco1.min_inputfreq = 0;
3610 pll_lim->vco1.max_inputfreq = INT_MAX;
3611 pll_lim->vco1.min_n = 0x1;
3612 pll_lim->vco1.max_n = 0xff;
3613 pll_lim->vco1.min_m = 0x1;
3614 if (crystal_straps == 0) {
3615 /* nv05 does this, nv11 doesn't, nv10 unknown */
3616 if (bios->chip_version < 0x11)
3617 pll_lim->vco1.min_m = 0x7;
3618 pll_lim->vco1.max_m = 0xd;
3620 if (bios->chip_version < 0x11)
3621 pll_lim->vco1.min_m = 0x8;
3622 pll_lim->vco1.max_m = 0xe;
3626 if (!pll_lim->refclk)
3627 switch (crystal_straps) {
3629 pll_lim->refclk = 13500;
3632 pll_lim->refclk = 14318;
3635 pll_lim->refclk = 27000;
3637 case (1 << 22 | 1 << 6):
3638 pll_lim->refclk = 25000;
3642 #if 0 /* for easy debugging */
3643 ErrorF("pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
3644 ErrorF("pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
3645 ErrorF("pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
3646 ErrorF("pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
3648 ErrorF("pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
3649 ErrorF("pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
3650 ErrorF("pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
3651 ErrorF("pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
3653 ErrorF("pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
3654 ErrorF("pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
3655 ErrorF("pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
3656 ErrorF("pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
3657 ErrorF("pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
3658 ErrorF("pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
3659 ErrorF("pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
3660 ErrorF("pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
3662 ErrorF("pll.unk1c: %d\n", pll_lim->unk1c);
3663 ErrorF("pll.max_log2p_bias: %d\n", pll_lim->max_log2p_bias);
3664 ErrorF("pll.log2p_bias: %d\n", pll_lim->log2p_bias);
3666 ErrorF("pll.refclk: %d\n", pll_lim->refclk);
3672 static int parse_bit_C_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3674 /* offset + 8 (16 bits): PLL limits table pointer
3676 * There's more in here, but that's unknown.
3679 if (bitentry->length < 10) {
3680 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand BIT C table\n");
3684 bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
3689 static int parse_bit_display_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3691 /* Parses the flat panel table segment that the bit entry points to.
3692 * Starting at bitentry->offset:
3694 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte records beginning with a freq
3695 * offset + 2 (16 bits): mode table pointer
3698 struct fppointers fpp;
3700 if (bitentry->length != 4) {
3701 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand BIT display table\n");
3705 memset(&fpp, 0, sizeof(struct fppointers));
3706 fpp.fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
3708 parse_fp_mode_table(pScrn, bios, &fpp);
3713 static unsigned int parse_bit_init_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3715 /* Parses the init table segment that the bit entry points to.
3716 * Starting at bitentry->offset:
3718 * offset + 0 (16 bits): init script tables pointer
3719 * offset + 2 (16 bits): macro index table pointer
3720 * offset + 4 (16 bits): macro table pointer
3721 * offset + 6 (16 bits): condition table pointer
3722 * offset + 8 (16 bits): io condition table pointer
3723 * offset + 10 (16 bits): io flag condition table pointer
3724 * offset + 12 (16 bits): init function table pointer
3728 if (bitentry->length < 14) {
3729 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand init table\n");
3733 bios->init_script_tbls_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3734 bios->macro_index_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
3735 bios->macro_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 4])));
3736 bios->condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 6])));
3737 bios->io_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
3738 bios->io_flag_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 10])));
3739 bios->init_function_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 12])));
3744 static int parse_bit_i_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3746 /* BIT 'i' (info?) table
3748 * offset + 0 (32 bits): BIOS version dword (as in B table)
3749 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
3750 * offset + 13 (16 bits): pointer to table containing DAC load detection comparison values
3752 * There's other things in the table, purpose unknown
3755 uint16_t daccmpoffset;
3756 uint8_t dacversion, dacheaderlen;
3758 if (bitentry->length < 6) {
3759 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3760 "BIT i table not long enough for BIOS version and feature byte\n");
3764 parse_bios_version(pScrn, bios, bitentry->offset);
3766 /* bit 4 seems to indicate a mobile bios, other bits possibly as for BMP feature byte */
3767 bios->feature_byte = bios->data[bitentry->offset + 5];
3769 if (bitentry->length < 15) {
3770 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3771 "BIT i table not long enough for DAC load detection comparison table\n");
3775 daccmpoffset = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 13])));
3777 /* doesn't exist on g80 */
3781 /* The first value in the table, following the header, is the comparison value
3782 * Purpose of subsequent values unknown -- TV load detection?
3785 dacversion = bios->data[daccmpoffset];
3786 dacheaderlen = bios->data[daccmpoffset + 1];
3788 if (dacversion != 0x00 && dacversion != 0x10) {
3789 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3790 "DAC load detection comparison table version %d.%d not known\n",
3791 dacversion >> 4, dacversion & 0xf);
3794 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3795 "DAC load detection comparison table version %x found\n", dacversion);
3797 bios->dactestval = le32_to_cpu(*((uint32_t *)(&bios->data[daccmpoffset + dacheaderlen])));
3802 static int parse_bit_lvds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3804 /* Parses the LVDS table segment that the bit entry points to.
3805 * Starting at bitentry->offset:
3807 * offset + 0 (16 bits): LVDS strap xlate table pointer
3810 if (bitentry->length != 2) {
3811 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand BIT LVDS table\n");
3815 /* no idea if it's still called the LVDS manufacturer table, but the concept's close enough */
3816 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3817 bios->fp.strapping = get_fp_strap(pScrn, bios);
3819 parse_lvds_manufacturer_table(pScrn, bios, 0);
3824 static int parse_bit_M_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3826 /* offset + 2 (8 bits): number of options in an INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
3827 * offset + 3 (16 bits): pointer to strap xlate table for RAM restrict option selection
3829 * There's a bunch of bits in this table other than the RAM restrict
3830 * stuff that we don't use - their use currently unknown
3835 /* Older bios versions don't have a sufficiently long table for what we want */
3836 if (bitentry->length < 0x5)
3839 /* set up multiplier for INIT_RAM_RESTRICT_ZM_REG_GROUP */
3840 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != 0x8f); i++)
3842 itbl_entry[i].length_multiplier = bios->data[bitentry->offset + 2] * 4;
3843 init_ram_restrict_zm_reg_group_blocklen = itbl_entry[i].length_multiplier;
3845 bios->ram_restrict_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 3])));
3850 static int parse_bit_tmds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3852 /* Parses the pointer to the TMDS table
3854 * Starting at bitentry->offset:
3856 * offset + 0 (16 bits): TMDS table pointer
3858 * The TMDS table is typically found just before the DCB table, with a
3859 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
3862 * At offset +7 is a pointer to a script, which I don't know how to run yet
3863 * At offset +9 is a pointer to another script, likewise
3864 * Offset +11 has a pointer to a table where the first word is a pxclk
3865 * frequency and the second word a pointer to a script, which should be
3866 * run if the comparison pxclk frequency is less than the pxclk desired.
3867 * This repeats for decreasing comparison frequencies
3868 * Offset +13 has a pointer to a similar table
3869 * The selection of table (and possibly +7/+9 script) is dictated by
3870 * "or" from the DCB.
3873 uint16_t tmdstableptr, script1, script2;
3875 if (bitentry->length != 2) {
3876 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand BIT TMDS table\n");
3880 tmdstableptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3882 if (tmdstableptr == 0x0) {
3883 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Pointer to TMDS table invalid\n");
3887 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found TMDS table revision %d.%d\n",
3888 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
3890 /* These two scripts are odd: they don't seem to get run even when they are not stubbed */
3891 script1 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 7]));
3892 script2 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 9]));
3893 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
3894 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "TMDS table script pointers not stubbed\n");
3896 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 11]));
3897 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 13]));
3902 static void parse_bit_structure(ScrnInfoPtr pScrn, bios_t *bios, const uint16_t bitoffset)
3904 int entries = bios->data[bitoffset + 4];
3905 /* parse i first, I next (which needs C & M before it), and L before D */
3906 char parseorder[] = "iCMILDT";
3907 bit_entry_t bitentry;
3910 for (i = 0; i < sizeof(parseorder); i++) {
3911 for (j = 0, offset = bitoffset + 6; j < entries; j++, offset += 6) {
3912 bitentry.id[0] = bios->data[offset];
3913 bitentry.id[1] = bios->data[offset + 1];
3914 bitentry.length = le16_to_cpu(*((uint16_t *)&bios->data[offset + 2]));
3915 bitentry.offset = le16_to_cpu(*((uint16_t *)&bios->data[offset + 4]));
3917 if (bitentry.id[0] != parseorder[i])
3920 switch (bitentry.id[0]) {
3922 parse_bit_C_tbl_entry(pScrn, bios, &bitentry);
3925 parse_bit_display_tbl_entry(pScrn, bios, &bitentry);
3928 parse_bit_init_tbl_entry(pScrn, bios, &bitentry);
3929 parse_init_tables(pScrn, bios);
3931 case 'i': /* info? */
3932 parse_bit_i_tbl_entry(pScrn, bios, &bitentry);
3935 if (bios->feature_byte & FEATURE_MOBILE)
3936 parse_bit_lvds_tbl_entry(pScrn, bios, &bitentry);
3938 case 'M': /* memory? */
3939 parse_bit_M_tbl_entry(pScrn, bios, &bitentry);
3942 parse_bit_tmds_tbl_entry(pScrn, bios, &bitentry);
3949 static void parse_bmp_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset)
3951 /* Parse the BMP structure for useful things
3953 * offset + 5: BMP major version
3954 * offset + 6: BMP minor version
3955 * offset + 10: BCD encoded BIOS version
3957 * offset + 18: init script table pointer (for bios versions < 5.10h)
3958 * offset + 20: extra init script table pointer (for bios versions < 5.10h)
3960 * offset + 24: memory init table pointer (used on early bios versions)
3961 * offset + 26: SDR memory sequencing setup data table
3962 * offset + 28: DDR memory sequencing setup data table
3964 * offset + 54: index of I2C CRTC pair to use for CRT output
3965 * offset + 55: index of I2C CRTC pair to use for TV output
3966 * offset + 56: index of I2C CRTC pair to use for flat panel output
3967 * offset + 58: write CRTC index for I2C pair 0
3968 * offset + 59: read CRTC index for I2C pair 0
3969 * offset + 60: write CRTC index for I2C pair 1
3970 * offset + 61: read CRTC index for I2C pair 1
3972 * offset + 67: maximum internal PLL frequency (single stage PLL)
3973 * offset + 71: minimum internal PLL frequency (single stage PLL)
3975 * offset + 75: script table pointers, as for parse_bit_init_tbl_entry
3977 * offset + 89: TMDS single link output A table pointer
3978 * offset + 91: TMDS single link output B table pointer
3979 * offset + 105: flat panel timings table pointer
3980 * offset + 107: flat panel strapping translation table pointer
3981 * offset + 117: LVDS manufacturer panel config table pointer
3982 * offset + 119: LVDS manufacturer strapping translation table pointer
3984 * offset + 142: PLL limits table pointer
3987 NVPtr pNv = NVPTR(pScrn);
3988 uint8_t bmp_version_major, bmp_version_minor;
3990 struct fppointers fpp;
3991 uint16_t legacy_scripts_offset, legacy_i2c_offset;
3993 memset(&fpp, 0, sizeof(struct fppointers));
3995 /* load needed defaults in case we can't parse this info */
3996 pNv->dcb_table.i2c_write[0] = 0x3f;
3997 pNv->dcb_table.i2c_read[0] = 0x3e;
3998 pNv->dcb_table.i2c_write[1] = 0x37;
3999 pNv->dcb_table.i2c_read[1] = 0x36;
4000 bios->digital_min_front_porch = 0x4b;
4001 bios->fmaxvco = 256000;
4002 bios->fminvco = 128000;
4003 bios->fp.duallink_transition_clk = 90000;
4005 bmp_version_major = bios->data[offset + 5];
4006 bmp_version_minor = bios->data[offset + 6];
4008 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BMP version %d.%d\n",
4009 bmp_version_major, bmp_version_minor);
4011 /* Make sure that 0x36 is blank and can't be mistaken for a DCB pointer on early versions */
4012 if (bmp_version_major < 5)
4013 *(uint16_t *)&bios->data[0x36] = 0;
4015 /* Seems that the minor version was 1 for all major versions prior to 5 */
4016 /* Version 6 could theoretically exist, but I suspect BIT happened instead */
4017 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
4018 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "You have an unsupported BMP version. Please send in your bios\n");
4022 if (bmp_version_major == 0) /* nothing that's currently useful in this version */
4024 else if (bmp_version_major == 1)
4025 bmplength = 44; /* exact for 1.01 */
4026 else if (bmp_version_major == 2)
4027 bmplength = 48; /* exact for 2.01 */
4028 else if (bmp_version_major == 3)
4029 bmplength = 54; /* guessed - mem init tables added in this version */
4030 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) /* don't know if 5.0 exists... */
4031 bmplength = 62; /* guessed - BMP I2C indices added in version 4*/
4032 else if (bmp_version_minor < 0x6)
4033 bmplength = 67; /* exact for 5.01 */
4034 else if (bmp_version_minor < 0x10)
4035 bmplength = 75; /* exact for 5.06 */
4036 else if (bmp_version_minor == 0x10)
4037 bmplength = 89; /* exact for 5.10h */
4038 else if (bmp_version_minor < 0x14)
4039 bmplength = 118; /* exact for 5.11h */
4040 else if (bmp_version_minor < 0x24) /* not sure of version where pll limits came in;
4041 * certainly exist by 0x24 though */
4042 /* length not exact: this is long enough to get lvds members */
4044 else if (bmp_version_minor < 0x27)
4045 /* length not exact: this is long enough to get pll limit member */
4048 /* length not exact: this is long enough to get dual link transition clock */
4052 if (nv_cksum(bios->data + offset, 8)) {
4053 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Bad BMP checksum\n");
4057 /* bit 4 seems to indicate a mobile bios, bit 5 that the flat panel
4058 * tables are present, and bit 6 a tv bios */
4059 bios->feature_byte = bios->data[offset + 9];
4061 parse_bios_version(pScrn, bios, offset + 10);
4063 legacy_scripts_offset = offset + 18;
4064 if (bmp_version_major < 2)
4065 legacy_scripts_offset -= 4;
4066 bios->init_script_tbls_ptr = le16_to_cpu(*(uint16_t *)&bios->data[legacy_scripts_offset]);
4067 bios->extra_init_script_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[legacy_scripts_offset + 2]);
4069 if (bmp_version_major > 2) { /* appears in BMP 3 */
4070 bios->legacy.mem_init_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 24]);
4071 bios->legacy.sdr_seq_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 26]);
4072 bios->legacy.ddr_seq_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 28]);
4075 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
4077 legacy_i2c_offset = offset + 54;
4078 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
4079 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
4080 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
4081 pNv->dcb_table.i2c_write[0] = bios->data[legacy_i2c_offset + 4];
4082 pNv->dcb_table.i2c_read[0] = bios->data[legacy_i2c_offset + 5];
4083 pNv->dcb_table.i2c_write[1] = bios->data[legacy_i2c_offset + 6];
4084 pNv->dcb_table.i2c_read[1] = bios->data[legacy_i2c_offset + 7];
4086 if (bmplength > 74) {
4087 bios->fmaxvco = le32_to_cpu(*((uint32_t *)&bios->data[offset + 67]));
4088 bios->fminvco = le32_to_cpu(*((uint32_t *)&bios->data[offset + 71]));
4090 if (bmplength > 88) {
4091 bit_entry_t initbitentry;
4092 initbitentry.length = 14;
4093 initbitentry.offset = offset + 75;
4094 parse_bit_init_tbl_entry(pScrn, bios, &initbitentry);
4096 if (bmplength > 94) {
4097 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[offset + 89]));
4098 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[offset + 91]));
4099 /* it seems the old style lvds script pointer (which I've not observed in use) gets
4100 * reused as the 18/24 bit panel interface default for EDID equipped panels */
4101 bios->fp.if_is_24bit = bios->data[offset + 95] & 1;
4103 if (bmplength > 108) {
4104 fpp.fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 105])));
4105 fpp.fpxlatetableptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 107])));
4108 if (bmplength > 120) {
4109 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 117])));
4110 bios->fp.fpxlatemanufacturertableptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 119])));
4112 if (bmplength > 143)
4113 bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 142])));
4115 if (bmplength > 157)
4116 bios->fp.duallink_transition_clk = le16_to_cpu(*((uint16_t *)&bios->data[offset + 156])) * 10;
4118 /* want pll_limit_tbl_ptr set (if available) before init is run */
4119 if (bmp_version_major < 5 || bmp_version_minor < 0x10) {
4120 init_exec_t iexec = {true, false};
4121 if (bios->init_script_tbls_ptr)
4122 parse_init_table(pScrn, bios, bios->init_script_tbls_ptr, &iexec);
4123 if (bios->extra_init_script_tbl_ptr)
4124 parse_init_table(pScrn, bios, bios->extra_init_script_tbl_ptr, &iexec);
4126 parse_init_tables(pScrn, bios);
4128 /* If it's not a laptop, you probably don't care about fptables */
4129 if (!(bios->feature_byte & FEATURE_MOBILE))
4132 bios->fp.strapping = get_fp_strap(pScrn, bios);
4133 parse_lvds_manufacturer_table(pScrn, bios, 0);
4134 parse_fp_mode_table(pScrn, bios, &fpp);
4137 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
4141 for (i = 0; i <= (n - len); i++) {
4142 for (j = 0; j < len; j++)
4143 if (data[i + j] != str[j])
4153 read_dcb_i2c_entry(ScrnInfoPtr pScrn, uint8_t dcb_version, uint16_t i2ctabptr, int index)
4155 NVPtr pNv = NVPTR(pScrn);
4156 bios_t *bios = &pNv->VBIOS;
4157 uint8_t *i2ctable = &bios->data[i2ctabptr];
4158 uint8_t headerlen = 0;
4159 int i2c_entries = MAX_NUM_DCB_ENTRIES;
4160 int recordoffset = 0, rdofs = 1, wrofs = 0;
4165 if (dcb_version >= 0x30) {
4166 if (i2ctable[0] != dcb_version) /* necessary? */
4167 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4168 "DCB I2C table version mismatch (%02X vs %02X)\n",
4169 i2ctable[0], dcb_version);
4170 headerlen = i2ctable[1];
4171 i2c_entries = i2ctable[2];
4173 /* same address offset used for read and write for C51 and G80 */
4174 if (bios->chip_version == 0x51)
4176 if (i2ctable[0] >= 0x40)
4179 /* it's your own fault if you call this function on a DCB 1.1 BIOS --
4180 * the test below is for DCB 1.2
4182 if (dcb_version < 0x14) {
4190 if (index > i2c_entries) {
4191 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4192 "DCB I2C index too big (%d > %d)\n",
4193 index, i2ctable[2]);
4196 if (i2ctable[headerlen + 4 * index + 3] == 0xff) {
4197 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4198 "DCB I2C entry invalid\n");
4202 if (bios->chip_version == 0x51) {
4203 int port_type = i2ctable[headerlen + 4 * index + 3];
4206 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4207 "DCB I2C table has port type %d\n", port_type);
4209 if (i2ctable[0] >= 0x40) {
4210 int port_type = i2ctable[headerlen + 4 * index + 3];
4213 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4214 "DCB I2C table has port type %d\n", port_type);
4217 pNv->dcb_table.i2c_read[index] = i2ctable[headerlen + recordoffset + rdofs + 4 * index];
4218 pNv->dcb_table.i2c_write[index] = i2ctable[headerlen + recordoffset + wrofs + 4 * index];
4222 parse_dcb_entry(ScrnInfoPtr pScrn, int index, uint8_t dcb_version, uint16_t i2ctabptr, uint32_t conn, uint32_t conf)
4224 NVPtr pNv = NVPTR(pScrn);
4225 struct dcb_entry *entry = &pNv->dcb_table.entry[index];
4227 memset(entry, 0, sizeof (struct dcb_entry));
4229 entry->index = index;
4230 /* safe defaults for a crt */
4232 entry->i2c_index = 0;
4235 entry->location = LOC_ON_CHIP;
4237 entry->duallink_possible = false;
4239 if (dcb_version >= 0x20) {
4240 entry->type = conn & 0xf;
4241 entry->i2c_index = (conn >> 4) & 0xf;
4242 entry->heads = (conn >> 8) & 0xf;
4243 entry->bus = (conn >> 16) & 0xf;
4244 entry->location = (conn >> 20) & 0xf;
4245 entry->or = (conn >> 24) & 0xf;
4246 /* Normal entries consist of a single bit, but dual link has the
4247 * adjacent more significant bit set too
4249 if ((1 << (ffs(entry->or) - 1)) * 3 == entry->or)
4250 entry->duallink_possible = true;
4252 switch (entry->type) {
4257 entry->lvdsconf.use_straps_for_mode = true;
4258 if (dcb_version < 0x22) {
4260 /* both 0x4 and 0x8 show up in v2.0 tables; assume they mean
4261 * the same thing, which is probably wrong, but might work */
4262 if (conf & 0x4 || conf & 0x8)
4263 entry->lvdsconf.use_power_scripts = true;
4267 entry->lvdsconf.use_power_scripts = true;
4270 /* I'm bored of getting this reported; left as a reminder for someone to fix it */
4271 if (dcb_version >= 0x40) {
4272 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4273 "G80+ LVDS not initialized by driver; ignoring conf bits\n");
4276 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4277 "Unknown LVDS configuration bits, please report\n");
4278 /* cause output setting to fail, so message is seen */
4279 pNv->dcb_table.entries = 0;
4285 /* weird type that appears on g80 mobile bios; nv driver treats it as a terminator */
4288 read_dcb_i2c_entry(pScrn, dcb_version, i2ctabptr, entry->i2c_index);
4289 } else if (dcb_version >= 0x14 ) {
4290 if (conn != 0xf0003f00 && conn != 0xf2247f10 &&
4291 conn != 0xf2204001 && conn != 0xf2204301 && conn != 0xf2204311 && conn != 0xf2208001 && conn != 0xf2244001 && conn != 0xf2244301 && conn != 0xf2244311 && conn != 0xf4204011 && conn != 0xf4208011 && conn != 0xf4248011 &&
4292 conn != 0xf2045f14 && conn != 0xf2205004) {
4293 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4294 "Unknown DCB 1.4 / 1.5 entry, please report\n");
4296 /* cause output setting to fail for non-TVs, so message is seen */
4297 if ((conn & 0xf) != 0x1)
4298 pNv->dcb_table.entries = 0;
4302 /* most of the below is a "best guess" atm */
4303 entry->type = conn & 0xf;
4304 if (entry->type == 4) { /* digital */
4306 entry->type = OUTPUT_LVDS;
4308 entry->type = OUTPUT_TMDS;
4310 /* what's in bits 5-13? could be some brooktree/chrontel/philips thing, in tv case */
4311 entry->i2c_index = (conn >> 14) & 0xf;
4312 /* raw heads field is in range 0-1, so move to 1-2 */
4313 entry->heads = ((conn >> 18) & 0x7) + 1;
4314 entry->location = (conn >> 21) & 0xf;
4315 entry->bus = (conn >> 25) & 0x7;
4316 /* set or to be same as heads -- hopefully safe enough */
4317 entry->or = entry->heads;
4319 switch (entry->type) {
4321 /* this is probably buried in conn's unknown bits */
4322 entry->lvdsconf.use_power_scripts = true;
4325 /* invent a DVI-A output, by copying the fields of the DVI-D output
4326 * reported to work by math_b on an NV20(!) */
4327 memcpy(&entry[1], &entry[0], sizeof(struct dcb_entry));
4328 entry[1].index = ++index;
4329 entry[1].type = OUTPUT_ANALOG;
4330 ErrorF("Concocting additional DCB entry for analogue "
4331 "encoder on DVI output\n");
4332 pNv->dcb_table.entries++;
4334 read_dcb_i2c_entry(pScrn, dcb_version, i2ctabptr, entry->i2c_index);
4335 } else if (dcb_version >= 0x12) {
4336 /* v1.2 tables normally have the same 5 entries, which are not
4337 * specific to the card, so use the defaults for a crt */
4338 /* DCB v1.2 does have an I2C table that read_dcb_i2c_table can handle, but cards
4339 * exist (seen on nv11) where the pointer to the table points to the wrong
4340 * place, so for now, we rely on the indices parsed in parse_bmp_structure
4342 entry->i2c_index = pNv->VBIOS.legacy.i2c_indices.crt;
4343 } else { /* pre DCB / v1.1 - use the safe defaults for a crt */
4344 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4345 "No information in BIOS output table; assuming a CRT output exists\n");
4346 entry->i2c_index = pNv->VBIOS.legacy.i2c_indices.crt;
4349 if (entry->type == OUTPUT_LVDS && pNv->VBIOS.fp.strapping != 0xff)
4350 entry->lvdsconf.use_straps_for_mode = true;
4352 pNv->dcb_table.entries++;
4357 void merge_like_dcb_entries(ScrnInfoPtr pScrn)
4359 /* DCB v2.0 lists each output combination separately.
4360 * Here we merge compatible entries to have fewer outputs, with more options
4363 NVPtr pNv = NVPTR(pScrn);
4364 int i, newentries = 0;
4366 for (i = 0; i < pNv->dcb_table.entries; i++) {
4367 struct dcb_entry *ient = &pNv->dcb_table.entry[i];
4370 for (j = i + 1; j < pNv->dcb_table.entries; j++) {
4371 struct dcb_entry *jent = &pNv->dcb_table.entry[j];
4373 if (jent->type == 100) /* already merged entry */
4376 /* merge heads field when all other fields the same */
4377 if (jent->i2c_index == ient->i2c_index && jent->type == ient->type && jent->location == ient->location && jent->or == ient->or) {
4378 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4379 "Merging DCB entries %d and %d\n", i, j);
4380 ient->heads |= jent->heads;
4381 jent->type = 100; /* dummy value */
4386 /* Compact entries merged into others out of dcb_table */
4387 for (i = 0; i < pNv->dcb_table.entries; i++) {
4388 if ( pNv->dcb_table.entry[i].type == 100 )
4391 if (newentries != i)
4392 memcpy(&pNv->dcb_table.entry[newentries], &pNv->dcb_table.entry[i], sizeof(struct dcb_entry));
4396 pNv->dcb_table.entries = newentries;
4399 static unsigned int parse_dcb_table(ScrnInfoPtr pScrn, bios_t *bios)
4401 NVPtr pNv = NVPTR(pScrn);
4402 uint16_t dcbptr, i2ctabptr = 0;
4404 uint8_t dcb_version, headerlen = 0x4, entries = MAX_NUM_DCB_ENTRIES;
4405 bool configblock = true;
4406 int recordlength = 8, confofs = 4;
4409 pNv->dcb_table.entries = 0;
4411 /* get the offset from 0x36 */
4412 dcbptr = le16_to_cpu(*(uint16_t *)&bios->data[0x36]);
4414 if (dcbptr == 0x0) {
4415 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4416 "No Display Configuration Block pointer found\n");
4417 /* this situation likely means a really old card, pre DCB, so we'll add the safe CRT entry */
4418 parse_dcb_entry(pScrn, 0, 0, 0, 0, 0);
4422 dcbtable = &bios->data[dcbptr];
4424 /* get DCB version */
4425 dcb_version = dcbtable[0];
4426 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4427 "Display Configuration Block version %d.%d found\n",
4428 dcb_version >> 4, dcb_version & 0xf);
4430 if (dcb_version >= 0x20) { /* NV17+ */
4433 if (dcb_version >= 0x30) { /* NV40+ */
4434 headerlen = dcbtable[1];
4435 entries = dcbtable[2];
4436 recordlength = dcbtable[3];
4437 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[4]);
4438 sig = le32_to_cpu(*(uint32_t *)&dcbtable[6]);
4440 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4441 "DCB header length %d, with %d possible entries\n",
4442 headerlen, entries);
4444 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
4445 sig = le32_to_cpu(*(uint32_t *)&dcbtable[4]);
4449 if (sig != 0x4edcbdcb) {
4450 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4451 "Bad Display Configuration Block signature (%08X)\n", sig);
4454 } else if (dcb_version >= 0x14) { /* some NV15/16, and NV11+ */
4458 strncpy(sig, (char *)&dcbtable[-7], 7);
4459 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
4463 if (strcmp(sig, "DEV_REC")) {
4464 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4465 "Bad Display Configuration Block signature (%s)\n", sig);
4468 } else if (dcb_version >= 0x12) { /* some NV6/10, and NV15+ */
4469 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
4470 configblock = false;
4471 } else { /* NV5+, maybe NV4 */
4472 /* DCB 1.1 seems to be quite unhelpful - we'll just add the safe CRT entry */
4473 parse_dcb_entry(pScrn, 0, dcb_version, 0, 0, 0);
4477 if (entries >= MAX_NUM_DCB_ENTRIES)
4478 entries = MAX_NUM_DCB_ENTRIES;
4480 for (i = 0; i < entries; i++) {
4481 uint32_t connection, config = 0;
4483 connection = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + recordlength * i]);
4485 config = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + confofs + recordlength * i]);
4487 /* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
4488 if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
4490 if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */
4493 ErrorF("Raw DCB entry %d: %08x %08x\n",
4494 pNv->dcb_table.entries, connection, config);
4495 if (!parse_dcb_entry(pScrn, pNv->dcb_table.entries, dcb_version, i2ctabptr, connection, config))
4499 merge_like_dcb_entries(pScrn);
4501 return pNv->dcb_table.entries;
4504 static void load_nv17_hw_sequencer_ucode(ScrnInfoPtr pScrn, bios_t *bios, uint16_t hwsq_offset, int entry)
4506 /* BMP based cards, from NV17, need a microcode loading to correctly
4507 * control the GPIO etc for LVDS panels
4509 * BIT based cards seem to do this directly in the init scripts
4511 * The microcode entries are found by the "HWSQ" signature.
4512 * The header following has the number of entries, and the entry size
4514 * An entry consists of a dword to write to the sequencer control reg
4515 * (0x00001304), followed by the ucode bytes, written sequentially,
4516 * starting at reg 0x00001400
4519 uint8_t bytes_to_write;
4520 uint16_t hwsq_entry_offset;
4523 if (bios->data[hwsq_offset] <= entry) {
4524 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4525 "Too few entries in HW sequencer table for requested entry\n");
4529 bytes_to_write = bios->data[hwsq_offset + 1];
4531 if (bytes_to_write != 36) {
4532 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unknown HW sequencer entry size\n");
4536 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Loading NV17 power sequencing microcode\n");
4538 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
4540 /* set sequencer control */
4541 nv32_wr(pScrn, 0x00001304, le32_to_cpu(*(uint32_t *)&bios->data[hwsq_entry_offset]));
4542 bytes_to_write -= 4;
4545 for (i = 0; i < bytes_to_write; i += 4)
4546 nv32_wr(pScrn, 0x00001400 + i, le32_to_cpu(*(uint32_t *)&bios->data[hwsq_entry_offset + i + 4]));
4548 /* twiddle NV_PBUS_DEBUG_4 */
4549 nv32_wr(pScrn, NV_PBUS_DEBUG_4, nv32_rd(pScrn, NV_PBUS_DEBUG_4) | 0x18);
4552 static void read_bios_edid(ScrnInfoPtr pScrn)
4554 bios_t *bios = &NVPTR(pScrn)->VBIOS;
4555 const uint8_t edid_sig[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
4556 uint16_t offset = 0, newoffset;
4557 int searchlen = NV_PROM_SIZE, i;
4560 if (!(newoffset = findstr(&bios->data[offset], searchlen, edid_sig, 8)))
4562 offset += newoffset;
4563 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
4566 searchlen -= offset;
4570 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found EDID in BIOS\n");
4572 bios->fp.edid = xalloc(EDID1_LEN);
4573 for (i = 0; i < EDID1_LEN; i++)
4574 bios->fp.edid[i] = bios->data[offset + i];
4577 bool NVInitVBIOS(ScrnInfoPtr pScrn)
4579 NVPtr pNv = NVPTR(pScrn);
4581 memset(&pNv->VBIOS, 0, sizeof(bios_t));
4582 pNv->VBIOS.data = xalloc(NV_PROM_SIZE);
4584 if (!NVShadowVBIOS(pScrn, pNv->VBIOS.data)) {
4585 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4586 "No valid BIOS image found\n");
4587 xfree(pNv->VBIOS.data);
4591 pNv->VBIOS.length = pNv->VBIOS.data[2] * 512;
4592 if (pNv->VBIOS.length > NV_PROM_SIZE)
4593 pNv->VBIOS.length = NV_PROM_SIZE;
4598 bool NVRunVBIOSInit(ScrnInfoPtr pScrn)
4600 NVPtr pNv = NVPTR(pScrn);
4601 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
4602 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
4603 int offset, ret = 0;
4605 crtc_access(pScrn, ACCESS_UNLOCK);
4607 if ((offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, bit_signature, sizeof(bit_signature)))) {
4608 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIT BIOS found\n");
4609 parse_bit_structure(pScrn, &pNv->VBIOS, offset + 6);
4610 } else if ((offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, bmp_signature, sizeof(bmp_signature)))) {
4611 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
4614 if ((hwsq_offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, hwsq_signature, sizeof(hwsq_signature))))
4615 /* always use entry 0? */
4616 load_nv17_hw_sequencer_ucode(pScrn, &pNv->VBIOS, hwsq_offset + sizeof(hwsq_signature), 0);
4618 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BMP BIOS found\n");
4619 parse_bmp_structure(pScrn, &pNv->VBIOS, offset);
4621 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4622 "No known BIOS signature found\n");
4626 crtc_access(pScrn, ACCESS_LOCK);
4634 unsigned int NVParseBios(ScrnInfoPtr pScrn)
4636 NVPtr pNv = NVPTR(pScrn);
4637 uint32_t saved_nv_pextdev_boot_0;
4640 if (!NVInitVBIOS(pScrn))
4643 /* these will need remembering across a suspend */
4644 saved_nv_pextdev_boot_0 = nv32_rd(pScrn, NV_PEXTDEV_BOOT_0);
4645 saved_nv_pfb_cfg0 = nv32_rd(pScrn, NV_PFB_CFG0);
4647 /* init script execution disabled */
4648 pNv->VBIOS.execute = false;
4650 nv32_wr(pScrn, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
4652 if (!NVRunVBIOSInit(pScrn))
4655 if (parse_dcb_table(pScrn, &pNv->VBIOS))
4656 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4657 "Found %d entries in DCB\n", pNv->dcb_table.entries);
4659 for (i = 0 ; i < pNv->dcb_table.entries; i++)
4660 if (pNv->dcb_table.entry[i].type == OUTPUT_LVDS)
4661 call_lvds_script(pScrn, &pNv->dcb_table.entry[i], nv_get_digital_bound_head(pNv, pNv->dcb_table.entry[i].or), LVDS_INIT, 0);
4663 if (pNv->VBIOS.feature_byte & FEATURE_MOBILE && !pNv->VBIOS.fp.native_mode)
4664 read_bios_edid(pScrn);
4666 /* allow subsequent scripts to execute */
4667 pNv->VBIOS.execute = true;