1 /* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */
3 * Copyright 1996-1997 David J. McKay
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
19 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
20 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nvreg.h,v 1.6 2002/01/25 21:56:06 tsi Exp $ */
29 //#define NV_IMAGE_PATTERN 0x18
32 #define NV_PRAMIN_OFFSET 0x00710000
33 #define NV_PRAMIN_SIZE 0x00100000
35 #define NV_PCRTC0_OFFSET 0x00600000
36 #define NV_PCRTC0_SIZE 0x00002000 /* empirical */
38 #define NV50_PCRTC_OFFSET 0x00610000
39 #define NV50_PCRTC_SIZE 0x00004000 /* Until a better guess comes along */
41 #define NV_PRAMDAC0_OFFSET 0x00680000
42 #define NV_PRAMDAC0_SIZE 0x00002000
44 #define NV_PFB_OFFSET 0x00100000
45 #define NV_PFB_SIZE 0x00001000
47 #define NV_PFIFO_OFFSET 0x00002000
48 #define NV_PFIFO_SIZE 0x00010000
50 #define NV_PGRAPH_OFFSET 0x00400000
51 #define NV_PGRAPH_SIZE 0x00010000
53 #define NV_PEXTDEV_OFFSET 0x00101000
54 #define NV_PEXTDEV_SIZE 0x00001000
56 #define NV_PTIMER_OFFSET 0x00009000
57 #define NV_PTIMER_SIZE 0x00001000
59 #define NV_PVIDEO_OFFSET 0x00008000
60 #define NV_PVIDEO_SIZE 0x00001000
62 /* TODO PMC size is 0x1000, but we need to get ride of abuses first */
63 #define NV_PMC_OFFSET 0x00000000
64 #define NV_PMC_SIZE 0x0000f000
66 #define NV_FIFO_OFFSET 0x00800000
67 #define NV_FIFO_SIZE 0x00800000
69 #define NV_PCIO0_OFFSET 0x00601000
70 #define NV_PCIO0_SIZE 0x00002000
72 #define NV_PDIO0_OFFSET 0x00681000
73 #define NV_PDIO0_SIZE 0x00002000
75 #define NV_PVIO_OFFSET 0x000C0000
76 #define NV_PVIO_SIZE 0x00008000
78 #define NV_PROM_OFFSET 0x00300000
79 #define NV_PROM_SIZE 0x00010000
81 /* Nvidia CRTC indexed registers */
82 /* VGA standard registers: - from Haiku */
83 #define NV_VGA_CRTCX_HTOTAL 0x00
84 #define NV_VGA_CRTCX_HDISPE 0x01
85 #define NV_VGA_CRTCX_HBLANKS 0x02
86 #define NV_VGA_CRTCX_HBLANKE 0x03
87 #define NV_VGA_CRTCX_HSYNCS 0x04
88 #define NV_VGA_CRTCX_HSYNCE 0x05
89 #define NV_VGA_CRTCX_VTOTAL 0x06
90 #define NV_VGA_CRTCX_OVERFLOW 0x07
91 #define NV_VGA_CRTCX_PRROWSCN 0x08
92 #define NV_VGA_CRTCX_MAXSCLIN 0x09
93 #define NV_VGA_CRTCX_VGACURCTRL 0x0a
94 #define NV_VGA_CRTCX_FBSTADDH 0x0c
95 #define NV_VGA_CRTCX_FBSTADDL 0x0d
96 #define NV_VGA_CRTCX_VSYNCS 0x10
97 #define NV_VGA_CRTCX_VSYNCE 0x11
98 #define NV_VGA_CRTCX_VDISPE 0x12
99 #define NV_VGA_CRTCX_PITCHL 0x13
100 #define NV_VGA_CRTCX_VBLANKS 0x15
101 #define NV_VGA_CRTCX_VBLANKE 0x16
102 #define NV_VGA_CRTCX_MODECTL 0x17
103 #define NV_VGA_CRTCX_LINECOMP 0x18
104 /* Extended VGA CRTC registers */
105 #define NV_VGA_CRTCX_REPAINT0 0x19
106 #define NV_VGA_CRTCX_REPAINT1 0x1a
107 #define NV_VGA_CRTCX_FIFO0 0x1b
108 #define NV_VGA_CRTCX_FIFO1 0x1c
109 #define NV_VGA_CRTCX_LOCK 0x1f
110 #define NV_VGA_CRTCX_FIFO_LWM 0x20
111 #define NV_VGA_CRTCX_BUFFER 0x21
112 #define NV_VGA_CRTCX_LSR 0x25
113 #define NV_VGA_CRTCX_26 0x26
114 #define NV_VGA_CRTCX_PIXEL 0x28
115 #define NV_VGA_CRTCX_HEB 0x2d
116 #define NV_VGA_CRTCX_CURCTL2 0x2f
117 #define NV_VGA_CRTCX_CURCTL0 0x30
118 #define NV_VGA_CRTCX_CURCTL1 0x31
119 #define NV_VGA_CRTCX_LCD 0x33
120 #define NV_VGA_CRTCX_INTERLACE 0x39
121 #define NV_VGA_CRTCX_3B 0x3b
122 #define NV_VGA_CRTCX_3C 0x3c
123 #define NV_VGA_CRTCX_EXTRA 0x41
124 #define NV_VGA_CRTCX_OWNER 0x44
125 #define NV_VGA_CRTCX_45 0x45
126 #define NV_VGA_CRTCX_SWAPPING 0x46
127 #define NV_VGA_CRTCX_FIFO_LWM_NV30 0x47
128 #define NV_VGA_CRTCX_4B 0x4b
129 #define NV_VGA_CRTCX_FP_HTIMING 0x53
130 #define NV_VGA_CRTCX_FP_VTIMING 0x54
131 #define NV_VGA_CRTCX_52 0x52
132 #define NV_VGA_CRTCX_55 0x55
133 #define NV_VGA_CRTCX_56 0x56
134 #define NV_VGA_CRTCX_57 0x57
135 #define NV_VGA_CRTCX_58 0x58
136 #define NV_VGA_CRTCX_59 0x59
138 #define NV_PGRAPH_STATUS (0x00000700)
139 #define NV_PFIFO_RAMHT (0x00000210)
140 #define NV_PFB_BOOT (0x00000000)
141 #define NV_PEXTDEV_BOOT (0x00000000)
143 #define NV_RAMDAC_CURSOR_POS 0x300
144 #define NV_RAMDAC_CURSOR_CTRL 0x320
145 #define NV_RAMDAC_CURSOR_DATA_LO 0x324
146 #define NV_RAMDAC_CURSOR_DATA_HI 0x328
148 #define NV_RAMDAC_NV10_CURSYNC 0x404
150 #define NV_RAMDAC_NVPLL 0x500
151 #define NV_RAMDAC_MPLL 0x504
153 # define NV_RAMDAC_PLL_COEFF_MDIV 0x000000FF
154 # define NV_RAMDAC_PLL_COEFF_NDIV 0x0000FF00
155 # define NV_RAMDAC_PLL_COEFF_PDIV 0x00070000
157 #define NV_RAMDAC_VPLL 0x508
158 #define NV_RAMDAC_PLL_SELECT 0x50c
159 /* Without this it will use vpll1 */
160 /* Maybe only for nv4x */
161 #define NV_RAMDAC_PLL_SELECT_USE_VPLL2_FALSE (0<<2)
162 #define NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE (1<<2)
163 #define NV_RAMDAC_PLL_SELECT_DLL_BYPASS (1<<4)
164 #define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_DEFAULT (0<<8)
165 #define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL (1<<8)
166 #define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL (2<<8)
167 #define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL (4<<8)
168 #define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL (7<<8)
169 /* Does this name make sense? */
170 #define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2 (1<<11)
171 #define NV_RAMDAC_PLL_SELECT_MPLL_BYPASS_FALSE (0<<12)
172 #define NV_RAMDAC_PLL_SELECT_MPLL_BYPASS_TRUE (1<<12)
173 #define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_NONE (0<<16)
174 #define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_VSCLK (1<<16)
175 #define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_PCLK (2<<16)
176 #define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_BOTH (3<<16)
178 #define NV_RAMDAC_PLL_SELECT_TVCLK_SOURCE_EXT (0<<20)
179 #define NV_RAMDAC_PLL_SELECT_TVCLK_SOURCE_VIP (1<<20)
181 #define NV_RAMDAC_PLL_SELECT_TVCLK_RATIO_DB1 (0<<24)
182 #define NV_RAMDAC_PLL_SELECT_TVCLK_RATIO_DB2 (1<<24)
183 #define NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB1 (0<<28)
184 #define NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 (1<<28)
185 #define NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB1 (0<<29)
186 #define NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2 (1<<29)
190 #define NV_RAMDAC_PLL_SETUP_CONTROL 0x510
191 #define NV_RAMDAC_PLL_TEST_COUNTER 0x514
192 #define NV_RAMDAC_PALETTE_TEST 0x518
193 #define NV_RAMDAC_VPLL2 0x520
194 #define NV_RAMDAC_SEL_CLK 0x524
195 #define NV_RAMDAC_DITHER_NV11 0x528
196 #define NV_RAMDAC_OUTPUT 0x52c
197 #define NV_RAMDAC_OUTPUT_DAC_ENABLE (1<<0)
198 #define NV_RAMDAC_OUTPUT_SELECT_CRTC1 (1<<8)
200 #define NV_RAMDAC_NVPLL_B 0x570
201 #define NV_RAMDAC_MPLL_B 0x574
202 #define NV_RAMDAC_VPLL_B 0x578
203 #define NV_RAMDAC_VPLL2_B 0x57c
205 #define NV_RAMDAC_580 0x580
206 /* This is not always activated, but only when VCLK_RATIO_DB1 is used */
207 #define NV_RAMDAC_580_VPLL1_ACTIVE (1<<8)
208 #define NV_RAMDAC_580_VPLL2_ACTIVE (1<<28)
210 #define NV_RAMDAC_594 0x594
212 #define NV_RAMDAC_GENERAL_CONTROL 0x600
213 #define NV_RAMDAC_TEST_CONTROL 0x608
214 #define NV_RAMDAC_TEST_DATA 0x610
216 /* This register is similar to TEST_CONTROL in the style of values */
217 #define NV_RAMDAC_670 0x670
219 #define NV_RAMDAC_TV_SETUP 0x700
220 #define NV_RAMDAC_TV_VBLANK_START 0x704
221 #define NV_RAMDAC_TV_VBLANK_END 0x708
222 #define NV_RAMDAC_TV_HBLANK_START 0x70c
223 #define NV_RAMDAC_TV_HBLANK_END 0x710
224 #define NV_RAMDAC_TV_BLANK_COLOR 0x714
225 #define NV_RAMDAC_TV_VTOTAL 0x720
226 #define NV_RAMDAC_TV_VSYNC_START 0x724
227 #define NV_RAMDAC_TV_VSYNC_END 0x728
228 #define NV_RAMDAC_TV_HTOTAL 0x72c
229 #define NV_RAMDAC_TV_HSYNC_START 0x730
230 #define NV_RAMDAC_TV_HSYNC_END 0x734
231 #define NV_RAMDAC_TV_SYNC_DELAY 0x738
233 #define REG_DISP_END 0
234 #define REG_DISP_TOTAL 1
235 #define REG_DISP_CRTC 2
236 #define REG_DISP_SYNC_START 3
237 #define REG_DISP_SYNC_END 4
238 #define REG_DISP_VALID_START 5
239 #define REG_DISP_VALID_END 6
241 #define NV_RAMDAC_FP_VDISP_END 0x800
242 #define NV_RAMDAC_FP_VTOTAL 0x804
243 #define NV_RAMDAC_FP_VCRTC 0x808
244 #define NV_RAMDAC_FP_VSYNC_START 0x80c
245 #define NV_RAMDAC_FP_VSYNC_END 0x810
246 #define NV_RAMDAC_FP_VVALID_START 0x814
247 #define NV_RAMDAC_FP_VVALID_END 0x818
248 #define NV_RAMDAC_FP_HDISP_END 0x820
249 #define NV_RAMDAC_FP_HTOTAL 0x824
250 #define NV_RAMDAC_FP_HCRTC 0x828
251 #define NV_RAMDAC_FP_HSYNC_START 0x82c
252 #define NV_RAMDAC_FP_HSYNC_END 0x830
253 #define NV_RAMDAC_FP_HVALID_START 0x834
254 #define NV_RAMDAC_FP_HVALID_END 0x838
256 #define NV_RAMDAC_FP_DITHER 0x83c
257 #define NV_RAMDAC_FP_CHECKSUM 0x840
258 #define NV_RAMDAC_FP_TEST_CONTROL 0x844
259 #define NV_RAMDAC_FP_CONTROL 0x848
260 # define NV_RAMDAC_FP_CONTROL_VSYNC_NEG (0 << 0)
261 # define NV_RAMDAC_FP_CONTROL_VSYNC_POS (1 << 0)
262 # define NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE (2 << 0)
263 # define NV_RAMDAC_FP_CONTROL_HSYNC_NEG (0 << 4)
264 # define NV_RAMDAC_FP_CONTROL_HSYNC_POS (1 << 4)
265 # define NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE (2 << 4)
266 # define NV_RAMDAC_FP_CONTROL_MODE_SCALE (0 << 8)
267 # define NV_RAMDAC_FP_CONTROL_MODE_CENTER (1 << 8)
268 # define NV_RAMDAC_FP_CONTROL_MODE_NATIVE (2 << 8)
270 # define NV_RAMDAC_FP_CONTROL_ENABLE (1<<28) // toggling this bit turns things on/off
272 #define NV_RAMDAC_FP_DEBUG_0 0x880
273 # define NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED (1 << 0)
274 # define NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED (1 << 4)
275 /* This doesn't seem to be essential for tmds, but still often set */
276 # define NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED (1 << 7)
277 # define NV_RAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK (1 << 28)
278 # define NV_RAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK (1 << 28)
279 # define NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL (2 << 28)
280 # define NV_RAMDAC_FP_DEBUG_0_PWRDOWN_BOTH (3 << 28)
281 #define NV_RAMDAC_FP_DEBUG_1 0x884
282 #define NV_RAMDAC_FP_DEBUG_2 0x888
283 #define NV_RAMDAC_FP_DEBUG_3 0x88C
285 #define NV_RAMDAC_FP_TMDS_CONTROL 0x8b0
286 /* 0xff - address mask */
287 #define NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE (1<<16)
288 #define NV_RAMDAC_FP_TMDS_DATA 0x8b4
289 /* 0xff - data mask */
291 /* What is the purpose of this second set? */
292 #define NV_RAMDAC_FP_TMDS_CONTROL_2 0x8b8
293 /* 0xff - address mask */
294 #define NV_RAMDAC_FP_TMDS_CONTROL_2_WRITE_DISABLE (1<<16)
295 #define NV_RAMDAC_FP_TMDS_DATA_2 0x8bc
296 /* 0xff - data mask */
298 /* Some kind of switch */
299 #define NV_RAMDAC_900 0x900
301 #define NV_RAMDAC_A20 0xA20
302 #define NV_RAMDAC_A24 0xA24
303 #define NV_RAMDAC_A34 0xA34
305 #define NV_CRTC_INTR_0 0x100
306 # define NV_CRTC_INTR_VBLANK 1
307 #define NV_CRTC_INTR_EN_0 0x140
308 #define NV_CRTC_START 0x800
309 #define NV_CRTC_CONFIG 0x804
310 #define NV_CRTC_CURSOR_CONFIG 0x810
311 #define NV_CRTC_GPIO 0x818
312 #define NV_CRTC_081C 0x81c
313 #define NV_CRTC_0830 0x830
314 #define NV_CRTC_0834 0x834
315 #define NV_CRTC_0850 0x850
316 #define NV_CRTC_FSEL 0x860
317 #define NV_CRTC_FSEL_I2C (1<<4)
318 #define NV_CRTC_FSEL_TVOUT1 (1<<8)
319 #define NV_CRTC_FSEL_TVOUT2 (2<<8)
320 #define NV_CRTC_FSEL_OVERLAY (1<<12)
321 #define NV_CRTC_FSEL_FPP2 (1<<16)
322 #define NV_CRTC_FSEL_FPP1 (2<<16)
324 #define NV_PFB_CFG0 0x200
325 #define NV_PFB_CFG1 0x204
326 #define NV_PFB_020C 0x20C
327 #define NV_PFB_TILE_NV10 0x240
328 #define NV_PFB_TILE_SIZE_NV10 0x244
329 #define NV_PFB_CLOSE_PAGE2 0x33C
330 #define NV_PFB_TILE_NV40 0x600
331 #define NV_PFB_TILE_SIZE_NV40 0x604
333 #define NV_PGRAPH_DEBUG_0 0x080
334 #define NV_PGRAPH_DEBUG_1 0x084
335 #define NV_PGRAPH_DEBUG_2_NV04 0x088
336 #define NV_PGRAPH_DEBUG_2 0x620
337 #define NV_PGRAPH_DEBUG_3 0x08c
338 #define NV_PGRAPH_DEBUG_4 0x090
340 #define NV_PGRAPH_INTR 0x100
341 #define NV_PGRAPH_INTR_EN 0x140
342 #define NV_PGRAPH_CTX_CONTROL 0x144
343 #define NV_PGRAPH_CTX_CONTROL_NV04 0x170
344 #define NV_PGRAPH_ABS_UCLIP_XMIN 0x53C
345 #define NV_PGRAPH_ABS_UCLIP_YMIN 0x540
346 #define NV_PGRAPH_ABS_UCLIP_XMAX 0x544
347 #define NV_PGRAPH_ABS_UCLIP_YMAX 0x548
348 #define NV_PGRAPH_BETA_AND 0x608
349 #define NV_PGRAPH_LIMIT_VIOL_PIX 0x610
351 #define NV_PGRAPH_BOFFSET0 0x640
352 #define NV_PGRAPH_BOFFSET1 0x644
353 #define NV_PGRAPH_BOFFSET2 0x648
355 #define NV_PGRAPH_BLIMIT0 0x684
356 #define NV_PGRAPH_BLIMIT1 0x688
357 #define NV_PGRAPH_BLIMIT2 0x68c
359 #define NV_PGRAPH_SURFACE 0x710
360 #define NV_PGRAPH_STATE 0x714
361 #define NV_PGRAPH_FIFO 0x720
363 #define NV_PGRAPH_PATTERN_SHAPE 0x810
365 #define NV_PGRAPH_TILE 0xb00
367 #define NV_PVIDEO_INTR_EN 0x140
368 #define NV_PVIDEO_BUFFER 0x700
369 #define NV_PVIDEO_STOP 0x704
370 #define NV_PVIDEO_UVPLANE_BASE(buff) (0x800+(buff)*4)
371 #define NV_PVIDEO_UVPLANE_LIMIT(buff) (0x808+(buff)*4)
372 #define NV_PVIDEO_UVPLANE_OFFSET_BUFF(buff) (0x820+(buff)*4)
373 #define NV_PVIDEO_BASE(buff) (0x900+(buff)*4)
374 #define NV_PVIDEO_LIMIT(buff) (0x908+(buff)*4)
375 #define NV_PVIDEO_LUMINANCE(buff) (0x910+(buff)*4)
376 #define NV_PVIDEO_CHROMINANCE(buff) (0x918+(buff)*4)
377 #define NV_PVIDEO_OFFSET_BUFF(buff) (0x920+(buff)*4)
378 #define NV_PVIDEO_SIZE_IN(buff) (0x928+(buff)*4)
379 #define NV_PVIDEO_POINT_IN(buff) (0x930+(buff)*4)
380 #define NV_PVIDEO_DS_DX(buff) (0x938+(buff)*4)
381 #define NV_PVIDEO_DT_DY(buff) (0x940+(buff)*4)
382 #define NV_PVIDEO_POINT_OUT(buff) (0x948+(buff)*4)
383 #define NV_PVIDEO_SIZE_OUT(buff) (0x950+(buff)*4)
384 #define NV_PVIDEO_FORMAT(buff) (0x958+(buff)*4)
385 # define NV_PVIDEO_FORMAT_PLANAR (1 << 0)
386 # define NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8 (1 << 16)
387 # define NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY (1 << 20)
388 # define NV_PVIDEO_FORMAT_MATRIX_ITURBT709 (1 << 24)
389 #define NV_PVIDEO_COLOR_KEY 0xB00
391 /* These are the real registers, not the redirected ones */
392 #define NV40_VCLK1_A 0x4010
393 #define NV40_VCLK1_B 0x4014
394 #define NV40_VCLK2_A 0x4018
395 #define NV40_VCLK2_B 0x401c