git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65
  66 static CARD8 NVReadPVIO(xf86CrtcPtr crtc, CARD32 address)
  67 {
  68         ScrnInfoPtr pScrn = crtc->scrn;
  69         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  70         NVPtr pNv = NVPTR(pScrn);
  71
  72         /* Only NV4x have two pvio ranges */
  73         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  74                 return NV_RD08(pNv->PVIO1, address);
  75         } else {
  76                 return NV_RD08(pNv->PVIO0, address);
  77         }
  78 }
  79
  80 static void NVWritePVIO(xf86CrtcPtr crtc, CARD32 address, CARD8 value)
  81 {
  82         ScrnInfoPtr pScrn = crtc->scrn;
  83         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  84         NVPtr pNv = NVPTR(pScrn);
  85
  86         /* Only NV4x have two pvio ranges */
  87         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  88                 NV_WR08(pNv->PVIO1, address, value);
  89         } else {
  90                 NV_WR08(pNv->PVIO0, address, value);
  91         }
  92 }
  93
  94 static void NVWriteMiscOut(xf86CrtcPtr crtc, CARD8 value)
  95 {
  96         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
  97 }
  98
  99 static CARD8 NVReadMiscOut(xf86CrtcPtr crtc)
 100 {
 101         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 102 }
 103
 104 void NVWriteVGA(NVPtr pNv, int head, CARD8 index, CARD8 value)
 105 {
 106         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 107
 108         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 109         NV_WR08(pCRTCReg, CRTC_DATA, value);
 110 }
 111
 112 CARD8 NVReadVGA(NVPtr pNv, int head, CARD8 index)
 113 {
 114         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 115
 116         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 117         return NV_RD08(pCRTCReg, CRTC_DATA);
 118 }
 119
 120 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
 121  * I suspect they in fact do nothing, but are merely a way to carry useful
 122  * per-head variables around
 123  *
 124  * Known uses:
 125  * CR57         CR58
 126  * 0x00         index to the appropriate dcb entry (or 7f for inactive)
 127  * 0x02         dcb entry's "or" value (or 00 for inactive)
 128  * 0x03         bit0 set for dual link (LVDS, possibly elsewhere too)
 129  * 0x08 or 0x09 pxclk in MHz
 130  * 0x0f         laptop panel info -     low nibble for PEXTDEV_BOOT strap
 131  *                                      high nibble for xlat strap value
 132  */
 133
 134 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
 135 {
 136         NVWriteVGA(pNv, head, 0x57, index);
 137         NVWriteVGA(pNv, head, 0x58, value);
 138 }
 139
 140 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
 141 {
 142         NVWriteVGA(pNv, head, 0x57, index);
 143         return NVReadVGA(pNv, head, 0x58);
 144 }
 145
 146 void NVWriteVgaCrtc(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 147 {
 148         ScrnInfoPtr pScrn = crtc->scrn;
 149         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 150         NVPtr pNv = NVPTR(pScrn);
 151
 152         NVWriteVGA(pNv, nv_crtc->head, index, value);
 153 }
 154
 155 CARD8 NVReadVgaCrtc(xf86CrtcPtr crtc, CARD8 index)
 156 {
 157         ScrnInfoPtr pScrn = crtc->scrn;
 158         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 159         NVPtr pNv = NVPTR(pScrn);
 160
 161         return NVReadVGA(pNv, nv_crtc->head, index);
 162 }
 163
 164 static void NVWriteVgaSeq(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 165 {
 166         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 167         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 168 }
 169
 170 static CARD8 NVReadVgaSeq(xf86CrtcPtr crtc, CARD8 index)
 171 {
 172         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 173         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 174 }
 175
 176 static void NVWriteVgaGr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 177 {
 178         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 179         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 180 }
 181
 182 static CARD8 NVReadVgaGr(xf86CrtcPtr crtc, CARD8 index)
 183 {
 184         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 185         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 186 }
 187
 188
 189 static void NVWriteVgaAttr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 190 {
 191   ScrnInfoPtr pScrn = crtc->scrn;
 192   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 193   NVPtr pNv = NVPTR(pScrn);
 194   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 195
 196   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 197   if (nv_crtc->paletteEnabled)
 198     index &= ~0x20;
 199   else
 200     index |= 0x20;
 201   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 202   NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 203 }
 204
 205 static CARD8 NVReadVgaAttr(xf86CrtcPtr crtc, CARD8 index)
 206 {
 207   ScrnInfoPtr pScrn = crtc->scrn;
 208   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 209   NVPtr pNv = NVPTR(pScrn);
 210   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 211
 212   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 213   if (nv_crtc->paletteEnabled)
 214     index &= ~0x20;
 215   else
 216     index |= 0x20;
 217   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 218   return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 219 }
 220
 221 void NVCrtcSetOwner(xf86CrtcPtr crtc)
 222 {
 223         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 224         ScrnInfoPtr pScrn = crtc->scrn;
 225         NVPtr pNv = NVPTR(pScrn);
 226         /* Non standard beheaviour required by NV11 */
 227         if (pNv) {
 228                 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 229                 ErrorF("pre-Owner: 0x%X\n", owner);
 230                 if (owner == 0x04) {
 231                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 232                         ErrorF("pbus84: 0x%X\n", pbus84);
 233                         pbus84 &= ~(1<<28);
 234                         ErrorF("pbus84: 0x%X\n", pbus84);
 235                         nvWriteMC(pNv, 0x1084, pbus84);
 236                 }
 237                 /* The blob never writes owner to pcio1, so should we */
 238                 if (pNv->NVArch == 0x11) {
 239                         NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
 240                 }
 241                 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->crtc * 0x3);
 242                 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 243                 ErrorF("post-Owner: 0x%X\n", owner);
 244         } else {
 245                 ErrorF("pNv pointer is NULL\n");
 246         }
 247 }
 248
 249 static void
 250 NVEnablePalette(xf86CrtcPtr crtc)
 251 {
 252   ScrnInfoPtr pScrn = crtc->scrn;
 253   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 254   NVPtr pNv = NVPTR(pScrn);
 255   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 256
 257   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 258   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 259   nv_crtc->paletteEnabled = TRUE;
 260 }
 261
 262 static void
 263 NVDisablePalette(xf86CrtcPtr crtc)
 264 {
 265   ScrnInfoPtr pScrn = crtc->scrn;
 266   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 267   NVPtr pNv = NVPTR(pScrn);
 268   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 269
 270   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 271   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 272   nv_crtc->paletteEnabled = FALSE;
 273 }
 274
 275 static void NVWriteVgaReg(xf86CrtcPtr crtc, CARD32 reg, CARD8 value)
 276 {
 277  ScrnInfoPtr pScrn = crtc->scrn;
 278   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 279   NVPtr pNv = NVPTR(pScrn);
 280   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 281
 282   NV_WR08(pCRTCReg, reg, value);
 283 }
 284
 285 /* perform a sequencer reset */
 286 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 287 {
 288   if (start)
 289     NVWriteVgaSeq(crtc, 0x00, 0x1);
 290   else
 291     NVWriteVgaSeq(crtc, 0x00, 0x3);
 292
 293 }
 294 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 295 {
 296         CARD8 tmp;
 297
 298         if (on) {
 299                 tmp = NVReadVgaSeq(crtc, 0x1);
 300                 NVVgaSeqReset(crtc, TRUE);
 301                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 302
 303                 NVEnablePalette(crtc);
 304         } else {
 305                 /*
 306                  * Reenable sequencer, then turn on screen.
 307                  */
 308                 tmp = NVReadVgaSeq(crtc, 0x1);
 309                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 310                 NVVgaSeqReset(crtc, FALSE);
 311
 312                 NVDisablePalette(crtc);
 313         }
 314 }
 315
 316 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 317 {
 318         CARD8 cr11;
 319
 320         NVCrtcSetOwner(crtc);
 321
 322         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 323         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 324         if (Lock) cr11 |= 0x80;
 325         else cr11 &= ~0x80;
 326         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 327 }
 328
 329 xf86OutputPtr
 330 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 331 {
 332         ScrnInfoPtr pScrn = crtc->scrn;
 333         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 334         int i;
 335         for (i = 0; i < xf86_config->num_output; i++) {
 336                 xf86OutputPtr output = xf86_config->output[i];
 337
 338                 if (output->crtc == crtc) {
 339                         return output;
 340                 }
 341         }
 342
 343         return NULL;
 344 }
 345
 346 xf86CrtcPtr
 347 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 348 {
 349         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 350         int i;
 351
 352         for (i = 0; i < xf86_config->num_crtc; i++) {
 353                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 354                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 355                 if (nv_crtc->crtc == index)
 356                         return crtc;
 357         }
 358
 359         return NULL;
 360 }
 361
 362 /*
 363  * Calculate the Video Clock parameters for the PLL.
 364  */
 365 static void CalcVClock (
 366         uint32_t                clockIn,
 367         uint32_t                *clockOut,
 368         CARD32          *pllOut,
 369         NVPtr           pNv
 370 )
 371 {
 372         unsigned lowM, highM, highP;
 373         unsigned DeltaNew, DeltaOld;
 374         unsigned VClk, Freq;
 375         unsigned M, N, P;
 376
 377         /* M: PLL reference frequency postscaler divider */
 378         /* P: PLL VCO output postscaler divider */
 379         /* N: PLL VCO postscaler setting */
 380
 381         DeltaOld = 0xFFFFFFFF;
 382
 383         VClk = (unsigned)clockIn;
 384
 385         /* Taken from Haiku, after someone with an NV28 had an issue */
 386         switch(pNv->NVArch) {
 387                 case 0x28:
 388                         lowM = 1;
 389                         highP = 32;
 390                         if (VClk > 340000) {
 391                                 highM = 2;
 392                         } else if (VClk > 200000) {
 393                                 highM = 4;
 394                         } else if (VClk > 150000) {
 395                                 highM = 6;
 396                         } else {
 397                                 highM = 14;
 398                         }
 399                         break;
 400                 default:
 401                         lowM = 1;
 402                         highP = 16;
 403                         if (VClk > 340000) {
 404                                 highM = 2;
 405                         } else if (VClk > 250000) {
 406                                 highM = 6;
 407                         } else {
 408                                 highM = 14;
 409                         }
 410                         break;
 411         }
 412
 413         for (P = 1; P <= highP; P++) {
 414                 Freq = VClk << P;
 415                 if ((Freq >= 128000) && (Freq <= 350000)) {
 416                         for (M = lowM; M <= highM; M++) {
 417                                 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
 418                                 if (N <= 255) {
 419                                         Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
 420                                         if (Freq > VClk) {
 421                                                 DeltaNew = Freq - VClk;
 422                                         } else {
 423                                                 DeltaNew = VClk - Freq;
 424                                         }
 425                                         if (DeltaNew < DeltaOld) {
 426                                                 *pllOut   = (P << 16) | (N << 8) | M;
 427                                                 *clockOut = Freq;
 428                                                 DeltaOld  = DeltaNew;
 429                                         }
 430                                 }
 431                         }
 432                 }
 433         }
 434 }
 435
 436 static void CalcVClock2Stage (
 437         uint32_t                clockIn,
 438         uint32_t                *clockOut,
 439         CARD32          *pllOut,
 440         CARD32          *pllBOut,
 441         NVPtr           pNv
 442 )
 443 {
 444         unsigned DeltaNew, DeltaOld;
 445         unsigned VClk, Freq;
 446         unsigned M, N, P;
 447         unsigned lowM, highM, highP;
 448
 449         DeltaOld = 0xFFFFFFFF;
 450
 451         *pllBOut = 0x80000401;  /* fixed at x4 for now */
 452
 453         VClk = (unsigned)clockIn;
 454
 455         /* Taken from Haiku, after someone with an NV28 had an issue */
 456         switch(pNv->NVArch) {
 457                 case 0x28:
 458                         lowM = 1;
 459                         highP = 32;
 460                         if (VClk > 340000) {
 461                                 highM = 2;
 462                         } else if (VClk > 200000) {
 463                                 highM = 4;
 464                         } else if (VClk > 150000) {
 465                                 highM = 6;
 466                         } else {
 467                                 highM = 14;
 468                         }
 469                         break;
 470                 default:
 471                         lowM = 1;
 472                         highP = 15;
 473                         if (VClk > 340000) {
 474                                 highM = 2;
 475                         } else if (VClk > 250000) {
 476                                 highM = 6;
 477                         } else {
 478                                 highM = 14;
 479                         }
 480                         break;
 481         }
 482
 483         for (P = 0; P <= highP; P++) {
 484                 Freq = VClk << P;
 485                 if ((Freq >= 400000) && (Freq <= 1000000)) {
 486                         for (M = lowM; M <= highM; M++) {
 487                                 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
 488                                 if ((N >= 5) && (N <= 255)) {
 489                                         Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
 490                                         if (Freq > VClk) {
 491                                                 DeltaNew = Freq - VClk;
 492                                         } else {
 493                                                 DeltaNew = VClk - Freq;
 494                                         }
 495                                         if (DeltaNew < DeltaOld) {
 496                                                 *pllOut   = (P << 16) | (N << 8) | M;
 497                                                 *clockOut = Freq;
 498                                                 DeltaOld  = DeltaNew;
 499                                         }
 500                                 }
 501                         }
 502                 }
 503         }
 504 }
 505
 506 /* Code taken from NVClock, with permission of the author (being a GPL->MIT code transfer). */
 507
 508 static void
 509 CalculateVClkNV4x_SingleVCO(NVPtr pNv, bios_t *bios, uint32_t clockIn, uint32_t *n1_best, uint32_t *m1_best, uint32_t *p_best)
 510 {
 511         uint32_t clock, M, N, P;
 512         uint32_t delta, bestDelta, minM, maxM, minN, maxN, maxP;
 513         uint32_t minVCOInputFreq, minVCOFreq, maxVCOFreq;
 514         uint32_t VCOFreq;
 515         uint32_t refClk = pNv->CrystalFreqKHz;
 516         bestDelta = clockIn;
 517
 518         /* bios clocks are in MHz, we use KHz */
 519         minVCOInputFreq = bios->pll.vco1.min_inputfreq*1000;
 520         minVCOFreq = bios->pll.vco1.minfreq*1000;
 521         maxVCOFreq = bios->pll.vco1.maxfreq*1000;
 522         minM = bios->pll.vco1.min_m;
 523         maxM = bios->pll.vco1.max_m;
 524         minN = bios->pll.vco1.min_n;
 525         maxN = bios->pll.vco1.max_n;
 526
 527         maxP = 6;
 528
 529         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 530         /  Choose a post divider in such a way to achieve this.
 531         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 532         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 533         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 534         /  some rare corner cases.
 535         */
 536         for (P=0, VCOFreq=maxVCOFreq/2; clockIn<=VCOFreq && P <= maxP; P++)
 537         {
 538                 VCOFreq /= 2;
 539         }
 540
 541         /* Calculate the m and n values. There are a lot of values which give the same speed;
 542         /  We choose the speed for which the difference with the request speed is as small as possible.
 543         */
 544         for (M=minM; M<=maxM; M++)
 545         {
 546                 /* The VCO has a minimum input frequency */
 547                 if ((refClk/M) < minVCOInputFreq)
 548                         break;
 549
 550                 for (N=minN; N<=maxN; N++)
 551                 {
 552                         /* Calculate the frequency generated by VCO1 */
 553                         clock = (int)(refClk * N / (float)M);
 554
 555                         /* Verify if the clock lies within the output limits of VCO1 */
 556                         if (clock < minVCOFreq)
 557                                 continue;
 558                         else if (clock > maxVCOFreq) /* It is no use to continue as the clock will only become higher */
 559                                 break;
 560
 561                         clock >>= P;
 562                         delta = abs((int)(clockIn - clock));
 563                         /* When the difference is 0 or less than .5% accept the speed */
 564                         if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 565                         {
 566                                 *m1_best = M;
 567                                 *n1_best = N;
 568                                 *p_best = P;
 569                                 return;
 570                         }
 571
 572                         /* When the new difference is smaller than the old one, use this one */
 573                         if (delta < bestDelta)
 574                         {
 575                                 bestDelta = delta;
 576                                 *m1_best = M;
 577                                 *n1_best = N;
 578                                 *p_best = P;
 579                         }
 580                 }
 581         }
 582 }
 583
 584 static void
 585 CalculateVClkNV4x_DoubleVCO(NVPtr pNv, bios_t *bios, uint32_t clockIn, uint32_t *n1_best, uint32_t *n2_best, uint32_t *m1_best, uint32_t *m2_best, uint32_t *p_best)
 586 {
 587         uint32_t clock1, clock2, M, M2, N, N2, P;
 588         uint32_t delta, bestDelta, minM, minM2, maxM, maxM2, minN, minN2, maxN, maxN2, maxP;
 589         uint32_t minVCOInputFreq, minVCO2InputFreq, maxVCO2InputFreq, minVCOFreq, minVCO2Freq, maxVCOFreq, maxVCO2Freq;
 590         uint32_t VCO2Freq, maxClock;
 591         uint32_t refClk = pNv->CrystalFreqKHz;
 592         bestDelta = clockIn;
 593
 594         /* bios clocks are in MHz, we use KHz */
 595         minVCOInputFreq = bios->pll.vco1.min_inputfreq*1000;
 596         minVCOFreq = bios->pll.vco1.minfreq*1000;
 597         maxVCOFreq = bios->pll.vco1.maxfreq*1000;
 598         minM = bios->pll.vco1.min_m;
 599         maxM = bios->pll.vco1.max_m;
 600         minN = bios->pll.vco1.min_n;
 601         maxN = bios->pll.vco1.max_n;
 602
 603         minVCO2InputFreq = bios->pll.vco2.min_inputfreq*1000;
 604         maxVCO2InputFreq = bios->pll.vco2.max_inputfreq*1000;
 605         minVCO2Freq = bios->pll.vco2.minfreq*1000;
 606         maxVCO2Freq = bios->pll.vco2.maxfreq*1000;
 607         minM2 = bios->pll.vco2.min_m;
 608         maxM2 = bios->pll.vco2.max_m;
 609         minN2 = bios->pll.vco2.min_n;
 610         maxN2 = bios->pll.vco2.max_n;
 611
 612         maxP = 6;
 613
 614         maxClock = maxVCO2Freq;
 615         /* If the requested clock is behind the bios limits, try it anyway */
 616         if (clockIn > maxVCO2Freq)
 617                 maxClock = clockIn + clockIn/200; /* Add a .5% margin */
 618
 619         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 620         /  Choose a post divider in such a way to achieve this.
 621         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 622         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 623         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 624         /  some rare corner cases.
 625         */
 626         for (P=0, VCO2Freq=maxClock/2; clockIn<=VCO2Freq && P <= maxP; P++)
 627         {
 628                 VCO2Freq /= 2;
 629         }
 630
 631         /* The PLLs on Geforce6/7 hardware can operate in a single stage made with only 1 VCO
 632         /  and a cascade mode of two VCOs. This second mode is in general used for relatively high
 633         /  frequencies. The loop below calculates the divider and multiplier ratios for the cascade
 634         /  mode. The code takes into account limits defined in the video bios.
 635         */
 636         for (M=minM; M<=maxM; M++)
 637         {
 638                 /* The VCO has a minimum input frequency */
 639                 if ((refClk/M) < minVCOInputFreq)
 640                         break;
 641
 642                 for (N=minN; N<=maxN; N++)
 643                 {
 644                         /* Calculate the frequency generated by VCO1 */
 645                         clock1 = (int)(refClk * N / (float)M);
 646                         /* Verify if the clock lies within the output limits of VCO1 */
 647                         if ( (clock1 < minVCOFreq) )
 648                                 continue;
 649                         else if (clock1 > maxVCOFreq) /* For future N, the clock will only increase so stop; xorg nv continues but that is useless */
 650                                 break;
 651
 652                         for (M2=minM2; M2<=maxM2; M2++)
 653                         {
 654                                 /* The clock fed to the second VCO needs to lie within a certain input range */
 655                                 if (clock1 / M2 < minVCO2InputFreq)
 656                                         break;
 657                                 else if (clock1 / M2 > maxVCO2InputFreq)
 658                                         continue;
 659
 660                                 N2 = (int)((float)((clockIn << P) * M * M2) / (float)(refClk * N)+.5);
 661                                 if( (N2 < minN2) || (N2 > maxN2) )
 662                                         continue;
 663
 664                                 /* The clock before being fed to the post-divider needs to lie within a certain range.
 665                                 /  Further there are some limits on N2/M2.
 666                                 */
 667                                 clock2 = (int)((float)(N*N2)/(M*M2) * refClk);
 668                                 if( (clock2 < minVCO2Freq) || (clock2 > maxClock))// || ((N2 / M2) < 4) || ((N2 / M2) > 10) )
 669                                         continue;
 670
 671                                 /* The post-divider delays the 'high' clock to create a low clock if requested.
 672                                 /  This post-divider exists because the VCOs can only generate frequencies within
 673                                 /  a limited frequency range. This range has been tuned to lie around half of its max
 674                                 /  input frequency. It tries to calculate all clocks (including lower ones) around this
 675                                 /  'center' frequency.
 676                                 */
 677                                 clock2 >>= P;
 678                                 delta = abs((int)(clockIn - clock2));
 679
 680                                 /* When the difference is 0 or less than .5% accept the speed */
 681                                 if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 682                                 {
 683                                         *m1_best = M;
 684                                         *m2_best = M2;
 685                                         *n1_best = N;
 686                                         *n2_best = N2;
 687                                         *p_best = P;
 688                                         return;
 689                                 }
 690
 691                                 /* When the new difference is smaller than the old one, use this one */
 692                                 if (delta < bestDelta)
 693                                 {
 694                                         bestDelta = delta;
 695                                         *m1_best = M;
 696                                         *m2_best = M2;
 697                                         *n1_best = N;
 698                                         *n2_best = N2;
 699                                         *p_best = P;
 700                                 }
 701                         }
 702                 }
 703         }
 704 }
 705
 706 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
 707
 708 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 709 /* They are only valid for NV4x, appearantly reordered for NV5x */
 710 /* gpu pll: 0x4000 + 0x4004
 711  * unknown pll: 0x4008 + 0x400c
 712  * vpll1: 0x4010 + 0x4014
 713  * vpll2: 0x4018 + 0x401c
 714  * unknown pll: 0x4020 + 0x4024
 715  * unknown pll: 0x4038 + 0x403c
 716  * Some of the unknown's are probably memory pll's.
 717  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 718  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 719  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 720  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 721  *     bit8: A switch that turns of the second divider and multiplier off.
 722  *     bit12: Also a switch, i haven't seen it yet.
 723  *     bit16-19: p-divider
 724  *     but 28-31: Something related to the mode that is used (see bit8).
 725  * 2) bit0-7: m-divider (a)
 726  *     bit8-15: n-multiplier (a)
 727  *     bit16-23: m-divider (b)
 728  *     bit24-31: n-multiplier (b)
 729  */
 730
 731 /* Modifying the gpu pll for example requires:
 732  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 733  * This is not needed for the vpll's which have their own bits.
 734  */
 735
 736 static void
 737 CalculateVClkNV4x(
 738         NVPtr pNv,
 739         uint32_t requested_clock,
 740         uint32_t *given_clock,
 741         uint32_t *pll_a,
 742         uint32_t *pll_b,
 743         uint32_t *reg580,
 744         Bool    *db1_ratio,
 745         Bool primary
 746 )
 747 {
 748         /* We have 2 mulitpliers, 2 dividers and one post divider */
 749         /* Note that p is only 3 bits */
 750         uint32_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
 751         uint32_t special_bits = 0;
 752
 753         bios_t *bios = &pNv->VBIOS;
 754
 755         if (!bios->pll.version) { /* load some reasonable defaults */
 756                 bios->pll.vco1.minfreq = 100;
 757                 bios->pll.vco1.maxfreq = 410;
 758                 bios->pll.vco2.minfreq = 400;
 759                 bios->pll.vco2.maxfreq = 1000;
 760
 761                 /* What input frequencies do they accept (past the m-divider)? */
 762                 bios->pll.vco1.min_inputfreq = 3;
 763                 bios->pll.vco1.max_inputfreq = 25;
 764                 bios->pll.vco2.min_inputfreq = 35;
 765                 bios->pll.vco2.max_inputfreq = 100;
 766
 767                 /* What values are accepted as multiplier and divider? */
 768                 bios->pll.vco1.min_n = 1;
 769                 bios->pll.vco1.max_n = 255;
 770                 bios->pll.vco1.min_m = 1;
 771                 bios->pll.vco1.max_m = 255;
 772                 bios->pll.vco2.min_n = 1;
 773                 bios->pll.vco2.max_n = 31;
 774                 bios->pll.vco2.min_m = 1;
 775                 bios->pll.vco2.max_m = 31;
 776         }
 777
 778         if (requested_clock < bios->pll.vco1.maxfreq*1000) { /* single VCO */
 779                 *db1_ratio = TRUE;
 780                 /* Turn the second set of divider and multiplier off */
 781                 /* Bogus data, the same nvidia uses */
 782                 n2_best = 1;
 783                 m2_best = 31;
 784                 CalculateVClkNV4x_SingleVCO(pNv, bios, requested_clock, &n1_best, &m1_best, &p_best);
 785         } else { /* dual VCO */
 786                 *db1_ratio = FALSE;
 787                 CalculateVClkNV4x_DoubleVCO(pNv, bios, requested_clock, &n1_best, &n2_best, &m1_best, &m2_best, &p_best);
 788         }
 789
 790         /* Are this all (relevant) G70 cards? */
 791         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 792                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 793                 if (*db1_ratio) {
 794                         special_bits = 0x1;
 795                 } else {
 796                         special_bits = 0x3;
 797                 }
 798         }
 799
 800         /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 801         /* Let's keep the special bits, if the bios already set them */
 802         *pll_a = (special_bits << 30) | (p_best << 16) | (n1_best << 8) | (m1_best << 0);
 803         *pll_b = (1 << 31) | (n2_best << 8) | (m2_best << 0);
 804
 805         if (*db1_ratio) {
 806                 if (primary) {
 807                         *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 808                 } else {
 809                         *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 810                 }
 811         } else {
 812                 if (primary) {
 813                         *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 814                 } else {
 815                         *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 816                 }
 817         }
 818
 819         if (*db1_ratio) {
 820                 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", n1_best, m1_best, p_best, *db1_ratio);
 821         } else {
 822                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
 823         }
 824 }
 825
 826 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 827 {
 828         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 829         state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 830         state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 831         state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 832         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 833         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 834         state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
 835         state->reg594 = nvReadRAMDAC0(pNv, NV_RAMDAC_594);
 836 }
 837
 838 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 839 {
 840         ScrnInfoPtr pScrn = crtc->scrn;
 841         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 842         NVPtr pNv = NVPTR(pScrn);
 843         CARD32 fp_debug_0[2];
 844         uint32_t index[2];
 845         fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 846         fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 847
 848         uint32_t reg_c040_old = nvReadMC(pNv, 0xc040);
 849
 850         /* The TMDS_PLL switch is on the actual ramdac */
 851         if (state->crosswired) {
 852                 index[0] = 1;
 853                 index[1] = 0;
 854                 ErrorF("Crosswired pll state load\n");
 855         } else {
 856                 index[0] = 0;
 857                 index[1] = 1;
 858         }
 859
 860         if (state->vpll2_b) {
 861                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 862                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 863
 864                 /* Wait for the situation to stabilise */
 865                 usleep(5000);
 866
 867                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 868                 /* for vpll2 change bits 18 and 19 are disabled */
 869                 reg_c040 &= ~(0x3 << 18);
 870                 nvWriteMC(pNv, 0xc040, reg_c040);
 871
 872                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 873                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 874
 875                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 876                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 877
 878                 ErrorF("writing pllsel %08X\n", state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 879                 /* Let's keep the primary vpll off */
 880                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 881
 882                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 883                 ErrorF("writing reg580 %08X\n", state->reg580);
 884
 885                 /* We need to wait a while */
 886                 usleep(5000);
 887                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 888
 889                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 890
 891                 /* Wait for the situation to stabilise */
 892                 usleep(5000);
 893         }
 894
 895         if (state->vpll1_b) {
 896                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 897                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 898
 899                 /* Wait for the situation to stabilise */
 900                 usleep(5000);
 901
 902                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 903                 /* for vpll2 change bits 16 and 17 are disabled */
 904                 reg_c040 &= ~(0x3 << 16);
 905                 nvWriteMC(pNv, 0xc040, reg_c040);
 906
 907                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 908                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 909
 910                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 911                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 912
 913                 ErrorF("writing pllsel %08X\n", state->pllsel);
 914                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 915
 916                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 917                 ErrorF("writing reg580 %08X\n", state->reg580);
 918
 919                 /* We need to wait a while */
 920                 usleep(5000);
 921                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 922
 923                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 924
 925                 /* Wait for the situation to stabilise */
 926                 usleep(5000);
 927         }
 928
 929         /* Let's be sure not to wake up any crtc's from dpms. */
 930         /* But we do want to keep our newly set crtc awake. */
 931         if (nv_crtc->head == 1) {
 932                 nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << 18)));
 933         } else {
 934                 nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << 16)));
 935         }
 936
 937         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 938         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 939
 940         ErrorF("writing reg594 %08X\n", state->reg594);
 941         nvWriteRAMDAC0(pNv, NV_RAMDAC_594, state->reg594);
 942 }
 943
 944 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 945 {
 946         state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 947         if(pNv->twoHeads) {
 948                 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 949         }
 950         if(pNv->twoStagePLL) {
 951                 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 952                 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 953         }
 954         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 955         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 956 }
 957
 958
 959 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 960 {
 961         if (state->vpll2) {
 962                 if(pNv->twoHeads) {
 963                         ErrorF("writing vpll2 %08X\n", state->vpll2);
 964                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
 965                 }
 966                 if(pNv->twoStagePLL) {
 967                         ErrorF("writing vpll2B %08X\n", state->vpll2B);
 968                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
 969                 }
 970
 971                 ErrorF("writing pllsel %08X\n", state->pllsel);
 972                 /* Let's keep the primary vpll off */
 973                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 974         }
 975
 976         if (state->vpll) {
 977                 ErrorF("writing vpll %08X\n", state->vpll);
 978                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
 979                 if(pNv->twoStagePLL) {
 980                         ErrorF("writing vpllB %08X\n", state->vpllB);
 981                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
 982                 }
 983
 984                 ErrorF("writing pllsel %08X\n", state->pllsel);
 985                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 986         }
 987
 988         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 989         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 990 }
 991
 992 /* It is unknown if the bus has a similar meaning on pre-NV40 hardware. */
 993 /* This code is currently used and pending removal should it turn out not be needed.*/
 994
 995 static uint8_t
 996 nv_get_sel_clk_offset(uint8_t NVArch, uint8_t bus)
 997 {
 998         switch(bus) {
 999                 case 0:
1000                         if (NVArch >= 0x44) {
1001                                 return 8;
1002                         } else {
1003                                 return 12;
1004                         }
1005                 case 1:
1006                         return 16;
1007                 case 2: /* bus 2 or 3 are either dvi on mobile or tv-out */
1008                 case 3: /* don't use this for tv-out */
1009                         return 4;
1010                 default:
1011                         ErrorF("Unknown bus, bad things may happen\n");
1012                         return 16;
1013         }
1014 }
1015
1016 static void
1017 nv_wipe_other_clocks(uint32_t *sel_clk, uint8_t NVArch, uint8_t head, uint8_t bus)
1018 {
1019         int i;
1020         /* head0 = 1, head1 = 4 */
1021         uint8_t our_clock = 1 + head*3;
1022
1023         if (!sel_clk)
1024                 return;
1025
1026         for (i = 0; i < 5; i++) {
1027                 int offset = i*4;
1028                 if (nv_get_sel_clk_offset(NVArch, bus) == offset) /* Let's keep our own clock */
1029                         continue;
1030
1031                 if (((*sel_clk << offset) & 0xf) == (our_clock << offset)) /* Let's wipe other entries */
1032                         *sel_clk &= ~(0xf << offset);
1033         }
1034 }
1035
1036 #define IS_NV44P (pNv->NVArch >= 0x44 ? 1 : 0)
1037 #define SEL_CLK_OFFSET (nv_get_sel_clk_offset(pNv->NVArch, nv_output->bus))
1038
1039 #define WIPE_OTHER_CLOCKS(_sel_clk, _head, _bus) (nv_wipe_other_clocks(_sel_clk, pNv->NVArch, _head, _bus))
1040
1041 /*
1042  * Calculate extended mode parameters (SVGA) and save in a
1043  * mode state structure.
1044  * State is not specific to a single crtc, but shared.
1045  */
1046 void nv_crtc_calc_state_ext(
1047         xf86CrtcPtr     crtc,
1048         int                     bpp,
1049         int                     DisplayWidth, /* Does this change after setting the mode? */
1050         int                     CrtcHDisplay,
1051         int                     CrtcVDisplay,
1052         int                     dotClock,
1053         int                     flags
1054 )
1055 {
1056         ScrnInfoPtr pScrn = crtc->scrn;
1057         uint32_t pixelDepth, VClk = 0;
1058         CARD32 CursorStart;
1059         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1060         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1061         NVCrtcRegPtr regp;
1062         NVPtr pNv = NVPTR(pScrn);
1063         RIVA_HW_STATE *state;
1064         int num_crtc_enabled, i;
1065
1066         state = &pNv->ModeReg;
1067
1068         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1069
1070         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1071         NVOutputPrivatePtr nv_output = NULL;
1072         if (output) {
1073                 nv_output = output->driver_private;
1074         }
1075
1076         /*
1077          * Extended RIVA registers.
1078          */
1079         pixelDepth = (bpp + 1)/8;
1080         if (pNv->Architecture == NV_ARCH_40) {
1081                 /* Does register 0x580 already have a value? */
1082                 if (!state->reg580) {
1083                         state->reg580 = pNv->misc_info.ramdac_0_reg_580;
1084                 }
1085                 if (nv_crtc->head == 1) {
1086                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE);
1087                 } else {
1088                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE);
1089                 }
1090         } else if (pNv->twoStagePLL) {
1091                 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
1092         } else {
1093                 CalcVClock(dotClock, &VClk, &state->pll, pNv);
1094         }
1095
1096         switch (pNv->Architecture) {
1097         case NV_ARCH_04:
1098                 nv4UpdateArbitrationSettings(VClk,
1099                                                 pixelDepth * 8,
1100                                                 &(state->arbitration0),
1101                                                 &(state->arbitration1),
1102                                                 pNv);
1103                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
1104                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
1105                 if (flags & V_DBLSCAN)
1106                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
1107                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
1108                 state->pllsel   |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
1109                 state->config   = 0x00001114;
1110                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
1111                 break;
1112         case NV_ARCH_10:
1113         case NV_ARCH_20:
1114         case NV_ARCH_30:
1115         default:
1116                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
1117                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
1118                         state->arbitration0 = 128;
1119                         state->arbitration1 = 0x0480;
1120                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
1121                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
1122                         nForceUpdateArbitrationSettings(VClk,
1123                                                 pixelDepth * 8,
1124                                                 &(state->arbitration0),
1125                                                 &(state->arbitration1),
1126                                                 pNv);
1127                 } else if (pNv->Architecture < NV_ARCH_30) {
1128                         nv10UpdateArbitrationSettings(VClk,
1129                                                 pixelDepth * 8,
1130                                                 &(state->arbitration0),
1131                                                 &(state->arbitration1),
1132                                                 pNv);
1133                 } else {
1134                         nv30UpdateArbitrationSettings(pNv,
1135                                                 &(state->arbitration0),
1136                                                 &(state->arbitration1));
1137                 }
1138
1139                 if (nv_crtc->head == 1) {
1140                         CursorStart = pNv->Cursor2->offset;
1141                 } else {
1142                         CursorStart = pNv->Cursor->offset;
1143                 }
1144
1145                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
1146                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
1147                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
1148
1149                 if (flags & V_DBLSCAN)
1150                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
1151
1152                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
1153                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
1154                 break;
1155         }
1156
1157         /* okay do we have 2 CRTCs running ? */
1158         num_crtc_enabled = 0;
1159         for (i = 0; i < xf86_config->num_crtc; i++) {
1160                 if (xf86_config->crtc[i]->enabled) {
1161                         num_crtc_enabled++;
1162                 }
1163         }
1164
1165         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
1166
1167         if (pNv->Architecture < NV_ARCH_40) {
1168                 /* We need this before the next code */
1169                 if (nv_crtc->head == 1) {
1170                         state->vpll2 = state->pll;
1171                         state->vpll2B = state->pllB;
1172                 } else {
1173                         state->vpll = state->pll;
1174                         state->vpllB = state->pllB;
1175                 }
1176         }
1177
1178         /* This stuff also applies to NV3x to some extend, but the rules may be different. */
1179         if (pNv->Architecture == NV_ARCH_40) {
1180                 /* This register is only used on the primary ramdac */
1181                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
1182
1183                 if (!state->sel_clk)
1184                         state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
1185
1186                 /* Note: Lower bits also exist, but trying to mess with those (in advance) is a bad idea.
1187                  * The blob doesn't do it, so it's probably not needed.
1188                  * I hope this solves the previous mess.
1189                  */
1190
1191                 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1192                         /* Only wipe when are a relevant (digital) output. */
1193                         state->sel_clk &= ~(0xf << 16);
1194                         Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1195                         /* Even with two dvi, this should not conflict. */
1196                         if (crossed_clocks) {
1197                                 state->sel_clk |= (0x1 << 16);
1198                         } else {
1199                                 state->sel_clk |= (0x4 << 16);
1200                         }
1201                 }
1202
1203                 /* Some cards, specifically dual dvi/lvds cards set another bitrange.
1204                  * I suspect inverse beheaviour to the normal bitrange, but i am not a 100% certain about this.
1205                  * This is all based on default settings found in mmio-traces.
1206                  * The blob never changes these, as it doesn't run unusual output configurations.
1207                  * It seems to prefer situations that avoid changing these bits (for a good reason?).
1208                  * I still don't know the purpose of value 2, it's similar to 4, but what exactly does it do?
1209                  */
1210                 for (i = 0; i < 4; i++) {
1211                         if (state->sel_clk & (0xf << 4*i)) {
1212                                 state->sel_clk &= ~(0xf << 4*i);
1213                                 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1214                                 if (crossed_clocks) {
1215                                         state->sel_clk |= (0x4 << 4*i);
1216                                 } else {
1217                                         state->sel_clk |= (0x1 << 4*i);
1218                                 }
1219                                 break; /* This should only occur once. */
1220                         }
1221                 }
1222
1223                 /* Are we crosswired? */
1224                 if (output && nv_crtc->head != nv_output->preferred_output) {
1225                         state->crosswired = TRUE;
1226                 } else {
1227                         state->crosswired = FALSE;
1228                 }
1229
1230                 if (nv_crtc->head == 1) {
1231                         if (state->db1_ratio[1])
1232                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1233                 } else if (nv_crtc->head == 0) {
1234                         if (state->db1_ratio[0])
1235                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1236                 }
1237         } else {
1238                 /* This seems true for nv34 */
1239                 state->sel_clk = 0x0;
1240                 state->crosswired = FALSE;
1241         }
1242
1243         if (nv_crtc->head == 1) {
1244                 if (!state->db1_ratio[1]) {
1245                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1246                 } else {
1247                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1248                 }
1249                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1250         } else {
1251                 /* The NV40 seems to have more similarities to NV3x than other cards. */
1252                 if (pNv->NVArch < 0x41)
1253                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
1254                 else
1255                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1256                 if (!state->db1_ratio[0]) {
1257                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1258                 } else {
1259                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1260                 }
1261         }
1262
1263         /* The blob uses this always, so let's do the same */
1264         if (pNv->Architecture == NV_ARCH_40) {
1265                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1266         }
1267
1268         /* The primary output doesn't seem to care */
1269         if (nv_output->preferred_output == 1) { /* This is the "output" */
1270                 /* non-zero values are for analog, don't know about tv-out and the likes */
1271                 if (output && nv_output->type != OUTPUT_ANALOG) {
1272                         state->reg594 = 0x0;
1273                 } else {
1274                         /* Are we a flexible output? */
1275                         if (ffs(pNv->dcb_table.entry[nv_output->dcb_entry].or) & OUTPUT_0) {
1276                                 state->reg594 = 0x1;
1277                                 pNv->restricted_mode = FALSE;
1278                         } else {
1279                                 state->reg594 = 0x0;
1280                                 pNv->restricted_mode = TRUE;
1281                         }
1282
1283                         /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1284                         /* bit 16-19 are bits that are set on some G70 cards */
1285                         /* Those bits are also set to the 3rd OUTPUT register */
1286                         if (nv_crtc->head == 1) {
1287                                 state->reg594 |= 0x100;
1288                         }
1289                 }
1290         }
1291
1292         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1293         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1294         if (pNv->Architecture >= NV_ARCH_30) {
1295                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1296         }
1297
1298         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1299         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1300 }
1301
1302 static void
1303 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1304 {
1305         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1306         ScrnInfoPtr pScrn = crtc->scrn;
1307         NVPtr pNv = NVPTR(pScrn);
1308         unsigned char seq1 = 0, crtc17 = 0;
1309         unsigned char crtc1A;
1310
1311         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
1312
1313         NVCrtcSetOwner(crtc);
1314
1315         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1316         switch(mode) {
1317                 case DPMSModeStandby:
1318                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1319                 seq1 = 0x20;
1320                 crtc17 = 0x80;
1321                 crtc1A |= 0x80;
1322                 break;
1323         case DPMSModeSuspend:
1324                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1325                 seq1 = 0x20;
1326                 crtc17 = 0x80;
1327                 crtc1A |= 0x40;
1328                 break;
1329         case DPMSModeOff:
1330                 /* Screen: Off; HSync: Off, VSync: Off */
1331                 seq1 = 0x20;
1332                 crtc17 = 0x00;
1333                 crtc1A |= 0xC0;
1334                 break;
1335         case DPMSModeOn:
1336         default:
1337                 /* Screen: On; HSync: On, VSync: On */
1338                 seq1 = 0x00;
1339                 crtc17 = 0x80;
1340                 break;
1341         }
1342
1343         NVVgaSeqReset(crtc, TRUE);
1344         /* Each head has it's own sequencer, so we can turn it off when we want */
1345         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1346         NVWriteVgaSeq(crtc, 0x1, seq1);
1347         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1348         usleep(10000);
1349         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1350         NVVgaSeqReset(crtc, FALSE);
1351
1352         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1353
1354         /* We can completely disable a vpll if the crtc is off. */
1355         if (pNv->Architecture == NV_ARCH_40) {
1356                 uint32_t reg_c040_old = nvReadMC(pNv, 0xc040);
1357                 if (mode == DPMSModeOn) {
1358                         nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << (16 + 2*nv_crtc->head))));
1359                 } else {
1360                         nvWriteMC(pNv, 0xc040, reg_c040_old & ~(pNv->misc_info.reg_c040 & (0x3 << (16 + 2*nv_crtc->head))));
1361                 }
1362         }
1363
1364         /* I hope this is the right place */
1365         if (crtc->enabled && mode == DPMSModeOn) {
1366                 pNv->crtc_active[nv_crtc->head] = TRUE;
1367         } else {
1368                 pNv->crtc_active[nv_crtc->head] = FALSE;
1369         }
1370 }
1371
1372 static Bool
1373 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1374                      DisplayModePtr adjusted_mode)
1375 {
1376         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1377         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->crtc);
1378
1379         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1380         NVOutputPrivatePtr nv_output = NULL;
1381         if (output) {
1382                 nv_output = output->driver_private;
1383         }
1384
1385         /* For internal panels and gpu scaling on DVI we need the native mode */
1386         if (output && (nv_output->type == OUTPUT_LVDS || (nv_output->type == OUTPUT_TMDS && nv_output->scaling_mode != SCALE_PANEL))) {
1387                 adjusted_mode->HDisplay = nv_output->native_mode->HDisplay;
1388                 adjusted_mode->HSkew = nv_output->native_mode->HSkew;
1389                 adjusted_mode->HSyncStart = nv_output->native_mode->HSyncStart;
1390                 adjusted_mode->HSyncEnd = nv_output->native_mode->HSyncEnd;
1391                 adjusted_mode->HTotal = nv_output->native_mode->HTotal;
1392                 adjusted_mode->VDisplay = nv_output->native_mode->VDisplay;
1393                 adjusted_mode->VScan = nv_output->native_mode->VScan;
1394                 adjusted_mode->VSyncStart = nv_output->native_mode->VSyncStart;
1395                 adjusted_mode->VSyncEnd = nv_output->native_mode->VSyncEnd;
1396                 adjusted_mode->VTotal = nv_output->native_mode->VTotal;
1397                 adjusted_mode->Clock = nv_output->native_mode->Clock;
1398
1399                 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
1400         }
1401
1402         return TRUE;
1403 }
1404
1405 static void
1406 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1407 {
1408         ScrnInfoPtr pScrn = crtc->scrn;
1409         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1410         NVCrtcRegPtr regp;
1411         NVPtr pNv = NVPTR(pScrn);
1412         NVFBLayout *pLayout = &pNv->CurrentLayout;
1413         int depth = pScrn->depth;
1414
1415         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1416
1417         /* Calculate our timings */
1418         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1419         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1420         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1421         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1422         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1423         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1424         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1425         int vertStart           = mode->CrtcVSyncStart          - 1;
1426         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1427         int vertTotal           = mode->CrtcVTotal                      - 2;
1428         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1429         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1430
1431         Bool is_fp = FALSE;
1432
1433         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1434         NVOutputPrivatePtr nv_output = NULL;
1435         if (output) {
1436                 nv_output = output->driver_private;
1437
1438                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1439                         is_fp = TRUE;
1440         }
1441
1442         ErrorF("Mode clock: %d\n", mode->Clock);
1443         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1444
1445         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1446         if (is_fp) {
1447                 vertStart = vertTotal - 3;
1448                 vertEnd = vertTotal - 2;
1449                 vertBlankStart = vertStart;
1450                 horizStart = horizTotal - 5;
1451                 horizEnd = horizTotal - 2;
1452                 horizBlankEnd = horizTotal + 4;
1453                 if (pNv->overlayAdaptor) {
1454                         /* This reportedly works around Xv some overlay bandwidth problems*/
1455                         horizTotal += 2;
1456                 }
1457         }
1458
1459         if(mode->Flags & V_INTERLACE)
1460                 vertTotal |= 1;
1461
1462         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1463         ErrorF("horizStart: 0x%X \n", horizStart);
1464         ErrorF("horizEnd: 0x%X \n", horizEnd);
1465         ErrorF("horizTotal: 0x%X \n", horizTotal);
1466         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1467         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1468         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1469         ErrorF("vertStart: 0x%X \n", vertStart);
1470         ErrorF("vertEnd: 0x%X \n", vertEnd);
1471         ErrorF("vertTotal: 0x%X \n", vertTotal);
1472         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1473         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1474
1475         /*
1476         * compute correct Hsync & Vsync polarity
1477         */
1478         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1479                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1480
1481                 regp->MiscOutReg = 0x23;
1482                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1483                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1484         } else {
1485                 int VDisplay = mode->VDisplay;
1486                 if (mode->Flags & V_DBLSCAN)
1487                         VDisplay *= 2;
1488                 if (mode->VScan > 1)
1489                         VDisplay *= mode->VScan;
1490                 if (VDisplay < 400) {
1491                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1492                 } else if (VDisplay < 480) {
1493                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1494                 } else if (VDisplay < 768) {
1495                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1496                 } else {
1497                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1498                 }
1499         }
1500
1501         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1502
1503         /*
1504         * Time Sequencer
1505         */
1506         if (depth == 4) {
1507                 regp->Sequencer[0] = 0x02;
1508         } else {
1509                 regp->Sequencer[0] = 0x00;
1510         }
1511         /* 0x20 disables the sequencer */
1512         if (mode->Flags & V_CLKDIV2) {
1513                 regp->Sequencer[1] = 0x29;
1514         } else {
1515                 regp->Sequencer[1] = 0x21;
1516         }
1517         if (depth == 1) {
1518                 regp->Sequencer[2] = 1 << BIT_PLANE;
1519         } else {
1520                 regp->Sequencer[2] = 0x0F;
1521                 regp->Sequencer[3] = 0x00;                     /* Font select */
1522         }
1523         if (depth < 8) {
1524                 regp->Sequencer[4] = 0x06;                             /* Misc */
1525         } else {
1526                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1527         }
1528
1529         /*
1530         * CRTC Controller
1531         */
1532         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1533         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1534         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1535         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1536                                 | SetBit(7);
1537         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1538         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1539                                 | SetBitField(horizEnd,4:0,4:0);
1540         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1541         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1542                                 | SetBitField(vertDisplay,8:8,1:1)
1543                                 | SetBitField(vertStart,8:8,2:2)
1544                                 | SetBitField(vertBlankStart,8:8,3:3)
1545                                 | SetBit(4)
1546                                 | SetBitField(vertTotal,9:9,5:5)
1547                                 | SetBitField(vertDisplay,9:9,6:6)
1548                                 | SetBitField(vertStart,9:9,7:7);
1549         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
1550         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1551                                 | SetBit(6)
1552                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1553         regp->CRTC[NV_VGA_CRTCX_VGACURCTRL] = 0x00;
1554         regp->CRTC[0xb] = 0x00;
1555         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1556         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1557         regp->CRTC[0xe] = 0x00;
1558         regp->CRTC[0xf] = 0x00;
1559         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1560         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1561         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1562         regp->CRTC[0x14] = 0x00;
1563         regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1564         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1565         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1566         /* 0x80 enables the sequencer, we don't want that */
1567         if (depth < 8) {
1568                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1569         } else {
1570                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1571         }
1572         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1573
1574         /*
1575          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1576          */
1577
1578         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1579                                 | SetBitField(vertBlankStart,10:10,3:3)
1580                                 | SetBitField(vertStart,10:10,2:2)
1581                                 | SetBitField(vertDisplay,10:10,1:1)
1582                                 | SetBitField(vertTotal,10:10,0:0);
1583
1584         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1585                                 | SetBitField(horizDisplay,8:8,1:1)
1586                                 | SetBitField(horizBlankStart,8:8,2:2)
1587                                 | SetBitField(horizStart,8:8,3:3);
1588
1589         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1590                                 | SetBitField(vertDisplay,11:11,2:2)
1591                                 | SetBitField(vertStart,11:11,4:4)
1592                                 | SetBitField(vertBlankStart,11:11,6:6);
1593
1594         if(mode->Flags & V_INTERLACE) {
1595                 horizTotal = (horizTotal >> 1) & ~1;
1596                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1597                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1598         } else {
1599                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1600         }
1601
1602         /*
1603         * Theory resumes here....
1604         */
1605
1606         /*
1607         * Graphics Display Controller
1608         */
1609         regp->Graphics[0] = 0x00;
1610         regp->Graphics[1] = 0x00;
1611         regp->Graphics[2] = 0x00;
1612         regp->Graphics[3] = 0x00;
1613         if (depth == 1) {
1614                 regp->Graphics[4] = BIT_PLANE;
1615                 regp->Graphics[5] = 0x00;
1616         } else {
1617                 regp->Graphics[4] = 0x00;
1618                 if (depth == 4) {
1619                         regp->Graphics[5] = 0x02;
1620                 } else {
1621                         regp->Graphics[5] = 0x40;
1622                 }
1623         }
1624         regp->Graphics[6] = 0x05;   /* only map 64k VGA memory !!!! */
1625         regp->Graphics[7] = 0x0F;
1626         regp->Graphics[8] = 0xFF;
1627
1628         /* I ditched the mono stuff */
1629         regp->Attribute[0]  = 0x00; /* standard colormap translation */
1630         regp->Attribute[1]  = 0x01;
1631         regp->Attribute[2]  = 0x02;
1632         regp->Attribute[3]  = 0x03;
1633         regp->Attribute[4]  = 0x04;
1634         regp->Attribute[5]  = 0x05;
1635         regp->Attribute[6]  = 0x06;
1636         regp->Attribute[7]  = 0x07;
1637         regp->Attribute[8]  = 0x08;
1638         regp->Attribute[9]  = 0x09;
1639         regp->Attribute[10] = 0x0A;
1640         regp->Attribute[11] = 0x0B;
1641         regp->Attribute[12] = 0x0C;
1642         regp->Attribute[13] = 0x0D;
1643         regp->Attribute[14] = 0x0E;
1644         regp->Attribute[15] = 0x0F;
1645         /* These two below are non-vga */
1646         regp->Attribute[16] = 0x01;
1647         regp->Attribute[17] = 0x00;
1648         regp->Attribute[18] = 0x0F;
1649         regp->Attribute[19] = 0x00;
1650         regp->Attribute[20] = 0x00;
1651 }
1652
1653 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1654 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1655
1656 /**
1657  * Sets up registers for the given mode/adjusted_mode pair.
1658  *
1659  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1660  *
1661  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1662  * be easily turned on/off after this.
1663  */
1664 static void
1665 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1666 {
1667         ScrnInfoPtr pScrn = crtc->scrn;
1668         NVPtr pNv = NVPTR(pScrn);
1669         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1670         NVFBLayout *pLayout = &pNv->CurrentLayout;
1671         NVCrtcRegPtr regp, savep;
1672         unsigned int i;
1673         Bool is_fp = FALSE;
1674
1675         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1676         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1677
1678         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1679         NVOutputPrivatePtr nv_output = NULL;
1680         if (output) {
1681                 nv_output = output->driver_private;
1682
1683                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1684                         is_fp = TRUE;
1685         }
1686
1687         /* Registers not directly related to the (s)vga mode */
1688
1689         /* bit2 = 0 -> fine pitched crtc granularity */
1690         /* The rest disables double buffering on CRTC access */
1691         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1692
1693         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1694                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1695                 if (nv_crtc->head == 0) {
1696                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1697                 }
1698
1699                 if (is_fp) {
1700                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1701                 }
1702         } else {
1703                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1704                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1705         }
1706
1707         /* Sometimes 0x10 is used, what is this? */
1708         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1709         /* Some kind of tmds switch for older cards */
1710         if (pNv->Architecture < NV_ARCH_40) {
1711                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1712         }
1713
1714         /*
1715         * Initialize DAC palette.
1716         */
1717         if(pLayout->bitsPerPixel != 8 ) {
1718                 for (i = 0; i < 256; i++) {
1719                         regp->DAC[i*3]     = i;
1720                         regp->DAC[(i*3)+1] = i;
1721                         regp->DAC[(i*3)+2] = i;
1722                 }
1723         }
1724
1725         /*
1726         * Calculate the extended registers.
1727         */
1728
1729         if(pLayout->depth < 24) {
1730                 i = pLayout->depth;
1731         } else {
1732                 i = 32;
1733         }
1734
1735         /* What is the meaning of this register? */
1736         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1737         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1738
1739         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1740         /* But what are those special conditions? */
1741         if (pNv->Architecture <= NV_ARCH_30) {
1742                 if (is_fp) {
1743                         if(nv_crtc->head == 1) {
1744                                 regp->head |= NV_CRTC_FSEL_FPP1;
1745                         } else if (pNv->twoHeads) {
1746                                 regp->head |= NV_CRTC_FSEL_FPP2;
1747                         }
1748                 }
1749         } else {
1750                 /* Some G70 cards have either FPP1 or FPP2 set, copy this if it's already present */
1751                 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1752                         regp->head |= savep->head & (NV_CRTC_FSEL_FPP1 | NV_CRTC_FSEL_FPP2);
1753                 }
1754         }
1755
1756         /* Except for rare conditions I2C is enabled on the primary crtc */
1757         if (nv_crtc->head == 0) {
1758                 if (pNv->overlayAdaptor) {
1759                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1760                 }
1761                 regp->head |= NV_CRTC_FSEL_I2C;
1762         }
1763
1764         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1765         /* This fixes my cursor corruption issue */
1766         regp->cursorConfig = 0x0;
1767         if(mode->Flags & V_DBLSCAN)
1768                 regp->cursorConfig |= (1 << 4);
1769         if (pNv->alphaCursor) {
1770                 /* bit28 means we go into alpha blend mode and not rely on the current ROP */
1771                 regp->cursorConfig |= 0x14011000;
1772         } else {
1773                 regp->cursorConfig |= 0x02000000;
1774         }
1775
1776         /* Unblock some timings */
1777         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1778         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1779
1780         /* What is the purpose of this register? */
1781         /* 0x14 may be disabled? */
1782         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1783
1784         /* 0x00 is disabled, 0x22 crt and 0x88 dfp */
1785         /* 0x11 is LVDS? */
1786         if (is_fp) {
1787                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1788         } else {
1789                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1790         }
1791
1792         /* These values seem to vary */
1793         if (nv_crtc->head == 1) {
1794                 regp->CRTC[NV_VGA_CRTCX_3C] = 0x0;
1795         } else {
1796                 regp->CRTC[NV_VGA_CRTCX_3C] = 0x70;
1797         }
1798
1799         /* 0x80 seems to be used very often, if not always */
1800         regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1801
1802         if (nv_crtc->head == 1) {
1803                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1804         } else {
1805                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1806         }
1807
1808         if (is_fp)
1809                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1810
1811         /* Are these(0x55 and 0x56) also timing related registers, since disabling them does nothing? */
1812         regp->CRTC[NV_VGA_CRTCX_55] = 0x0;
1813
1814         /* Common values like 0x14 and 0x04 are converted to 0x10 and 0x00 */
1815         regp->CRTC[NV_VGA_CRTCX_56] = 0x0;
1816
1817         /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1818         if (nv_crtc->head == 1) {
1819                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1820         } else {
1821                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1822         }
1823
1824         /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1825         regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1826
1827         regp->unk830 = mode->CrtcVDisplay - 3;
1828         regp->unk834 = mode->CrtcVDisplay - 1;
1829
1830         /* This is what the blob does */
1831         regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1832
1833         /* Never ever modify gpio, unless you know very well what you're doing */
1834         regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1835
1836         /* Switch to non-vga mode (the so called HSYNC mode) */
1837         regp->config = 0x2;
1838
1839         /* Some misc regs */
1840         regp->CRTC[NV_VGA_CRTCX_43] = 0x1;
1841         if (pNv->Architecture == NV_ARCH_40) {
1842                 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
1843                 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
1844         }
1845
1846         /*
1847          * Calculate the state that is common to all crtc's (stored in the state struct).
1848          */
1849         ErrorF("crtc %d %d %d\n", nv_crtc->crtc, mode->CrtcHDisplay, pScrn->displayWidth);
1850         nv_crtc_calc_state_ext(crtc,
1851                                 i,
1852                                 pScrn->displayWidth,
1853                                 mode->CrtcHDisplay,
1854                                 mode->CrtcVDisplay,
1855                                 adjusted_mode->Clock,
1856                                 mode->Flags);
1857
1858         /* Enable slaved mode */
1859         if (is_fp) {
1860                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1861         }
1862 }
1863
1864 static void
1865 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1866 {
1867         ScrnInfoPtr pScrn = crtc->scrn;
1868         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1869         NVCrtcRegPtr regp;
1870         NVPtr pNv = NVPTR(pScrn);
1871         NVFBLayout *pLayout = &pNv->CurrentLayout;
1872         Bool is_fp = FALSE;
1873         Bool is_lvds = FALSE;
1874         float aspect_ratio, panel_ratio;
1875         uint32_t h_scale, v_scale;
1876
1877         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1878
1879         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1880         NVOutputPrivatePtr nv_output = NULL;
1881         if (output) {
1882                 nv_output = output->driver_private;
1883
1884                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1885                         is_fp = TRUE;
1886
1887                 if (nv_output->type == OUTPUT_LVDS)
1888                         is_lvds = TRUE;
1889         }
1890
1891         if (is_fp) {
1892                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1893                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1894                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
1895                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1896                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1897                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1898                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1899
1900                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1901                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1902                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VDisplay;
1903                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1904                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1905                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1906                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1907
1908                 ErrorF("Horizontal:\n");
1909                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1910                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1911                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1912                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1913                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1914                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1915                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1916
1917                 ErrorF("Vertical:\n");
1918                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1919                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1920                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1921                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1922                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1923                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1924                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1925         }
1926
1927         /*
1928         * bit0: positive vsync
1929         * bit4: positive hsync
1930         * bit8: enable center mode
1931         * bit9: enable native mode
1932         * bit26: a bit sometimes seen on some g70 cards
1933         * bit31: set for dual link LVDS
1934         * nv10reg contains a few more things, but i don't quite get what it all means.
1935         */
1936
1937         if (pNv->Architecture >= NV_ARCH_30) {
1938                 regp->fp_control = 0x01100000;
1939         } else {
1940                 regp->fp_control = 0x00000000;
1941         }
1942
1943         if (is_fp) {
1944                 regp->fp_control |= (1 << 28);
1945         } else {
1946                 regp->fp_control |= (2 << 28);
1947                 if (pNv->Architecture < NV_ARCH_30)
1948                         regp->fp_control |= (1 << 24);
1949         }
1950
1951         if (is_lvds && pNv->VBIOS.fp.dual_link) {
1952                 regp->fp_control |= (8 << 28);
1953         } else {
1954                 /* If the special bit exists, it exists on both ramdac's */
1955                 regp->fp_control |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1956         }
1957
1958         if (is_fp) {
1959                 if (nv_output->scaling_mode == SCALE_PANEL) { /* panel needs to scale */
1960                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1961                 /* This is also true for panel scaling, so we must put the panel scale check first */
1962                 } else if (mode->Clock == adjusted_mode->Clock) { /* native mode */
1963                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1964                 } else { /* gpu needs to scale */
1965                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1966                 }
1967         }
1968
1969         /* Deal with vsync/hsync polarity */
1970         if (is_fp) {
1971                 if (adjusted_mode->Flags & V_PVSYNC) {
1972                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1973                 }
1974
1975                 if (adjusted_mode->Flags & V_PHSYNC) {
1976                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1977                 }
1978         } else {
1979                 /* The blob doesn't always do this, but often */
1980                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1981                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1982         }
1983
1984         if (is_fp) {
1985                 ErrorF("Pre-panel scaling\n");
1986                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1987                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1988                 ErrorF("panel_ratio=%f\n", panel_ratio);
1989                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1990                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1991                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1992                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1993                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1994                 ErrorF("h_scale=%d\n", h_scale);
1995                 ErrorF("v_scale=%d\n", v_scale);
1996
1997                 /* This can override HTOTAL and VTOTAL */
1998                 regp->debug_2 = 0;
1999
2000                 /* We want automatic scaling */
2001                 regp->debug_1 = 0;
2002
2003                 regp->fp_hvalid_start = 0;
2004                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
2005
2006                 regp->fp_vvalid_start = 0;
2007                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
2008
2009                 /* 0 = panel scaling */
2010                 if (nv_output->scaling_mode == SCALE_PANEL) {
2011                         ErrorF("Flat panel is doing the scaling.\n");
2012                 } else {
2013                         ErrorF("GPU is doing the scaling.\n");
2014
2015                         if (nv_output->scaling_mode == SCALE_ASPECT) {
2016                                 /* GPU scaling happens automaticly at a ratio of 1.33 */
2017                                 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
2018                                 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
2019                                         uint32_t diff;
2020
2021                                         ErrorF("Scaling resolution on a widescreen panel\n");
2022
2023                                         /* Scaling in both directions needs to the same */
2024                                         h_scale = v_scale;
2025
2026                                         /* Set a new horizontal scale factor and enable testmode (bit12) */
2027                                         regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
2028
2029                                         diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
2030                                         regp->fp_hvalid_start = diff/2;
2031                                         regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
2032                                 }
2033
2034                                 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
2035                                 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
2036                                         uint32_t diff;
2037
2038                                         ErrorF("Scaling resolution on a portrait panel\n");
2039
2040                                         /* Scaling in both directions needs to the same */
2041                                         v_scale = h_scale;
2042
2043                                         /* Set a new vertical scale factor and enable testmode (bit28) */
2044                                         regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
2045
2046                                         diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
2047                                         regp->fp_vvalid_start = diff/2;
2048                                         regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
2049                                 }
2050                         }
2051                 }
2052
2053                 ErrorF("Post-panel scaling\n");
2054         }
2055
2056         if (pNv->Architecture >= NV_ARCH_10) {
2057                 /* Bios and blob don't seem to do anything (else) */
2058                 regp->nv10_cursync = (1<<25);
2059         }
2060
2061         /* These are the common blob values, minus a few fp specific bit's */
2062         /* Let's keep the TMDS pll and fpclock running in all situations */
2063         regp->debug_0 = 0x1101100;
2064
2065         if (is_fp && nv_output->scaling_mode != SCALE_NOSCALE) {
2066                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
2067                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
2068         } else if (is_fp) { /* no_scale mode, so we must center it */
2069                 uint32_t diff;
2070
2071                 diff = nv_output->fpWidth - mode->HDisplay;
2072                 regp->fp_hvalid_start = diff/2;
2073                 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
2074
2075                 diff = nv_output->fpHeight - mode->VDisplay;
2076                 regp->fp_vvalid_start = diff/2;
2077                 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
2078         }
2079
2080         /* Is this crtc bound or output bound? */
2081         /* Does the bios TMDS script try to change this sometimes? */
2082         if (is_fp) {
2083                 /* I am not completely certain, but seems to be set only for dfp's */
2084                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
2085         }
2086
2087         if (output)
2088                 ErrorF("output %d debug_0 %08X\n", nv_output->preferred_output, regp->debug_0);
2089
2090         /* Flatpanel support needs at least a NV10 */
2091         if(pNv->twoHeads) {
2092                 /* The blob does this differently. */
2093                 /* TODO: Find out what precisely and why. */
2094                 if(pNv->FPDither || (is_lvds && pNv->VBIOS.fp.if_is_18bit)) {
2095                         if (pNv->NVArch == 0x11) {
2096                                 regp->dither = 0x00010000;
2097                         } else {
2098                                 regp->dither = 0x00000001;
2099                         }
2100                 }
2101         }
2102
2103         /* Kindly borrowed from haiku driver */
2104         /* bit4 and bit5 activate indirect mode trough color palette */
2105         switch (pLayout->depth) {
2106                 case 32:
2107                 case 16:
2108                         regp->general = 0x00101130;
2109                         break;
2110                 case 24:
2111                 case 15:
2112                         regp->general = 0x00100130;
2113                         break;
2114                 case 8:
2115                 default:
2116                         regp->general = 0x00101100;
2117                         break;
2118         }
2119
2120         if (pNv->alphaCursor) {
2121                 /* PIPE_LONG mode, something to do with the size of the cursor? */
2122                 regp->general |= (1<<29);
2123         }
2124
2125         /* Some values the blob sets */
2126         /* This may apply to the real ramdac that is being used (for crosswired situations) */
2127         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
2128         regp->unk_a20 = 0x0;
2129         regp->unk_a24 = 0xfffff;
2130         regp->unk_a34 = 0x1;
2131 }
2132
2133 /**
2134  * Sets up registers for the given mode/adjusted_mode pair.
2135  *
2136  * The clocks, CRTCs and outputs attached to this CRTC must be off.
2137  *
2138  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
2139  * be easily turned on/off after this.
2140  */
2141 static void
2142 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
2143                  DisplayModePtr adjusted_mode,
2144                  int x, int y)
2145 {
2146         ScrnInfoPtr pScrn = crtc->scrn;
2147         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2148         NVPtr pNv = NVPTR(pScrn);
2149
2150         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->crtc);
2151
2152         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->crtc);
2153         xf86PrintModeline(pScrn->scrnIndex, mode);
2154         NVCrtcSetOwner(crtc);
2155
2156         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
2157         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
2158         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
2159
2160         NVVgaProtect(crtc, TRUE);
2161         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
2162         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
2163         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
2164         if (pNv->Architecture == NV_ARCH_40) {
2165                 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
2166         } else {
2167                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
2168         }
2169
2170         NVVgaProtect(crtc, FALSE);
2171
2172         NVCrtcSetBase(crtc, x, y);
2173
2174 #if X_BYTE_ORDER == X_BIG_ENDIAN
2175         /* turn on LFB swapping */
2176         {
2177                 unsigned char tmp;
2178
2179                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
2180                 tmp |= (1 << 7);
2181                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
2182         }
2183 #endif
2184 }
2185
2186 void nv_crtc_save(xf86CrtcPtr crtc)
2187 {
2188         ScrnInfoPtr pScrn = crtc->scrn;
2189         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2190         NVPtr pNv = NVPTR(pScrn);
2191
2192         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->crtc);
2193
2194         /* We just came back from terminal, so unlock */
2195         NVCrtcLockUnlock(crtc, FALSE);
2196
2197         NVCrtcSetOwner(crtc);
2198         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
2199         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
2200         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
2201         if (pNv->Architecture == NV_ARCH_40) {
2202                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
2203         } else {
2204                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
2205         }
2206 }
2207
2208 void nv_crtc_restore(xf86CrtcPtr crtc)
2209 {
2210         ScrnInfoPtr pScrn = crtc->scrn;
2211         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2212         NVPtr pNv = NVPTR(pScrn);
2213         RIVA_HW_STATE *state;
2214
2215         state = &pNv->SavedReg;
2216
2217         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->crtc);
2218
2219         NVCrtcSetOwner(crtc);
2220
2221         /* Just to be safe */
2222         NVCrtcLockUnlock(crtc, FALSE);
2223
2224         NVVgaProtect(crtc, TRUE);
2225         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
2226         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
2227         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
2228         if (pNv->Architecture == NV_ARCH_40) {
2229                 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
2230         } else {
2231                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
2232         }
2233         nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
2234         NVVgaProtect(crtc, FALSE);
2235 }
2236
2237 void
2238 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
2239 {
2240         ScrnInfoPtr pScrn = crtc->scrn;
2241         NVPtr pNv = NVPTR(pScrn);
2242         CARD32 val = 0;
2243
2244         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2245
2246         if (set) {
2247                 NVCrtcRegPtr regp;
2248
2249                 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2250                 val = regp->head;
2251         }
2252
2253         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, val);
2254 }
2255
2256 void nv_crtc_prepare(xf86CrtcPtr crtc)
2257 {
2258         ScrnInfoPtr pScrn = crtc->scrn;
2259         NVPtr pNv = NVPTR(pScrn);
2260         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2261
2262         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->crtc);
2263
2264         /* Just in case */
2265         NVCrtcLockUnlock(crtc, 0);
2266
2267         NVResetCrtcConfig(crtc, FALSE);
2268
2269         crtc->funcs->dpms(crtc, DPMSModeOff);
2270
2271         /* Sync the engine before adjust mode */
2272         if (pNv->EXADriverPtr) {
2273                 exaMarkSync(pScrn->pScreen);
2274                 exaWaitSync(pScrn->pScreen);
2275         }
2276
2277         NVCrtcBlankScreen(crtc, FALSE); /* Blank screen */
2278
2279         /* Some more preperation. */
2280         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
2281         uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2282         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2283         /* Set FP_CONTROL to a neutral mode, (almost) off i believe. */
2284         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, 0x21100222);
2285
2286         usleep(5000); /* Give it some time to settle */
2287 }
2288
2289 void nv_crtc_commit(xf86CrtcPtr crtc)
2290 {
2291         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2292         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->crtc);
2293
2294         crtc->funcs->dpms (crtc, DPMSModeOn);
2295
2296         if (crtc->scrn->pScreen != NULL)
2297                 xf86_reload_cursors (crtc->scrn->pScreen);
2298
2299         NVResetCrtcConfig(crtc, TRUE);
2300 }
2301
2302 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2303 {
2304         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2305         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->crtc);
2306
2307         return FALSE;
2308 }
2309
2310 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2311 {
2312         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2313         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->crtc);
2314 }
2315
2316 static void
2317 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2318                                         int size)
2319 {
2320         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2321         ScrnInfoPtr pScrn = crtc->scrn;
2322         NVPtr pNv = NVPTR(pScrn);
2323         int i, j;
2324
2325         NVCrtcRegPtr regp;
2326         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2327
2328         switch (pNv->CurrentLayout.depth) {
2329         case 15:
2330                 /* R5G5B5 */
2331                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2332                 for (i = 0; i < 32; i++) {
2333                         for (j = 0; j < 8; j++) {
2334                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2335                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2336                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2337                         }
2338                 }
2339                 break;
2340         case 16:
2341                 /* R5G6B5 */
2342                 /* First deal with the 5 bit colors */
2343                 for (i = 0; i < 32; i++) {
2344                         for (j = 0; j < 8; j++) {
2345                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2346                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2347                         }
2348                 }
2349                 /* Now deal with the 6 bit color */
2350                 for (i = 0; i < 64; i++) {
2351                         for (j = 0; j < 4; j++) {
2352                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2353                         }
2354                 }
2355                 break;
2356         default:
2357                 /* R8G8B8 */
2358                 for (i = 0; i < 256; i++) {
2359                         regp->DAC[i * 3] = red[i] >> 8;
2360                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
2361                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2362                 }
2363                 break;
2364         }
2365
2366         NVCrtcLoadPalette(crtc);
2367 }
2368
2369 /**
2370  * Allocates memory for a locked-in-framebuffer shadow of the given
2371  * width and height for this CRTC's rotated shadow framebuffer.
2372  */
2373
2374 static void *
2375 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
2376 {
2377         ErrorF("nv_crtc_shadow_allocate is called\n");
2378         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2379         ScrnInfoPtr pScrn = crtc->scrn;
2380 #if !NOUVEAU_EXA_PIXMAPS
2381         ScreenPtr pScreen = pScrn->pScreen;
2382 #endif /* !NOUVEAU_EXA_PIXMAPS */
2383         NVPtr pNv = NVPTR(pScrn);
2384         void *offset;
2385
2386         unsigned long rotate_pitch;
2387         int size, align = 64;
2388
2389         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2390         size = rotate_pitch * height;
2391
2392         assert(nv_crtc->shadow == NULL);
2393 #if NOUVEAU_EXA_PIXMAPS
2394         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
2395                         align, size, &nv_crtc->shadow)) {
2396                 ErrorF("Failed to allocate memory for shadow buffer!\n");
2397                 return NULL;
2398         }
2399
2400         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
2401                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2402                                 "Failed to map shadow buffer.\n");
2403                 return NULL;
2404         }
2405
2406         offset = nv_crtc->shadow->map;
2407 #else
2408         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
2409         if (nv_crtc->shadow == NULL) {
2410                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2411                         "Couldn't allocate shadow memory for rotated CRTC\n");
2412                 return NULL;
2413         }
2414         offset = pNv->FB->map + nv_crtc->shadow->offset;
2415 #endif /* NOUVEAU_EXA_PIXMAPS */
2416
2417         return offset;
2418 }
2419
2420 /**
2421  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
2422  */
2423 static PixmapPtr
2424 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
2425 {
2426         ErrorF("nv_crtc_shadow_create is called\n");
2427         ScrnInfoPtr pScrn = crtc->scrn;
2428 #if NOUVEAU_EXA_PIXMAPS
2429         ScreenPtr pScreen = pScrn->pScreen;
2430         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2431 #endif /* NOUVEAU_EXA_PIXMAPS */
2432         unsigned long rotate_pitch;
2433         PixmapPtr rotate_pixmap;
2434 #if NOUVEAU_EXA_PIXMAPS
2435         struct nouveau_pixmap *nvpix;
2436 #endif /* NOUVEAU_EXA_PIXMAPS */
2437
2438         if (!data)
2439                 data = crtc->funcs->shadow_allocate (crtc, width, height);
2440
2441         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2442
2443 #if NOUVEAU_EXA_PIXMAPS
2444         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
2445         rotate_pixmap = pScreen->CreatePixmap(pScreen,
2446                                                                 0, /* width */
2447                                                                 0, /* height */
2448         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
2449                                                                 pScrn->depth,
2450                                                                 0);
2451         #else
2452                                                                 pScrn->depth);
2453         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
2454 #else
2455         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
2456                                                                 width, height,
2457                                                                 pScrn->depth,
2458                                                                 pScrn->bitsPerPixel,
2459                                                                 rotate_pitch,
2460                                                                 data);
2461 #endif /* NOUVEAU_EXA_PIXMAPS */
2462
2463         if (rotate_pixmap == NULL) {
2464                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2465                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
2466         }
2467
2468 #if NOUVEAU_EXA_PIXMAPS
2469         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2470         if (!nvpix) {
2471                 ErrorF("No shadow private, stage 1\n");
2472         } else {
2473                 nvpix->bo = nv_crtc->shadow;
2474                 nvpix->mapped = TRUE;
2475         }
2476
2477         /* Modify the pixmap to actually be the one we need. */
2478         pScreen->ModifyPixmapHeader(rotate_pixmap,
2479                                         width,
2480                                         height,
2481                                         pScrn->depth,
2482                                         pScrn->bitsPerPixel,
2483                                         rotate_pitch,
2484                                         data);
2485
2486         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2487         if (!nvpix || !nvpix->bo)
2488                 ErrorF("No shadow private, stage 2\n");
2489 #endif /* NOUVEAU_EXA_PIXMAPS */
2490
2491         return rotate_pixmap;
2492 }
2493
2494 static void
2495 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
2496 {
2497         ErrorF("nv_crtc_shadow_destroy is called\n");
2498         ScrnInfoPtr pScrn = crtc->scrn;
2499         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2500         ScreenPtr pScreen = pScrn->pScreen;
2501
2502         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
2503                 pScreen->DestroyPixmap(rotate_pixmap);
2504         }
2505
2506 #if !NOUVEAU_EXA_PIXMAPS
2507         if (data && nv_crtc->shadow) {
2508                 exaOffscreenFree(pScreen, nv_crtc->shadow);
2509         }
2510 #endif /* !NOUVEAU_EXA_PIXMAPS */
2511
2512         nv_crtc->shadow = NULL;
2513 }
2514
2515 /* NV04-NV10 doesn't support alpha cursors */
2516 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2517         .dpms = nv_crtc_dpms,
2518         .save = nv_crtc_save, /* XXX */
2519         .restore = nv_crtc_restore, /* XXX */
2520         .mode_fixup = nv_crtc_mode_fixup,
2521         .mode_set = nv_crtc_mode_set,
2522         .prepare = nv_crtc_prepare,
2523         .commit = nv_crtc_commit,
2524         .destroy = NULL, /* XXX */
2525         .lock = nv_crtc_lock,
2526         .unlock = nv_crtc_unlock,
2527         .set_cursor_colors = nv_crtc_set_cursor_colors,
2528         .set_cursor_position = nv_crtc_set_cursor_position,
2529         .show_cursor = nv_crtc_show_cursor,
2530         .hide_cursor = nv_crtc_hide_cursor,
2531         .load_cursor_image = nv_crtc_load_cursor_image,
2532         .gamma_set = nv_crtc_gamma_set,
2533         .shadow_create = nv_crtc_shadow_create,
2534         .shadow_allocate = nv_crtc_shadow_allocate,
2535         .shadow_destroy = nv_crtc_shadow_destroy,
2536 };
2537
2538 /* NV11 and up has support for alpha cursors. */
2539 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2540 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2541         .dpms = nv_crtc_dpms,
2542         .save = nv_crtc_save, /* XXX */
2543         .restore = nv_crtc_restore, /* XXX */
2544         .mode_fixup = nv_crtc_mode_fixup,
2545         .mode_set = nv_crtc_mode_set,
2546         .prepare = nv_crtc_prepare,
2547         .commit = nv_crtc_commit,
2548         .destroy = NULL, /* XXX */
2549         .lock = nv_crtc_lock,
2550         .unlock = nv_crtc_unlock,
2551         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2552         .set_cursor_position = nv_crtc_set_cursor_position,
2553         .show_cursor = nv_crtc_show_cursor,
2554         .hide_cursor = nv_crtc_hide_cursor,
2555         .load_cursor_argb = nv_crtc_load_cursor_argb,
2556         .gamma_set = nv_crtc_gamma_set,
2557         .shadow_create = nv_crtc_shadow_create,
2558         .shadow_allocate = nv_crtc_shadow_allocate,
2559         .shadow_destroy = nv_crtc_shadow_destroy,
2560 };
2561
2562
2563 void
2564 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2565 {
2566         NVPtr pNv = NVPTR(pScrn);
2567         xf86CrtcPtr crtc;
2568         NVCrtcPrivatePtr nv_crtc;
2569
2570         if (pNv->NVArch >= 0x11) {
2571                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2572         } else {
2573                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2574         }
2575         if (crtc == NULL)
2576                 return;
2577
2578         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2579         nv_crtc->crtc = crtc_num;
2580         nv_crtc->head = crtc_num;
2581
2582         crtc->driver_private = nv_crtc;
2583
2584         NVCrtcLockUnlock(crtc, FALSE);
2585 }
2586
2587 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2588 {
2589         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2590         int i;
2591         NVCrtcRegPtr regp;
2592
2593         regp = &state->crtc_reg[nv_crtc->head];
2594
2595         NVWriteMiscOut(crtc, regp->MiscOutReg);
2596
2597         for (i = 1; i < 5; i++)
2598                 NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2599
2600         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2601         NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2602
2603         for (i = 0; i < 25; i++)
2604                 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2605
2606         for (i = 0; i < 9; i++)
2607                 NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2608
2609         NVEnablePalette(crtc);
2610         for (i = 0; i < 21; i++)
2611                 NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2612
2613         NVDisablePalette(crtc);
2614 }
2615
2616 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2617 {
2618         /* TODO - implement this properly */
2619         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2620         ScrnInfoPtr pScrn = crtc->scrn;
2621         NVPtr pNv = NVPTR(pScrn);
2622
2623         if (pNv->Architecture == NV_ARCH_40) {  /* HW bug */
2624                 volatile CARD32 curpos = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS);
2625                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS, curpos);
2626         }
2627 }
2628 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2629 {
2630         ScrnInfoPtr pScrn = crtc->scrn;
2631         NVPtr pNv = NVPTR(pScrn);
2632         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2633         NVCrtcRegPtr regp;
2634         int i;
2635
2636         regp = &state->crtc_reg[nv_crtc->head];
2637
2638         /* If we ever get down to pre-nv10 cards, then we must reinstate some limits. */
2639         nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2640         nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2641         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2642         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2643         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2644         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2645         nvWriteMC(pNv, 0x1588, 0);
2646
2647         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2648         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2649         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2650         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2651         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2652         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2653         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2654
2655         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, regp->config);
2656         uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2657         if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
2658                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 | 0x10000);
2659         } else {
2660                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2661         }
2662
2663         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2664         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2665
2666         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2667         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2668         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2669         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2670         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2671         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2672         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_56, regp->CRTC[NV_VGA_CRTCX_56]);
2673         if (override) {
2674                 for (i = 0; i < 0x10; i++)
2675                         NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2676         }
2677         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2678         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2679
2680         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2681         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2682         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2683         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2684         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2685         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2686         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2687         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2688         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2689         if (pNv->Architecture >= NV_ARCH_30) {
2690                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2691         }
2692
2693         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_43, regp->CRTC[NV_VGA_CRTCX_43]);
2694         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
2695         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
2696
2697         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2698         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2699         nv_crtc_fix_nv40_hw_cursor(crtc);
2700         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2701         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2702
2703         /* Setting 1 on this value gives you interrupts for every vblank period. */
2704         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2705         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2706
2707         pNv->CurrentState = state;
2708 }
2709
2710 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2711 {
2712         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2713         int i;
2714         NVCrtcRegPtr regp;
2715
2716         regp = &state->crtc_reg[nv_crtc->head];
2717
2718         regp->MiscOutReg = NVReadMiscOut(crtc);
2719
2720         for (i = 0; i < 25; i++)
2721                 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2722
2723         NVEnablePalette(crtc);
2724         for (i = 0; i < 21; i++)
2725                 regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2726         NVDisablePalette(crtc);
2727
2728         for (i = 0; i < 9; i++)
2729                 regp->Graphics[i] = NVReadVgaGr(crtc, i);
2730
2731         for (i = 1; i < 5; i++)
2732                 regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2733
2734 }
2735
2736 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2737 {
2738         ScrnInfoPtr pScrn = crtc->scrn;
2739         NVPtr pNv = NVPTR(pScrn);
2740         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2741         NVCrtcRegPtr regp;
2742         int i;
2743
2744         regp = &state->crtc_reg[nv_crtc->head];
2745
2746         /* If we ever get down to pre-nv10 cards, then we must reinstate some limits. */
2747         regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2748         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2749         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2750         regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2751         regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2752         regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2753         regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2754
2755         regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2756         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2757         if (pNv->Architecture >= NV_ARCH_30) {
2758                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2759         }
2760         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2761         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2762         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2763         regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2764
2765         regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2766         regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2767         regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2768         regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2769         regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2770
2771         regp->config = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG);
2772
2773         regp->head = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2774         regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2775         regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2776
2777         regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2778
2779         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2780         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2781         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2782         regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2783         regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2784         regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2785         regp->CRTC[NV_VGA_CRTCX_56] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_56);
2786         for (i = 0; i < 0x10; i++)
2787                 regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2788
2789         regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2790         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2791         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2792         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2793
2794         regp->CRTC[NV_VGA_CRTCX_43] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_43);
2795         regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_85);
2796         regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_86);
2797 }
2798
2799 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2800 {
2801         ScrnInfoPtr pScrn = crtc->scrn;
2802         NVPtr pNv = NVPTR(pScrn);
2803         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2804         NVCrtcRegPtr regp;
2805         int i;
2806
2807         regp = &state->crtc_reg[nv_crtc->head];
2808
2809         regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2810
2811         regp->fp_control        = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL);
2812         regp->debug_0   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0);
2813         regp->debug_1   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2814         regp->debug_2   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2815
2816         regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2817         regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2818         regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2819
2820         if (pNv->NVArch == 0x11) {
2821                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2822         } else if (pNv->twoHeads) {
2823                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2824         }
2825         regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2826
2827         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2828
2829         for (i = 0; i < 7; i++) {
2830                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2831                 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2832         }
2833
2834         for (i = 0; i < 7; i++) {
2835                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2836                 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2837         }
2838
2839         regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2840         regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2841         regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2842         regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2843 }
2844
2845 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2846 {
2847         ScrnInfoPtr pScrn = crtc->scrn;
2848         NVPtr pNv = NVPTR(pScrn);
2849         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2850         NVCrtcRegPtr regp;
2851         int i;
2852
2853         regp = &state->crtc_reg[nv_crtc->head];
2854
2855         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2856
2857         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
2858         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
2859         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2860         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2861
2862         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2863         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2864         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2865
2866         if (pNv->NVArch == 0x11) {
2867                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2868         } else if (pNv->twoHeads) {
2869                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2870         }
2871         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2872
2873         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2874
2875         for (i = 0; i < 7; i++) {
2876                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2877                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2878         }
2879
2880         for (i = 0; i < 7; i++) {
2881                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2882                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2883         }
2884
2885         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2886         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2887         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2888         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2889 }
2890
2891 void
2892 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
2893 {
2894         ScrnInfoPtr pScrn = crtc->scrn;
2895         NVPtr pNv = NVPTR(pScrn);
2896         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2897         NVFBLayout *pLayout = &pNv->CurrentLayout;
2898         CARD32 start = 0;
2899
2900         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2901
2902         start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2903         if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
2904 #if NOUVEAU_EXA_PIXMAPS
2905                 start = nv_crtc->shadow->offset;
2906 #else
2907                 start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
2908 #endif
2909         } else {
2910                 start += pNv->FB->offset;
2911         }
2912
2913         /* 30 bits addresses in 32 bits according to haiku */
2914         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2915
2916         /* set NV4/NV10 byte adress: (bit0 - 1) */
2917         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2918
2919         crtc->x = x;
2920         crtc->y = y;
2921 }
2922
2923 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, CARD8 value)
2924 {
2925   ScrnInfoPtr pScrn = crtc->scrn;
2926   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2927   NVPtr pNv = NVPTR(pScrn);
2928   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2929
2930   NV_WR08(pDACReg, VGA_DAC_MASK, value);
2931 }
2932
2933 static CARD8 NVCrtcReadDacMask(xf86CrtcPtr crtc)
2934 {
2935   ScrnInfoPtr pScrn = crtc->scrn;
2936   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2937   NVPtr pNv = NVPTR(pScrn);
2938   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2939
2940   return NV_RD08(pDACReg, VGA_DAC_MASK);
2941 }
2942
2943 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, CARD8 value)
2944 {
2945   ScrnInfoPtr pScrn = crtc->scrn;
2946   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2947   NVPtr pNv = NVPTR(pScrn);
2948   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2949
2950   NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
2951 }
2952
2953 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, CARD8 value)
2954 {
2955   ScrnInfoPtr pScrn = crtc->scrn;
2956   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2957   NVPtr pNv = NVPTR(pScrn);
2958   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2959
2960   NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
2961 }
2962
2963 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, CARD8 value)
2964 {
2965   ScrnInfoPtr pScrn = crtc->scrn;
2966   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2967   NVPtr pNv = NVPTR(pScrn);
2968   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2969
2970   NV_WR08(pDACReg, VGA_DAC_DATA, value);
2971 }
2972
2973 static CARD8 NVCrtcReadDacData(xf86CrtcPtr crtc, CARD8 value)
2974 {
2975   ScrnInfoPtr pScrn = crtc->scrn;
2976   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2977   NVPtr pNv = NVPTR(pScrn);
2978   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2979
2980   return NV_RD08(pDACReg, VGA_DAC_DATA);
2981 }
2982
2983 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
2984 {
2985         int i;
2986         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2987         NVCrtcRegPtr regp;
2988         ScrnInfoPtr pScrn = crtc->scrn;
2989         NVPtr pNv = NVPTR(pScrn);
2990
2991         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2992
2993         NVCrtcSetOwner(crtc);
2994         NVCrtcWriteDacMask(crtc, 0xff);
2995         NVCrtcWriteDacWriteAddr(crtc, 0x00);
2996
2997         for (i = 0; i<768; i++) {
2998                 NVCrtcWriteDacData(crtc, regp->DAC[i]);
2999         }
3000         NVDisablePalette(crtc);
3001 }
3002
3003 /* on = unblank */
3004 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
3005 {
3006         unsigned char scrn;
3007
3008         NVCrtcSetOwner(crtc);
3009
3010         scrn = NVReadVgaSeq(crtc, 0x01);
3011         if (on) {
3012                 scrn &= ~0x20;
3013         } else {
3014                 scrn |= 0x20;
3015         }
3016
3017         NVVgaSeqReset(crtc, TRUE);
3018         NVWriteVgaSeq(crtc, 0x01, scrn);
3019         NVVgaSeqReset(crtc, FALSE);
3020 }
3021
3022 /*************************************************************************** \
3023 |*                                                                           *|
3024 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
3025 |*                                                                           *|
3026 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
3027 |*     international laws.  Users and possessors of this source code are     *|
3028 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
3029 |*     use this code in individual and commercial software.                  *|
3030 |*                                                                           *|
3031 |*     Any use of this source code must include,  in the user documenta-     *|
3032 |*     tion and  internal comments to the code,  notices to the end user     *|
3033 |*     as follows:                                                           *|
3034 |*                                                                           *|
3035 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
3036 |*                                                                           *|
3037 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
3038 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
3039 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
3040 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
3041 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
3042 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
3043 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
3044 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
3045 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
3046 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
3047 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
3048 |*                                                                           *|
3049 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
3050 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
3051 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
3052 |*     computer  software  documentation,"  as such  terms  are  used in     *|
3053 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
3054 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
3055 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
3056 |*     all U.S. Government End Users  acquire the source code  with only     *|
3057 |*     those rights set forth herein.                                        *|
3058 |*                                                                           *|
3059  \***************************************************************************/