randr12: Intermediate commit.

[nouveau] / src / nvreg.h

/* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */
/*
 * Copyright 1996-1997  David J. McKay
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nvreg.h,v 1.6 2002/01/25 21:56:06 tsi Exp $ */

#ifndef __NVREG_H_
#define __NVREG_H_

//#define NV_IMAGE_PATTERN              0x18


#define NV_PRAMIN_OFFSET            0x00710000
#define NV_PRAMIN_SIZE              0x00100000

#define NV_PCRTC0_OFFSET            0x00600000
#define NV_PCRTC0_SIZE              0x00002000 /* empirical */

#define NV50_PCRTC_OFFSET               0x00610000
#define NV50_PCRTC_SIZE         0x00004000 /* Until a better guess comes along */

#define NV_PRAMDAC0_OFFSET          0x00680000
#define NV_PRAMDAC0_SIZE            0x00002000

#define NV_PFB_OFFSET               0x00100000
#define NV_PFB_SIZE                 0x00001000

#define NV_PFIFO_OFFSET             0x00002000
#define NV_PFIFO_SIZE               0x00010000

#define NV_PGRAPH_OFFSET            0x00400000
#define NV_PGRAPH_SIZE              0x00010000

#define NV_PEXTDEV_OFFSET           0x00101000
#define NV_PEXTDEV_SIZE             0x00001000

#define NV_PTIMER_OFFSET            0x00009000
#define NV_PTIMER_SIZE              0x00001000

#define NV_PVIDEO_OFFSET            0x00008000
#define NV_PVIDEO_SIZE              0x00001000

/* TODO PMC size is 0x1000, but we need to get ride of abuses first */
#define NV_PMC_OFFSET               0x00000000
#define NV_PMC_SIZE                 0x0000f000

#define NV_FIFO_OFFSET              0x00800000
#define NV_FIFO_SIZE                0x00800000

#define NV_PCIO0_OFFSET             0x00601000
#define NV_PCIO0_SIZE               0x00002000

#define NV_PDIO0_OFFSET             0x00681000
#define NV_PDIO0_SIZE               0x00002000

#define NV_PVIO_OFFSET              0x000C0000
#define NV_PVIO_SIZE                0x00008000

#define NV_PROM_OFFSET              0x00300000
#define NV_PROM_SIZE                0x00010000

/* Nvidia CRTC indexed registers */
/* VGA standard registers: - from Haiku */
#define NV_VGA_CRTCX_HTOTAL             0x00
#define NV_VGA_CRTCX_HDISPE             0x01
#define NV_VGA_CRTCX_HBLANKS            0x02
#define NV_VGA_CRTCX_HBLANKE            0x03
#define NV_VGA_CRTCX_HSYNCS             0x04
#define NV_VGA_CRTCX_HSYNCE             0x05
#define NV_VGA_CRTCX_VTOTAL             0x06
#define NV_VGA_CRTCX_OVERFLOW           0x07
#define NV_VGA_CRTCX_PRROWSCN           0x08
#define NV_VGA_CRTCX_MAXSCLIN           0x09
#define NV_VGA_CRTCX_VGACURCTRL         0x0a
#define NV_VGA_CRTCX_FBSTADDH           0x0c
#define NV_VGA_CRTCX_FBSTADDL           0x0d
#define NV_VGA_CRTCX_VSYNCS             0x10
#define NV_VGA_CRTCX_VSYNCE             0x11
#define NV_VGA_CRTCX_VDISPE             0x12
#define NV_VGA_CRTCX_PITCHL             0x13
#define NV_VGA_CRTCX_VBLANKS            0x15
#define NV_VGA_CRTCX_VBLANKE            0x16
#define NV_VGA_CRTCX_MODECTL            0x17
#define NV_VGA_CRTCX_LINECOMP           0x18
/* Extended VGA CRTC registers */
#define NV_VGA_CRTCX_REPAINT0           0x19
#define NV_VGA_CRTCX_REPAINT1           0x1a
#define NV_VGA_CRTCX_FIFO0              0x1b
#define NV_VGA_CRTCX_FIFO1              0x1c
#define NV_VGA_CRTCX_LOCK               0x1f
#define NV_VGA_CRTCX_FIFO_LWM           0x20
#define NV_VGA_CRTCX_BUFFER             0x21
#define NV_VGA_CRTCX_LSR                0x25
#define NV_VGA_CRTCX_26         0x26
#define NV_VGA_CRTCX_PIXEL              0x28
#define NV_VGA_CRTCX_HEB                0x2d
#define NV_VGA_CRTCX_CURCTL2            0x2f
#define NV_VGA_CRTCX_CURCTL0            0x30
#define NV_VGA_CRTCX_CURCTL1            0x31
#define NV_VGA_CRTCX_LCD                0x33
#define NV_VGA_CRTCX_INTERLACE          0x39
#define NV_VGA_CRTCX_3B         0x3b
#define NV_VGA_CRTCX_3C         0x3c
#define NV_VGA_CRTCX_EXTRA              0x41
#define NV_VGA_CRTCX_43                 0x43
#define NV_VGA_CRTCX_OWNER              0x44
#define NV_VGA_CRTCX_45                 0x45
#define NV_VGA_CRTCX_SWAPPING           0x46
#define NV_VGA_CRTCX_FIFO_LWM_NV30      0x47
#define NV_VGA_CRTCX_4B                 0x4b
#define NV_VGA_CRTCX_FP_HTIMING         0x53
#define NV_VGA_CRTCX_FP_VTIMING         0x54
#define NV_VGA_CRTCX_52                 0x52
#define NV_VGA_CRTCX_55                 0x55
#define NV_VGA_CRTCX_56                 0x56
#define NV_VGA_CRTCX_57                 0x57
#define NV_VGA_CRTCX_58                 0x58
#define NV_VGA_CRTCX_59                 0x59
#define NV_VGA_CRTCX_85                 0x85
#define NV_VGA_CRTCX_86                 0x86


#define NV_PGRAPH_STATUS            (0x00000700)
#define NV_PFIFO_RAMHT              (0x00000210)
#define NV_PFB_BOOT                 (0x00000000)
#define NV_PEXTDEV_BOOT             (0x00000000)
#define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT (1 << 15)

#define NV_RAMDAC_CURSOR_POS  0x300
#define NV_RAMDAC_CURSOR_CTRL       0x320
#define NV_RAMDAC_CURSOR_DATA_LO    0x324
#define NV_RAMDAC_CURSOR_DATA_HI    0x328

#define NV_RAMDAC_NV10_CURSYNC      0x404

#define NV_RAMDAC_NVPLL             0x500
#define NV_RAMDAC_MPLL              0x504

#       define NV_RAMDAC_PLL_COEFF_MDIV     0x000000FF
#       define NV_RAMDAC_PLL_COEFF_NDIV     0x0000FF00
#       define NV_RAMDAC_PLL_COEFF_PDIV     0x00070000
#       define NV30_RAMDAC_ENABLE_VCO2  (1 << 7)

#define NV_RAMDAC_VPLL              0x508
#define NV_RAMDAC_PLL_SELECT        0x50c
/* Without this it will use vpll1 */
/* Maybe only for nv4x */
#define NV_RAMDAC_PLL_SELECT_USE_VPLL2_FALSE    (0<<2)
#define NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE             (1<<2)
#define NV_RAMDAC_PLL_SELECT_DLL_BYPASS         (1<<4)
#define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_DEFAULT         (0<<8)
#define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL            (1<<8)
#define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL            (2<<8)
#define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL           (4<<8)
#define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL             (7<<8)
/* Does this name make sense? */
#define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2           (1<<11)
#define NV_RAMDAC_PLL_SELECT_MPLL_BYPASS_FALSE  (0<<12)
#define NV_RAMDAC_PLL_SELECT_MPLL_BYPASS_TRUE   (1<<12)
#define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_NONE            (0<<16)
#define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_VSCLK           (1<<16)
#define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_PCLK            (2<<16)
#define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_BOTH            (3<<16)

#define NV_RAMDAC_PLL_SELECT_TVCLK_SOURCE_EXT           (0<<20)
#define NV_RAMDAC_PLL_SELECT_TVCLK_SOURCE_VIP           (1<<20)

#define NV_RAMDAC_PLL_SELECT_TVCLK_RATIO_DB1            (0<<24)
#define NV_RAMDAC_PLL_SELECT_TVCLK_RATIO_DB2            (1<<24)
#define NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB1             (0<<28)
#define NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2             (1<<28)
#define NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB1            (0<<29)
#define NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2            (1<<29)



#define NV_RAMDAC_PLL_SETUP_CONTROL 0x510
#define NV_RAMDAC_PLL_TEST_COUNTER  0x514
#define NV_RAMDAC_PALETTE_TEST      0x518
#define NV_RAMDAC_VPLL2             0x520
#define NV_RAMDAC_SEL_CLK           0x524
#define NV_RAMDAC_DITHER_NV11       0x528
#define NV_RAMDAC_OUTPUT            0x52c
#define NV_RAMDAC_OUTPUT_DAC_ENABLE                     (1<<0)
#define NV_RAMDAC_OUTPUT_SELECT_CRTC1                   (1<<8)

#define NV_RAMDAC_NVPLL_B           0x570
#define NV_RAMDAC_MPLL_B            0x574
#define NV_RAMDAC_VPLL_B            0x578
#define NV_RAMDAC_VPLL2_B           0x57c
/* Educated guess, should remain on for NV4x vpll's. */
#define NV31_RAMDAC_ENABLE_VCO2         (1 << 31)

#define NV_RAMDAC_580                   0x580
/* This is not always activated, but only when VCLK_RATIO_DB1 is used */
#define NV_RAMDAC_580_VPLL1_ACTIVE                      (1<<8)
#define NV_RAMDAC_580_VPLL2_ACTIVE                      (1<<28)

#define NV_RAMDAC_594                   0x594

#define NV_RAMDAC_GENERAL_CONTROL   0x600
#define NV_RAMDAC_TEST_CONTROL      0x608
#define NV_RAMDAC_TEST_DATA         0x610

/* This register is similar to TEST_CONTROL in the style of values */
#define NV_RAMDAC_670                   0x670

#define NV_RAMDAC_TV_SETUP          0x700
#define NV_RAMDAC_TV_VBLANK_START   0x704
#define NV_RAMDAC_TV_VBLANK_END     0x708
#define NV_RAMDAC_TV_HBLANK_START   0x70c
#define NV_RAMDAC_TV_HBLANK_END     0x710
#define NV_RAMDAC_TV_BLANK_COLOR    0x714
#define NV_RAMDAC_TV_VTOTAL         0x720
#define NV_RAMDAC_TV_VSYNC_START    0x724
#define NV_RAMDAC_TV_VSYNC_END      0x728
#define NV_RAMDAC_TV_HTOTAL         0x72c
#define NV_RAMDAC_TV_HSYNC_START    0x730
#define NV_RAMDAC_TV_HSYNC_END      0x734
#define NV_RAMDAC_TV_SYNC_DELAY     0x738

#define REG_DISP_END 0
#define REG_DISP_TOTAL 1
#define REG_DISP_CRTC 2
#define REG_DISP_SYNC_START 3
#define REG_DISP_SYNC_END 4
#define REG_DISP_VALID_START 5
#define REG_DISP_VALID_END 6

#define NV_RAMDAC_FP_VDISP_END      0x800
#define NV_RAMDAC_FP_VTOTAL         0x804
#define NV_RAMDAC_FP_VCRTC          0x808
#define NV_RAMDAC_FP_VSYNC_START    0x80c
#define NV_RAMDAC_FP_VSYNC_END      0x810
#define NV_RAMDAC_FP_VVALID_START   0x814
#define NV_RAMDAC_FP_VVALID_END     0x818
#define NV_RAMDAC_FP_HDISP_END      0x820
#define NV_RAMDAC_FP_HTOTAL         0x824
#define NV_RAMDAC_FP_HCRTC          0x828
#define NV_RAMDAC_FP_HSYNC_START    0x82c
#define NV_RAMDAC_FP_HSYNC_END      0x830
#define NV_RAMDAC_FP_HVALID_START   0x834
#define NV_RAMDAC_FP_HVALID_END     0x838

#define NV_RAMDAC_FP_DITHER             0x83c
#define NV_RAMDAC_FP_CHECKSUM           0x840
#define NV_RAMDAC_FP_TEST_CONTROL       0x844
#define NV_RAMDAC_FP_CONTROL            0x848
#       define NV_RAMDAC_FP_CONTROL_VSYNC_NEG           (0 << 0)
#       define NV_RAMDAC_FP_CONTROL_VSYNC_POS           (1 << 0)
#       define NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE       (2 << 0)
#       define NV_RAMDAC_FP_CONTROL_HSYNC_NEG           (0 << 4)
#       define NV_RAMDAC_FP_CONTROL_HSYNC_POS           (1 << 4)
#       define NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE       (2 << 4)
#       define NV_RAMDAC_FP_CONTROL_MODE_SCALE  (0 << 8)
#       define NV_RAMDAC_FP_CONTROL_MODE_CENTER (1 << 8)
#       define NV_RAMDAC_FP_CONTROL_MODE_NATIVE (2 << 8)
#define NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 (1 << 24)
#define NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS (1 << 28)
#define NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE (2 << 28)

#define NV_RAMDAC_FP_DEBUG_0            0x880
#       define NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED                      (1 << 0)
#       define NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED                      (1 << 4)
/* This doesn't seem to be essential for tmds, but still often set */
#       define NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED                        (1 << 7)
#       define NV_RAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK                       (1 << 28)
#       define NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL            (2 << 28)
#       define NV_RAMDAC_FP_DEBUG_0_PWRDOWN_BOTH                        (3 << 28)
#define NV_RAMDAC_FP_DEBUG_1        0x884
#define NV_RAMDAC_FP_DEBUG_2        0x888
#define NV_RAMDAC_FP_DEBUG_3        0x88C

/* Some unknown regs, purely for NV30 it seems. */
#define NV30_RAMDAC_890                 0x890
#define NV30_RAMDAC_894                 0x894
#define NV30_RAMDAC_89C                 0x89C

#define NV_RAMDAC_FP_TMDS_CONTROL   0x8b0
/* 0xff - address mask */
#define NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE (1<<16)
#define NV_RAMDAC_FP_TMDS_DATA      0x8b4
/* 0xff - data mask */

/* What is the purpose of this second set? */
#define NV_RAMDAC_FP_TMDS_CONTROL_2   0x8b8
/* 0xff - address mask */
#define NV_RAMDAC_FP_TMDS_CONTROL_2_WRITE_DISABLE (1<<16)
#define NV_RAMDAC_FP_TMDS_DATA_2      0x8bc
/* 0xff - data mask */

/* Some kind of switch */
#define NV_RAMDAC_900                   0x900

#define NV_RAMDAC_A20           0xA20
#define NV_RAMDAC_A24           0xA24
#define NV_RAMDAC_A34           0xA34

#define NV_CRTC_INTR_0              0x100
#       define NV_CRTC_INTR_VBLANK           1
#define NV_CRTC_INTR_EN_0           0x140
#define NV_CRTC_START               0x800
#define NV_CRTC_CONFIG               0x804
#define NV_CRTC_CURSOR_CONFIG       0x810
#define NV_CRTC_GPIO                    0x818
#define NV_CRTC_081C                0x81c
#define NV_CRTC_0830                0x830
#define NV_CRTC_0834                0x834
#define NV_CRTC_0850                    0x850
#define NV_CRTC_FSEL                0x860
#define NV_CRTC_FSEL_I2C           (1<<4)
#define NV_CRTC_FSEL_TVOUT1        (1<<8)
#define NV_CRTC_FSEL_TVOUT2        (2<<8)
#define NV_CRTC_FSEL_OVERLAY       (1<<12)
#define NV_CRTC_FSEL_FPP2          (1<<16)
#define NV_CRTC_FSEL_FPP1          (2<<16)

#define NV_PFB_CFG0                 0x200
#define NV_PFB_CFG1                 0x204
#define NV_PFB_020C                 0x20C
#define NV_PFB_TILE_NV10            0x240
#define NV_PFB_TILE_SIZE_NV10       0x244
#define NV_PFB_CLOSE_PAGE2          0x33C
#define NV_PFB_TILE_NV40            0x600
#define NV_PFB_TILE_SIZE_NV40       0x604

#define NV_PGRAPH_DEBUG_0           0x080
#define NV_PGRAPH_DEBUG_1           0x084
#define NV_PGRAPH_DEBUG_2_NV04      0x088
#define NV_PGRAPH_DEBUG_2           0x620
#define NV_PGRAPH_DEBUG_3           0x08c
#define NV_PGRAPH_DEBUG_4           0x090

#define NV_PGRAPH_INTR              0x100
#define NV_PGRAPH_INTR_EN           0x140
#define NV_PGRAPH_CTX_CONTROL       0x144
#define NV_PGRAPH_CTX_CONTROL_NV04  0x170
#define NV_PGRAPH_ABS_UCLIP_XMIN    0x53C
#define NV_PGRAPH_ABS_UCLIP_YMIN    0x540
#define NV_PGRAPH_ABS_UCLIP_XMAX    0x544
#define NV_PGRAPH_ABS_UCLIP_YMAX    0x548
#define NV_PGRAPH_BETA_AND          0x608
#define NV_PGRAPH_LIMIT_VIOL_PIX    0x610

#define NV_PGRAPH_BOFFSET0          0x640
#define NV_PGRAPH_BOFFSET1          0x644
#define NV_PGRAPH_BOFFSET2          0x648

#define NV_PGRAPH_BLIMIT0           0x684
#define NV_PGRAPH_BLIMIT1           0x688
#define NV_PGRAPH_BLIMIT2           0x68c

#define NV_PGRAPH_SURFACE           0x710
#define NV_PGRAPH_STATE             0x714
#define NV_PGRAPH_FIFO              0x720

#define NV_PGRAPH_PATTERN_SHAPE     0x810

#define NV_PGRAPH_TILE              0xb00

#define NV_PVIDEO_INTR_EN           0x140
#define NV_PVIDEO_BUFFER            0x700
#define NV_PVIDEO_STOP              0x704
#define NV_PVIDEO_UVPLANE_BASE(buff)        (0x800+(buff)*4)
#define NV_PVIDEO_UVPLANE_LIMIT(buff)       (0x808+(buff)*4)
#define NV_PVIDEO_UVPLANE_OFFSET_BUFF(buff) (0x820+(buff)*4)
#define NV_PVIDEO_BASE(buff)        (0x900+(buff)*4)
#define NV_PVIDEO_LIMIT(buff)       (0x908+(buff)*4)
#define NV_PVIDEO_LUMINANCE(buff)   (0x910+(buff)*4)
#define NV_PVIDEO_CHROMINANCE(buff) (0x918+(buff)*4)
#define NV_PVIDEO_OFFSET_BUFF(buff) (0x920+(buff)*4)
#define NV_PVIDEO_SIZE_IN(buff)     (0x928+(buff)*4)
#define NV_PVIDEO_POINT_IN(buff)    (0x930+(buff)*4)
#define NV_PVIDEO_DS_DX(buff)       (0x938+(buff)*4)
#define NV_PVIDEO_DT_DY(buff)       (0x940+(buff)*4)
#define NV_PVIDEO_POINT_OUT(buff)   (0x948+(buff)*4)
#define NV_PVIDEO_SIZE_OUT(buff)    (0x950+(buff)*4)
#define NV_PVIDEO_FORMAT(buff)      (0x958+(buff)*4)
#       define NV_PVIDEO_FORMAT_PLANAR    (1 << 0)
#       define NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8    (1 << 16)
#       define NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY        (1 << 20)
#       define NV_PVIDEO_FORMAT_MATRIX_ITURBT709         (1 << 24)
#define NV_PVIDEO_COLOR_KEY          0xB00

/* These are the real registers, not the redirected ones */
#define NV40_VCLK1_A                    0x4010
#define NV40_VCLK1_B                    0x4014
#define NV40_VCLK2_A                    0x4018
#define NV40_VCLK2_B                    0x401c

#endif